ELPIDA HB52E648EN-A6B

HB52E648EN-A6B/B6B,
HB52E649EN-A6B/B6B
512 MB Unbuffered SDRAM DIMM, 100 MHz Memory Bus
(HB52E648EN) 64-Mword × 64-bit, 2-Bank Module
(16 pcs of 32 M × 8 Components)
(HB52E649EN) 64-Mword × 72-bit, 2-Bank Module
(18 pcs of 32 M × 8 Components)
PC100 SDRAM
E0013H10 (1st edition)
(Previous ADE-203-1116A (Z))
Preliminary
Jan. 19, 2001
Description
The HB52E648EN, HB52E649EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and
have been developed as an optimized main memory solution for 8-byte processor applications. They are
synchronous Dynamic RAM Module, mounted 256-Mbit SDRAMs (HM5225805BTT) sealed in TSOP
package, and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). The HB52E648EN
is organized 32M × 64 × 2-bank mounted 16 pieces of 256-Mbit SDRAM. The HB52E649EN is organized
32M × 72 × 2-bank mounted 18 pieces of 256-Mbit SDRAM. An outline of the products is 168-pin socket
type package (dual lead out). Therefore, they make high density mounting possible without surface mount
technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside
each TSOP on the module board.
Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
: Intel PCB Reference design (Rev. 1.0)
• 168-pin socket type package (dual lead out)
 Outline: 133.37 mm (Length) × 34.925 mm (Height) × 4.00 mm (Thickness)
 Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width : × 64 Non parity (HB52E648EN)
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Elpida
Memory, Inc. regarding specification.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52E648EN/HB52E649EN-A6B/B6B
•
•
•
•
•
•
•
•
•
: × 72 ECC (HB52E649EN)
Single pulsed RAS
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
 Sequential
 Interleave
Programmable CE latency : 2/3 (HB52E648EN/52E649EN-A6B)
: 3 (HB52E648EN/52E649EN-B6B)
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
 Auto refresh
 Self refresh
Ordering Information
Type No.
Frequency
CE latency
Package
Contact pad
HB52E648EN-A6B
HB52E648EN-B6B
100 MHz
100 MHz
2/ 3
3
168-pin dual lead out soc ket ty pe
Gold
HB52E649EN-A6B
HB52E649EN-B6B
100 MHz
100 MHz
2/ 3
3
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
85 pin 94 pin 95 pin 124 pin 125 pin
Preliminary Data Sheet E0013H10
2
84 pin
168 pin
HB52E648EN/HB52E649EN-A6B/B6B
(HB52E648EN)
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
S2
87
DQ33
129
NC (S3)* 2
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VC C
48
NC
90
VC C
132
NC
7
DQ4
49
VC C
91
DQ36
133
VC C
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
NC
94
DQ39
136
NC
11
DQ8
53
NC
95
DQ40
137
NC
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VC C
101
DQ45
143
VC C
18
VC C
60
DQ20
102
VC C
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
NC
63
NC
(CKE1)* 1
105
NC
147
NC
22
NC
64
VSS
106
NC
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
Preliminary Data Sheet E0013H10
3
HB52E648EN/HB52E649EN-A6B/B6B
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
26
VC C
68
VSS
110
VC C
152
VSS
27
W
69
DQ24
111
CE
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
156
DQ59
3
30
S0
72
DQ27
114
NC (S1)*
31
NC
73
VC C
115
RE
157
VC C
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10 (AP)
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VC C
82
SDA
124
VC C
166
SA1
41
VC C
83
SCL
125
CK1
167
SA2
42
CK0
84
VC C
126
A12
168
VC C
Not es : 1. CKE1: HB52E648EN
2. S3: HB52E648EN
3. S1: HB52E648EN
Preliminary Data Sheet E0013H10
4
HB52E648EN/HB52E649EN-A6B/B6B
(HB52E649EN)
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
S2
87
DQ33
129
NC (S3)* 2
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VC C
48
NC
90
VC C
132
NC
7
DQ4
49
VC C
91
DQ36
133
VC C
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VC C
101
DQ45
143
VC C
18
VC C
60
DQ20
102
VC C
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
(CKE1)* 1
105
CB4
147
NC
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
VC C
68
VSS
110
VC C
152
VSS
27
W
69
DQ24
111
CE
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
156
DQ59
3
30
S0
72
DQ27
114
NC (S1)*
31
NC
73
VC C
115
RE
157
VC C
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
Preliminary Data Sheet E0013H10
5
HB52E648EN/HB52E649EN-A6B/B6B
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10 (AP)
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VC C
82
SDA
124
VC C
166
SA1
41
VC C
83
SCL
125
CK1
167
SA2
42
CK0
84
VC C
126
A12
168
VC C
Not es : 1. CKE1: HB52E649EN
2. S3: HB52E649EN
3. S1: HB52E649EN
Pin Description (HB52E648EN)
Pin name
Function
A0 to A12
Address input
 Row address
A0 to A12
 Column address
A0 to A9
BA0/ BA1
Bank selec t addres s
DQ0 to DQ63
Dat a input / out put
S0 to S3
Chip selec t input
RE
Row enable (RAS) input
CE
Column enable (CAS) input
W
Writ e enable input
DQMB0 t o DQMB7
By t e dat a mas k
CK0 to CK3
Cloc k input
CKE0, CKE1
Cloc k enable input
WP
Writ e prot ec t for serial PD
SDA
Dat a input / out put for serial PD
SCL
Cloc k input for s erial PD
SA0 to SA2
Serial addres s input
VC C
Primary pos it iv e power supply
VSS
Ground
NC
No connec t ion
Preliminary Data Sheet E0013H10
6
HB52E648EN/HB52E649EN-A6B/B6B
Pin Description (HB52E649EN)
Pin name
Function
A0 to A12
Address input
 Row address
A0 to A12
 Column address
A0 to A9
BA0/ BA1
Bank selec t addres s
DQ0 to DQ63
Dat a input / out put
CB0 to CB7
Chec k bit (Dat a input / out put )
S0 to S3
Chip selec t input
RE
Row enable (RAS) input
CE
Column enable (CAS) input
W
Writ e enable input
DQMB0 t o DQMB7
By t e dat a mas k
CK0 to CK3
Cloc k input
CKE0, CKE1
Cloc k enable input
WP
Writ e prot ec t for serial PD
SDA
Dat a input / out put for serial PD
SCL
Cloc k input for s erial PD
SA0 to SA2
Serial addres s input
VC C
Primary pos it iv e power supply
VSS
Ground
NC
No connec t ion
Preliminary Data Sheet E0013H10
7
HB52E648EN/HB52E649EN-A6B/B6B
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses
bits
0
0
0
0
1
1
0
1
0D
13
4
Number of column
addresses bits
0
0
0
0
1
0
1
0
0A
10
5
Number of banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
(HB52E648EN)
0
1
0
0
0
0
0
0
40
64
(HB52E649EN)
0
1
0
0
1
0
0
0
48
72
7
Module data width
(continued)
0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal
levels
0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest CE latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
10
SDRAM access from Clock
(highest CE latency)
6 ns
0
1
1
0
0
0
0
0
60
11
Module configuration type
(HB52E648EN)
0
0
0
0
0
0
0
0
00
Non parity
(HB52E649EN)
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82
Normal
(7.8125 µs)
Self refresh
13
SDRAM width
0
0
0
0
1
0
0
0
08
32M × 8
14
Error checking SDRAM width
(HB52E648EN)
0
0
0
0
0
0
0
0
00
—
(HB52E649EN)
0
0
0
0
1
0
0
0
08
×8
0
0
0
0
0
0
1
01
1 CLK
0
0
0
1
1
1
1
0F
1, 2, 4, 8
15
SDRAM device attributes:
minimum clock delay for
back-to-back random column
addresses
0
16
SDRAM device attributes:
Burst lengths supported
0
Preliminary Data Sheet E0013H10
8
HB52E648EN/HB52E649EN-A6B/B6B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
17
SDRAM device attributes:
0
number of banks on SDRAM
device
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
0
0
0
0
0
1
1
0
06
2, 3
19
SDRAM device attributes:
S latency
0
0
0
0
0
0
0
1
01
0
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM module attributes
0
0
0
0
0
0
0
0
00
Non buffer
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6B) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
SDRAM cycle time
(2nd highest CE latency)
(-B6B) 15 ns
1
1
1
1
0
0
0
0
F0
SDRAM access from Clock
(2nd highest CE latency)
(-A6B) 6 ns
0
1
1
0
0
0
0
0
60
SDRAM access from Clock
(2nd highest CE latency)
(-B6B) 9 ns
1
0
0
1
0
0
0
0
90
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time 0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min 0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on
module
0
1
0
0
0
0
0
0
40
2 bank
256 M byte
32
Address and command
signal input setup time
0
0
1
0
0
0
0
0
20
2.0 ns
33
Address and command
signal input hold time
0
0
0
1
0
0
0
0
10
1.0 ns
34
Data signal input setup time 0
0
1
0
0
0
0
0
20
2.0 ns
24
CL = 2
Preliminary Data Sheet E0013H10
9
HB52E648EN/HB52E649EN-A6B/B6B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
35
0
0
0
1
0
0
0
0
10
1.0 ns
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev.1.2A
63
Checksum for bytes 0 to 62
(HB52E648EN-A6B)
1
0
1
1
1
0
1
0
BA
186
(HB52E648EN-B6B)
0
0
1
1
1
0
1
0
3A
58
(HB52E649EN-A6B)
1
1
0
0
1
1
0
0
CC
204
(HB52E649EN-B6B)
0
1
0
0
1
1
0
0
4C
76
Manufacturer’s JEDEC ID
code
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manufacturer’s JEDEC ID
code
0
0
0
0
0
0
0
0
00
72
Manufacturing location
×
×
×
×
×
×
×
×
××
* 3 (ASCII8bit code)
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
0
0
1
0
1
45
E
78
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
79
Manufacturer’s part number
0
0
1
1
0
1
0
0
34
4
80
Manufacturer’s part number
(HB52E648EN)
0
0
1
1
1
0
0
0
38
8
0
0
1
1
1
0
0
1
39
9
64
Data signal input hold time
(HB52E649EN)
81
Manuf ac t urer’s part number
0
1
0
0
0
1
0
1
45
E
82
Manuf ac t urer’s part number
0
1
0
0
1
1
1
0
4E
N
83
Manuf ac t urer’s part number
0
0
1
0
1
1
0
1
2D
—
84
Manuf ac turer’s part number
(HB52E648EN/ 649EN-A6B) 0
1
0
0
0
0
0
1
41
A
(HB52E648EN/ 649EN-B6B) 0
1
0
0
0
0
1
0
42
B
85
Manuf ac t urer’s part number
0
0
1
1
0
1
1
0
36
6
86
Manuf ac t urer’s part number
0
1
0
0
0
0
1
0
42
B
87
Manuf ac t urer’s part number
0
0
1
0
0
0
0
0
20
(Spac e)
88
Manuf ac t urer’s part number
0
0
1
0
0
0
0
0
20
(Spac e)
Preliminary Data Sheet E0013H10
10
HB52E648EN/HB52E649EN-A6B/B6B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
89
Manuf ac t urer’s part number
0
0
1
0
0
0
0
0
20
(Spac e)
90
Manuf ac t urer’s part number
0
0
1
0
0
0
0
0
20
(Spac e)
91
Rev is ion code
0
0
1
1
0
0
0
0
30
I nit ial
92
Rev is ion code
0
0
1
0
0
0
0
0
20
(Spac e)
93
Manuf ac t uring dat e
×
×
×
×
×
×
×
×
××
Year code
(BCD)*4
94
Manuf ac t uring dat e
×
×
×
×
×
×
×
×
××
Week code
(BCD)*4
—
—
—
—
—
—
—
—
*5
95 to 98 As s embly serial number
*6
99 to 125 Manuf ac t urer spec if ic dat a
—
126
I nt el s pec if ic ation frequenc y 0
1
1
0
0
1
0
0
64
100 MHz
127
I nt el s pec ific ation CE# lat enc y
s upport
(HB52E648EN/ 649EN-A6B) 1
1
1
1
1
1
1
1
FF
CL = 2, 3
(HB52E648EN/ 649EN-B6B) 1
1
1
1
1
1
0
1
FD
CL = 3
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
Preliminary Data Sheet E0013H10
11
HB52E648EN/HB52E649EN-A6B/B6B
Block Diagram (HB52E648EN)
A0 to A12, BA0, BA1
RE, CE, W
S1
S0
CS
DQM
DQMB0
DQ0
to DQ7
8 N0, N1 I/O0
to I/O7
DQMB1
CS
DQM
DQ8
to DQ15
8 N2, N3 I/O0
to I/O7
CS
CS
D0
D1
DQM
CS
DQMB4
DQM
I/O0
to I/O7
8 N8, N9
DQ32
to DQ39
I/O0
to I/O7
I/O0
to I/O7
CS
DQM
DQMB5
CS
DQM
CS
DQM
D8
D9
I/O0
to I/O7
D4
8 N10, N11 I/O0
DQ40
to I/O7
to DQ47
D5
DQM
D12
D13
I/O0
to I/O7
S3
S2
CS
DQM
DQMB2
DQ16
to DQ23
8 N4, N5 I/O0
to I/O7
DQMB3
CS
DQM
DQ24
to DQ31
8 N6, N7 I/O0
to I/O7
CS
D2
D3
DQM
CS
D10
DQM
DQMB6
I/O0
to I/O7
8 N12, N13 I/O0
DQ48
to I/O7
to DQ55
CS
DQM
DQMB7
I/O0
to I/O7
D11
CS
DQM
8 N14, N15 I/O0
DQ56
to I/O7
to DQ63
VCC
R100
CK0
CLK; 4 SDRAMs + 3.3 pF cap
CS
D6
DQM
D14
I/O0
to I/O7
D7
CS
DQM
D15
I/O0
to I/O7
VCC (D0 to D15, U0)
C0 to C15
C16 to C31
VSS
VSS (D0 to D15, U0)
R101
CK1
CLK; 4 SDRAMs + 3.3 pF cap CKE0
CKE (D0 to D7)
VCC
R102
CK2
CLK; 4 SDRAMs + 3.3 pF cap
R103
CK3
R0
CKE1
CLK; 4 SDRAMs + 3.3 pF cap
CKE (D8 to D15)
Serial PD
SCL
SCL
SDA
SDA
U0
A0
A1
WP
A2
R1
SA0 SA1 SA2 VSS
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
* D0 to D15: HM5225805
U0: 2-kbit EEPROM
C0 to C15: 0.33 µF, C16 to C31: 0.10 µF
R0: 10 kΩ, R1: 47 kΩ
N0 to N15: Network registor 10 Ω
R100 to R103: 10 Ω
Preliminary Data Sheet E0013H10
12
HB52E648EN/HB52E649EN-A6B/B6B
Block Diagram (HB52E649EN)
A0 to A12, BA0, BA1
RE, CE, W
S1
S0
DQ0
to DQ7
8 N0, N1 I/O0
to I/O7
DQMB1
CS
DQM
DQ8
to DQ15
8 N2, N3 I/O0
to I/O7
CS
DQM
CB0
to CB7
8 N4, N5 I/O0
to I/O7
CS
CS
CS
DQM
DQMB0
D0
D1
DQM
DQM
DQMB4
D9
I/O0
to I/O7
8 N10, N11 I/O0
DQ32
to I/O7
to DQ39
CS
DQM
DQMB5
D10
8 N12, N13 I/O0
DQ40
to I/O7
to DQ47
I/O0
to I/O7
CS
D2
CS
DQM
CS
D5
DQM
D14
I/O0
to I/O7
D6
CS
DQM
D15
I/O0
to I/O7
DQM
D11
I/O0
to I/O7
S3
S2
CS
DQM
DQMB2
DQ16
to DQ23
8 N6, N7 I/O0
to I/O7
DQMB3
CS
DQM
DQ24
to DQ31
8 N8, N9 I/O0
to I/O7
CS
D3
D4
DQM
CS
D12
I/O0
to I/O7
8 N14, N15 I/O0
DQ48
to I/O7
to DQ55
CS
DQM
DQMB7
D13
VCC
CLK (5 SDRAMs)
D7
D8
CS
DQM
D17
I/O0
to I/O7
VSS (D0 to D17, U0)
CKE0
CKE (D0 to D8)
VCC
R102
R0
CLK (4 SDRAMs + 3.3 pF cap)
CKE1
CKE (D9 to D17)
Serial PD
R103
CK3
D16
I/O0
to I/O7
C18 to C35
VSS
CLK (5 SDRAMs)
CK2
CS
DQM
VCC (D0 to D17, U0)
C0 to C17
R101
CK1
CS
DQM
8 N16, N17 I/O0
DQ56
to I/O7
to DQ63
I/O0
to I/O7
R100
CK0
DQM
DQMB6
CLK (4 SDRAMs + 3.3 pF cap)
SCL
SCL
SDA
SDA
U0
A0
A1
A2
WP
R1
VSS
SA0 SA1 SA2
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
3. SDRAM D11 DQMB input is wired to DQMB5
* D0 to D17: HM5225805
U0: 2-kbit EEPROM
C0 to C17: 0.33 µF, C18 to C35: 0.10 µF
R0: 10 kΩ, R1: 47 kΩ
N0 to N17: Network registor 10 Ω
R100 to R103: 10 Ω
Preliminary Data Sheet E0013H10
13
HB52E648EN/HB52E649EN-A6B/B6B
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Volt age on any pin relat ive to VSS
VT
–0. 5 to VC C + 0. 5
(≤ 4. 6 (max ))
V
1
Supply volt age relat iv e to VSS
VC C
–0. 5 to +4. 6
V
1
Short c irc uit out put current
I out
50
mA
Power dis s ipat ion (HB52E648EN)
PT
8. 0
W
Power dis s ipat ion (HB52E649EN)
PT
9. 0
W
Operating temperat ure
Topr
0 to +65
°C
St orage temperature
Ts t g
–55 to +125
°C
Not e:
1. Res pect to VSS
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply volt age
VC C
3. 0
3. 6
V
1, 2
VSS
0
0
V
3
I nput high volt age
VIH
2. 0
VC C + 0. 3
V
1, 4
I nput low volt age
VIL
–0. 3
0. 8
V
1, 5
Not es : 1.
2.
3.
4.
5.
All volt age ref erred to VSS
The supply volt age wit h all VC C pins mus t be on the same lev el.
The supply volt age wit h all VSS pins mus t be on the same lev el.
VIH (max ) = VC C + 2. 0 V for puls e wit h ≤ 3 ns at VC C .
VIL (min) = VSS – 2. 0 V for puls e widt h ≤ 3 ns at VSS.
Preliminary Data Sheet E0013H10
14
HB52E648EN/HB52E649EN-A6B/B6B
VIL/VIH Clamp (Component characteristic)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins.
Minimum VIL Clamp Current
VIL (V)
I (mA)
–2
–32
–1. 8
–25
–1. 6
–19
–1. 4
–13
–1. 2
–8
–1
–4
–0. 9
–2
–0. 8
–0. 6
–0. 6
0
–0. 4
0
–0. 2
0
0
0
0
–5
–2
–1.5
–1
–0.5
0
I (mA)
–10
–15
–20
–25
–30
–35
VIL (V)
Preliminary Data Sheet E0013H10
15
HB52E648EN/HB52E649EN-A6B/B6B
Minimum VIH Clamp Current
VIH (V)
I (mA)
VC C + 2
10
VC C + 1. 8
8
VC C + 1. 6
5. 5
VC C + 1. 4
3. 5
VC C + 1. 2
1. 5
VC C + 1
0. 3
VC C + 0. 8
0
VC C + 0. 6
0
VC C + 0. 4
0
VC C + 0. 2
0
VC C + 0
0
10
I (mA)
8
6
4
2
0
VCC + 0
VCC + 0.5
VCC + 1
VIH (V)
Preliminary Data Sheet E0013H10
16
VCC + 1.5
VCC + 2
HB52E648EN/HB52E649EN-A6B/B6B
IOL/IOH Characteristics (Component characteristic)
Output Low Current (IOL)
I OL
I OL
Vout (V)
Mi n (mA)
Max (mA)
0
0
0
0. 4
27
71
0. 65
41
108
0. 85
51
134
1
58
151
1. 4
70
188
1. 5
72
194
1. 65
75
203
1. 8
77
209
1. 95
77
212
3
80
220
3. 45
81
223
250
IOL (mA)
200
150
min
max
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Vout (V)
Preliminary Data Sheet E0013H10
17
HB52E648EN/HB52E649EN-A6B/B6B
Output High Current (I OH ) (Ta = 0 to 65˚C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH
I OH
Vout (V)
Mi n (mA)
Max (mA)
3. 45
—
–3
3. 3
—
–28
3
0
–75
2. 6
–21
–130
2. 4
–34
–154
2
–59
–197
1. 8
–67
–227
1. 65
–73
–248
1. 5
–78
–270
1. 4
–81
–285
1
–89
–345
0
–93
–503
0
0
0.5
1
1.5
2
2.5
3
3.5
IOH (mA)
–100
–200
min
max
–300
–400
–500
–600
Vout (V)
Preliminary Data Sheet E0013H10
18
HB52E648EN/HB52E649EN-A6B/B6B
DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB52E648EN)
HB52E648EN
-A6B/B6B
Parameter
Symbol Min
Max
Unit
Test conditions
Notes
Operating current
(CE lat enc y = 2)
—
1000
mA
Burs t lengt h = 1
t R C = min
1, 2, 3
ICC1
(CE lat enc y = 3)
ICC1
—
1000
mA
St andby current in power down
I C C 2P
—
48
mA
CKE = VIL, tC K = 12 ns
6
St andby current in power down
(input signal stable)
I C C 2PS
—
32
mA
CKE = VIL, tC K = ∞
7
St andby current in non power
down
I C C 2N
—
320
mA
CKE, S = VIH ,
t C K = 12 ns
4
Ac t iv e st andby current in power I C C 3P
down
—
64
mA
CKE = VIL, tC K = 12 ns
1, 2, 6
Ac t iv e st andby current in non
power down
I C C 3N
—
480
mA
CKE, S = VIH ,
t C K = 12 ns
1, 2, 4
t C K = min, BL = 4
1, 2, 5
ICC4
—
1040
mA
ICC4
—
1040
mA
Ref resh current
ICC5
—
2000
mA
t R C = min
3
Self ref res h current
ICC6
—
48
mA
VIH ≥ VC C – 0. 2 V
VIL ≤ 0. 2 V
8
I nput leak age current
I LI
–10
10
µA
0 ≤ Vin ≤ VC C
Out put leak age current
I LO
–10
10
µA
0 ≤ Vout ≤ VC C
DQ = dis able
Out put high voltage
VOH
2. 4
—
V
I OH = –4 mA
Out put low volt age
VOL
—
0. 4
V
I OL = 4 mA
Burs t operat ing c urrent
(CE lat enc y = 2)
(CE lat enc y = 3)
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0013H10
19
HB52E648EN/HB52E649EN-A6B/B6B
DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB52E649EN)
HB52E649EN
-A6B/B6B
Parameter
Symbol Min
Max
Unit
Test conditions
Notes
Operating current
(CE lat enc y = 2)
—
1125
mA
Burs t lengt h = 1
t R C = min
1, 2, 3
ICC1
(CE lat enc y = 3)
ICC1
—
1125
mA
St andby current in power down
I C C 2P
—
54
mA
CKE = VIL, tC K = 12 ns
6
St andby current in power down
(input signal stable)
I C C 2PS
—
36
mA
CKE = VIL, tC K = ∞
7
St andby current in non power
down
I C C 2N
—
360
mA
CKE, S = VIH ,
t C K = 12 ns
4
Ac t iv e st andby current in power I C C 3P
down
—
72
mA
CKE = VIL, tC K = 12 ns
1, 2, 6
Ac t iv e st andby current in non
power down
I C C 3N
—
540
mA
CKE, S = VIH ,
t C K = 12 ns
1, 2, 4
t C K = min, BL = 4
1, 2, 5
ICC4
—
1170
mA
ICC4
—
1170
mA
Ref resh current
ICC5
—
2250
mA
t R C = min
3
Self ref res h current
ICC6
—
54
mA
VIH ≥ VC C – 0. 2 V
VIL ≤ 0. 2 V
8
I nput leak age current
I LI
–10
10
µA
0 ≤ Vin ≤ VC C
Out put leak age current
I LO
–10
10
µA
0 ≤ Vout ≤ VC C
DQ = dis able
Out put high voltage
VOH
2. 4
—
V
I OH = –4 mA
Out put low volt age
VOL
—
0. 4
V
I OL = 4 mA
Burs t operat ing c urrent
(CE lat enc y = 2)
(CE lat enc y = 3)
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0013H10
20
HB52E648EN/HB52E649EN-A6B/B6B
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB52E648EN)
Parameter
Symbol
Max
Unit
Notes
I nput c apac it ance (Addres s)
CI1
105
pF
1, 2, 4
I nput c apac it ance (RE, CE, W)
CI2
90
pF
1, 2, 4
I nput c apac it ance (CKE)
CI3
68
pF
1, 2, 4
I nput c apac it ance (S)
CI4
38
pF
1, 2, 4
I nput c apac it ance (CK)
CI5
50
pF
1, 2, 4
I nput c apac it ance (DQMB)
CI6
23
pF
1, 2, 4
I nput /Out put capac it anc e (DQ)
CI/O1
22
pF
1, 2, 3, 4
Not es : 1.
2.
3.
4.
Capac it anc e measured wit h Boont on Met er or ef fec t iv e capac it anc e meas uring met hod.
Meas urement condit ion: f = 1 MHz , 1. 4 V bias , 200 mV swing.
DQMB = VIH to dis able Dat a-out .
This paramet er is sampled and not 100% tes t ed.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB52E649EN)
Parameter
Symbol
Max
Unit
Notes
I nput c apac it ance (Addres s)
CI1
112
pF
1, 2, 4
I nput c apac it ance (RE, CE, W)
CI2
97
pF
1, 2, 4
I nput c apac it ance (CKE)
CI3
70
pF
1, 2, 4
I nput c apac it ance (S)
CI4
40
pF
1, 2, 4
I nput c apac it ance (CK)
CI5
50
pF
1, 2, 4
I nput c apac it ance (DQMB)
CI6
27
pF
1, 2, 4
I nput /Out put capac it anc e (DQ)
CI/O1
22
pF
1, 2, 3, 4
Not es : 1.
2.
3.
4.
Capac it anc e measured wit h Boont on Met er or ef fec t iv e capac it anc e meas uring met hod.
Meas urement condit ion: f = 1 MHz , 1. 4 V bias , 200 mV swing.
DQMB = VIH to dis able Dat a-out .
This paramet er is sampled and not 100% tes t ed.
Preliminary Data Sheet E0013H10
21
HB52E648EN/HB52E649EN-A6B/B6B
AC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52E648EN/649EN
-A6B/B6B
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
Sy s t em cloc k cy cle time
(CE lat enc y = 2)
tCK
Tc lk
10
—
ns
tCK
Tc lk
10
—
ns
CK high puls e widt h
t C KH
Tc h
3
—
ns
1
CK low puls e widt h
t C KL
Tc l
3
—
ns
1
Ac c es s time from CK
(CE lat enc y = 2)
t AC
Tac
—
6
ns
(CE lat enc y = 3)
t AC
Tac
—
6
ns
Dat a-out hold time
t OH
Toh
3
—
ns
1, 2
CK to Dat a-out low impedanc e
t LZ
2
—
ns
1, 2, 3
CK to Dat a-out high impedanc e
tHZ
—
6
ns
1, 4
Dat a-in set up time
tDS
Ts i
2
—
ns
1
Dat a in hold time
tDH
Thi
1
—
ns
1
Address set up time
t AS
Ts i
2
—
ns
1
Address hold time
t AH
Thi
1
—
ns
1
CKE set up time
t C ES
Ts i
2
—
ns
1, 5
CKE set up time for power down ex it
t C ESP
Tpde
2
—
ns
1
CKE hold time
t C EH
Thi
1
—
ns
1
Command set up time
tCS
Ts i
2
—
ns
1
Command hold time
tCH
Thi
1
—
ns
1
Ref / Act iv e to Ref / Ac t iv e command
period
tRC
Trc
70
—
ns
1
Ac t iv e to prec harge command period
t R AS
Tras
50
120000
ns
1
Ac t iv e command to column command
(s ame bank )
tRCD
Trc d
20
—
ns
1
Prec harge to ac tiv e command period
tRP
Trp
20
—
ns
1
Writ e rec ov ery or dat a-in t o prec harge t D PL
lead time
Tdpl
20
—
ns
1
Ac t iv e (a) to Act iv e (b) command
period
tRRD
Trrd
20
—
ns
1
Trans it ion time (ris e and f all)
tT
1
5
ns
Ref resh period
t R EF
—
64
ms
1
(CE lat enc y = 3)
1, 2
Preliminary Data Sheet E0013H10
22
Notes
HB52E648EN/HB52E649EN-A6B/B6B
Notes: 1.
2.
3.
4.
5.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is C L = 50 pF.
t LZ (min) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
DQ
2.0 V
0.8 V
CL
t
T
tT
Preliminary Data Sheet E0013H10
23
HB52E648EN/HB52E649EN-A6B/B6B
Relationship Between Frequency and Minimum Latency
HB52E648EN/649EN
Parameter
-A6B/B6B
Frequency (MHz)
100
PC100
Symbol Symbol 10
tCK (ns)
Notes
Ac t iv e command to column command (s ame bank ) I R C D
2
1
Ac t iv e command to ac t iv e command (s ame bank ) I R C
7
= [I R AS + IR P]
1
Ac t iv e command to prec harge command
(s ame bank )
I R AS
5
1
Prec harge command to ac t ive command
(s ame bank )
IRP
2
1
Writ e rec ov ery or dat a-in to prec harge command
(s ame bank )
I D PL
2
1
Ac t iv e command to ac t iv e command
(dif f erent bank )
IRRD
2
1
Self ref res h ex it time
I SR EX
Ts rx
1
2
Las t dat a in to ac t iv e command
(Aut o prec harge, same bank)
I APW
Tdal
4
= [I D PL + IR P]
Self ref res h ex it to command input
I SEC
7
= [I R C ]
3
Prec harge command to high impedanc e
(CE lat enc y = 2)
I H ZP
Troh
2
I H ZP
Troh
3
(CE lat enc y = 3)
Tdpl
Las t dat a out to ac t iv e command (auto prec harge) I APR
(s ame bank )
Las t dat a out to prec harge (early prec harge)
(CE lat enc y = 2)
(CE lat enc y = 3)
1
I EP
–1
I EP
–2
Column command to column command
ICCD
Tc c d
1
Writ e c ommand to dat a in lat enc y
I WC D
Tdwd
0
DQMB to dat a in
I D ID
Tdqm
0
DQMB to dat a out
I D OD
Tdqz
2
CKE to CK dis able
I C LE
Tc k e
1
Regis ter set to ac t iv e command
I R SA
Tmrd
1
S to command dis able
ICDD
0
Power down ex it t o command input
I PEC
1
Preliminary Data Sheet E0013H10
24
HB52E648EN/HB52E649EN-A6B/B6B
Not es : 1. I R C D to IR R D are rec ommended value.
2. Be valid [DSEL] or [NOP] at nex t command of self ref res h ex it .
3. Ex c ept [DSEL] and [NOP]
Preliminary Data Sheet E0013H10
25
HB52E648EN/HB52E649EN-A6B/B6B
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at
CK rising edge.
S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on
the combination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the
read or write command cycle CK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
BA0/BA1 (BS) is precharged.
BA0/BA1 (input pin): BA0/BA1 are bank select signal (BS). The memory array is divided into bank 0,
bank 1, bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is
Low, bank 1 is selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is
High, bank 3 is selected.
CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the
next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for
power-down and clock suspend modes.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is
Low, the data is written.
DQ0 to DQ63 (input/output pins): Data is input to and output from these pins.
CB0 to CB7 (input/output pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.
Preliminary Data Sheet E0013H10
26
HB52E648EN/HB52E649EN-A6B/B6B
Physical Outline
Unit: mm
inch
Front side
133.37 ± 0.15
5.251 ± 0.006
(DATUM -A-)
B
C
0.450
36.83
1.450
Back side
4.00 min
0.157 min
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Component area
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
(Front)
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
1
84
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
11.43
,,
,,
,,
,
A
1.27 ± 0.10
0.050 ± 0.004
54.61
2.150
127.35 ± 0.15
5.014 ± 0.006
2 – φ 3.00 ± 0.10
2 – φ 0.118 ± 0.003
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Component area
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
(Back)
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
(DATUM -A-)
R FULL
3.125 ± 0.125
0.123 ± 0.005
1.27
0.050
0.20 ± 0.15
0.010 ± 0.0004
2.50 ± 0.20
0.098 ± 0.008
1.00 ± 0.05
0.039 ± 0.002
Detail B
34.925
1.375
85
Detail A
17.80
0.70
168
4.00 ±0.10
0.157 ± 0.004
4.00 max
0.157 max
(63.67)
(2.51)
Detail C
(DATUM -A-)
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
1.00
0.039
3.125 ± 0.125
0.123 ± 0.005
3.00 ± 0.10
0.118 ± 0.004
3.00 typ
0.118 typ
R FULL
6.35
0.250
4.175
0.164
2.00 ± 0.10
0.079 ± 0.004
Note: Tolerance on all dimensions ± 0.15/0.006 unless otherwise specified.
Preliminary Data Sheet E0013H10
27
HB52E648EN/HB52E649EN-A6B/B6B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained
in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third
party’s rights, including intellectual property rights, in connection with use of the information contained
in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands
especially high quality and reliability or where its failure or malfunction may directly threaten human
life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control,
transportation, traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory,
Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure
or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider
normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic
measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not
cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc.
product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
Preliminary Data Sheet E0013H10
28