ETC HB52D48GB-A6FL

HB52D48GB-F
32 MB Unbuffered SDRAM Micro DIMM
4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module
(4 pcs of 4 M × 16 components)
PC100 SDRAM
ADE-203-1149 (Z)
Preliminary
Rev. 0.0
Jan. 13, 2000
Description
The HB52D48GB is a 4M × 64 × 1 banks Synchronous Dynamic RAM Micro Dual In-line Memory Module
(Micro DIMM), mounted 4 pieces of 64-Mbit SDRAM (HM5264165FTT) sealed in TSOP package and 1
piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin
Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density mounting possible
without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are
mounted beside TSOP on the module board.
Features
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
 Outline: 38.00 mm (Length) × 30.00 mm (Height) × 3.80 mm (Thickness)
 Lead pitch: 0.50 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page
• 2 variations of burst sequence
 Sequential (BL = 1/2/4/8/full page)
 interleave (BL = 1/2/4/8)
Preliminary:The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.
This Material Copyrighted by Its Respective Manufacturer
HB52D48GB-F
• Programmable CE latency : 2/3 (HB52D48GB-A6F/A6FL)
: 3 (HB52D48GB-B6F/B6FL)
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• Low self refresh current: HB52D48GB-A6FL/B6FL (L-version)
• Full page burst length capability
 Sequential burst
 Burst stop capability
Ordering Information
Type No.
Frequency
CE latency
Package
Contact pad
HB52D48GB-A6F
HB52D48GB-B6F
HB52D48GB-A6FL
HB52D48GB-B6FL
100 MHz
100 MHz
100 MHz
100 MHz
2/3
3
2/3
3
Micro DIMM (144-pin)
Gold
Pin Arrangement
Front Side
1pin
143pin
2pin
144pin
Back Side
2 Material Copyrighted by Its Respective Manufacturer
This
HB52D48GB-F
Front side
Back side
Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
1
VSS
73
NC
2
VSS
74
CK1
3
DQ0
75
VSS
4
DQ32
76
VSS
5
DQ1
77
NC
6
DQ33
78
NC
7
DQ2
79
NC
8
DQ34
80
NC
9
DQ3
81
VCC
10
DQ35
82
VCC
11
VCC
83
DQ16
12
VCC
84
DQ48
13
DQ4
85
DQ17
14
DQ36
86
DQ49
15
DQ5
87
DQ18
16
DQ37
88
DQ50
17
DQ6
89
DQ19
18
DQ38
90
DQ51
19
DQ7
91
VSS
20
DQ39
92
VSS
21
VSS
93
DQ20
22
VSS
94
DQ52
23
DQMB0
95
DQ21
24
DQMB4
96
DQ53
25
DQMB1
97
DQ22
26
DQMB5
98
DQ54
27
VCC
99
DQ23
28
VCC
100
DQ55
29
A0
101
VCC
30
A3
102
VCC
31
A1
103
A6
32
A4
104
A7
33
A2
105
A8
34
A5
106
A13 (BA0)
35
VSS
107
VSS
36
VSS
108
VSS
37
DQ8
109
A9
38
DQ40
110
A12 (BA1)
39
DQ9
111
A10 (AP)
40
DQ41
112
A11
41
DQ10
113
VCC
42
DQ42
114
VCC
43
DQ11
115
DQMB2
44
DQ43
116
DQMB6
45
VCC
117
DQMB3
46
VCC
118
DQMB7
47
DQ12
119
VSS
48
DQ44
120
VSS
49
DQ13
121
DQ24
50
DQ45
122
DQ56
51
DQ14
123
DQ25
52
DQ46
124
DQ57
53
DQ15
125
DQ26
54
DQ47
126
DQ58
55
VSS
127
DQ27
56
VSS
128
DQ59
57
NC
129
VCC
58
NC
130
VCC
59
NC
131
DQ28
60
NC
132
DQ60
This Material Copyrighted by Its Respective Manufacturer
3
HB52D48GB-F
Front side
Back side
Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
61
CK0
133
DQ29
62
CKE0
134
DQ61
63
VCC
135
DQ30
64
VCC
136
DQ62
65
RE
137
DQ31
66
CE
138
DQ63
67
W
139
VSS
68
NC
140
VSS
69
S0
141
SDA
70
NC
142
SCL
71
NC
143
VCC
72
NC
144
VCC
Pin Description
Pin name
Function
A0 to A11
Address input
 Row address A0 to A11
 Column address A0 to A7
A12/A13
Bank select address
DQ0 to DQ63
Data-input/output
S0
Chip select
RE
Row address asserted bank enable
CE
Column address asserted
W
Write enable
DQMB0 to DQMB7
Byte input/output mask
CK0/CK1
Clock input
CKE0
Clock enable
SDA
Data-input/output for serial PD
SCL
Clock input for serial PD
VCC
Power supply
VSS
Ground
NC
No connection
4 Material Copyrighted by Its Respective Manufacturer
This
BA1, BA0
HB52D48GB-F
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits 0
0
0
0
1
1
0
0
0C
12
4
Number of column addresses
bits
0
0
0
0
1
0
0
0
08
8
5
Number of banks
0
0
0
0
0
0
0
1
01
1
6
Module data width
0
1
0
0
0
0
0
0
40
64
7
Module data width (continued) 0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels 0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest CE latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
10
SDRAM access from Clock
(highest CE latency)
6 ns
0
1
1
0
0
0
0
0
60
11
Module configuration type
0
0
0
0
0
0
0
0
00
Non parity
12
Refresh rate/type
1
0
0
0
0
0
0
0
80
Normal
(15.625 µs)
Self refresh
13
SDRAM width
0
0
0
1
0
0
0
0
10
4M × 16
14
Error checking SDRAM width
0
0
0
0
0
0
0
0
00
—
15
0
SDRAM device attributes:
minimum clock delay for backto-back random column
addresses
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
1
0
0
0
1
1
1
1
8F
1, 2, 4, 8, full
page
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
0
0
0
0
0
1
1
0
06
2, 3
19
SDRAM device attributes:
S latency
0
0
0
0
0
0
0
1
01
0
This Material Copyrighted by Its Respective Manufacturer
5
HB52D48GB-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM module attributes
0
0
0
0
0
0
0
0
00
Unbuffer
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6F/A6FL) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
1
1
1
1
0
0
0
0
F0
0
1
1
0
0
0
0
0
60
1
0
0
0
0
0
0
0
80
(-B6F/B6FL) 15 ns
24
SDRAM access from Clock
(2nd highest CE latency)
(-A6F/A6FL) 6 ns
(-B6F/B6FL) 8 ns
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on
module
0
0
0
0
1
0
0
0
08
32M byte
32
Address and command signal 0
input setup time
0
1
0
0
0
0
0
20
2 ns
33
Address and command signal 0
input hold time
0
0
1
0
0
0
0
10
1 ns
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6F/A6FL)
0
0
0
0
0
1
0
0
04
4
0
1
1
1
0
1
0
0
74
116
Manuf act urer’s JEDEC ID c ode
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manuf act urer’s JEDEC ID c ode
0
0
0
0
0
0
0
0
00
72
×
×
×
×
×
×
×
×
××
(-B6F/B6FL)
64
Manufacturing location
6 Material Copyrighted by Its Respective Manufacturer
This
* 3 (ASCII8bit code)
HB52D48GB-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
78
Manufacturer’s part number
0
0
1
1
0
1
0
0
34
4
79
Manufacturer’s part number
0
0
1
1
1
0
0
0
38
8
80
Manufacturer’s part number
0
1
0
0
0
1
1
1
47
G
81
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
82
Manufacturer’s part number
0
0
1
0
1
1
0
1
2D
—
83
Manufacturer’s part number
(-A6F/A6FL)
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
(-B6F/B6FL)
84
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
85
Manufacturer’s part number
0
1
0
0
0
1
1
0
46
F
86
Manufacturer’s part number
(L-version)
0
1
0
0
1
1
0
0
4C
L
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
87
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
88
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
89
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Year code
(BCD)*4
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD)*4
95 to 98 Assembly serial number
*6
99 to 125 Manufacturer specific data
—
—
—
—
—
—
—
—
—
*5
126
Intel specification frequency
0
1
1
0
0
1
0
0
64
100 MHz
127
Intel specification CE# latency 1
support
(-A6F/A6FL)
1
0
0
0
1
1
1
C7
CL = 2, 3
1
0
0
0
1
0
1
C5
CL = 3
(-B6F/B6FL)
1
This Material Copyrighted by Its Respective Manufacturer
7
HB52D48GB-F
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
8 Material Copyrighted by Its Respective Manufacturer
This
HB52D48GB-F
Block Diagram
S0
W
CS
DQMB0
CS
DQMB4
8 N0, N1
8 N8, N9
DQ0 to DQ7
DQ32 to DQ39
D0
D2
DQMB1
DQMB5
8 N2, N3
8 N10, N11
DQ8 to DQ15
DQ40 to DQ47
CS
DQMB2
CS
DQMB6
8 N4, N5
8 N12, N13
DQ16 to DQ23
DQ48 to DQ55
D1
D3
DQMB3
DQMB7
8 N6, N7
DQ24 to DQ31
RE
RAS (D0 to D3)
CE
CAS (D0 to D3)
A0 to A11 (D0 to D3)
A0 to A11
BA0
A13 (D0 to D3)
BA1
A12 (D0 to D3)
CKE0
CKE (D0 to D3)
CLK (D0)
CLK (D1)
CK0
CLK (D2)
CLK (D3)
R0
CK1
C200
VCC
VCC (D0 to D3, U0)
C0-C7
VSS
8 N14, N15
DQ56 to DQ63
C100-C103
Serial PD
SCL
SDA
SCL
A0
SDA
U0
A1
A2
VSS
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
* D0 to D3: HM5264165
U0: 2-kbit EEPROM
C0 to C7: 0.33 µF
C100 to C103: 0.1 µF
C200: 10 pF
N0 to N15: Network resistors (10 Ω)
R0: Resistor (10 Ω)
VSS (D0 to D3, U0)
This Material Copyrighted by Its Respective Manufacturer
9
HB52D48GB-F
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
4.0
W
Operating temperature
Topr
0 to +65
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
1. Respect to V SS .
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC
3.0
3.6
V
1, 2
VSS
0
0
V
3
Input high voltage
VIH
2.0
VCC + 0.3
V
1, 4, 5
Input low voltage
VIL
–0.3
0.8
V
1, 6
Notes: 1.
2.
3.
4.
5.
6.
All voltage referred to VSS
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC.
Others: V IH (max) = 4.6 V for pulse width ≤ 5 ns at VCC.
VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS.
10 Material Copyrighted by Its Respective Manufacturer
This
HB52D48GB-F
VIL/VIH Clamp (Component characteristic)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins.
Minimum VIL Clamp Current
VIL (V)
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
–1.2
–8
–1
–4
–0.9
–2
–0.8
–0.6
–0.6
0
–0.4
0
–0.2
0
0
0
0
–5
–2
–1.5
–1
–0.5
0
I (mA)
–10
–15
–20
–25
–30
–35
VIL (V)
This Material Copyrighted by Its Respective Manufacturer
11
HB52D48GB-F
Minimum VIH Clamp Current
VIH (V)
I (mA)
VCC + 2
10
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
VCC + 0.6
0
VCC + 0.4
0
VCC + 0.2
0
VCC + 0
0
10
I (mA)
8
6
4
2
0
VCC + 0
VCC + 0.5
VCC + 1
VIH (V)
12 Material Copyrighted by Its Respective Manufacturer
This
VCC + 1.5
VCC + 2
HB52D48GB-F
IOL/IOH Characteristics (Component characteristic)
Output Low Current (IOL)
I OL
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
1
58
151
1.4
70
188
1.5
72
194
1.65
75
203
1.8
77
209
1.95
77
212
3
80
220
3.45
81
223
250
IOL (mA)
200
150
min
max
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Vout (V)
This Material Copyrighted by Its Respective Manufacturer
13
HB52D48GB-F
Output High Current (I OH ) (Ta = 0 to 65˚C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH
I OH
Vout (V)
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
1.8
–67
–227
1.65
–73
–248
1.5
–78
–270
1.4
–81
–285
1
–89
–345
0
–93
–503
0
0
0.5
1
1.5
2
2.5
3
3.5
IOH (mA)
–100
–200
min
max
–300
–400
–500
–600
Vout (V)
14 Material Copyrighted by Its Respective Manufacturer
This
HB52D48GB-F
DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52D48GB
-A6F/B6F/A6FL/B6FL
Parameter
Symbol Min
Max
Unit
Test conditions
Notes
Operating current
I CC1
—
260
mA
Burst length = 1
t RC = min
1, 2, 3
Standby current in power down I CC2P
—
6
mA
CKE0 = VIL, t CK = 12 ns 6
Standby current in power down I CC2PS
(input signal stable)
—
4
mA
CKE0 = VIL, t CK = ∞
7
Standby current in non power
down
I CC2N
—
40
mA
CKE0, S = VIH,
t CK = 12 ns
4
Active standby current in power I CC3P
down
—
16
mA
CKE0, S = VIH,
t CK = 12 ns
1, 2, 6
Active standby current in non
power down
I CC3N
—
72
mA
CKE0, S = VIH,
t CK = 12 ns
1, 2, 4
Burst operating current
I CC4
—
260
mA
t CK = 12 ns, BL = 4
1, 2, 5
Refresh current
I CC5
—
440
mA
t RC = min
3
Self refresh current
I CC6
—
4
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
Self refresh current
(L-version)
I CC6
—
1.6
mA
Input leakage current
I LI
–10
10
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–10
10
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
V
I OL = 4 mA
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
This Material Copyrighted by Its Respective Manufacturer
15
HB52D48GB-F
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CIN
40
pF
1, 2, 4
Input capacitance (RE, CE, W, CK0/CK1, CKE0)
CIN
40
pF
1, 2, 4
Input capacitance (S0)
CIN
40
pF
1, 2, 4
Input capacitance (DQMB0 to DQMB7)
CIN
20
pF
1, 2, 4
Input/Output capacitance (DQ0 to DQ63)
CI/O
20
pF
1, 2, 3, 4
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Data-out.
This parameter is sampled and not 100% tested.
16 Material Copyrighted by Its Respective Manufacturer
This
HB52D48GB-F
AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52D48GB
-A6F/A6FL
-B6F/B6FL
Parameter
HITACHI PC100
Symbol Symbol Min
Max
Min
Max
Unit
Notes
System clock cycle time
(CE latency = 2)
t CK
Tclk
10
—
15
—
ns
1
(CE latency = 3)
t CK
Tclk
10
—
10
—
ns
CK high pulse width
t CKH
Tch
3
—
3
—
ns
1
CK low pulse width
t CKL
Tcl
3
—
3
—
ns
1
Access time from CK
(CE latency = 2)
t AC
Tac
—
6
—
8
ns
1, 2
(CE latency = 3)
t AC
Tac
—
6
—
6
ns
Data-out hold time
t OH
Toh
3
—
3
—
ns
1, 2
CK to Data-out low impedance t LZ
2
—
2
—
ns
1, 2, 3
CK to Data-out high impedance t HZ
—
6
—
6
ns
1, 4
Tsi
2
—
2
—
ns
1, 5, 6
CKE setup time for power down t CESP
exit
Tpde
2
—
2
—
ns
1
Data-in hold time
t AH, t CH,
t DH, t CEH
Thi
1
—
1
—
ns
1, 5
Ref/Active to Ref/Active
command period
t RC
Trc
70
—
70
—
ns
1
Active to Precharge command
period
t RAS
Tras
50
120000
50
120000
ns
1
Active command to column
command (same bank)
t RCD
Trcd
20
—
20
—
ns
1
Precharge to active command
period
t RP
Trp
20
—
20
—
ns
1
Write recovery or data-in to
precharge lead time
t DPL
Tdpl
10
—
10
—
ns
1
Active (a) to Active (b)
command period
t RRD
Trrd
20
—
20
—
ns
1
Transition time (rise and fall)
tT
1
5
1
5
ns
Refresh period
t REF
—
64
—
64
ms
Data-in setup time
t AS , t CS,
t DS, t CES
This Material Copyrighted by Its Respective Manufacturer
17
HB52D48GB-F
Notes: 1.
2.
3.
4.
5.
6.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is CL = 50 pF.
t LZ (min) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES define CKE setup time to CK rising edge except power down exit command.
t AS /tAH: Address, tCS/tCH: S, RE, CE, W, DQMB
t DS/tDH: Data-in, tCES/tCEH: CKE
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
I/O
2.0 V
0.8 V
CL
t
T
18 Material Copyrighted by Its Respective Manufacturer
This
tT
HB52D48GB-F
Relationship Between Frequency and Minimum Latency
HB52D48GB
Parameter
-A6F/A6FL/B6F/B6FL
Frequency (MHz)
100
tCK (ns)
HITACHI
Symbol
PC100
Symbol
10
Notes
Active command to column command
(same bank)
lRCD
2
1
Active command to active command
(same bank)
lRC
7
= [lRAS+ lRP]
1
Active command to precharge command
(same bank)
lRAS
5
1
Precharge command to active command
(same bank)
lRP
2
1
Write recovery or data-in to precharge
command (same bank)
lDPL
1
1
Active command to active command
(different bank)
lRRD
2
1
Self refresh exit time
lSREX
Tsrx
1
2
Last data in to active command
(Auto precharge, same bank)
lAPW
Tdal
4
= [lDPL + lRP]
Self refresh exit to command input
lSEC
7
= [lRC]
3
Precharge command to high impedance
(CE latency = 2)
lHZP
Troh
2
lHZP
Troh
3
(CE latency = 3)
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge (early precharge)
(CE latency = 2)
(CE latency = 3)
Tdpl
lAPR
1
lEP
–1
lEP
–2
Column command to column command
lCCD
Tccd
1
Write command to data in latency
lWCD
Tdwd
0
DQMB to data in
lDID
Tdqm
0
DQMB to data out
lDOD
Tdqz
2
CKE to CK disable
lCLE
Tcke
1
Register set to active command
lRSA
Tmrd
1
This Material Copyrighted by Its Respective Manufacturer
19
HB52D48GB-F
HB52D48GB
Parameter
-A6F/A6FL/B6F/B6FL
Frequency (MHz)
100
tCK (ns)
HITACHI
Symbol
S to command disable
lCDD
0
Power down exit to command input
lPEC
1
Burst stop to output valid data hold
(CE latency = 2)
lBSR
1
lBSR
2
lBSH
2
lBSH
3
lBSW
0
(CE latency = 3)
Burst stop to output high impedance
(CE latency = 2)
(CE latency = 3)
Burst stop to write data ignore
PC100
Symbol
10
Notes: 1. lRCD to l RRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP].
20 Material Copyrighted by Its Respective Manufacturer
This
Notes
HB52D48GB-F
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read
or write command cycle CK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BA) is
precharged.
A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0,
bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low,
bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3
is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down
mode, clock suspend mode and self refresh mode.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5264165F/HM5264805F/HM5264405F-75/A60/B60 datasheet.
This Material Copyrighted by Its Respective Manufacturer
21
HB52D48GB-F
Physical Outline
42.0 Max
Unit: mm
(38.0)
1
A
17.625
B
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
,,
3.5 Min
3.5 Min
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
Component area
,,,,,,,,,,,,,,,,,,,,,,
(front)
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
3.80 Max
1.0 Min
2.5 Min
15.0
30.0
1.0 Min
0.80 ± 0.08
35.50
0.875
37.0 ± 0.08
35.50
17.875
R1.0 ± 0.1
0.625
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
Component area
,,,,,,,,,,,,,,,,,,,,,,
(back)
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,
1.0 Min
4.0 ± 0.1
2
4-R1.0 ± 0.1
1.0 Min
Detail B
Detail A
0.37 ± 0.03
1.0 ± 0.08
22 Material Copyrighted by Its Respective Manufacturer
This
0.25 Max
5.0 ± 0.1
2.00 Min
0.50
HB52D48GB-F
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan)
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/index.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
This Material Copyrighted by Its Respective Manufacturer
23
HB52D48GB-F
Revision Record
Rev. Date
0.0
Contents of Modification
Jan. 13, 2000 Initial issue
(referred to HM5264165F/HM5264805F/HM5264405F75/A60/B60 rev 1.0)
24 Material Copyrighted by Its Respective Manufacturer
This
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