HB52F168GB-B HB52D168GB-B EO 128 MB Unbuffered SDRAM Micro DIMM 16-Mword × 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M × 16 components) PC133/100 SDRAM L E0008H10 (1st edition) (Previous ADE-203-1219A (Z)) Jan. 19, 2001 Description Pr The HB52F168GB and HB52D168GB are a 16M × 64 × 1 banks Synchronous Dynamic RAM Micro Dual In-line Memory Module (Micro DIMM), mounted 4 pieces of 256-Mbit SDRAM (HM5225165BTT) sealed in TSOP package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TSOP on the module board. od Features t uc • 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 38.00 mm (Length) × 30.00 mm (Height) × 3.80 mm (Thickness) Lead pitch: 0.50 mm • 3.3 V power supply • Clock frequency: 133/100 MHz (max) • LVTTL interface • Data bus width: × 64 Non parity • Single pulsed RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length: 1/2/4/8 • 2 variations of burst sequence Sequential Interleave This product became EOL in September, 2002. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HB52F168GB-B, HB52D168GB-B • • • • EO Programmable CE latency: 2/3 Byte control by DQMB Refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh • Low self refresh current : HB52F168GB-xxBL : HB52D168GB-xxBL Ordering Information CE latency Package Contact pad HB52F168GB-75B* HB52F168GB-75BL* 1 133 MHz 133 MHz 3 3 Micro DIMM (144-pin) Gold HB52D168GB-A6B HB52D168GB-A6BL HB52D168GB-B6B* 2 HB52D168GB-B6BL* 2 100 MHz 100 MHz 100 MHz 100 MHz 2/3 2/3 3 3 L Frequency Type No. 1 Pr Notes: 1. 100 MHz operation at CE latency = 2. 2. 66 MHz operation at CE latency = 2. Pin Arrangement od Front Side 1pin 2pin 143pin 144pin Data Sheet E0008H10 2 t uc Back Side HB52F168GB-B, HB52D168GB-B Front side Back side Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 1 VSS 73 NC 2 VSS 74 CK1 3 DQ0 75 VSS 4 DQ32 76 VSS 5 DQ1 77 NC 6 DQ33 78 NC 7 DQ2 79 NC 8 DQ34 80 NC 9 DQ3 81 VCC 10 DQ35 82 VCC 11 VCC 83 DQ16 12 VCC 84 DQ48 13 DQ4 85 DQ17 14 DQ36 86 DQ49 15 DQ5 87 DQ18 16 DQ37 88 DQ50 17 DQ6 89 DQ19 18 DQ38 90 DQ51 19 DQ7 91 VSS 20 DQ39 92 VSS 21 VSS 93 DQ20 22 VSS 94 DQ52 23 DQMB0 95 DQ21 24 DQMB4 96 DQ53 25 DQMB1 97 DQ22 26 DQMB5 98 DQ54 27 VCC 99 29 A0 31 EO Pin No. L Pr 28 VCC 100 DQ55 101 VCC 30 A3 102 VCC A1 103 A6 32 A4 104 A7 33 A2 105 A8 34 A5 106 BA0 35 VSS 107 VSS 36 VSS 108 VSS 37 DQ8 109 A9 38 DQ40 110 BA1 39 DQ9 111 A10 (AP) 41 DQ10 113 VCC 43 DQ11 115 DQMB2 45 VCC 117 DQMB3 47 DQ12 119 VSS 49 DQ13 121 DQ24 51 DQ14 123 DQ25 53 DQ15 125 55 VSS 57 59 od DQ23 DQ41 112 A11 42 DQ42 114 VCC 44 DQ43 116 DQMB6 46 VCC 118 DQMB7 48 DQ44 120 VSS 50 DQ45 122 DQ56 52 DQ46 124 DQ57 DQ26 54 DQ47 126 DQ58 127 DQ27 56 VSS 128 DQ59 NC 129 VCC 58 NC 130 VCC NC 131 DQ28 60 NC 132 DQ60 t uc 40 Data Sheet E0008H10 3 HB52F168GB-B, HB52D168GB-B Front side Back side Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 61 CK0 133 DQ29 62 CKE0 134 DQ61 63 VCC 135 DQ30 64 VCC 136 DQ62 65 RE 137 DQ31 66 CE 138 DQ63 67 W 139 VSS 68 NC 140 VSS 69 S0 141 SDA 70 A12 142 SCL 71 NC 143 VCC 72 NC 144 VCC EO Pin No. Pin name A0 to A12 L Pin Description Function Address input Row address A0 to A12 Column address A0 to A8 DQ0 to DQ63 S0 RE CE W Pr BA0/BA1 Bank select address Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable od Byte input/output mask CK0/CK1 Clock input CKE0 Clock enable SDA Data-input/output for serial PD SCL Clock input for serial PD VCC Power supply VSS Ground NC No connection Data Sheet E0008H10 4 t uc DQMB0 to DQMB7 HB52F168GB-B, HB52D168GB-B Serial PD Matrix*1 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments EO Number of bytes used by module manufacturer 1 0 0 0 0 0 0 0 80 128 1 Total SPD memory size 0 0 0 0 1 0 0 0 08 256 byte 2 Memory type 0 0 0 0 0 1 0 0 04 SDRAM 3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13 4 Number of column addresses bits 0 0 0 0 1 0 0 1 09 9 5 Number of banks 0 0 0 0 0 0 0 1 01 1 6 Module data width 0 1 0 0 0 0 0 0 40 64 7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+) 8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL 9 0 1 1 1 0 1 0 1 75 CL = 3 L 0 SDRAM cycle time (highest CE latency) (-75) 7.5 ns 10 Pr (-A6/B6) 10 ns SDRAM access from Clock (highest CE latency) (-75) 5.4 ns (-A6/B6) 6 ns 1 0 1 0 0 0 0 0 A0 0 1 0 1 0 1 0 0 54 0 1 1 0 0 0 0 0 60 0 0 0 0 0 0 00 Module configuration type 0 0 12 Refresh rate/type 1 0 13 SDRAM width 0 0 14 Error checking SDRAM width 0 0 15 0 SDRAM device attributes: minimum clock delay for backto-back random column addresses 0 16 SDRAM device attributes: Burst lengths supported 0 17 SDRAM device attributes: number of banks on SDRAM device 18 19 od 11 Non parity 0 0 0 1 0 82 Normal (7.8125 µs) Self refresh 0 1 0 0 0 0 10 × 16 0 0 0 0 0 0 00 — 0 0 0 0 0 1 01 1 CLK 0 0 0 1 1 0 0 0 0 0 1 SDRAM device attributes: CE latency 0 0 0 0 0 1 SDRAM device attributes: S latency 0 0 0 0 0 0 t uc 0 1 1 0F 1, 2, 4, 8 0 0 04 4 1 0 06 2, 3 0 1 01 0 Data Sheet E0008H10 5 HB52F168GB-B, HB52D168GB-B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 20 0 0 0 0 0 0 0 1 01 0 SDRAM device attributes: W latency EO 21 SDRAM module attributes 0 0 0 0 0 0 0 0 00 Unbuffer 22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0E VCC ± 10% 23 SDRAM cycle time (2nd highest CE latency) (-75/A6) 10 ns 1 0 1 0 0 0 0 0 A0 CL = 2 1 1 1 1 0 0 0 0 F0 0 1 1 0 0 0 0 0 60 1 0 0 0 0 0 0 0 80 (-B6) 15 ns 24 L SDRAM access from Clock (2nd highest CE latency) (-75/A6) 6 ns (-B6) 8 ns SDRAM cycle time (3rd highest CE latency) Undefined 0 0 0 0 0 0 0 0 00 26 SDRAM access from Clock (3rd highest CE latency) Undefined 0 0 0 0 0 0 0 0 00 27 Minimum row precharge time 0 0 0 1 0 1 0 0 14 20 ns 28 Row active to row active min (-75) 0 0 0 0 1 1 1 1 0F 15 ns 0 0 0 1 0 1 0 0 14 20 ns 0 0 0 1 0 1 0 0 14 20 ns 0 0 1 0 1 1 0 1 2D 45 ns 0 0 1 1 0 0 1 0 32 50 ns 1 0 0 0 0 0 20 128M byte 0 1 0 1 0 1 15 1.5 ns (-A6/B6) 29 RE to CE delay min 30 Minimum RE pulse width (-75) (-A6/B6) Density of each bank on module 0 0 32 Address and command signal 0 input setup time (-75) 0 (-A6/B6) 33 0 0 1 0 0 0 Address and command signal 0 input hold time (-75) 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 (-A6/B6) 34 Data signal input setup time (-75) (-A6/B6) Data Sheet E0008H10 6 t uc 31 od Pr 25 0 0 20 2.0 ns 0 0 08 0.8 ns 0 0 10 1.0 ns 0 1 15 1.5 ns 0 0 20 2.0 ns HB52F168GB-B, HB52D168GB-B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 35 0 0 0 0 1 0 0 0 08 0.8 ns 0 0 0 1 0 0 0 0 10 1.0 ns 36 to 61 Superset information 0 0 0 0 0 0 0 0 00 Future use 62 SPD data revision code 0 0 0 1 0 0 1 0 12 Rev. 1.2B 63 Checksum for bytes 0 to 62 (-75) 0 0 1 1 1 0 0 1 39 57 (-A6) 1 0 1 0 0 0 0 0 A0 160 (-B6) 0 0 0 1 0 0 0 0 10 16 0 0 0 0 0 1 1 1 07 HITACHI 65 to 71 Manuf act urer’s JEDEC ID c ode 0 0 0 0 0 0 0 0 00 72 Manufacturing location × × × × × × × × ×× * 2 (ASCII8bit code) 73 Manufacturer’s part number 0 1 0 0 1 0 0 0 48 H 74 Manufacturer’s part number 0 1 0 0 0 0 1 0 42 B 75 Manufacturer’s part number 0 0 1 1 0 1 0 1 35 5 76 Manufacturer’s part number 0 0 1 1 0 0 1 0 32 2 77 Manufacturer’s part number (-75) 0 1 0 0 0 1 1 0 46 F 0 1 0 0 0 1 0 0 44 D 1 1 0 0 0 1 31 1 od Data signal input hold time (-75) EO (-A6/B6) 64 Manuf act urer’s JEDEC ID c ode L Pr (-A6/B6) 78 Manufacturer’s part number 0 0 79 Manufacturer’s part number 0 0 80 Manufacturer’s part number 0 0 81 Manufacturer’s part number 0 1 82 Manufacturer’s part number 0 1 83 Manufacturer’s part number 0 0 84 Manufacturer’s part number (-75) 0 0 (-A6) 0 (-B6) Manufacturer’s part number (-75) (-A6/B6) 1 0 1 1 0 36 6 1 1 1 0 0 0 38 8 0 0 0 1 1 1 47 G 0 0 0 0 1 0 42 B 1 0 1 1 0 1 2D — 1 1 0 1 1 1 37 7 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 86 Manufacturer’s part number 0 1 0 0 0 0 87 Manufacturer’s part number (L-version) 0 1 0 0 1 1 Manufacturer’s part number 0 0 1 0 0 0 Manufacturer’s part number 0 0 1 0 0 0 88 t uc 85 1 0 1 41 A 1 0 42 B 0 1 35 5 1 0 36 6 1 0 42 B 0 0 4C L 0 0 20 (Space) 0 0 20 (Space) Data Sheet E0008H10 7 HB52F168GB-B, HB52D168GB-B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 89 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 90 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 91 Revision code 0 0 1 1 0 0 0 0 30 Initial 92 Revision code 0 0 1 0 0 0 0 0 20 (Space) 93 Manufacturing date × × × × × × × × ×× Year code (BCD) 94 Manufacturing date × × × × × × × × ×× Week code (BCD) EO Byte No. Function described 95 to 98 Assembly serial number *3 99 to 125 Manufacturer specific data — — — — — — — — — *4 L 126 Intel specification frequency 0 1 1 0 0 1 0 0 64 100 MHz 127 Intel specification CE# latency 1 support (-75/A6) 1 0 0 0 1 1 1 C7 CL = 2, 3 1 0 0 0 1 0 1 C5 CL = 3 (-B6) 1 t uc od Pr Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These SPD are based on Rev. 1.2B Specification. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined (“1” or “0”). Data Sheet E0008H10 8 HB52F168GB-B, HB52D168GB-B Block Diagram EO S0 W CS DQMB0 8 N8, N9 DQ0 to DQ7 DQ32 to DQ39 D0 D2 DQMB1 DQMB5 8 N2, N3 8 N10, N11 DQ8 to DQ15 DQ40 to DQ47 L DQMB2 CS 8 N12, N13 DQ16 to DQ23 DQ48 to DQ55 D1 D3 DQMB3 DQMB7 8 N6, N7 8 N14, N15 Pr DQ56 to DQ63 RAS (D0 to D3) RE CE CAS (D0 to D3) A0 to A12 (D0 to D3) A0 to A12 BA0 (D0 to D3) BA1 BA1 (D0 to D3) CKE0 CKE (D0 to D3) CLK (D0) CLK (D1) CK0 CLK (D2) R0 CK1 C200 VCC VCC (D0 to D3, U0) C0-C7 VSS SDA SCL A0 SDA U0 A1 C100-C103 VSS (D0 to D3, U0) A2 VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. t uc CLK (D3) SCL Serial PD od BA0 CS DQMB6 8 N4, N5 DQ24 to DQ31 CS DQMB4 8 N0, N1 * D0 to D3: HM5225165 U0: 2-kbit EEPROM C0 to C7: 0.33 µF C100 to C103: 0.1 µF C200: 10 pF N0 to N15: Network resistors (10 Ω) R0: Resistor (10 Ω) Data Sheet E0008H10 9 HB52F168GB-B, HB52D168GB-B Absolute Maximum Ratings Parameter Value Unit Note Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 (max)) V 1 Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation PT 4.0 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –55 to +125 °C EO Symbol Note: 1. Respect to V SS . L DC Operating Conditions (Ta = 0 to +65°C) Parameter Supply voltage Input low voltage Max Unit Notes VCC 3.0 3.6 V 1, 2 VSS 0 0 V 3 VIH 2.0 VCC + 0.3 V 1, 4 VIL –0.3 0.8 V 1, 5 All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC. VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS . t uc od Notes: 1. 2. 3. 4. 5. Min Pr Input high voltage Symbol Data Sheet E0008H10 10 HB52F168GB-B, HB52D168GB-B DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) HB52F168GB-B/HB52D168GB-B EO -75 -A6/B6 Symbol Min Max Min Max Unit Test conditions Notes Operating current (CE latency = 2) I CC1 — 400 — 400 mA Burst length = 1 t RC = min 1, 2, 3 (CE latency = 3) I CC1 — 460 400 mA Standby current in power down I CC2P — 12 — 12 mA CKE0 = VIL, t CK = 12 ns 6 Standby current in power down (input signal stable) I CC2PS — 8 — 8 mA CKE0 = VIL, t CK = ∞ 7 Standby current in non power down I CC2N — 80 — 80 mA CKE0, S = VIH, t CK = 12 ns 4 Active standby current in power down I CC3P — 16 — 16 mA CKE0, S = VIH, t CK = 12 ns 1, 2, 6 Active standby current in non power down I CC3N — 120 — 120 mA CKE0, S = VIH, t CK = 12 ns 1, 2, 4 Burst operating current (CE latency = 2) I CC4 — 440 440 mA t CK = min, BL = 4 1, 2, 5 I CC4 — 580 440 mA Refresh current I CC5 — 880 — 880 mA t RC = min 3 Self refresh current I CC6 — 12 — 12 mA VIH ≥ VCC – 0.2 V VIL ≤ 0.2 V 8 Self refresh current (L-version) I CC6 — 8 Input leakage current I LI –10 Output leakage current I LO Output high voltage Output low voltage L Parameter Pr (CE latency = 3) — od — 8 mA 10 –10 10 µA 0 ≤ Vin ≤ VCC –10 10 –10 10 µA 0 ≤ Vout ≤ VCC DQ = disable VOH 2.4 — 2.4 — V I OH = –4 mA VOL — 0.4 — 0.4 V I OL = 4 mA t uc Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current. Data Sheet E0008H10 11 HB52F168GB-B, HB52D168GB-B Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Max Unit Notes Input capacitance (Address) CIN 40 pF 1, 2, 4 Input capacitance (RE, CE, W, CK0/CK1, CKE0) CIN 40 pF 1, 2, 4 Input capacitance (S0) CIN 40 pF 1, 2, 4 Input capacitance (DQMB0 to DQMB7) CIN 20 pF 1, 2, 4 Input/Output capacitance (DQ0 to DQ63) CI/O 20 pF 1, 2, 3, 4 EO Symbol Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested. L Notes: 1. 2. 3. 4. t uc od Pr Data Sheet E0008H10 12 HB52F168GB-B, HB52D168GB-B AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) EO HB52F168GB-B/HB52D168GB-B -75 -A6 -B6 Symbol PC100 Symbol Min Max Min Max Min Max Unit Notes System clock cycle time (CE latency = 2) t CK Tclk 10 — 10 — 15 — ns 1 (CE latency = 3) t CK Tclk 7.5 — 10 — 10 — ns CK high pulse width (CE latency = 2) t CKH Tch 3 — 3 — 3 — ns (CE latency = 3) t CKH Tch 2.5 — 3 — 3 — ns CK low pulse width (CE latency = 2) t CKL Tcl 3 — 3 — 3 — ns (CE latency = 3) t CKL Tcl 2.5 — 3 — 3 — ns Access time from CK (CE latency = 2) t AC Tac — 6 — 6 — 8 ns (CE latency = 3) t AC Data-out hold time (CE latency = 2) t OH (CE latency = 3) t OH CK to Data-out low impedance t LZ CK to Data-out high impedance (CE latency = 2) t HZ — (CE latency = 3) t HZ — L Parameter 1 1 1, 2 — 5.4 — 6 — 6 ns Toh 3 — 3 — 3 — ns 1, 2 Toh 2.7 — 3 — 3 — ns 1, 2 2 — 2 — 2 — ns 1, 2, 3 od Pr Tac 1, 4 6 — 6 — 6 ns 5.4 — 6 — 6 ns — 2 — 2 — ns — 2 — 2 — ns t AS , t CS, t DS, t CES Tsi 2 (CE latency = 3) t AS , t CS, t DS, t CES Tsi 1.5 CKE setup time for power down exit (CE latency = 2) t CESP Tpde 2 — 2 — (CE latency = 3) t CESP Tpde 1.5 — 2 — Data-in hold time (CE latency = 2) t AH, t CH, t DH, t CEH Thi 1 — 1 — (CE latency = 3) t AH, t CH, t DH, t CEH Thi 0.8 — 1 — 1, 5, 6 t uc Data-in setup time (CE latency = 2) 2 — ns 2 — ns 1 — ns 1 — ns 1 1, 5 Data Sheet E0008H10 13 HB52F168GB-B, HB52D168GB-B HB52F168GB-B/HB52D168GB-B -75 -A6 -B6 Symbol PC100 Symbol Min Max Min Max Min Max Unit Notes Ref/Active to Ref/Active command period (CE latency = 2) t RC Trc 70 — 70 — 70 — ns 1 (CE latency = 3) t RC Trc 67.5 — 70 — 70 — ns Active to Precharge command period (CE latency = 2) t RAS Tras 50 120000 50 120000 50 120000 ns (CE latency = 3) t RAS Tras 45 120000 50 120000 50 120000 ns EO Parameter 1 L t RCD Trcd 20 — 20 — 20 — ns 1 Precharge to active command period t RP Trp 20 — 20 — 20 — ns 1 Tdpl 20 — 20 — 20 — ns 1 Tdpl 15 — 20 — 20 — ns Trrd 20 — 20 — 20 — ns Trrd 15 — 20 — 20 — ns 5 1 5 1 5 ns 64 — 64 — 64 ms Write recovery or data-in t DPL to precharge lead time (CE latency = 2) (CE latency = 3) Active (a) to Active (b) command period (CE latency = 2) t RRD t RRD Transition time (rise and fall) tT 1 Refresh period t REF — AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command. Data Sheet E0008H10 14 1 t uc Notes: 1. 2. 3. 4. 5. od (CE latency = 3) t DPL Pr Active command to column command (same bank) HB52F168GB-B, HB52D168GB-B Test Conditions EO • Input and output timing reference levels: 1.5 V • Input waveform and output load: See following figures 2.4 V input 0.4 V DQ 2.0 V 0.8 V CL t T tT L t uc od Pr Data Sheet E0008H10 15 HB52F168GB-B, HB52D168GB-B Relationship Between Frequency and Minimum Latency HB52F168GB-B/HB52D168GB-B EO Parameter 133 100 Frequency (MHz) CE latency = 3 CE latency = 2 PC100 Symbol Symbol 7.5 10 Notes Active command to column command (same bank) I RCD 3 2 1 Active command to active command (same bank) I RC 9 7 = [IRAS + IRP] 1 Active command to precharge command I RAS (same bank) 6 5 1 Precharge command to active command I RP (same bank) 3 2 1 2 2 1 2 2 1 tCK (ns) L I DPL Tdpl Active command to active command (different bank) I RRD Self refresh exit time I SREX Tsrx 1 1 2 Last data in to active command (Auto precharge, same bank) I APW Tdal 5 4 = [IDPL + IRP] Self refresh exit to command input I SEC 9 7 = [IRC] 3 Precharge command to high impedance I HZP Last data out to active command (auto precharge) (same bank) I APR Last data out to precharge (early precharge) I EP Column command to column command I CCD Write command to data in latency I WCD DQMB to data in I DID DQMB to data out od Pr Write recovery or data-in to precharge command (same bank) Troh 2 1 1 –2 –1 Tccd 1 1 Tdwd 0 0 Tdqm 0 0 I DOD Tdqz 2 CKE to CK disable I CLE Tcke 1 Register set to active command I RSA Tmrd 1 S to command disable I CDD 0 Power down exit to command input I PEC 1 Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP] Data Sheet E0008H10 16 t uc 3 2 1 1 0 1 HB52F168GB-B, HB52D168GB-B Pin Functions EO CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. L A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1(BA) is precharged. Pr BA0/BA1 (input pin): BA0/BA1 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is Low and BA1 is High, bank1 is selected. If BA0 is High and BA1 is Low, bank2 is selected. If BA0 is High and BA1 is High, bank3 is selected. od CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VSS (power supply pins): Ground is connected. Detailed Operation Part Refer to the SDRAM DIMM Operation Guide. t uc VCC (power supply pins): 3.3 V is applied. Data Sheet E0008H10 17 HB52F168GB-B, HB52D168GB-B Physical Outline EO (38.0) 1 A 17.625 3.80 Max B ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; 3.5 Min 1.0 Min 3.5 Min ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;; (front) ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; L 15.0 Unit: mm 2.5 Min 30.0 1.0 Min 42.0 Max 0.80 ± 0.08 35.50 0.875 Pr 37.0 ± 0.08 35.50 17.875 2 4-R1.0 ± 0.1 1.0 Min od ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;; (back) ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; 0.625 4.0 ± 0.1 R1.0 ± 0.1 1.0 Min t uc Detail B Detail A 0.37 ± 0.03 1.0 ± 0.08 Data Sheet E0008H10 18 0.25 Max 5.0 ± 0.1 2.00 Min 0.50 HB52F168GB-B, HB52D168GB-B Cautions EO 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. L t uc od Pr Data Sheet E0008H10 19