HB52F648EN-75B, HB52F649EN-75B 512 MB Unbuffered SDRAM DIMM, 133 MHz Memory Bus (HB52F648EN) 64-Mword × 64-bit, 2-Bank Module (16 pcs of 32 M × 8 Components) (HB52F649EN) 64-Mword × 72-bit, 2-Bank Module (18 pcs of 32 M × 8 Components) PC133 SDRAM E0012H10 (1st edition) (Previous ADE-203-1115A (Z)) Preliminary Jan. 17, 2001 Description The HB52F648EN, HB52F649EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and have been developed as an optimized main memory solution for 8-byte processor applications. They are synchronous Dynamic RAM Module, mounted 256-Mbit SDRAMs (HM5225805BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). The HB52F648EN is organized 32M × 64 × 2-bank mounted 16 pieces of 256-Mbit SDRAM. The HB52F649EN is organized 32M × 72× 2-bank mounted 18 pieces of 256-Mbit SDRAM. An outline of the products is 168-pin socket type package (dual lead out). Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. Features • Fully compatible with : JEDEC standard outline 8-byte DIMM • 168-pin socket type package (dual lead out) Outline: 133.37 mm (Length) × 34.925 mm (Height) × 4.00 mm (Thickness) Lead pitch: 1.27 mm • 3.3 V power supply • Clock frequency: 133 MHz (max) • LVTTL interface Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Elpida Memory, Inc. regarding specification. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HB52F648EN/HB52F649EN-75B • Data bus width : × 64 Non parity (HB52F648EN) : × 72 ECC (HB52F649EN) • Single pulsed RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length: 1/2/4/8 • 2 variations of burst sequence Sequential Interleave • Programmable CE latency : 3 (133 MHz) : 2 (100 MHz) • Byte control by DQMB • Refresh cycles: 8192 refresh cycles/64 ms • 2 variations of refresh Auto refresh Self refresh Ordering Information CE latency Package Contact pad 1 3 168-pin dual lead out socket type Gold 1 3 Type No. Frequency HB52F648EN-75B* 133 MHz HB52F649EN-75B* 133 MHz Note: 1. 100 MHz operation at CE latency = 2. Pin Arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 85 pin 94 pin 95 pin 124 pin 125 pin Preliminary Data Sheet E0012H10 2 84 pin 168 pin HB52F648EN/HB52F649EN-75B (HB52F648EN) Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 NC 86 DQ32 128 CKE0 3 DQ1 45 S2 87 DQ33 129 NC (S3)*2 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VCC 48 NC 90 VCC 132 NC 7 DQ4 49 VCC 91 DQ36 133 VCC 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC 94 DQ39 136 NC 11 DQ8 53 NC 95 DQ40 137 NC 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VCC 101 DQ45 143 VCC 18 VCC 60 DQ20 102 VCC 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 NC (CKE1)*1 105 NC 147 NC 22 NC 64 VSS 106 NC 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 VCC 68 VSS 110 VCC 152 VSS 27 W 69 DQ24 111 CE 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 156 DQ59 30 S0 72 DQ27 114 NC (S1)* 3 Preliminary Data Sheet E0012H10 3 HB52F648EN/HB52F649EN-75B Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 31 NC 73 VCC 115 RE 157 VCC 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CK2 121 A9 163 CK3 38 A10 (AP) 80 NC 122 BA0 164 NC 39 BA1 81 WP 123 A11 165 SA0 40 VCC 82 SDA 124 VCC 166 SA1 41 VCC 83 SCL 125 CK1 167 SA2 42 CK0 84 VCC 126 A12 168 VCC Notes: 1. CKE1: HB52F648EN 2. S3: HB52F648EN 3. S1: HB52F648EN Preliminary Data Sheet E0012H10 4 HB52F648EN/HB52F649EN-75B (HB52F649EN) Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 NC 86 DQ32 128 CKE0 3 DQ1 45 S2 87 DQ33 129 NC (S3)*2 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VCC 48 NC 90 VCC 132 NC 7 DQ4 49 VCC 91 DQ36 133 VCC 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VCC 101 DQ45 143 VCC 18 VCC 60 DQ20 102 VCC 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 1 21 CB0 63 NC (CKE1)* 105 CB4 147 NC 22 CB1 64 VSS 106 CB5 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 VCC 68 VSS 110 VCC 152 VSS 27 W 69 DQ24 111 CE 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 156 DQ59 3 30 S0 72 DQ27 114 NC (S1)* 31 NC 73 VCC 115 RE 157 VCC 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 Preliminary Data Sheet E0012H10 5 HB52F648EN/HB52F649EN-75B Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CK2 121 A9 163 CK3 38 A10 (AP) 80 NC 122 BA0 164 NC 39 BA1 81 WP 123 A11 165 SA0 40 VCC 82 SDA 124 VCC 166 SA1 41 VCC 83 SCL 125 CK1 167 SA2 42 CK0 84 VCC 126 A12 168 VCC Notes: 1. CKE1: HB52F649EN 2. S3: HB52F649EN 3. S1: HB52F649EN Pin Description (HB52F648EN) Pin name Function A0 to A12 Address input Row address A0 to A12 Column address A0 to A9 BA0/BA1 Bank select address DQ0 to DQ63 Data input/output S0 to S3 Chip select input RE Row enable (RAS) input CE Column enable (CAS) input W Write enable input DQMB0 to DQMB7 Byte data mask CK0 to CK3 Clock input CKE0, CKE1 Clock enable input WP Write protect for serial PD SDA Data input/output for serial PD SCL Clock input for serial PD SA0 to SA2 Serial address input VCC Primary positive power supply VSS Ground NC No connection Preliminary Data Sheet E0012H10 6 HB52F648EN/HB52F649EN-75B Pin Description (HB52F649EN) Pin name Function A0 to A12 Address input Row address A0 to A12 Column address A0 to A9 BA0/BA1 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output) S0 to S3 Chip select input RE Row enable (RAS) input CE Column enable (CAS) input W Write enable input DQMB0 to DQMB7 Byte data mask CK0 to CK3 Clock input CKE0, CKE1 Clock enable input WP Write protect for serial PD SDA Data input/output for serial PD SCL Clock input for serial PD SA0 to SA2 Serial address input VCC Primary positive power supply VSS Ground NC No connection Preliminary Data Sheet E0012H10 7 HB52F648EN/HB52F649EN-75B Serial PD Matrix*1 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 Number of bytes used by module manufacturer 1 0 0 0 0 0 0 0 80 128 1 Total SPD memory size 0 0 0 0 1 0 0 0 08 256 byte 2 Memory type 0 0 0 0 0 1 0 0 04 SDRAM 3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13 4 Number of column addresses bits 0 0 0 0 1 0 1 0 0A 10 5 Number of banks 0 0 0 0 0 0 1 0 02 2 6 Module data width (HB52F648EN) 0 1 0 0 0 0 0 0 40 64 (HB52F649EN) 0 1 0 0 1 0 0 0 48 72 7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+) 8 Module int erf ac e signal lev els 0 0 0 0 0 0 0 1 01 LVTTL 9 SDRAM cycle time (highest CE latency) 7.5 ns 0 1 1 1 0 1 0 1 75 CL = 3 10 SDRAM access from Clock (highest CE latency) 5.4 ns 0 1 0 1 0 1 0 0 54 11 Module configuration type (HB52F648EN) 0 0 0 0 0 0 0 0 00 Non parity (HB52F649EN) 0 0 0 0 0 0 1 0 02 ECC 12 Refresh rate/type 1 0 0 0 0 0 1 0 82 Normal (7.8125 µs) Self refresh 13 SDRAM width 0 0 0 0 1 0 0 0 08 32M × 8 14 Error checking SDRAM width (HB52F648EN) 0 0 0 0 0 0 0 0 00 — (HB52F649EN) 0 0 0 0 1 0 0 0 08 ×8 0 0 0 0 0 0 1 01 1 CLK 0 0 0 1 1 1 1 0F 1, 2, 4, 8 15 SDRAM device attributes: minimum clock delay for back-to-back random column addresses 0 16 SDRAM device attributes: Burst lengths supported 0 Preliminary Data Sheet E0012H10 8 HB52F648EN/HB52F649EN-75B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 17 SDRAM device attributes: 0 number of banks on SDRAM device 0 0 0 0 1 0 0 04 4 18 SDRAM device attributes: CE latency 0 0 0 0 0 1 1 0 06 2, 3 19 SDRAM device attributes: S latency 0 0 0 0 0 0 0 1 01 0 20 SDRAM device attributes: W latency 0 0 0 0 0 0 0 1 01 0 21 SDRAM module attributes 0 0 0 0 0 0 0 0 00 Non buffer 22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0E VCC ± 10% 23 SDRAM cycle time (2nd highest CE latency) 10 ns 1 0 1 0 0 0 0 0 A0 CL = 2 24 SDRAM access from Clock (2nd highest CE latency) 6 ns 0 1 1 0 0 0 0 0 60 25 SDRAM cycle time (3rd highest CE latency) Undefined 0 0 0 0 0 0 0 0 00 26 SDRAM access from Clock (3rd highest CE latency) Undefined 0 0 0 0 0 0 0 0 00 27 Minimum row precharge time 0 0 0 1 0 1 0 0 14 20 ns 28 Row active to row active min 0 0 0 0 1 1 1 1 0F 15 ns 29 RE to CE delay min 0 0 0 1 0 1 0 0 14 20 ns 30 Minimum RE pulse width 0 0 1 0 1 1 0 1 2D 45 ns 31 Density of each bank on module 0 1 0 0 0 0 0 0 40 2 bank 256 M byte 32 Address and command signal input setup time 0 0 0 1 0 1 0 1 15 1.5 ns 33 Address and command signal input hold time 0 0 0 0 1 0 0 0 08 0.8 ns 34 Data signal input setup time 0 0 0 1 0 1 0 1 15 1.5 ns 35 Data signal input hold time 0 0 0 0 1 0 0 0 08 0.8 ns 36 to 61 Superset information 0 0 0 0 0 0 0 0 00 Future use 62 0 0 0 0 0 0 1 0 02 JEDEC2 SPD data revision code Preliminary Data Sheet E0012H10 9 HB52F648EN/HB52F649EN-75B Byte No. Function described 63 Checksum for bytes 0 to 62 (HB52F648EN) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 1 0 0 0 0 1 1 43 67 0 1 0 1 0 1 0 1 55 85 Manuf ac t urer’s JEDEC ID c ode 0 0 0 0 0 1 1 1 07 HITACHI 65 to 71 Manuf ac t urer’s JEDEC ID c ode 0 0 0 0 0 0 0 0 00 72 Manufacturing location × × × × × × × × ×× * 2 (ASCII8bit code) 73 Manufacturer’s part number 0 1 0 0 1 0 0 0 48 H 74 Manufacturer’s part number 0 1 0 0 0 0 1 0 42 B 75 Manufacturer’s part number 0 0 1 1 0 1 0 1 35 5 76 Manufacturer’s part number 0 0 1 1 0 0 1 0 32 2 77 Manufacturer’s part number 0 1 0 0 0 1 1 0 46 F 78 Manufacturer’s part number 0 0 1 1 0 1 1 0 36 6 79 Manufacturer’s part number 0 0 1 1 0 1 0 0 34 4 80 Manufacturer’s part number (HB52F648EN) 0 0 1 1 1 0 0 0 38 8 0 0 1 1 1 0 0 1 39 9 (HB52F649EN) 64 (HB52F649EN) 81 Manufacturer’s part number 0 1 0 0 0 1 0 1 45 E 82 Manufacturer’s part number 0 1 0 0 1 1 1 0 4E N 83 Manufacturer’s part number 0 0 1 0 1 1 0 1 2D — 84 Manufacturer’s part number 0 0 1 1 0 1 1 1 37 7 85 Manufacturer’s part number 0 0 1 1 0 1 0 1 35 5 86 Manufacturer’s part number 0 1 0 0 0 0 1 0 42 B 87 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 88 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 89 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 90 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) Preliminary Data Sheet E0012H10 10 HB52F648EN/HB52F649EN-75B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 91 Revision code 0 0 1 1 0 0 0 0 30 Initial 92 Revision code 0 0 1 0 0 0 0 0 20 (Space) 93 Manufacturing date × × × × × × × × ×× Year code (BCD) 94 Manufacturing date × × × × × × × × ×× Week code (BCD) — — — — — — — — *4 95 to 98 Assembly serial number *3 99 to 125 Manufacturer specific data — 126 Reserved (Intel specification 0 frequency) 1 1 0 0 1 0 0 64 127 Reserved (Intel specification 1 CE# latency support) 1 1 1 1 1 1 1 FF Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined (“1” or “0”). Preliminary Data Sheet E0012H10 11 HB52F648EN/HB52F649EN-75B Block Diagram (HB52F648EN) A0 to A12, BA0, BA1 RE, CE, W S1 S0 CS DQM DQMB0 DQ0 to DQ7 8 10 Ω DQMB1 DQ8 to DQ15 8 10 Ω CS CS D0 DQM D8 I/O0 to I/O7 I/O0 to I/O7 8 DQ32 to DQ39 CS DQM CS DQM DQMB5 D1 I/O0 to I/O7 D9 I/O0 to I/O7 DQM DQMB4 8 DQ40 to DQ47 10 Ω 10 Ω CS D4 DQM I/O0 to I/O7 I/O0 to I/O7 CS DQM CS DQM D5 I/O0 to I/O7 D12 D13 I/O0 to I/O7 S3 S2 CS DQM DQMB2 DQ16 to DQ23 8 10 Ω DQMB3 DQ24 to DQ31 8 10 Ω 10 Ω CK0 CS D2 DQM CS D10 I/O0 to I/O7 I/O0 to I/O7 8 DQ48 to DQ55 CS DQM CS DQM DQMB7 I/O0 to I/O7 D3 I/O0 to I/O7 D11 DQM DQMB6 8 DQ56 to DQ63 10 Ω 10 Ω CS D6 I/O0 to I/O7 I/O0 to I/O7 CS DQM CS DQM D7 I/O0 to I/O7 VCC 0.33 µF CLK; 4 SDRAMs + 3.3 pF cap × 16 pcs VSS DQM D14 D15 I/O0 to I/O7 VCC (D0 to D15, U0) 0.1 µF × 16 pcs VSS (D0 to D15, U0) 10 Ω CK1 CLK; 4 SDRAMs + 3.3 pF cap CKE0 CKE (D0 to D7) 10 Ω CK2 CLK; 4 SDRAMs + 3.3 pF cap 10 Ω CK3 10 kΩ CKE1 CLK; 4 SDRAMs + 3.3 pF cap CKE (D8 to D15) Serial PD SCL SCL SDA SDA U0 A0 A1 A2 WP 47 kΩ SA0 SA1 SA2 VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D15: HM5225805 U0: 2-kbit EEPROM Preliminary Data Sheet E0012H10 12 HB52F648EN/HB52F649EN-75B Block Diagram (HB52F649EN) A0 to A12, BA0, BA1 RE, CE, W S1 S0 8 10 Ω DQ0 to DQ7 DQMB1 DQ8 to DQ15 8 10 Ω 8 10 Ω CB0 to CB7 CS CS CS DQM DQMB0 D0 DQM D9 I/O0 to I/O7 I/O0 to I/O7 8 DQ32 to DQ39 CS DQM CS DQM DQMB5 D1 I/O0 to I/O7 I/O0 to I/O7 CS DQM CS D2 I/O0 to I/O7 D10 DQM DQMB4 8 DQ40 to DQ47 10 Ω 10 Ω CS DQM D5 I/O0 to I/O7 I/O0 to I/O7 CS DQM CS DQM D6 I/O0 to I/O7 D14 D15 I/O0 to I/O7 DQM D11 I/O0 to I/O7 S3 S2 CS DQM DQMB2 DQ16 to DQ23 8 10 Ω DQMB3 DQ24 to DQ31 8 10 Ω CS D3 DQM CS D12 I/O0 to I/O7 I/O0 to I/O7 8 DQ48 to DQ55 CS DQM CS DQM DQMB7 I/O0 to I/O7 D4 D13 I/O0 to I/O7 CLK (5 SDRAMs) 10 Ω CK1 8 DQ56 to DQ63 10 Ω 10 Ω I/O0 to I/O7 CS DQM CS DQM D8 D17 I/O0 to I/O7 VCC (D0 to D17, U0) VSS (D0 to D17, U0) CKE0 CKE (D0 to D8) VCC 10 kΩ CLK (4 SDRAMs + 3.3 pF cap) CKE1 10 Ω CK3 D16 0.1 µF × 18 pcs 10 Ω CK2 D7 I/O0 to I/O7 0.33 µF × 18 pcs VSS CLK (5 SDRAMs) CS DQM I/O0 to I/O7 VCC 10 Ω CK0 DQM DQMB6 CKE (D9 to D17) Serial PD CLK (4 SDRAMs + 3.3 pF cap) SCL SCL SDA SDA U0 A0 A1 A2 WP 47 kΩ VSS SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D17: HM5225805 U0: 2-kbit EEPROM Preliminary Data Sheet E0012H10 13 HB52F648EN/HB52F649EN-75B Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 (max)) V 1 Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation (HB52F648EN) PT 8.0 W Power dissipation (HB52F649EN) PT 9.0 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –55 to +125 °C Note: 1. Respect to V SS DC Operating Conditions (Ta = 0 to +65°C) Parameter Symbol Min Max Unit Notes Supply voltage VCC 3.0 3.6 V 1, 2 VSS 0 0 V 3 Input high voltage VIH 2.0 VCC + 0.3 V 1, 4 Input low voltage VIL –0.3 0.8 V 1, 5 Notes: 1. 2. 3. 4. 5. All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulth width ≤ 3 ns at VCC. VIL (min) = VSS – 2.0 V for pulth width ≤ 3 ns at VSS . Preliminary Data Sheet E0012H10 14 HB52F648EN/HB52F649EN-75B VIL/VIH Clamp (Component characteristic) This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins. Minimum VIL Clamp Current VIL (V) I (mA) –2 –32 –1.8 –25 –1.6 –19 –1.4 –13 –1.2 –8 –1 –4 –0.9 –2 –0.8 –0.6 –0.6 0 –0.4 0 –0.2 0 0 0 0 –5 –2 –1.5 –1 –0.5 0 I (mA) –10 –15 –20 –25 –30 –35 VIL (V) Preliminary Data Sheet E0012H10 15 HB52F648EN/HB52F649EN-75B Minimum VIH Clamp Current VIH (V) I (mA) VCC + 2 10 VCC + 1.8 8 VCC + 1.6 5.5 VCC + 1.4 3.5 VCC + 1.2 1.5 VCC + 1 0.3 VCC + 0.8 0 VCC + 0.6 0 VCC + 0.4 0 VCC + 0.2 0 VCC + 0 0 10 I (mA) 8 6 4 2 0 VCC + 0 VCC + 0.5 VCC + 1 VIH (V) Preliminary Data Sheet E0012H10 16 VCC + 1.5 VCC + 2 HB52F648EN/HB52F649EN-75B IOL/IOH Characteristics (Component characteristic) Output Low Current (IOL) I OL I OL Vout (V) Min (mA) Max (mA) 0 0 0 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 250 IOL (mA) 200 150 min max 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Vout (V) Preliminary Data Sheet E0012H10 17 HB52F648EN/HB52F649EN-75B Output High Current (I OH ) (Ta = 0 to 65˚C, V CC = 3.0 V to 3.45 V, VSS = 0 V) I OH I OH Vout (V) Min (mA) Max (mA) 3.45 — –3 3.3 — –28 3 0 –75 2.6 –21 –130 2.4 –34 –154 2 –59 –197 1.8 –67 –227 1.65 –73 –248 1.5 –78 –270 1.4 –81 –285 1 –89 –345 0 –93 –503 0 0 0.5 1 1.5 2 2.5 3 3.5 IOH (mA) –100 –200 min max –300 –400 –500 –600 Vout (V) Preliminary Data Sheet E0012H10 18 HB52F648EN/HB52F649EN-75B DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB52F648EN) HB52F648EN-75B PC133 CE latency = 3 PC100 CE latency = 2 Parameter Symbol Min Max Min Max Unit Test conditions Notes Operating current I CC1 — 1120 — 1120 mA Burst length = 1 t RC = min 1, 2, 3 Standby current in power down I CC2P — 48 — 48 mA CKE = VIL, t CK = 12 ns 6 Standby current in power down (input signal stable) I CC2PS — 32 — 32 mA CKE = VIL, t CK = ∞ 7 Standby current in non power down I CC2N — 320 — 320 mA CKE, S = VIH, t CK = 12 ns 4 Active standby current in power down I CC3P — 64 — 64 mA CKE = VIL, t CK = 12 ns 1, 2, 6 Active standby current in non power down I CC3N — 480 — 480 mA CKE, S = VIH, t CK = 12 ns 1, 2, 4 Burst operating current I CC4 — 1320 — 1040 mA t CK = min, BL = 4 1, 2, 5 Refresh current I CC5 — 2000 — 2000 mA t RC = min 3 Self refresh current I CC6 — 48 — 48 mA VIH ≥ VCC – 0.2 V VIL ≤ 0.2 V 8 Input leakage current I LI –10 10 –10 10 µA 0 ≤ Vin ≤ VCC Output leakage current I LO –10 10 –10 10 µA 0 ≤ Vout ≤ VCC DQ = disable Output high voltage VOH 2.4 — 2.4 — V I OH = –4 mA Output low voltage VOL — 0.4 — 0.4 V I OL = 4 mA Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current. Preliminary Data Sheet E0012H10 19 HB52F648EN/HB52F649EN-75B DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB52F649EN) HB52F649EN-75B PC133 CE latency = 3 PC100 CE latency = 2 Parameter Symbol Min Max Min Max Unit Test conditions Notes Operating current I CC1 — 1260 — 1260 mA Burst length = 1 t RC = min 1, 2, 3 Standby current in power down I CC2P — 54 — 54 mA CKE = VIL, t CK = 12 ns 6 Standby current in power down (input signal stable) I CC2PS — 36 — 36 mA CKE = VIL, t CK = ∞ 7 Standby current in non power down I CC2N — 360 — 360 mA CKE, S = VIH, t CK = 12 ns 4 Active standby current in power down I CC3P — 72 — 72 mA CKE = VIL, t CK = 12 ns 1, 2, 6 Active standby current in non power down I CC3N — 540 — 540 mA CKE, S = VIH, t CK = 12 ns 1, 2, 4 Burst operating current I CC4 — 1485 — 1170 mA t CK = min, BL = 4 1, 2, 5 Refresh current I CC5 — 2250 — 2250 mA t RC = min 3 Self refresh current I CC6 — 54 — 54 mA VIH ≥ VCC – 0.2 V VIL ≤ 0.2 V 8 Input leakage current I LI –10 10 –10 10 µA 0 ≤ Vin ≤ VCC Output leakage current I LO –10 10 –10 10 µA 0 ≤ Vout ≤ VCC DQ = disable Output high voltage VOH 2.4 — 2.4 — V I OH = –4 mA Output low voltage VOL — 0.4 — 0.4 V I OL = 4 mA Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current. Preliminary Data Sheet E0012H10 20 HB52F648EN/HB52F649EN-75B Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB52F648EN) Parameter Symbol Max Unit Notes Input capacitance (Address) CI1 105 pF 1, 2, 4 Input capacitance (RE, CE, W) CI2 90 pF 1, 2, 4 Input capacitance (CKE) CI3 68 pF 1, 2, 4 Input capacitance (S) CI4 38 pF 1, 2, 4 Input capacitance (CK) CI5 50 pF 1, 2, 4 Input capacitance (DQMB) CI6 23 pF 1, 2, 4 Input/Output capacitance (DQ) CI/O1 22 pF 1, 2, 3, 4 Notes: 1. 2. 3. 4. Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested. Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB52F649EN) Parameter Symbol Max Unit Notes Input capacitance (Address) CI1 112 pF 1, 2, 4 Input capacitance (RE, CE, W) CI2 97 pF 1, 2, 4 Input capacitance (CKE) CI3 70 pF 1, 2, 4 Input capacitance (S) CI4 40 pF 1, 2, 4 Input capacitance (CK) CI5 50 pF 1, 2, 4 Input capacitance (DQMB) CI6 27 pF 1, 2, 4 Input/Output capacitance (DQ) CI/O1 22 pF 1, 2, 3, 4 Notes: 1. 2. 3. 4. Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested. Preliminary Data Sheet E0012H10 21 HB52F648EN/HB52F649EN-75B AC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) HB52F648EN/649EN-75B PC133 CE latency = 3 PC100 CE latency = 2 Parameter PC100 Symbol Symbol Min Max Min Max Unit Notes System clock cycle time t CK Tclk 7.5 — 10 — ns 1 CK high pulse width t CKH Tch 2.5 — 3 — ns 1 CK low pulse width t CKL Tcl 2.5 — 3 — ns 1 Access time from CK t AC Tac — 5.4 — 6 ns 1, 2 Data-out hold time t OH Toh 2.7 — 3 — ns 1, 2 CK to Data-out low impedance t LZ 2 — 2 — ns 1, 2, 3 CK to Data-out high impedance t HZ — 5.4 — 6 ns 1, 4 Data-in setup time t DS Tsi 1.5 — 2 — ns 1 Data in hold time t DH Thi 0.8 — 1 — ns 1 Address setup time t AS Tsi 1.5 — 2 — ns 1 Address hold time t AH Thi 0.8 — 1 — ns 1 CKE setup time t CES Tsi 1.5 — 2 — ns 1, 5 CKE setup time for power down exit t CESP Tpde 1.5 — 2 — ns 1 CKE hold time t CEH Thi 0.8 — 1 — ns 1 Command setup time t CS Tsi 1.5 — 2 — ns 1 Command hold time t CH Thi 0.8 — 1 — ns 1 Ref/Active to Ref/Active command period t RC Trc 67.5 — 70 — ns 1 Active to precharge command period t RAS Tras 45 120000 50 120000 ns 1 Active command to column command (same bank) t RCD Trcd 20 — 20 — ns 1 Precharge to active command period t RP Trp 20 — 20 — ns 1 Write recovery or data-in to precharge lead time t DPL Tdpl 15 — 20 — ns 1 Active (a) to Active (b) command period t RRD Trrd 15 — 20 — ns 1 Transition time (rise to fall) tT 1 5 1 5 ns Refresh period t REF — 64 — 64 ms Preliminary Data Sheet E0012H10 22 HB52F648EN/HB52F649EN-75B Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command. Test Conditions • Input and output timing reference levels: 1.5 V • Input waveform and output load: See following figures 2.4 V input 0.4 V DQ 2.0 V 0.8 V CL t T tT Preliminary Data Sheet E0012H10 23 HB52F648EN/HB52F649EN-75B Relationship Between Frequency and Minimum Latency Parameter HB52F648EN/649EN-75B Frequency (MHz) 133 100 CE latency = 3 CE latency = 2 PC100 Symbol Symbol 7.5 10 Notes Active command to column command (same bank) I RCD 3 2 1 Active command to active command (same bank) I RC 9 7 = [IRAS + IRP] 1 Active command to precharge command I RAS (same bank) 6 5 1 Precharge command to active command I RP (same bank) 3 2 1 2 2 1 2 2 1 tCK (ns) Write recovery or data-in to precharge command (same bank) I DPL Tdpl Active command to active command (different bank) I RRD Self refresh exit time I SREX Tsrx 1 1 2 Last data in to active command (Auto precharge, same bank) I APW Tdal 5 4 = [IDPL + IRP] Self refresh exit to command input I SEC 9 7 = [IRC] 3 Precharge command to high impedance I HZP 3 2 Last data out to active command (auto precharge) (same bank) I APR 1 1 Last data out to precharge (early precharge) I EP –2 –1 Column command to column command I CCD Tccd 1 1 Write command to data in latency I WCD Tdwd 0 0 DQMB to data in I DID Tdqm 0 0 DQMB to data out I DOD Tdqz 2 2 CKE to CK disable I CLE Tcke 1 1 Register set to active command I RSA Tmrd 1 1 S to command disable I CDD 0 0 Power down exit to command input I PEC 1 1 Troh Preliminary Data Sheet E0012H10 24 HB52F648EN/HB52F649EN-75B Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP] Pin Functions CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BS) is precharged. BA0/BA1 (input pin): BA0/BA1 are bank select signal (BS). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is Low, bank 1 is selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is High, bank 3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (input/output pins): Data is input to and output from these pins. CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected. Preliminary Data Sheet E0012H10 25 HB52F648EN/HB52F649EN-75B Detailed Operation Part Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet. Preliminary Data Sheet E0012H10 26 HB52F648EN/HB52F649EN-75B Physical Outline Unit: mm inch Front side 133.37 ± 0.15 5.251 ± 0.006 (DATUM -A-) B C 0.450 36.83 1.450 Back side 4.00 min 0.157 min ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 11.43 ,, ,, ,, , A 1.27 ± 0.10 0.050 ± 0.004 54.61 2.150 127.35 ± 0.15 5.014 ± 0.006 2 – φ 3.00 ± 0.10 2 – φ 0.118 ± 0.003 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (DATUM -A-) R FULL 3.125 ± 0.125 0.123 ± 0.005 1.27 0.050 0.20 ± 0.15 0.010 ± 0.0004 2.50 ± 0.20 0.098 ± 0.008 1.00 ± 0.05 0.039 ± 0.002 Detail B 34.925 1.375 85 Detail A 17.80 0.70 168 4.00 ±0.10 0.157 ± 0.004 4.00 max 0.157 max (63.67) (2.51) Detail C (DATUM -A-) 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 1.00 0.039 3.125 ± 0.125 0.123 ± 0.005 3.00 ± 0.10 0.118 ± 0.004 3.00 typ 0.118 typ R FULL 6.35 0.250 4.175 0.164 2.00 ± 0.10 0.079 ± 0.004 Note: Tolerance on all dimensions ± 0.15/0.006 unless otherwise specified. Preliminary Data Sheet E0012H10 27 HB52F648EN/HB52F649EN-75B Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. Preliminary Data Sheet E0012H10 28