ELPIDA HM538254BJ-10

2 M VRAM (256-kword × 8-bit)
Hyper Page Mode (HM538254B)
LP
EO
Description
HM538253B Series
HM538254B Series
E0163H10 (Ver. 1.0)
(Previous ADE-203-264A/265 (Z))
Jul. 6, 2001 (K)
Features
ro
The HM538253B/HM538254B is a 2-Mbit multiport video RAM equipped with a 256-kword × 8-bit dynamic
RAM and a 512-word × 8-bit SAM (full-sized SAM). Its RAM and SAM operate independently and
asynchronously. The HM538253B/HM538254B is upwardly compatible with the HM534253B/HM538123B
except that the pseudo-write-transfer cycle is replaced with masked-write-transfer cycle, which has been
approved by JEDEC. Furthermore, several new features have been added to the HM538253B/HM538254B
which do not conflict with the conventional features. The stopping column feature realizes allows greater
flexibility for split SAM register lengths. Persistent mask is also installed according to the TMS34020
features. The HM538254B has Hyper page mode which enables fast page cycle.
ct
du
• Multiport organization:RAM and SAM can operate asynchronously and simultaneously:
 RAM: 256-kword × 8-bit
 SAM: 512-word × 8-bit
• Access time
 RAM: 70 ns/80 ns/100 ns max
 SAM: 20 ns/23 ns/25 ns max
• Cycle time
 RAM: 130 ns/150 ns/180 ns min
 SAM: 25 ns/28 ns/30 ns min
• Low power
 Active
RAM: 605 mW/550 mW/495 mW
SAM: 358 mW/330 mW/303 mW
 Standby 38.5 mW max
• Masked-write-transfer cycle capability
• Stopping column feature capability
• Persistent mask capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EO
HM538253B/HM538254B Series
LP
• Fast page mode capability (HM538253B)
 Cycle time:
45 ns/50 ns/55 ns
 Power RAM:
605 mW/578 mW/550 mW
• Hyper page mode capability (HM538254B)
 Cycle time:
35 ns/40 ns/45 ns
 Power RAM:
715 mW/660 mW/605 mW
• Mask write mode capability
• Bidirectional data transfer cycle between RAM and SAM capability
• Split transfer cycle capability
• Block write mode capability
• Flash write mode capability
• 3 variations of refresh (8 ms/512 cycles)
 RAS-only refresh
 CAS-before-RAS refresh
 Hidden refresh
• TTL compatible
Ordering Information
Access Time
HM538253BJ-7
HM538253BJ-8
HM538253BJ-10
70 ns
80 ns
100 ns
HM538254BJ-7
HM538254BJ-8
HM538254BJ-10
70 ns
80 ns
100 ns
HM538253BTT-7
HM538253BTT-8
HM538253BTT-10
70 ns
80 ns
100 ns
HM538254BTT-7
HM538254BTT-8
HM538254BTT-10
70 ns
80 ns
100 ns
ro
Type No.
Package
400-mil, 40-pin plastic SOJ (CP-40D)
du
44-pin thin small outline package (TTP-44/40DA)
ct
Data Sheet E0163H10
2
EO
HM538253B/HM538254B Series
Pin Arrangement
HM538253BJ Series
HM538254BJ Series
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
SC
SI/O0
SI/O1
SI/O2
SI/O3
DT/OE
I/O0
I/O1
I/O2
NL
NL
I/O3
VSS
WE
RAS
A8
A7
A6
A5
A4
VCC
V SS
SI/O7
SI/O6
SI/O5
SI/O4
SE
I/O7
I/O6
I/O5
I/O4
VSS
DSF1
NC
CAS
QSF
A0
A1
A2
A3
V SS
(Top view)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V SS
SI/O7
SI/O6
SI/O5
SI/O4
SE
I/O7
I/O6
I/O5
I/O4
NL
NL
VSS
DSF1
NC
CAS
QSF
A0
A1
A2
A3
V SS
(Top view)
ct
du
ro
LP
VCC
SC
SI/O0
SI/O1
SI/O2
SI/O3
DT/OE
I/O0
I/O1
I/O2
I/O3
VSS
WE
RAS
A8
A7
A6
A5
A4
VCC
HM538253BTT Series
HM538254BTT Series
Data Sheet E0163H10
3
EO
HM538253B/HM538254B Series
Pin Description
Function
A0-A8
Address inputs
I/O0-I/O7
RAM port data inputs/outputs
SI/O0-SI/O7
SAM port data inputs/outputs
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DT/OE
Data transfer/output enable
SC
Serial clock
SE
SAM port enable
DSF1
Special function input flag
QSF
Special function output flag
VCC
Power supply
VSS
Ground
NL
No lead
NC
No connection
ct
du
ro
LP
Pin Name
Data Sheet E0163H10
4
EO
HM538253B/HM538254B Series
Block Diagram
A0 – A8
A0 – A8
Row Address
Buffer
Refresh
Counter
0
Serial Input
Buffer
Transfer
Gate
Data
Register
SI/O0 – SI/O7
ct
I/O0 – I/O7
Timing Generator
RAS
CAS
DT/OE
WE
DSF1
SC
SE
Mask
Register
Address Mask
Register
Color
Resister
Output
Buffer
Serial Output
Buffer
du
ro
Input Data
Control
Input
Buffer
511
Transfer
Gate
Data
Register
Sense Amplifier & I/O Bus
Column Decoder
Block Write Flash Write
Control
Control
0
511 Memory Array
QSF
SAM Column Decoder
LP
Serial Address
Counter
Row Decoder
SAM I/O Bus
A0 – A8
Column Address
Buffer
Data Sheet E0163H10
5
EO
HM538253B/HM538254B Series
Pin Functions
RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address
and signals as shown in table 1 are input at the falling edge of R A S. The input level of these signals
determines the operation cycle of the HM538253B/HM538254B.
CAS (input pin): Column address and DSF1 signals are fetched into the chip at the falling edge of CAS,
which determines the operation mode of the HM538253B/HM538254B.
LP
A0–A8 (input pins): Row address (AX0–AX8) is determined by A0–A8 level at the falling edge of RAS.
Column address (AY0–AY8) is determined by A0–A8 level at the falling edge of CAS. In transfer cycles,
row address is the address on the word line which transfers data with the SAM data register, and column
address is the SAM start address after transfer.
WE: The WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge
of RAS, the HM538253B/ HM538254B turns to mask write mode. According to the I/O level at the time,
write on each I/O can be masked. (WE level at the falling edge of RAS is don’t care in read cycle.) When
WE is high at the falling edge of RAS, no mask write cycle is executed. After that, WE switches to read/write
cycles. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS.
When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high,
data is transferred from RAM to SAM (data is read from RAM).
ro
I/O0–I/O7 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins is masked and internal data is retained.
After that, they function as input/output pins as those of a standard DRAM. In block write cycle, the data
functions as column mask data at the falling edges of CAS and WE.
du
DT/OE (input pin): The DT/OE pin functions as a DT (data transfer) pin at the falling edge of RAS and as
an OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer
cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently.
SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously
with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into
the SAM data register.
SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a
mask for serial write because the internal pointer is incremented at the rising edge of SC.
ct
SI/O0–SI/O7 (input/output pins): SI/Os are SAM input/output pins. I/O direction is determined by the
previous transfer cycle. If it was a read transfer cycle, SI/O outputs data. If it was a masked write transfer
cycle, SI/O inputs data.
DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS
when new functions such as color register and mask register read/write, split transfer, and flash write, are
used.
Data Sheet E0163H10
6
EO
HM538253B/HM538254B Series
DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all
operations of the HM538253B/HM538254B.
QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing
address 255 in SAM, and from high to low by accessing address 511 in SAM.
Table 1
Operation Cycles of the HM538253B/HM538254B
RAS
CAS
Address
I/On Input
CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS
CAS
RAS
CAS/WE
CBRS
0
CBRR
0
CBRN
0
MWT
1
MSWT
1
RT
1
SRT
1
RWM
1
BWM
1
RW (No)
LP
Mnemonic
Code
0
1
0
—
0
Stop
—
—
—
—
1
0
0
—
0
—
—
—
—
—
1
1
0
—
0
—
—
—
—
0
0
0
0
—
0
Row
TAP
WM
—
0
0
1
0
—
0
Row
TAP
WM
—
0
1
0
0
—
0
Row
TAP
—
—
0
1
1
0
—
0
Row
TAP
—
—
1
0
0
0
0
0
Row
Column WM
Input data
1
0
0
0
1
0
Row
Column WM
Column Mask
1
1
1
0
0
0
0
Row
Column —
Input Data
BW (No)
1
1
1
0
0
1
0
Row
Column —
Column Mask
FWM
1
1
0
1
0
—
0
Row
—
WM
—
LMR and
1
Old Mask Set
1
1
1
0
0
0
(Row)
—
—
Mask Data
LCR
1
1
1
1
0
1
0
(Row)
—
—
Color
Option
0
0
0
0
0
—
0
Data
—
du
ro
—
Mode
—
ct
Data Sheet E0163H10
7
EO
HM538253B/HM538254B Series
Table 1
Operation Cycles of the HM538253B/HM538254B (cont)
Register
Write
Mask
Pers
W.M.
WM
Color
No. Of
Bndry
Function
CBRS
—
—
—
—
Set
CBR refresh with stop register set
CBRR
—
Reset
Reset
—
Reset
CBR refresh with register reset
CBRN
—
—
—
—
—
CBR refresh (no reset)
MWT
Yes
No
Yes
Load/use
Use
—
—
Masked write transfer (new/old mask)
MSWT
Yes
No
Yes
Load/use
Use
—
Use
Masked split write transfer (new/old mask)
RT
—
—
—
—
—
Read transfer
SRT
—
—
—
—
Use
Split read transfer
RWM
Yes
No
Yes
Load/use
Use
—
—
Read/write (new/old mask)
BWM
Yes
No
Yes
Load/use
Use
—
Block write (new/old mask)
RW (no)
No
No
—
—
—
Read/write (no mask)
BW (no)
No
No
—
Use
—
Block write (no mask)
FWM
Yes
No
Yes
Load/use
Use
Use
—
Masked flash write (new/old mask)
LMR and
Old Mask Set
—
Set
Load
—
—
Load mask register and old mask set
LCR
—
—
—
Load
—
Load color resister set
Option
—
—
—
—
—
du
ro
LP
Mnemonic
Code
Notes: 1. With CBRS, all SAM operations use stop register.
2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR
3. DSF2 is fixed low in all operation (for the addition of operation modes in future).
Operation of HM538253B/HM538254B
RAM Port Operation
ct
RAM Read Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling
edge of CAS: Mnemonic Code; R) Row address is entered at the RAS falling edge and column address at the
C AS falling edge to the device as in standard DRAM operation. Then, when WE is high and DT/OE is low
while C AS is low, the selected address data outputs through the I/O pin. At the falling edge of RAS , DT/OE
and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address
access time (tAA) and RAS to column address delay time (tRAD ) specifications are added to enable fast page
mode/hyper page mode.
Data Sheet E0163H10
8
EO
HM538253B/HM538254B Series
RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write)(DT/OE high, CAS high and DSF1
are low at the falling edge of R AS, and DSF1 is low at the falling edge of CAS): Mnemonic Code; W
LP
No Mask Write Cycle (WE high at the falling edge of RAS): When CAS is set low and WE is set low after
RAS low, a write cycle is executed. If WE is set low before the CAS falling edge, this cycle becomes an early
write cycle and all I/O become in high impedance. If WE is set low after the CAS falling edge, this cycle
becomes a delayed write cycle. I/O does not become high impedance in this cycle, so data should be entered
with OE in high. If W E is set low after tC W D (min) and tAWD (min) after the CAS falling edge, this cycle
becomes a read-modify-write cycle and enables read/write at the same address in one cycle. In this cycle also,
to avoid I/O contention, data should be input after reading data and driving OE high.
Mask Write Mode (WE low at the falling edge of RAS):If WE is set low at the falling edge of RAS, two
modes of mask write cycle are possible.
In new mask mode, mask data is loaded from I/O pin and used. Whether or not an I/O is written depends on
I/O level at the falling edge of RAS. The data is written in high level I/Os, and the data is masked and retained
in low level I/Os. This mask data is effective during the RAS cycle. So, in page mode cycles the mask data is
retained during the page access.
ro
If a load mask register cycle (LMR) has been performed, Mask write cycle (RAM write cycle, flash write
cycle, block write cycle, masked write transfer cycle and masked sprit write transfer cycle) becomes all
persistent mask mode. The mask data is not loaded from I/O pins and the mask data stored in mask registers
persistently are used. This operation known as persistent write mask is reset by CBRR cycle, and becomes a
new mask.
du
Fast Page Mode Cycle (HM538253B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS):
Fast page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while
RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block
write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and
access time from CAS precharge (t ACP ) are added. In one RAS cycle, 512-word memory cells of the same row
address can be accessed. It is necessary to specify access frequency within tRASP max (100 µs).
ct
Hyper Page Mode Cycle (HM538254B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS):
Hyper page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while
RAS is low. Its cycle time is one forth of the random read/write cycle. In this cycle, read, write, and block
write cycles can be mixed. Note that address access time (t AA ), RAS to column address delay time (tRAD), and
access time from CAS precharge (t ACP ) are added. column address is latched by CAS low edge triger, access
time from CAS is determined by tCAC (tAA from column address, t ACP from CAS high edge). Dout data is held
during CAS high and is sustained until next Dout. Data output enable/disable is controlled by DT/OE and
when both RAS and CAS become high, Data output becomes High-Z. In one RAS cycle, 512-word memory
cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max
(100 µs).
Color Register Set/Read Cycle (CAS high, DT/OE high, W E high and DSF1 high at the falling edge of
RAS: Mnemonic Code; LCR) In color register set cycle, color data is set to the internal color register used in
flash write cycle or block write cycle. 8 bits of internal color register are provided at each I/O. This register is
composed of static circuits, so once it is set, it retains the data until reset. Since color register set cycle is the
Data Sheet E0163H10
9
EO
HM538253B/HM538254B Series
same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. In this
cycle, the HM538253B/ HM538254B refreshes the row address fetched at the falling edge of RAS.
LP
Mask Register Set/Read Cycle (CAS high, DT/OE high, WE high, and DSF1 low at the falling edge of R AS:
Mnemonic Code; LMR) In this cycle, mask data is set to the internal mask register persistently used in mask
write cycle, block write cycle, flash write cycle, masked write transfer, and masked split write transfer. 8 bits
of internal mask register are provided at each I/O. This mask register is composed of static circuits. So once it
is reset by CBRR cycle, it retains the data until reset or reselect. Once LMR is set, mask write cycle data is
written by persistent mask data. Since mask register set cycle is just the same as the usual read and write
cycle, so read, early write, and delayed write cycle can be executed.
Flash Write Cycle (CAS high, D T/OE high, W E low, and DSF1 high at the falling edge of R A S:
Mnemonic; FW) In a flash write cycle, a row of data (512 word × 8 bit) is cleared to 0 or 1 at each I/O
according to the data in the color register mentioned before. It is also necessary to mask I/O in this cycle.
When CAS and DT/OE are set high, WE is low, and DSF1 is high at the falling edge of RAS, this cycle starts.
Then, the row address to clear is given to row address. Mask data is the same as that of a RAM write cycle.
Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/512 of the usual
cycle time. (See figure 1.)
ro
Block Write Cycle (CAS high, DT/OE high and DSF1 low at the falling edge of RAS, DSF1 high and WE
low at the falling edge of CAS: Mnemonic; BW) In a block write cycle, 4 columns of data (4 column × 8 bit)
are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are
disregarded. The mask data on I/Os and the mask data on column address can be determined independently.
I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) The block write cycle
is as the same as the usual write cycle, so early and delayed write, read-modify-write, and page mode write
cycle can be executed.
No Mask Mode Block Write Cycle (WE high at the falling edge of RAS): The data on 8 I/Os are all cleared
when WE is high at the falling edge of RAS.
du
Mask Block Write Cycle (WE low at the falling edge of RAS):When WE is low at the falling edge of RAS,
the HM538253B/HM538254B starts mask block write cycle to clear the data on an optional I/O. The mask
data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data
is retained. In new mask mode, the mask data is available in the RAS cycle. In persistent mask mode, I/O
does not care about mask mode.
ct
Data Sheet E0163H10
10
EO
HM538253B/HM538254B Series
Color Register Set Cycle
Flash Write Cycle
Flash Write Cycle
RAS
CAS
Address
Row
Xi
Xj
WE
DSF1
I/O
LP
DT/OE
Color Data
Set color register
*1
*1
Execute flash write into each
I/O on row address Xi using
color register.
Execute flash write into
each I/O on row address
Xj using color register.
ro
Note: 1. I/O Mask Data (In new mask mode)
Low: Mask
High: Non Mask
In persistent mask mode, I/O don't care
Figure 1 Use of Flash Write
ct
du
Data Sheet E0163H10
11
EO
HM538253B/HM538254B Series
Color Register Set Cycle
Block Write Cycle
Block Write Cycle
RAS
CAS
Address
Row
Row
*1
WE
DSF1
LP
DT/OE
Color Data
I/O
*1
WE
Low
High
Column A2–A8
Mode
New mask mode
Persistent
mask mode
No mask
*1
Row
Column A2–A8
*1
Column Mask
*1
Column Mask
I/O data/RAS
Mask
H or L
(mask register used)
H or L
Column0 (A0 = 0, A1 = 0) Mask Data
Column1 (A0 = 1, A1 = 0) Mask Data
Column2 (A0 = 0, A1 = 1) Mask Data
Column3 (A0 = 1, A1 = 1) Mask Data
Low: Mask
du
I/O0
I/O1
I/O2
I/O3
ro
I/O Mask Data (In new mask mode)
Low: Mask
High: Non Mask
In persistent mask mode, I/O H or L
Column Mask Data
High: Non Mask
Figure 2 Use of Block Write
Transfer Operation
The HM538253B/HM538254B provides the read transfer cycle, split read transfer cycle, masked write
transfer cycle and masked split write transfer cycle as data transfer cycles. These transfer cycles are set by
driving CAS high and DT/OE low at the falling edge of RAS. They have following functions:
ct
• Transfer data between row address and SAM data register
 Read transfer cycle and split read transfer cycle: RAM to SAM
 Masked write transfer cycle and masked split write transfer cycle: SAM to RAM
• Determine SI/O state (except for split read transfer and masked split write transfer cycle)
 Read transfer cycle: SI/O output
 Masked write transfer cycle: SI/O input
• Determine first SAM address to access after transferring at column address (SAM start address).
Data Sheet E0163H10
12
EO
HM538253B/HM538254B Series
 SAM start address must be determined by read transfer cycle or masked write transfer cycle (split
transfer cycle isn’t available) before SAM access, after power on, and determined for each transfer
cycle.
• Use the stopping columns (boundaries) in the serial shift register. If the stopping columns have been set,
split transfer cycles use the stopping columns, but any boundaries cannot be set as the start address.
• Load/use mask data in masked write transfer cycle and masked split write transfer cycle.
Read Transfer Cycle (CAS high, D T/OE low, W E high and DSF1 low at the falling edge of R A S):
Mnemonic; RT
LP
This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF1 low at the falling edge of
RAS. The row address data (512 × 8 bits) determined by this cycle is transferred to SAM data register
synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs
from SAM start address determined by column address. In read transfer cycle, DT/OE must rise to transfer
data from RAM to SAM.
This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min)
specified between the last SAM access before transfer and DT/OE rising edge and t SDH (min) specified
between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.)
CAS
Address
DT/OE
SC
SI/O
L
Yj
du
DSF1
Xi
ro
RAS
t SDD
t SDH
SAM Data before Transfer
Yj + 1
SAM Data after Transfer
ct
Figure 3 Real Time Read Transfer
Yj
When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high
impedance before t SZS (min) of the first SAM access to avoid data contention.
Masked Write Transfer cycle (CAS high, DT/OE low, WE low, and DSF1 low at the falling edge of RAS):
Masked write transfer cycle can transfer only selected I/O data in a row of data input by serial write cycle to
RAM. Whether I/O data is transferred or not depends on the corresponding I/O level (mask data) at the falling
Data Sheet E0163H10
13
EO
HM538253B/HM538254B Series
edge of RAS. This mask transfer operation is the same as a mask write operation in RAM cycles, so the
persistent mode can be supported.
The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The
column address is specified as the first address for serial write after terminating this cycle. Also in this cycle,
SAM access becomes enabled after t SRD (min) after RAS becomes high. SAM access is inhibited during RAS
low. In this period, SC must not be risen.
(Row address)
A8 ........ A0
000000000
LP
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of
RAM by write transfer cycle. However, the address to write data must be the same as that of the read transfer
cycle or the split read transfer cycle (row address AX8). Figure 4 shows the example of row bit data transfer.
In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to 111111111.
Same as the case of AX8 = 1.
SAM
........
SAM
(Row address)
A8 ........A0
000000000
Possible
RAM
011111111
100000000
RAM
011111111
100000000
Impossible
ro
RAM
RAM
111111111
111111111
SAM
(Read transfer cycle)
SAM
(Write transfer cycle)
Figure 4 Example of Row Bit Data Transfer
du
Split Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF1 high at the falling edge of RAS): To
execute a continuous serial read by real-time read transfer, the HM538253B/HM538254B must satisfy SC and
DT/OE timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it
possible to execute a continuous serial read without the above timing limitation.
The HM538253B/HM538254B supports two types of split register operation. One is the normal split register
operation to split the data register into two halves. The other is the boundary split register operation using
stopping columns described later.
ct
Figure 5 shows the block diagram for the normal split register operation. SAMdata register (DR) consists of 2
split buffers, whose organizations are 256-word × 8-bit each. Suppose that data is read from upper data
register DR1. (The row address AX8 is 0 and SAM address A8 is 1.) When split read transfer is executed
setting row address AX8 to 0 and SAM start addresses A0 to A7, 256-word × 8-bit data is transferred from
RAM to the lower data register DR0 (SAM address A8 is 0) automatically. After data is read from data
register DR1, data read begins from SAM start addresses of data register DR0. If the next split read transfer
isn’t executed while data is read from data register DR0, data read begins from SAM start address 0 of DR1
after data is read from data register DR0. If split read transfer is executed setting row address AX8 to 1 and
SAM start addresses A0 to A7 while data is read from data register DR1, 256-word × 8-bit data is transferred
to data register DR2. After data is read from data register DR1, data read begins from the SAM start addresses
Data Sheet E0163H10
14
EO
HM538253B/HM538254B Series
of data register DR2. If the next split read transfer isn’t executed while data is read from data register DR2,
data read begins from SAM start address 0 of data register DR1 after data is read from data register DR2. In
split read data transfer, the SAM start address A8 is automatically set in the data register, which isn’t used.
DR3
Memory
Array
AX8 = 1
DR2
SAM I/O Bus
SAM Column Decoder
DR0
SAM I/O Bus
LP
Memory
Array
AX8 = 0
DR1
The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to high
by accessing SAM last address 255 and from high to low by accessing address 511.
ro
SAM I/O Buffer
SI/O
Figure 5 Split Transfer Block Diagram
du
Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF1 is high at the falling
edge of RAS. The cycle can be executed asyncronously with SC. However, the HM538253B/ HM538254B
must be satisfied tSTS (min) timing specified between SC rising (boundary address) and RAS falling. In split
transfer cycle, the HM538253B/HM538254B must satisfy t RST (min), tCST (min) and tAST (min) timings
specified between RAS or CAS falling and column address. (See figure 6.)
In split read transfer, SI/O isn’t switched to output state. Therefore, read transfer must be executed to switch
SI/O to output state when the previous transfer cycle is masked write transfer cycle or masked split write
transfer cycle.
ct
Masked Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF1 high at the falling edge of
RAS): A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in
write transfer. Masked split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST
(min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch
SI/O to input state in this cycle. If SI/O is in output state, masked write transfer cycle should be executed to
switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be
written to other addresses of RAM by masked split write transfer cycle. However masked write transfer cycle
must be executed before masked split write transfer cycle. And in this masked split write transfer cycle, the
Data Sheet E0163H10
15
EO
HM538253B/HM538254B Series
MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read
transfer cycle. In this cycle, the boundary split register operation using stopping columns is possible as with
split read transfer cycle.
RAS
tSTS (min)
tRST (min)
CAS
LP
Address
t CST (min)
Xi
Yj
t AST (min)
DT/OE
DSF1
SC
Bi
Ym
Bj – 1
Bj
Yj
ro
Note: Ym is the SAM start address in before SRT. Bi and Bj initiate the boundary address.
Figure 6 Split Transfer Limitation
Table 2
Stopping Column Boundary Table
Stop Address
A3
B2
4
0
×
B3
8
1
0
B4
16
1
1
B5
32
1
1
B6
64
1
1
B7
128
1
1
B8
256
1
1
Notes: 1. A0, A1, and A8: H or L
2. ×: H or L
A4
A5
A6
A7
×
×
×
×
×
×
×
×
0
×
×
×
1
0
×
×
1
1
0
×
1
1
1
0
1
1
1
1
ct
A2
du
Boundary Code Column Size
Stopping Column in Split Transfer Cycle: The HM538253B/HM538254B has the boundary split register
operation using stopping columns. If a CBRS cycle has been performed, split transfer cycle performs the
boundary operation. Figure 7 shows an example of boundary split register. (Boundary code is B7.)
Data Sheet E0163H10
16
EO
HM538253B/HM538254B Series
First a read data transfer cycle is executed, and SAM start addresses A0 to A8 are set. The RAM data is
transferred to the SAM, and SAM serial read starts from the start address (Y1) on the lower SAM. After that,
a split read transfer cycle is executed, and the next start address (Y2) is set. The RAM data is transferred to
the upper SAM. When the serial read arrive at the first boundary after the split read transfer cycle, the next
read jumps to the start address (Y2) on the upper SAM (jump 1) and continues. Then the second split read
transfer cycle is executed, and another start address (Y3) is set. The RAM data is transferred to the lower
SAM. When the serial read arrive at the other boundary again, the next read jumps to the start address (Y3)
on the lower SAM. In stopping column, split transfer is needed for jump operation between lower SAM and
upper SAM.
LP
Stopping Column Set Cycle (CBRS): Start a stopping column set cycle by driving CAS low, WE low, and
DSF1 high at the falling edge of R AS. Stopping column data (boundaries) are latched from address inputs on
the falling edge of RAS. To determine the boundary, A2 to A7 can be used, and A0, A1, and A8 don’t care.
In the HM538253B/HM538254B, 7 types of boundary (B2 to B8) can be set including the default case. (See
stopping column boundary table.) If A2 to A6 are set high and A7 is set low, the boundaries (B7) are
selected. Figure 6 shows the example. Once a CBRS is executed, next sprit transfer cycle data become
stopping columm data. Stopping columm is reset by CBBR.
Column size
128 bit
(Y3)
Jump 1
Lower SAM
256 bit
(Y2)
du
Start
ro
(Y1)
Boundaries (B7)
Jump 2
Upper SAM
256 bit
Figure 7 Example of Boundary Split Register
ct
Register Reset Cycle (CBRR): Start a register reset cycle (CBRR) by driving CAS low, W E high, and
DSF1 low at the falling edge of R AS. A CBRR can reset the persistent mask operation and stopping column
operation, so the HM538253B/HM538254B becomes the new mask operation and boundary code B8. When
a CBRR is executed for stopping column operation reset and split transfer operation, it needs to satisfy t STS
(min) and tRST (min) between RAS falling and SC rising.
No Reset CBR cycle (CBRN): This cycle becomes no reset CBR cycle (CBRN) by driving CAS low, WE
high and DSF1 high at the falling edge of RAS. The CBRN can only execute the refresh operation.
Data Sheet E0163H10
17
EO
HM538253B/HM538254B Series
SAM Port Operation
Serial Read Cycle
SAM port is in read mode when the previous data transfer cycle is a read transfer cycle. Access is
synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high
impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address
511), the internal pointer indicates address 0 at the next access.
LP
Serial Write Cycle
If the previous data transfer cycle is a masked write transfer cycle, SAM port goes into write mode. In this
cycle, SI/O data is fetched into the data register at the SC rising edge like in the serial read cycle. If SE is
high, SI/O data isn’t fetched into the data register. The internal pointer is incremented by the SC rising, so SE
high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer
indicates address 0 at the next access.
Refresh
RAM Refresh
ro
RAM, which is composed of dynamic circuits, requires refresh cycles to retain data. Refresh is executed by
accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2)
CAS-before-R AS (CBRN, CBRS, and CBRR) refresh cycle, and (3) Hidden refresh cycle. The cycles which
activate RAS, such as read/write cycles or transfer cycles, can also refresh the row address. Therefore, no
refresh cycle is required when all row addresses are accessed within 8 ms.
du
RAS-Only Refresh Cycle: R AS-only refresh cycle is executed by activating only the RAS cycle with C AS
fixed high after inputting the row address (refresh address) from external circuits. To distinguish this cycle
from a data transfer cycle, DT/OE must be high at the falling edge of RAS.
CBR Refresh Cycle: CBR refresh cycle (CBRN, CBRS and CBRR) is set by activating CAS before RAS. In
this cycle, the refresh address needs not to be input through external circuits because it is input through an
internal refresh counter. In this cycle, output is high impedance and power dissipation is low because CAS
circuits are not operating.
ct
Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS
when DT/OE and CAS keep low in normal RAM read cycles.
SAM Refresh
SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh.
Data Sheet E0163H10
18
EO
HM538253B/HM538254B Series
Absolute Maximum Ratings
Symbol
Value
Unit
Voltage on any pin relative to V SS
VT
–1.0 to +7.0
V
Supply voltage relative to VSS
VCC
–0.5 to +7.0
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
LP
Parameter
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol
Min
Typ
Max
Unit
Notes
VCC
4.5
5.0
5.5
V
1
VIH
2.4
—
6.5
V
1
—
0.8
V
1
VIL
–0.5
ct
du
ro
Notes: 1. All voltage referred to VSS
2 –3.0 V for pulse width ≤ 10 ns.
*2
Data Sheet E0163H10
19
EO
HM538253B/HM538254B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM538253B/HM538254B
-7
-8
-10
Parameter
Symbol Min Max Min Max Min
Max Unit Test Conditions
Operating current
I CC1
—
110 —
100 —
90
I CC7
—
165 —
150 —
140 mA
Standby current
—
115 —
105 —
90
I CC7BW
—
170 —
155 —
140 mA
I CC2
—
7
—
7
—
7
mA
I CC8
—
65
—
60
—
55
mA
I CC3
—
110 —
100 —
90
I CC9
—
165 —
150 —
135 mA
I CC4
—
110 —
105 —
100 mA
I CC10
—
160 —
155 —
—
130 —
125 —
—
185 —
175 —
Fast page mode
I CC4BW
block write current *3
I CC10BW
mA
mA
RAS, CAS
cycling
t RC = min
RAS, CAS
cycling
t RC = min
165 mA
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
RAS, CAS = VIH SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
RAS cycling
CAS = VIH
t RC = min
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
CAS cycling
RAS = VIL
t PC = min
150 mA
120 mA
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
du
Fast page mode
current
(HM538253B) *3
I CC1BW
ro
RAS-only refresh
current
LP
Block write current
mA
CAS cycling
RAS = VIL
t PC = min
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
SC = VIL, SE =
VIH
ct
SE = VIL,
SC cycling
t SCC = min
Data Sheet E0163H10
20
EO
HM538253B/HM538254B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max Min Max Min
Max Unit Test Conditions
Hyper page mode
current
(HM538254B) *3
I CC4
—
130 —
120 —
110 mA
I CC10
—
185 —
170 —
160 mA
—
155 —
140 —
130 mA
mA
I CC10BW
—
210 —
190 —
175 175
I CC5
—
85
75
65
I CC11
—
140 —
—
130 —
115 —
100 mA
I CC12
—
180 —
165 —
145 mA
Input leakage
current
I LI
–10 10
–10 10
–10
Output leakage
current
I LO
–10 10
–10 10
–10
Output high voltage VOH
2.4
—
2.4
—
2.4
Output low voltage
—
0.4
—
0.4
—
LP
Parameter
Hyper page mode
I CC4BW
block write current *3
CAS-before-RAS
refresh current
130 —
mA
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
CAS cycling
RAS = VIL
t PC = min
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
RAS cycling
t RC = min
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
120 mA
RAS, CAS
cycling
t RC = min
SC = VIL, SE =
VIH
SE = VIL,
SC cycling
t SCC = min
du
VOL
—
ro
Data transfer current I CC6
—
CAS cycling
RAS = VIL
t PC = min
10
µA
10
µA
—
V
I OH = –1 mA
0.4
V
I OL = 2.1 mA
ct
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once while RAS is low and CAS is high.
3. Address can be changed once in 1 page cycle (tPC).
Data Sheet E0163H10
21
EO
HM538253B/HM538254B Series
Capacitance (Ta = 25°C, VCC = 5 V ± 10%, f = 1 MHz, Bias: Clock, I/O = VCC, Address =
VSS)
Parameter
Symbol
Typ
Max
Unit
Note
Input capacitance (Address)
CI1
—
5
pF
1
Input capacitance (Clocks)
CI2
—
5
pF
1
Output capacitance (I/O, SI/O, QSF)
CI/O
—
7
pF
1
Note:
1. This parameter is sampled and not 100% tested.
LP
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *16
Test Conditions
Input rise and fall time: 5 ns
Input pulse levels: VSS to 3.0 V
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: RAM 1 TTL + CL (50 pF)
SAM, QSF 1 TTL + CL (30 pF) (Including scope and jig)
ct
du
ro
•
•
•
•
•
Data Sheet E0163H10
22
EO
HM538253B/HM538254B Series
Common Parameter
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Random read or write cycle time
t RC
130 —
150 —
180 —
ns
RAS precharge time
t RP
50
—
60
—
70
ns
RAS pulse width
t RAS
70
10000
80
10000
100 10000
ns
t CAS
20
—
20
—
25
—
ns
Row address setup time
t ASR
0
—
0
—
0
—
ns
Row address hold time
t RAH
10
—
10
—
10
—
ns
Column address setup time
t ASC
0
—
0
—
0
—
ns
Column address hold time
t CAH
12
—
15
—
15
—
ns
RAS to CAS delay time
t RCD
20
50
20
60
20
75
ns
RAS hold time referred to CAS
t RSH
20
—
20
—
25
—
ns
CAS hold time referred to RAS
t CSH
70
—
80
—
100 —
ns
CAS to RAS precharge time
t CRP
10
—
10
—
10
—
ns
Transition time (rise to fall)
tT
3
50
3
50
3
50
ns
Refresh period
t REF
—
8
—
8
—
8
ms
DT to RAS setup time
t DTS
0
—
0
—
0
—
ns
DT to RAS hold time
t DTH
10
—
10
—
10
—
ns
DSF1 to RAS setup time
t FSR
0
—
0
—
0
—
ns
DSF1 to RAS hold time
t RFH
10
—
10
—
10
—
ns
DSF1 to CAS setup time
t FSC
0
—
0
—
0
—
ns
DSF1 to CAS hold time
t CFH
12
—
15
—
15
—
ns
Data-in to CAS delay time
t DZC
0
—
0
—
0
—
ns
4
Data-in to OE delay time
t DZO
0
—
0
—
0
—
ns
4
Output buffer turn-off delay referred to
CAS
t OFF1
—
15
—
20
—
20
ns
5
Output buffer turn-off delay referred to
OE
t OFF2
—
15
—
20
—
20
ns
5
CAS pulse width
—
2
3
ct
du
ro
LP
Parameter
Data Sheet E0163H10
23
EO
HM538253B/HM538254B Series
Read Cycle (RAM), Page Mode Read Cycle
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Access time from RAS
t RAC
—
70
—
80
—
100
ns
6, 7
Access time from CAS
t CAC
—
20
—
20
—
25
ns
7, 8
Access time from OE
t OAC
—
20
—
20
—
25
ns
7
Address access time
t AA
—
35
—
40
—
45
ns
7, 9
Read command setup time
t RCS
0
—
0
—
0
—
ns
Read command hold time
t RCH
0
—
0
—
0
—
ns
10
Read command hold time referred to
RAS
t RRH
0
—
5
—
10
—
ns
10
RAS to column address delay time
t RAD
15
35
15
40
15
55
ns
2
Column address to RAS lead time
t RAL
35
—
40
—
45
—
ns
Column address to CAS lead time
t CAL
35
—
40
—
45
—
ns
Page mode cycle time
t PC
45
—
50
—
55
—
ns
CAS precharge time
t CP
7
—
10
—
10
—
ns
—
45
—
50
ns
ro
LP
Parameter
Access time from CAS precharge
t ACP
Page mode RAS pulse width
t RASP
—
40
70
100000 80
100000 100 100000 ns
ct
du
Data Sheet E0163H10
24
EO
HM538253B/HM538254B Series
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Write command setup time
t WCS
0
—
0
—
0
—
ns
Write command hold time
t WCH
12
—
15
—
15
—
ns
Write command pulse width
t WP
12
—
15
—
15
—
ns
Write command to RAS lead time
t RWL
20
—
20
—
20
—
ns
Write command to CAS lead time
t CWL
20
—
20
—
20
—
ns
Data-in setup time
t DS
0
—
0
—
0
—
ns
12
t DH
12
—
15
—
15
—
ns
12
WE to RAS setup time
t WS
0
—
0
—
0
—
ns
WE to RAS hold time
t WH
10
—
10
—
10
—
ns
Mask data to RAS setup time
t MS
0
—
0
—
0
—
ns
Mask data to RAS hold time
t MH
10
—
10
—
10
—
ns
OE hold time referred to WE
t OEH
15
—
20
—
20
—
ns
Page mode cycle time
t PC
45
—
50
—
55
—
ns
CAS precharge time
t CP
7
—
10
—
10
—
ns
CAS to data-in delay time
t CDD
15
—
20
—
20
—
ns
Page mode RAS pulse width
t RASP
70
100000 80
Data-in hold time
11
13
100000 100 100000 ns
ct
du
ro
LP
Parameter
Data Sheet E0163H10
25
EO
HM538253B/HM538254B Series
Read-Modify-Write Cycle
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Read-modify-write cycle time
t RWC
180 —
200 —
230 —
ns
RAS pulse width (read-modify-write
cycle)
t RWS
120 10000
130 10000
150 10000
ns
CAS to WE delay time
t CWD
40
—
45
—
50
—
ns
14
Column address to WE delay time
t AWD
60
—
65
—
70
—
ns
14
OE to data-in delay time
t ODD
15
—
20
—
20
—
ns
12
Access time from RAS
t RAC
—
70
—
80
—
100
ns
6, 7
Access time from CAS
t CAC
—
20
—
20
—
25
ns
7, 8
Access time from OE
t OAC
—
20
—
20
—
25
ns
7
Address access time
t AA
—
35
—
40
—
45
ns
7, 9
RAS to column address delay time
t RAD
15
35
15
40
15
55
ns
Read command setup time
t RCS
0
—
0
—
0
—
ns
Write command to RAS lead time
t RWL
20
—
20
—
20
—
ns
Write command to CAS lead time
t CWL
20
—
20
—
20
—
ns
Write command pulse width
t WP
12
—
15
—
15
—
ns
Data-in setup time
t DS
0
—
0
—
0
—
ns
12
Data-in hold time
t DH
12
—
15
—
15
—
ns
12
OE hold time referred to WE
t OEH
15
—
20
—
20
—
ns
Refresh Cycle
du
ro
LP
Parameter
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
CAS setup time (CAS-before-RAS
refresh)
t CSR
10
—
10
—
10
—
ns
CAS hold time (CAS-before-RAS
refresh)
t CHR
10
—
10
—
10
—
ns
RAS precharge to CAS hold time
t RPC
10
—
10
—
10
—
ns
Data Sheet E0163H10
26
ct
Parameter
EO
HM538253B/HM538254B Series
Flash Write Cycle, Block Write Cycle, and Register Read Cycle
HM538253B/HM538254B
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Unit Notes
CAS to data-in delay time
t CDD
15
—
20
—
20
—
ns
13
OE to data-in delay time
t ODD
15
—
20
—
20
—
ns
13
LP
CBR Refresh with Register Reset
HM538253B/HM538254B
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Split transfer setup time
t STS
20
—
20
—
25
—
ns
Split transfer hold time referred to RAS
t RST
70
—
80
—
100 —
ns
Parameter
ro
Hyper Page Mode Cycle (HM538254B)
-7
HM538254B
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Unit Notes
Column address to CAS lead time
t CAL
Hyper page mode cycle time
t PC
Hyper page CAS precharge time
t CP
Hyper page data out hold time
—
30
—
35
—
ns
35
—
40
—
45
—
ns
5
—
10
—
10
—
ns
t DOH
4
—
5
—
5
—
ns
Data-out buffer turn-off time (RAS)
t RHZ
—
15
—
20
—
20
ns
5
Data-out buffer turn-off time (CAS)
t CHZ
—
15
—
20
—
20
ns
5
RAS to data-in delay time
t RDD
20
—
20
—
20
—
ns
13
ct
du
25
Data Sheet E0163H10
27
EO
HM538253B/HM538254B Series
Read Transfer Cycle
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
DT hold time referred to RAS
t RDH
60
10000
65
10000
80
10000
ns
DT hold time referred to CAS
t CDH
20
—
20
—
25
—
ns
DT hold time referred to
t ADH
25
—
30
—
30
—
ns
DT precharge time
t DTP
20
—
20
—
30
—
ns
DT to RAS delay time
t DRD
60
—
70
—
80
—
ns
SC to RAS setup time
t SRS
15
—
20
—
30
—
ns
1st SC to RAS hold time
t SRH
70
—
80
—
100 —
ns
1st SC to CAS hold time
t SCH
25
—
25
—
25
—
ns
1st SC to column address hold time
t SAH
40
—
45
—
50
—
ns
Last SC to DT delay time
t SDD
5
—
5
—
5
—
ns
1st SC to DT hold time
t SDH
10
—
13
—
15
—
ns
DT to QSF delay time
t DQD
—
30
—
35
—
35
ns
QSF hold time referred to DT
t DQH
5
—
5
—
5
—
ns
Serial data-in to 1st SC delay time
t SZS
0
—
0
—
0
—
ns
Serial clock cycle time
t SCC
25
—
28
—
30
—
ns
SC pulse width
t SC
5
—
10
—
10
—
ns
SC precharge time
t SCP
10
—
10
—
10
—
ns
SC access time
t SCA
—
20
—
23
—
25
ns
Serial data-out hold time
t SOH
5
—
5
—
5
—
ns
Serial data-in setup time
t SIS
0
—
Serial data-in hold time
t SIH
15
—
RAS to column address delay time
t RAD
15
35
Column address to RAS lead time
t RAL
35
—
RAS to QSF delay time
t RQD
—
70
CAS to QSF delay time
t CQD
—
35
QSF hold time referred to RAS
t RQH
20
—
QSF hold time referred to CAS
t CQH
5
—
du
ro
LP
Parameter
15
0
—
0
—
ns
15
—
15
—
ns
15
40
15
55
ns
40
—
45
—
ns
—
75
—
85
ns
15
—
35
—
35
ns
15
20
—
25
—
ns
5
—
5
—
ns
ct
Data Sheet E0163H10
28
15
EO
HM538253B/HM538254B Series
Masked Write Transfer Cycle
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
SC setup time referred to RAS
t SRS
15
—
20
—
30
—
ns
RAS to SC delay time
t SRD
20
—
25
—
25
—
ns
Serial output buffer turn-off time
referenced to RAS
t SRZ
10
30
10
35
10
50
ns
RAS to serial data-in delay time
t SID
30
—
35
—
50
—
ns
RAS to QSF delay time
t RQD
—
70
—
75
—
85
ns
15
CAS to QSF delay time
t CQD
—
35
—
35
—
35
ns
15
QSF hold time referred to RAS
t RQH
20
—
20
—
25
—
ns
QSF hold time referred to CAS
t CQH
5
—
5
—
5
—
ns
Serial clock cycle time
t SCC
25
—
28
—
30
—
ns
SC pulse width
t SC
5
—
10
—
10
—
ns
t SCP
10
—
10
—
10
—
ns
t SCA
—
20
—
23
—
25
ns
SC precharge time
SC access time
Serial data-out hold time
t SOH
Serial data-in setup time
t SIS
Serial data-in hold time
t SIH
ro
LP
Parameter
5
—
5
—
5
—
ns
0
—
0
—
0
—
ns
15
—
15
—
15
—
ns
15
ct
du
Data Sheet E0163H10
29
EO
HM538253B/HM538254B Series
Split Read Transfer Cycle, Masked Split Write Transfer Cycle
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Split transfer setup time
t STS
20
—
20
—
25
—
ns
Split transfer hold time referred to RAS
t RST
70
—
80
—
100 —
ns
Split transfer hold time referred to CAS
t CST
20
—
20
—
25
—
ns
Split transfer hold time referred to
column address
t AST
35
—
40
—
45
—
ns
SC to QSF delay time
t SQD
—
30
—
30
—
30
ns
QSF hold time referred to SC
t SQH
5
—
5
—
5
—
ns
Serial clock cycle time
t SCC
25
—
28
—
30
—
ns
SC pulse width
t SC
5
—
10
—
10
—
ns
t SCP
10
—
10
—
10
—
ns
t SCA
—
20
—
23
—
25
ns
Serial data-out hold time
t SOH
5
—
5
—
5
—
ns
Serial data-in setup time
t SIS
0
—
0
—
0
—
ns
Serial data-in hold time
t SIH
RAS to column address delay time
t RAD
Column address to RAS lead time
t RAL
SC precharge time
SC access time
Serial Read Cycle, Serial Write Cycle
ro
LP
Parameter
15
—
15
—
15
—
ns
15
35
15
40
15
55
ns
35
—
40
—
45
—
ns
15
15
du
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Serial clock cycle time
t SCC
25
—
28
—
30
—
ns
SC pulse width
t SC
5
—
10
—
10
—
ns
SC precharge width
t SCP
10
—
10
—
10
—
ns
Access time from SC
t SCA
—
20
—
23
—
25
ns
15
Access time from SE
t SEA
—
17
—
20
—
25
ns
15
Serial data-out hold time
t SOH
5
—
5
—
5
—
ns
Serial output buffer turn-off time referred t SHZ
to SE
—
15
—
20
—
20
ns
5,17
SE to serial output in low-Z
t SLZ
0
—
0
—
0
—
ns
5,17
Serial data-in setup time
t SIS
0
—
0
—
0
—
ns
Data Sheet E0163H10
30
ct
Parameter
EO
HM538253B/HM538254B Series
Serial Read Cycle, Serial Write Cycle (cont)
HM538253B/HM538254B
-7
-8
-10
Symbol Min Max
Min Max
Min Max
Unit Notes
Serial data-in hold time
t SIH
15
—
15
—
15
—
ns
Serial write enable setup time
t SWS
0
—
0
—
0
—
ns
Serial wrtie enable hold time
t SWH
15
—
15
—
15
—
ns
Serial write disable setup time
t SWIS
0
—
0
—
0
—
ns
Serial write disable hold time
t SWIH
15
—
15
—
15
—
ns
LP
Parameter
ct
du
ro
Notes: 1. AC measurements assume t T = 5 ns.
2. When t RCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT
is measured between VIH and VIL.
4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle
and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied.
5. t RHZ (max), tCHZ (max), tOFF1 (max), tOFF2 (max), tSHZ (max) and tSLZ (min) are defined as the time at
which the output acheives the open circuit condition (VOH – 100 mV, VOL + 100 mV). This parameter
is sampled and not 100% tested.
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
7. Measured with a load circuit equivalent to 1 TTL loads and 50 pF.
8. When t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max), access time is specified by tCAC .
9. When t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max), access time is specified by tAA .
10. If either tRCH or tRRH is satisfied, operation is guaranteed. (HM538253)
If both tRCH and t RRH are satisfied, operation is guaranteed, (HM538254)
11. When t WCS ≥ tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high
impedance) condition.
12. These parameters are specified by the later falling edge of CAS or WE.
13. Either t CDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or
OE prior to applying data to the device when output buffer is on. (HM538253B)
Either t CDD (min), tODD (min) or tRDD (min) must be satisfied because the output buffer must be turned
off by CAS, OE or RAS prior to applying data to the device when output buffer is on. (HM538254B)
14. When t AWD ≥ tAWD (min) and tCWD ≥ tCWD (min) in read-modify-write cycle, the data of the selected
address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be
satisfied because output buffer must be turned off by OE prior to applying data to the device.
15. Measured with a load circuit equivalent to 1 TTL loads and 30 pF.
16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory
cycle or refresh cycle), then start operation. Hitachi recommends that least 8 initialization cycle is
CBRR for internal register reset.
17. When t SHZ and t SLZ are measured in the same V CC and Ta condition and tr and tf of SE are less than
5 ns, t SHZ < tSLZ + 5 ns.
18. After power-up, QSF output may be High-Z, so 1SC cycle is needed to be Low-Z it.
19. DSF 2 pin is open pin, but Hitachi recommends it is fixed low in all operation for the addition mode
in future.
Data Sheet E0163H10
31
EO
HM538253B/HM538254B Series
20. XXX: H or L (H : VIH (min) ≤ V IN ≤ V IH (max), L : VIL (min) ≤ V IN ≤ V IL (max)
///////: Invalid Dout
Timing Waveforms*20
Read Cycle (HM538253B)
LP
RAS
t RC
t RAS
t CRP
t CSH
t RSH
t CAS
t RCD
CAS
t ASR
Address
WE
Row
t RAL
t CAL
t CAH
Column
t RCS
t DZC
I/O
(Input)
t DZO
t DTS
t DTH
t FSR
t RFH
DT/OE
DSF1
t ASC
t RRH
t FSC
t RCH
t CAC
t AA
t CDD
t OFF1
t RAC
ro
I/O
(Output)
t RAD
t RAH
t RP
t OAC
Valid Dout
t OFF2
t CFH
ct
du
Data Sheet E0163H10
32
EO
HM538253B/HM538254B Series
Fast Page Mode Read Cycle (HM538253B)
t RC
t RASP
RAS
WE
I/O
(Output)
I/O
(Input)
DT/OE
t RAH
t ASC
t CAL
t CAH
Row
Column
t RCS
t RCH
Column
t RCS t RCH
t AA
t ACP
t CAC
t DTS
t DZO
t DTH
t FSR
t RFH
t CDD
t OAC t OFF2
t FSC
t CFH
t RCS
t OFF1
Valid
Dout
t DZC
t CAL
t CAH
t ASC
Column
t RAC t OFF1
t AA
t CAC
t DZC
t OAC
t OFF1
Valid Dout
t CDD
t OFF2
t DZC
t FSC
t CFH
t RRH
t RCH
t AA
t ACP
t CAC
Valid
Dout
t FSC
t CRP
t RAL
t CAL
t CAH
t ASC
t RSH
t CAS
t CP
t CAS
t CDD
t OAC
t CFH
ct
du
ro
DSF1
t RAD
t ASR
t CP
LP
Address
t PC
t CSH
t CAS
t RCD
CAS
t RP
Data Sheet E0163H10
33
EO
HM538253B/HM538254B Series
Write Cycle
Table 3 below applies to early write, delayed write, page mode write, and read-modify write.
Table 3
Menu
Write Cycle State
Cycle
RAS
CAS
RAS
RAS
CAS
DSF1
DSF1
WE
I/O
I/O
W1
W2
W3
W4
W5
LP
*1
RWM
Write mask (new/old)
Write DQs to I/Os
0
0
0
Write mask
Valid data
BWM
Write mask (new/old)
Block write
0
1
0
Write mask*2
Column mask*2
RW
Normal write (no mask)
0
0
1
Don’t care*1
Valid data
*2
BW
Block write (no mask)
0
1
1
Don’t care
Column mask*2
LMR*4
Load write mask resister
1
0
1
Don’t care
Write mask data*3
LCR*4
Load color resister
1
1
1
Don’t care
Color data
Notes: 1.
Mode
I/O data/RAS
Low
New mask mode
Mask
Persistent mask mode
H or L (mask register used)
No mask
H or L
High
I/O Mask data (In new mask mode)
Low:
Mask
High:
Non mask
In persistent mask mode, I/O H or L
2. Reference Figure 2 use of block write.
3. I/O write mask data
Low:
Mask
High:
Non mask
4. Column Address: H or L
ct
du
ro
WE
Data Sheet E0163H10
34
EO
HM538253B/HM538254B Series
Early Write Cycle
t RC
t RAS
t RP
RAS
CAS
t ASR
I/O
(Output)
I/O
(Input)
DT/OE
t ASC
t CAH
Column
t WH
t WCS
t WCH
W3
t MH
t MS
W4
t DTS
High-Z
t DH
t DS
W5
t DTH
t FSR
DSF1
t RAH
Row
t WS
WE
t RSH
t CAS
LP
Address
t CRP
t CSH
t RCD
W1
t RFH
t CFH
t FSC
W2
ct
du
ro
WI to W5: See write cycle state table for the logic states.
Data Sheet E0163H10
35
EO
HM538253B/HM538254B Series
Delayed Write Cycle
t RC
t RAS
t RP
RAS
t CAS
CAS
t ASR
t RAH
t WS
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
t ASC
Row
t CAH
Column
LP
Address
t CRP
t CSH
t RSH
t RCD
t RWL
t WH
t MS
t MH
t DH
t DS
t DZC
W5
W4
t DTS
t DTH
t FSR
t RFH
t OFF2
t ODD
t FSC
W1
t CWL
t WP
W3
t OEH
t CFH
W2
ro
WI to W5: See write cycle state table for the logic states.
Fast/Hyper Page Mode Write Cycle (Early Write)
t RC
t RP
t RASP
t CSH
t RCD
CAS
Address
t ASR
t RAH t ASC
t CAS
t RSH
t CAS
t CP
t CAH t ASC
Column
t CAH
t WCS t WCH
t WCS t WCH
High-Z
t MS
t MH
t DS
DT/OE
t FSR
t DH
t DS
W5
t DH
t DH
t DS
W5
W5
t DTH
t RFH
t FSC
W1
t CFH
W2
t FSC
t CFH
W2
t FSC
t CFH
W2
WI to W5: See write cycle state table for the logic states.
Data Sheet E0163H10
ct
W4
t DTS
36
t CRP
Column
W3
I/O
(Input)
DSF1
t CP
t CAH t ASC
Row
Column
t WS t WH t WCS t WCH
WE
I/O
(Output)
t PC
t CAS
du
RAS
EO
HM538253B/HM538254B Series
Fast/Hyper Page Mode Write Cycle (Delayed Write)
t RC
t RASP
t RP
RAS
CAS
t CSH
t PC
t RCD
t ASR t RAH t ASC
Column
Row
t WS
t CRP
t CAS
t ASC
t CAH
Column
t CAH
Column
t RWL
t CWL
t CWL
t WH
t RSH
t CP
t CAS
t ASC
t CAH
LP
Address
t CP
t CAS
t WP
t CWL
t WP
t WP
W3
WE
I/O
(Output)
t MS
I/O
(Input)
t MH
High-Z
t DS t DH
t DS t DH
t DS t DH
W5
W5
W5
W4
t OEH
t DTS
DT/OE
t FSR
DSF1
t RFH t FSC
W1
t CFH
t FSC t CFH
W2
t FSC
W2
t CFH
W2
ro
WI to W5: See write cycle state table for the logic states.
Read-Modify-Write Cycle
t RWC
t RP
t RWS
RAS
t RAD
t ASR
Address
t CAH
Column
t WH
t AWD
t CWD
t RCS
t CAC
t AA
W3
WE
t RAC
t RWL
t CWL
t WP
Valid Dout
t MS
t MH
W4
t DTS
t OAC
t DZC
t DTH
t OFF2
t ODD
t DZO
DT/OE
t RFH
t FSR
DSF1
W1
t FSC
t CRP
t CFH
W2
WI to W5: See write cycle state table for the logic states.
t DS
t DH
W5
ct
I/O
(Input)
t ASC
Row
t WS
I/O
(Output)
t RAH
du
t RCD
CAS
t OEH
Data Sheet E0163H10
37
EO
HM538253B/HM538254B Series
RAS-Only Refresh Cycle (HM538253B)
t RC
t RP
t RAS
RAS
t RPC
t CRP
CAS
t ASR
t RAH
Row
Address
I/O
(Output)
LP
t OFF1
t CDD
I/O
(Input)
DT/OE
DSF1
t OFF2
t ODD
t DTS
t DTH
t FSR
t RFH
WE : H or L
ro
CAS-Before-RAS Refresh Cycle (CBRN) (HM538253B)
t RP
RAS
t RPC
t CP
t CSR
t CHR
CAS
t WS
t WH
WE
t OFF1
High-Z
I/O
(Output)
DT/OE
t FSR
DSF1
t RFH
t RP
t RPC
t CSR
Inhibit Falling Transition
ct
du
Address
t RC
t RAS
SC : H or L
Data Sheet E0163H10
38
EO
HM538253B/HM538254B Series
Hidden Refresh Cycle (HM538253B)
t RC
t RAS
t RC
t RAS
t RP
t RP
RAS
t RCD
CAS
Address
t CRP
t CHR
t RAD t RAL
t RAH t
ASC t CAH
Row
Column
t RCS
LP
WE
t ASR
t RSH
t RRH
t WH
t WS
t CAC
t AA
t RAC
I/O
(Output)
I/O
(Input)
t DZC
DSF1
t FSR
Valid Dout
t OAC
t OFF2
t DZO
t DTH
t DTS
DT/OE
t OFF1
t RFH
t FSR
t CFH
t FSC
ro
CAS-Before-RAS Set Cycle (CBRS)
t RFH
t RC
t RAS
t RP
RAS
t CSR
t CHR
du
t RPC
t RP
t CRP
Inhibit falling transition
CAS
t ASR
Address*1
(A2-A7)
t RAH
Stop Address
t WS t WH
WE
High-Z
DT/OE
t FSR
t RFH
DSF1
Note: A0, A1, A8: H or L
SC: H or L
ct
I/O
(Output)
I/O
(Input)
Data Sheet E0163H10
39
EO
HM538253B/HM538254B Series
CAS-Before-RAS Reset Cycle (CBRR)
t RC
t RP
t RAS
t RP
RAS
t RPC
t CSR
t CHR
t CRP
Inhibit falling transition
CAS
t WS
WE
I/O
(Output)
I/O
(Input)
DT/OE
t FSR
DSF1
t STS
SC
Bi*1
t WH
High-Z
t RFH
t RST
ro
LP
Address
Bj-2
Bj-1
Bj*1
Notes: 1. Bi, Bj initiate the boundary addresses.
When a CBRR is executed for stopping column operation reset and split transfer
operation, it needs to satisfy tSTS (min) and tRST (min) between RAS falling and
SC rising.
2. Ym, Yn are the SAM start address in before SRT/MSWT.
ct
du
Data Sheet E0163H10
40
EO
HM538253B/HM538254B Series
Flash Write Cycle (HM538253B)
t RC
t RAS
t RP
RAS
t CRP
CAS
t RCD
t ASR
LP
t WS
WE
t OFF1
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
t RAH
Row
Address
t OFF2
t WH
t CDD
t MS
t ODD
t DTS
High-Z
t MH
Mask Data
t DTH
t FSR
t RFH
ct
du
ro
Data Sheet E0163H10
41
EO
HM538253B/HM538254B Series
Register Read Cycle (Mask data, Color data) (HM538253B)
t RC
t RAS
t RP
RAS
CAS
WE
t RAH
Row
t WS t WH
I/O
(Input)
t CAC
DSF1
t CDD
Valid Out
t OFF2
t OAC
t ODD
t DZO
t DTH
t RFH
t FSC
ro
t FSR
t RCH
t OFF1
t DZC
t DTS
DT/OE
t RRH
t RCS
t RAC
I/O
(Output)
t RSH
t CAS
LP
Address
t ASR
t CRP
t CSH
t RCD
t CFH
*1
Note: 1. State of DFS1 at falling edge of CAS
State
Mask data
(LMR)
1
Color data
(LCR)
ct
du
Accessed
data
0
Data Sheet E0163H10
42
EO
HM538253B/HM538254B Series
Read Transfer Cycle 1
t RC
t RP
t RAS
RAS
t CRP
t CSH
t RCD
t RSH
t CAS
CAS
Row
t WS
WE
I/O
(Output)
t RAL
t ASC t CAH
LP
Address
t RAD
t RAH
t ASR
SAM Start
Address
t WH
High-Z
t CDH
t DTS
DT/OE
t FSR
DSF1
SI/O
(Input)
Valid Sout
t RDH
t SCC
t SCA
t SOH
Valid Sout
t SCC
t SCC
t SDH
t SDD
ro
SI/O
(Output)
t SCA
t SOH
t DTP
t RFH
t SCC
SC
t DRD
t ADH
t SCP
t SCA
t SCA
t SOH
Valid Sout
t SC
t SOH
t SOH
Valid Sout
Valid Sout
Previous Row
New Row
High-Z
t DQD
t DQH
QSF
SAM Address MSB
ct
du
Data Sheet E0163H10
43
EO
HM538253B/HM538254B Series
Read Transfer Cycle 2
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RSH
t CAS
t RCD
CAS
t RAD
t RAH
t RAL
t ASC
t CAH
LP
t ASR
Address
SAM Start
Address
Row
t WS
WE
I/O
(Output)
t DTS
DT/OE
t FSR
DSF1
t WH
High-Z
t DTH
t DRD
t DTP
t RFH
t SRS
t SDH
t SAH
ro
t SC
t SCP
t SCC
t SC
Inhibit Rising Transition
SC
t SOH
t SRH
t SIH
Valid
Sin
t RQD
t RQH
Valid Sout
t SZS
t CQD
t DQD
t CQH
du
SI/O
(Input)
t SIS
t SCA
t SCA
t SCH
SI/O
(Output)
t SCP
t DQH
QSF
SAM Address MSB
ct
Data Sheet E0163H10
44
EO
HM538253B/HM538254B Series
Masked Write Transfer Cycle
t RC
t RP
t RAS
RAS
CAS
t RAH
t RSH
t CAS
t ASC
t CAH
LP
Address
t ASR
t CRP
t CSH
t RCD
SAM Start
Address
Row
t WS t WH
WE
I/O
(Output)
DT/OE
High-Z
t DTS t DTH
t FSR t RFH
DSF1
SC
SI/O
(Output)
SI/O
(Input)
t SCA
Valid
t SRZ
High-Z
I/O
(Input)
t SCC
t SC t SCP
t CQD
I/O Mask Data *1
Valid Sin
t SIS t SIH
Valid Sin
ct
Note: 1. I/O mask data (In new mask mode)
Low: Mask
High: Non mask
I/O: H or L in persistent mask mode.
t SIS t SIH
du
t CQH
t RQD
t RQH
SAM Address MSB
t MS t MH
QSF
t SCP
Inhibit Rising Transition
t SID
Valid
t SOH
t SRD
ro
t SRS
t SC
Data Sheet E0163H10
45
EO
HM538253B/HM538254B Series
Split Read Transfer Cycle (HM538253B)
t RC
t RP
t RAS
RAS
t CSH
t CRP
t RAD
t ASR
t RAL
t RAH
LP
t CAH
t ASC
SAM Start
Address Yi
Row
t WS
WE
t CRP
t CAS
CAS
Address
t RSH
t RCD
t WH
t OFF1
I/O
(Output)
DT/OE
DSF1
t DTS
t DTH
t FSR
t RFH
High-Z
ro
t CST
t AST
t RST
t SCC
t SC
t STS
SC
Bi *2
Ym*1
t SQD
QSF
Valid
Sout
Valid
Sout
Valid
Sout
High-Z
t SQH
Bj – 2
Bj – 1
Valid
Sout
du
SI/O
(Input)
Ym + 2
Bj *2
t SOH
t SOH
Valid Sout
Ym + 1
t SCA
t SCA
SI/O
(Output)
t SCP
Valid
Sout
t SQD
t SQH
SAM Address MSB
ct
Notes: 1. Ym is the SAM start address in before SRT.
2. Bi, Bj initiate the boundary address.
3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t set on the boundary address.
Data Sheet E0163H10
46
Yi
EO
HM538253B/HM538254B Series
t ASR t RAH
t ASC t CAH
Address
Row
SAM Start
Address Yi
Masked Split Write Transfer Cycle (HM538253B)
t RC
t RAS
t RP
RAS
t CSH
t RSH
t CAS
t RCD
CAS
LP
t WS tWH
WE
t OFF1
I/O
(Output)
High-Z
t DTS t DTH
DT/OE
t FSR t RFH
ro
DSF1
t RST
Bi*2
Ym*1
Ym+1
t SIS t SIH
Valid
Sin
t SIS t SIH
Valid
Sin
Valid
Sin
t SQD
t SQH
Valid
Sin
Bj-2
Bj-1
Bj*2
Yi
t SIS t SIH
Valid
Sin
Valid
Sin
Valid
Sin
t SQD
t SQH
SAM Address MSB
QSF
t CDD t MS
I/O
(Input)
Ym+2
du
SI/O
(Output)
SI/O
(Input)
t CST
t SCC
t SC t SCP
t STS
SC
t AST
t MH
I/O Mask Data*3
ct
Notes: 1. Ym is the SAM start address in before MSWT.
2. Bi, Bj initiate the boundary address.
3. I/O Mask data (In new mask mode)
Low: Mask
High: Non mask
I/O: H or L in persistent mask mode.
4. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t set on the boundary address.
Data Sheet E0163H10
47
EO
HM538253B/HM538254B Series
Serial Read Cycle
SE
SC
SI/O
(Output)
tSCC
tSCC
tSC
tSCP
tSCA
tSOH
Valid Sout
tSWIH
SI/O
(Input)
tSCC
tSCC
tSC
tSCP
tSC
tSCP
tSIS
tSIH
tSC
tSCP
tSIH
tSIS
Valid Sin
Valid Sin
tSIH
Valid Sin
ro
Read Cycle (HM538254B)
Valid
Sout
tSWS
tSCC
tSIS
tSCA
tSOH
tSEA
tSCA
tSLZ
LP
tSWIS
tSC
SC
tSC
Valid Sout
tSWH
SE
tSCC
tSCP
tSC
tSHZ
Valid Sout
Serial Write Cycle
tSCP
tSC
t RC
t RAS
RAS
t RP
t CRP
t CSH
CAS
t ASR
Address
t RAL
t RAD
t RAH
t ASC
Row
t CAH
Column
t RCS
WE
t RAC
t RHZ
t RCH
t CDD
t CHZ
Valid Dout
t DZO
t DTS
t DTH
t FSR
t RFH
t RDD
DT/OE
t FSC
t OFF2
ct
t OAC
t DZC
I/O
(Input)
t CFH
DSF1
Data Sheet E0163H10
48
t CAL
t RRH
t CAC
t AA
I/O
(Output)
du
t RSH
t CAS
t RCD
t ODD
EO
HM538253B/HM538254B Series
Hyper Page Mode Read Cycle (HM538254B)
t RC
t RASP
RAS
WE
I/O
(Output)
I/O
(Input)
DT/OE
t RAD
t ASR
t RAH t ASC
t CP
t CAL
t CAH
Row
Column
t RCS
t DZO
t DTH
t FSR
t RFH
Column
Column
t RRH
t CFH
Valid Dout
t DOH
t CHZ
t RHZ
Valid Dout
t CDD
t ODD
t DOH
t RDD
t OFF2
t FSC
t FSC
t CFH
t CFH
ro
RAS-Only Refresh Cycle (HM538254B)
t RCH
t AA
t ACP
t CAC
t AA
t ACP
t CAC
t OAC
t FSC
DSF1
t CAL
t CAH
t ASC
Valid Dout
t DTS
t CRP
t RAL
t CAL
t CAH
t RAC
t AA
t CAC
t DZC
t RSH
t CAS
t CP
t CAS
t ASC
LP
Address
t PC
t CSH
t CAS
t RCD
CAS
t RP
t RC
t RP
t RAS
t RPC
t CRP
CAS
t ASR
t RAH
Row
Address
t CHZ
I/O
(Output)
t CDD
I/O
(Input)
du
RAS
t OFF2
t ODD
t DTH
t FSR
t RFH
DT/OE
DSF1
ct
t DTS
WE : H or L
Data Sheet E0163H10
49
EO
HM538253B/HM538254B Series
CAS-Before-RAS Refresh Cycle (CBRN) (HM538254B)
RAS
t RC
t RP
t RP
t RAS
t RPC
t CP
t CSR
t RPC
t CHR
CAS
t CSR
Inhibit Falling Transition
Address
t CHZ
t RHZ
I/O
(Output)
DT/OE
t WH
LP
WE
t WS
High-Z
t FSR
DSF1
t RFH
SC : H or L
Hidden Refresh Cycle (HM538254B)
ro
t RC
t RAS
RAS
t RCD
CAS
t ASR
Address
t RP
t RSH
t RRH
t CAC
t AA
t RAC
t WS
t WH
t CHZ
t RHZ
Valid Dout
t DZC
I/O
(Input)
t DTS
t FSR
t OAC
t DZO
t DTH
t RFH
t FSC
t CFH
t FSR
t OFF2
t RFH
ct
DSF1
Data Sheet E0163H10
50
t CRP
t CHR
du
Column
t RCS
WE
DT/OE
t RP
t RAD t RAL
t RAH t
ASC t CAH
Row
I/O
(Output)
t RC
t RAS
EO
HM538253B/HM538254B Series
Flash Write Cycle (HM538254B)
t RC
t RAS
t RP
RAS
t CRP
CAS
t RCD
t ASR
Row
Address
t CHZ
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
t WS
t WH
LP
WE
t RAH
t OFF2
t CDD
t MS
t ODD
t DTS
High-Z
t MH
Mask Data
t DTH
t FSR
t RFH
ct
du
ro
Data Sheet E0163H10
51
EO
HM538253B/HM538254B Series
Register Read Cycle (Mask data, Color data) (HM538254B)
t RC
t RAS
t RP
RAS
CAS
WE
t RAH
Row
t WS t WH
I/O
(Input)
t FSR
t RHZ
Valid Out
t OFF2
t ODD
t OAC
t DZO
t RDD
t DTH
t RFH
t FSC
t CFH
ro
DSF1
t RCH
t CDD
t CHZ
t CAC
t DZC
t DTS
DT/OE
t RRH
t RCS
t RAC
I/O
(Output)
t RSH
t CAS
LP
Address
t ASR
t CRP
t CSH
t RCD
*1
Note: 1. State of DFS1 at falling edge of CAS
State
Mask data
(LMR)
1
Color data
(LCR)
ct
du
Accessed
data
0
Data Sheet E0163H10
52
EO
HM538253B/HM538254B Series
Split Read Transfer Cycle (HM538254B)
t RC
t RP
t RAS
RAS
t CSH
t CRP
t RAD
t ASR
t RAL
t RAH
LP
t CAH
t ASC
SAM Start
Address Yi
Row
t WS
WE
t CRP
t CAS
CAS
Address
t RSH
t RCD
t WH
t CHZ
I/O
(Output)
DT/OE
DSF1
t DTS
t DTH
t FSR
t RFH
High-Z
ro
t CST
t AST
t RST
t SCC
t SC
t STS
SC
Bi *2
Ym*1
t SQD
QSF
Valid
Sout
Valid
Sout
Valid
Sout
High-Z
t SQH
Bj – 2
Bj – 1
Valid
Sout
du
SI/O
(Input)
Ym + 2
Bj *2
Yi
t SOH
t SOH
Valid Sout
Ym + 1
t SCA
t SCA
SI/O
(Output)
t SCP
Valid
Sout
t SQD
t SQH
SAM Address MSB
ct
Notes: 1. Ym is the SAM start address in before SRT.
2. Bi, Bj initiate the boundary address.
3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t on the boundary address.
Data Sheet E0163H10
53
EO
HM538253B/HM538254B Series
t ASR t RAH
t ASC t CAH
Address
Row
SAM Start
Address Yi
Masked Split Write Transfer Cycle (HM538254B)
t RC
t RAS
t RP
RAS
t CSH
t RSH
t CAS
t RCD
CAS
LP
t WS tWH
WE
t CHZ
I/O
(Output)
High-Z
t DTS t DTH
DT/OE
t FSR t RFH
DSF1
ro
t RST
Ym*1
Bi*2
Ym+1
SI/O
(Output)
Valid
Sin
t SQD
t SQH
t SIH
t SIS t SIH
Valid
Sin
Valid
Sin
Invalid
Dout
Valid
Sin
Bj-2
Bj-1
Bj*2
Yi
t SIS t SIH
Valid
Sin
Valid
Sin
Valid
Sin
t SQD
t SQH
SAM Address MSB
QSF
t CDD t MS
I/O
(Input)
Ym+2
du
t SIS
SI/O
(Input)
t CST
t SCC
t SC t SCP
t STS
SC
t AST
t MH
I/O Mask Data*3
ct
Notes: 1. Ym is the SAM start address in before MSWT.
2. Bi, Bj initiate the boundary address.
3. I/O Mask data (In new mask mode)
Low: Mask
High: Non mask
I/O: H or L in persistent mask mode.
4. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t set or the boundary address.
Data Sheet E0163H10
54
EO
HM538253B/HM538254B Series
Package Dimensions
HM538253BJ/HM538254BJ Series (CP-40D)
Unit: mm
25.80
26.16 Max
0.80
1.30 Max
+0.25
–0.17
3.50 ± 0.26
20
0.74
0.31
2.30 +– 0.14
10.16 ± 0.13
LP
1
11.18 ± 0.13
21
40
1.27
0.43 ± 0.10
9.40 ± 0.25
ro
0.10
HM538253BTT/HM538254BTT Series (TTP-44/40DA)
10.16
23
0.30 ± 0.10
10 13
0.80
22
0.21 M
0.10
0.17 ± 0.05
1.20 Max
2.40
ct
11.76 ± 0.20
1.005 Max
0.13 ± 0.05
1
du
44
18.41
18.81 Max
35 32
Unit: mm
0 – 5°
0.80
0.50 ± 0.10
Data Sheet E0163H10
55
EO
HM538253B/HM538254B Series
Cautions
ct
du
ro
LP
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information contained in this
document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage
when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as
fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury,
fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
Data Sheet E0163H10
56