DATA SHEET MOS INTEGRATED CIRCUIT MC-4516CD642XS 16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM) Description EO The MC-4516CD642XS is 16,777,216 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on which 8 pieces of 128M SDRAM: µPD45128163 are assembled. This module provide high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features L • 16,777,216 words by 64 bits organization • Clock frequency and access time from CLK Part number /CAS latency Clock frequency (MAX.) Access time from CLK (MAX.) CL = 3 133 MHz 5.4 ns CL = 2 100 MHz 6 ns CL = 3 133 MHz 5.4 ns CL = 2 100 MHz 6 ns MC-4516CD642XS-A75 Pr MC-4516CD642XS-A75L • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle od • Quad internal banks controlled by BA0, BA1 (Bank Select) • Programmable burst-length: 1, 2, 4, 8 and Full Page • Programmable wrap sequence (Sequential / Interleave) • Programmable /CAS latency (2, 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • LVTTL compatible • 4,096 refresh cycles/64 ms • Burst termination by Burst Stop command and Precharge command • 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm) • Unbuffered type • Serial PD t uc • Single 3.3 V ± 0.3 V power supply The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0116N20 (Ver. 2.0) Date Published September 2001 (K) Printed in Japan This product became EOL in March, 2004. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. MC-4516CD642XS Ordering Information Part number Clock frequency Package Mounted devices MHz (MAX.) MC-4516CD642XS-A75 MC-4516CD642XS-A75L 133 MHz 133 MHz 144-pin Small Outline DIMM 8 pieces of µPD45128163G5 (Rev. X) (Socket Type) (10.16 mm (400) TSOP (II)) Edge connector: Gold plated 31.75 mm height L EO t uc od Pr 2 Data Sheet E0116N20 MC-4516CD642XS Pin Configuration 144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss NC NC Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss NC NC L EO 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 CKE0 CLK0 Vcc Vcc /CAS /RAS CKE1 /WE NC /CS0 NC /CS1 CLK1 NC Vss Vss NC NC NC NC VCC Vcc DQ 48 DQ 16 DQ 49 DQ 17 DQ 50 DQ 18 DQ 51 DQ 19 Vss Vss DQ 52 DQ 20 DQ 53 DQ 21 DQ 54 DQ 22 DQ 55 DQ 23 Vcc Vcc A7 A6 BA0 (A13) A8 Vss Vss BA1 (A12) A9 A11 A10 Vcc Vcc DQMB6 DQMB2 DQMB7 DQMB3 Vss Vss DQ 56 DQ 24 DQ 57 DQ 25 DQ 58 DQ 26 DQ 59 DQ 27 VCC Vcc DQ 60 DQ 28 DQ 61 DQ 29 DQ 62 DQ 30 DQ 63 DQ 31 Vss Vss SCL SDA VCC Vcc 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 /xxx indicates active low signal. Pr A0 - A11 : Address Inputs [Row: A0 - A11, Column: A0 - A8] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63 : Data Inputs/Outputs CLK0, CLK1 : Clock Input od Data Sheet E0116N20 CKE0, CKE1 : Clock Enable Input /CS0, /CS1 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable SDA SCL VCC VSS NC t uc 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : No Connection 3 MC-4516CD642XS Block Diagram CKE1 CKE0 /CS1 /CS0 UDQM /CS CKE DQ 7 LDQM /CS CKE DQ 8 DQMB1 DQ 8 DQ 1 DQ 6 DQ 9 DQ 2 DQ 5 DQ 3 UDQM /CS CKE DQ 7 LDQM /CS CKE DQ 9 DQ 6 DQ 9 DQ 10 DQ 10 DQ 5 DQ 10 DQ 4 DQ 11 DQ 11 DQ 4 DQ 11 DQ 4 DQ 3 DQ 12 DQ 12 DQ 3 DQ 12 DQ 5 DQ 2 DQ 13 DQ 13 DQ 2 DQ 13 DQ 6 DQ 1 DQ 14 DQ 14 DQ 1 DQ 7 DQ 0 DQ 15 DQ 0 DQMB0 DQ 0 D0 D4 DQ 14 D2 LDQM DQ 0 DQ 15 UDQM DQ 0 DQ 1 DQ 41 DQ 14 DQ 1 DQ 13 DQ 2 DQ 42 DQ 13 DQ 2 DQ 35 DQ 12 DQ 3 DQ 43 DQ 12 DQ 3 DQ 36 DQ 11 DQ 4 DQ 44 DQ 11 DQ 4 DQ 37 DQ 10 DQ 5 DQ 45 DQ 10 DQ 5 DQ 38 DQ 9 DQ 6 DQ 46 DQ 9 DQ 6 DQ 39 DQ 8 DQ 7 DQ 47 DQ 8 DQ 7 DQMB4 DQ 32 LDQM UDQM DQ 15 DQ 33 DQ 14 DQ 34 D6 LDQM /CS CKE LDQM /CS CKE DQ 8 DQMB3 DQ 24 UDQM /CS CKE DQ 7 DQ 7 DQ 8 DQ 6 DQ 9 DQ 25 DQ 6 DQ 9 DQ 18 DQ 5 DQ 10 DQ 26 DQ 5 DQ 10 DQ 19 DQ 4 DQ 11 DQ 27 DQ 4 DQ 11 DQ 20 DQ 3 DQ 21 DQ 2 DQ 22 DQ 1 DQ 23 DQ 0 DQ 17 Pr UDQM /CS CKE DQMB2 DQ 16 D1 DQ 12 DQ 28 DQ 3 DQ 12 DQ 13 DQ 29 DQ 2 DQ 13 DQ 14 DQ 30 DQ 1 DQ 31 DQ 0 DQ 15 LDQM DQMB6 UDQM D5 DQ 14 D3 UDQM DQ 0 DQ 15 DQ 0 DQ 1 DQ 57 DQ 14 DQ 1 DQ 2 DQ 58 DQ 13 DQ 2 DQ 59 DQ 12 DQ 3 DQ 60 DQ 11 DQ 4 DQ 61 DQ 10 DQ 5 DQ 62 DQ 9 DQ 6 DQ 63 DQ 8 DQ 7 DQ 15 DQ 49 DQ 14 DQ 50 DQ 13 DQ 51 DQ 12 DQ 3 DQ 52 DQ 11 DQ 4 DQ 53 DQ 10 DQ 5 DQ 54 DQ 9 DQ 6 DQ 55 DQ 8 DQ 7 od LDQM DQ 48 VCC SDA A1 A2 CLK0 CLK1 /RAS A0 - A11 A0 - A11 : D0 - D7 BA0 A13 : D0 - D7 BA1 A12 : D0 - D7 /CAS /WE Remarks 1. D0 - D7: µPD45128163 (2M words x 16 bits x 4 banks) 2. The value of all resistors is 10 Ω. Data Sheet E0116N20 t uc SCL VSS D7 D0 - D7 C A0 DQ 15 DQMB7 DQ 56 SERIAL PD 4 DQ 15 DQMB5 DQ 40 L EO DQ 15 DQ 8 D0 - D7 CLK : D0 - D3 CLK : D4 - D7 /RAS : D0 - D7 /CAS : D0 - D7 /WE : D0 - D7 MC-4516CD642XS Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit VCC –0.5 to +4.6 V Voltage on input pin relative to GND VT –0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 8 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C EO Voltage on power supply pin relative to GND Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating L conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage Symbol Condition VCC Low level input voltage Operating ambient temperature Pr High level input voltage MIN. TYP. MAX. Unit 3.0 3.3 3.6 V VIH 2.0 VCC + 0.3 V VIL –0.3 +0.8 V TA 0 70 °C MAX. Unit pF Capacitance (TA = 25 °C, f = 1 MHz) Input capacitance Symbol CI1 od Parameter Test condition MIN. TYP. A0 - A11, BA0 (A13), BA1 (A12), 30 60 /RAS, /CAS, /WE CLK0, CLK1 23 37 CI3 CKE0, CKE1 18 30 CI4 /CS0, /CS1 18 30 CI5 DQMB0 - DQMB7 7 14 CI/O DQ0 - DQ63 9 18 Data Sheet E0116N20 t uc Data input/output capacitance CI2 pF 5 MC-4516CD642XS DC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Operating current Symbol ICC1 Precharge standby current in power down mode Precharge standby current in ICC2P ICC2PS ICC2N non power down mode EO power down mode Active standby current in ICC3P ICC3PS ICC3N non power down mode Operating current Burst length = 1, tRC ≥ tRC (MIN.) Unit Notes /CAS latency = 2 560 mA 1 /CAS latency = 3 580 8 CKE ≤ VIL (MAX.), tCK = ∞ 8 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 160 CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. 64 CKE ≤ VIL (MAX.), tCK = 15 ns 40 CKE ≤ VIL (MAX.), tCK = ∞ 32 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 240 mA mA mA mA Input signals are changed one time during 30 ns. ICC3NS ICC4 CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. 160 tCK ≥ tCK (MIN.), IO = 0 mA /CAS latency = 2 700 /CAS latency = 3 860 ICC5 /CAS latency = 2 1,040 /CAS latency = 3 1,080 tRC ≥ tRC (MIN.) L Self refresh current MAX. CKE ≤ VIL (MAX.), tCK = 15 ns (Burst mode) CBR (Auto) refresh current MIN. Input signals are changed one time during 30 ns. ICC2NS Active standby current in Test condition ICC6 CKE ≤ 0.2 V mA 2 mA 3 -** 16 mA -**L 6.4 mA –8 +8 µA IO(L) DOUT is disabled, VO = 0 to 3.6 V –3 +3 µA High level output voltage VOH IO = –4.0 mA 2.4 Low level output voltage VOL IO = +4.0 mA II(L) Output leakage current Pr VI = 0 to 3.6 V, All other pins not under test = 0 V Input leakage current V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In od addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). t uc 6 Data Sheet E0116N20 MC-4516CD642XS AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter AC high level input voltage / low level input voltage Value Unit 2.4 / 0.4 V 1.4 V 1 ns 1.4 V Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level CLK tCL 2.4 V 1.4 V 0.4 V tSETUP tHOLD Input 2.4 V 1.4 V 0.4 V L EO tCK tCH tAC tOH Output t uc od Pr Data Sheet E0116N20 7 MC-4516CD642XS Synchronous Characteristics Parameter Clock cycle time Access time from CLK Symbol -A75 Unit MIN. MAX. Note /CAS latency = 3 tCK3 7.5 (133 MHz) ns /CAS latency = 2 tCK2 10 (100 MHz) ns /CAS latency = 3 tAC3 5.4 ns 1 /CAS latency = 2 tAC2 6 ns 1 CLK high level width tCH 2.5 ns CLK low level width tCL 2.5 ns /CAS latency = 3 tOH3 3 ns 1 /CAS latency = 2 tOH2 3 ns 1 tLZ 0 ns /CAS latency = 3 tHZ3 3 5.4 ns /CAS latency = 2 tHZ2 3 6 ns Data-in setup time tDS 1.5 ns Data-in hold time tDH 0.8 ns Address setup time tAS 1.5 ns Address hold time tAH 0.8 ns CKE setup time tCKS 1.5 ns CKE hold time tCKH 0.8 ns CKE setup time (Power down exit) tCKSP 1.5 ns tCMS 1.5 ns tCMH 0.8 ns EO Data-out hold time Data-out low-impedance time Data-out high-impedance time L DQMB0 - DQMB7) setup time Command (/CS0, /CS1, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time Note 1. Output load od Pr Command (/CS0, /CS1, /RAS, /CAS, /WE, Z = 50 Ω Output 50 pF 8 Data Sheet E0116N20 t uc Remark These specifications are applied to the monolithic device. MC-4516CD642XS Asynchronous Characteristics Parameter Symbol -A75 MIN. Unit MAX. tRC 67.5 ns REF to REF/ACT command period (Refresh) tRC1 67.5 ns ACT to PRE command period tRAS 45 PRE to ACT command period tRP 20 ns Delay time ACT to READ/WRITE command tRCD 20 ns ACT (one) to ACT (another) command period tRRD 15 ns Data-in to PRE command /CAS latency = 3 tDPL3 8 ns period /CAS latency = 2 tDPL2 8 ns Data-in to ACT (REF) command /CAS latency = 3 tDAL3 1CLK+22.5 ns period (Auto precharge) tDAL2 1CLK+20 ns tRSC 2 CLK tT 0.5 EO ACT to REF/ACT command period (Operation) /CAS latency = 2 Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) tREF Note 120,000 ns 30 ns 64 ms 1 L Note 1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation. t uc od Pr Data Sheet E0116N20 9 MC-4516CD642XS Serial PD (1/2) Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 0 Defines the number of bytes written into 80H 1 0 0 0 0 0 0 0 128 bytes serial PD memory Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes 2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM 3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows 4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns 5 Number of banks 02H 0 0 0 0 0 0 1 0 2 bank 6 Data width 40H 0 1 0 0 0 0 0 0 64 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL 9 CL = 3 Cycle time -A75 75H 0 1 1 1 0 1 0 1 7.5 ns 10 CL = 3 Access time -A75 54H 0 1 0 1 0 1 0 0 5.4 ns 11 DIMM configuration type 00H 0 0 0 0 0 0 0 0 None 12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal 13 SDRAM width 10H 0 0 0 1 0 0 0 0 ×16 14 Error checking SDRAM width 00H 0 0 0 0 0 0 0 0 None 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F 17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks 18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0 21 SDRAM module attributes 00H 0 0 0 0 0 0 0 0 22 SDRAM device attributes: General 0EH 0 0 0 0 1 1 1 0 23 CL = 2 Cycle time -A75 A0H 1 0 1 0 0 0 0 0 10 ns 24 CL = 2 Access time -A75 60H 0 1 1 0 0 0 0 0 6 ns 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 20 ns 0 0 0 0 1 1 1 1 15 ns L EO 1 27 tRP (MIN.) -A75 14H 28 tRRD (MIN.) -A75 0FH 29 tRCD (MIN.) -A75 14H 0 0 0 1 30 tRAS (MIN.) -A75 2DH 0 0 1 0 31 Module bank density 10H 0 0 0 1 Data Sheet E0116N20 t uc 10 00H od Pr 25-26 0 1 0 0 20 ns 1 1 0 0 45 ns 0 0 0 0 64M bytes MC-4516CD642XS (2/2) Byte No. 32 Function Described Command and address Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes -A75 15H 0 0 0 1 0 1 0 1 1.5 ns -A75 08H 0 0 0 0 1 0 0 0 0.8 ns signal setup time 33 Command and address signal hold time 34 Data signal input setup time -A75 15H 0 0 0 1 0 1 0 1 1.5 ns 35 Data signal input hold time -A75 08H 0 0 0 0 1 0 0 0 0.8 ns 00H 0 0 0 0 0 0 0 0 36-61 SPD revision -A75 12H 0 0 0 1 0 0 1 0 63 Checksum for bytes 0 - 62 -A75 A7H 1 0 1 0 0 1 1 1 EO 62 64-71 72 1.2 A Manufacture’s JEDEC ID code Manufacturing location Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific L 73-90 126 Intel specification frequency -A75 64H 0 1 1 0 0 1 0 0 127 Intel specification /CAS -A75 C7H 1 1 0 0 0 1 1 1 Timing Chart Pr latency support Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N). t uc od Data Sheet E0116N20 11 MC-4516CD642XS Package Drawing 144-PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) M1 (AREA B) Y N Z R Q EO M2 (AREA A) L U1 S A H U2 T (OPTIONAL HOLES) C B L I M E D A1 (AREA A) F Pr D2 D1 X V 12 Data Sheet E0116N20 MILLIMETERS A 67.6 A1 67.6±0.15 B 23.2 C 29.0 D 4.6 D1 1.5±0.10 D2 4.0 E F 32.8 3.7 H 0.8 (T.P.) I L 3.3 20.0 M M1 31.75±0.15 9.75 M2 22.0 N 3.8 MAX. Q R2.0 t uc od detail of A part W ITEM R 4.00±0.10 S φ 1.8 T U1 1.0±0.1 3.2 MIN. U2 4.0 MIN. V W 0.25 MAX. 0.6±0.05 X Y 2.55 MIN. 2.0 MIN. Z 2.0 MIN. MC-4516CD642XS CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0107 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES 2 L EO Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES 3 Pr No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES t uc od Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Data Sheet E0116N20 13 MC-4516CD642XS The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. Pr [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. M01E0107 t uc od If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.