DATA SHEET MOS INTEGRATED CIRCUIT MC-45V16AB642 16M-WORD BY 64-BIT VirtualChannelTM DYNAMIC RAM MODULE UNBUFFERED TYPE Description The MC-45V16AB642 is a 16,777,216 words by 64 bits VirtualChannel dynamic RAM module on which 8 pieces of 128M VirtualChannel DRAM : µPD45V128821 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 16,777,216 words by 64 bits organization • Clock frequency and access time from CLK Part number Read Clock Access time latency frequency from CLK Maximum supply current mA Operating Refresh MHz (MAX.) ns (MAX.) Prefetch Restore Channel Auto Self 1,840 16 read / write (Burst) MC-45V16AB642KF-A75 2 133 5.4 1,200 520 • Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Dual internal banks controlled by BA0 (Bank Select) • Wrap sequence (interleave) • Burst length (4) • Read latency (2) • Prefetch read latency (4) • Auto refresh and self refresh • Single 3.3 V ± 0.3 V power supply • Interface: LVTTL • Refresh cycle: 4K cycles/64 ms • 168-pin dual in-line memory module (Pin pitch = 1.27 mm) • Unbuffered type • Serial PD • Auto precharge and without auto precharge The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0027N10 (1st edition) (Previous No. M15112EJ2V0DS00) Date Published January 2001 CP (K) Printed in Japan This Product became EOL in January, 2003. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. MC-45V16AB642 Ordering Information Part number Clock Read frequency latency MHz (MAX.) MC-45V16AB642KF-A75 133 Prefetch Package Mounted devices read latency 2 4 8 pieces of µPD45V128821G5 168-pin Dual In-line Memory Module (Socket Type) (10.16 mm (400) TSOP (II)) Edge connector : Gold plated 34.93 mm height 2 E0027N10 MC-45V16AB642 Pin Configuration 168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal. VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC VSS NC NC Vcc /CAS DQMB4 DQMB5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 A12 Vcc 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 : Address Inputs [Row: A0 - A12, Column: A0 - A7] BA0 (A13) : VirtualChannel DRAM Bank Select DQ0 - DQ63 : Data Inputs/Outputs CLK0 - CLK3 : Clock Input CKE0 : Clock Enable Input /CS0, /CS2 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe E0027N10 /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable SA0 - SA2 : Address Input for EEPROM SDA : Serial Data I/O for PD SCL : Clock Input for PD VCC : Power Supply VSS : Ground WP NC 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 A0 - A12 : Write Protect : No Connection 3 MC-45V16AB642 Block Diagram /WE /CS0 /CS2 DQMB0 DQMB2 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D0 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 7 DQM /WE DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 /CS DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D3 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D4 DQ 3 DQ 2 DQ 1 DQ 0 DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D6 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D7 DQ 3 DQ 2 DQ 1 DQ 0 /WE DQMB6 /WE DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQMB7 DQ 5 DQM /CS DQ 7 DQ 6 DQ 4 D5 DQ 3 DQ 2 DQ 1 DQ 0 /WE CLK : D0, D1, D4, D5 3.3 pF CLK2 CLK : D2, D3, D6, D7 3.3 pF CLK1, CLK3 10 pF DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 A0 - A12 A0 - A12 : D0 - D7 CLK0 /WE DQMB5 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 D1 DQMB4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D2 DQ 3 DQ 2 DQ 1 DQ 0 DQMB3 DQMB1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 BA0 A13 : D0 - D7 /RAS /RAS : D0 - D7 /CAS /CAS : D0 - D7 CKE0 CKE : D0 - D7 SERIAL PD SDA VCC SCL D0 - D7 C VSS A0 D0 - D7 A1 A2 SA0 SA1 SA2 Remarks 1. The value of all resistors is 10 Ω except WP. 2. D0 - D7: µPD45V128821 (8M words × 8 bits × 2 banks) 4 WP 47 kΩ E0027N10 MC-45V16AB642 Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Voltage on power supply pin relative to GND Unit VCC –0.5 to +4.6 V Voltage on input pin relative to GND VT –0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 8 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Rating Caution Condition Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Supply voltage High level input voltage Low level input voltage Parameter Operating ambient temperature Symbol Condition MIN. TYP. MAX. Unit VCC 3.0 3.3 3.6 V VIH 2.0 VCC + 0.3 V VIL −0.3 +0.8 V TA 0 70 °C MAX. Unit pF Capacitance (TA = 25°°C, f = 1 MHz) Input capacitance Data input/output capacitance Symbol Test condition MIN. TYP. CI1 A0 - A12, BA0 (A13), /RAS, /CAS, /WE 38 62 CI2 CLK0, CLK2 24 40 CI3 CKE0 32 52 CI4 /CS0, /CS2 17 29 CI5 DQMB0 - DQMB7 7 13 CI/O DQ0 - DQ63 7 13 Parameter pF E0027N10 5 MC-45V16AB642 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition Operating current (Prefetch ICC1P mode at one bank active) Grade tRC ≥ tRC (MIN.) MIN. MAX. Unit Notes -A75 1,200 mA 1 -A75 1,200 mA 1 9.6 mA Prefetch is executed one time during tRC. Operating current (Restore ICC1R tRC ≥ tRC (MIN.) ICC2P CKE ≤ VIL (MAX.), tCK = 15 ns mode at one bank active) Precharge standby current ICC2PS CKE ≤ VIL (MAX.), tCK = ∞ in power down mode Precharge standby current ICC2N power down mode Active standby current in ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable. ICC3P ICC3N CKE ≤ VIL (MAX.), tCK = 15 ns 48 48 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), ICC4 tCK ≥ tCK (MIN.), IO = 0 mA mA 160 -A75 520 mA 2 -A75 1,840 mA 3 -A75 16 mA –8 +8 µA +1.5 µA Background : precharge standby ICC5 tRCF ≥ tRCF Self refresh current ICC6 CKE ≤ 0.2 V Input leakage current II (L) VI = 0 to 3.6 V, All other pins not under test = 0 V (MIN.) Low level output voltage 240 ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable. Auto Refresh current High level output voltage mA Input signals are changed one time during 30 ns. (Burst mode) Output leakage current mA 80 ICC3PS CKE ≤ VIL (MAX.), tCK = ∞ non power down mode Operating current 160 Input signals are changed one time during 30 ns. in non power down mode Active standby current in 9.6 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), IO (L) DOUT is disabled, VO = 0 to 3.6 V –1.5 VOH IO = – 4.0 mA 2.4 VOL IO = + 4.0 mA V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). 6 E0027N10 MC-45V16AB642 AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions • AC measurements assume tT = 1 ns. • Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. • If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). • An access time is measured at 1.4 V. tCK tCK tCL tCH tCL CLK tCKH tCKS CKE tH tS Command Address DQM (Input) Valid tDS Valid tDH Valid tAC tAC tLZ Data (Output) tDS Data (Input) tDH Hi-Z tOH Valid Valid tHZ Hi-Z E0027N10 7 MC-45V16AB642 AC characteristics Parameter Symbol -A75 Unit MIN. MAX. tCK2 7.5 − ns Access time from CLK tAC2 − 5.4 ns CLK high level width tCH 2.5 − ns CLK low level width tCL 2.5 − ns Data-out hold time tOH 2.7 − ns Data-out low-impedance time tLZ 0 − ns Data-out high-impedance time tHZ2 2.5 5.4 ns Data-in setup time tDS 1.5 − ns Data-in hold time tDH 0.8 − ns Address, Command, DQM setup time tS 1.5 − ns Address, Command, DQM hold time tH 0.8 − ns tCKS 1.5 − ns Clock cycle time CKE setup time CKE hold time tCKH 0.8 − ns CKE setup time (Power down exit) tCKSP 1.5 − ns tT 0.5 30 ns Refresh time (4,096 refresh cycle) tREF − 64 ms Mode register set cycle time tRSC 2 − CLK Transition time 1 1 Note 1. Output load. Note Z = 50 Ω Output 50 pF 8 E0027N10 MC-45V16AB642 AC characteristics (Background to Background operation) Parameter Symbol -A75 Unit MIN. MAX. Notes tRC 67.5 − ns REF to REF / ACT Command period tRCF 67.5 − ns ACT to PRE Command period tRAS 52.5 120,000 ns PRE to ACT / REF Command period tRP 20 − ns ACT to PFC / PFCA Command delay time tAPD 15 − ns ACT to PFR Command delay time (Prefetch Read Operation) tAPRD 15 − ns PFC to PRE Command delay time tPPL 22.5 − ns PFCA / PFR to ACT / REF Command delay time tPAL 45 − ns RST / RSTA to ACT(R) Note1 Command delay time tRAD 7.5 30 ns tRPD 37.5 − ns tPPD 22.5 − ns ACT to ACT / ACT(R) or ACT(R) to ACT Command delay time tRRD 15 − ns ACT(R) to ACT(R) Command delay time tRRDR 30 − ns PFC / PFCA to RST / RSTA Command delay time tPRD 22.5 − ns ACT to ACT / REF Command period 2 ACT(R) Note1 to PFC / PFCA / PFR Command delay time PFC to PFC / PFCA Command delay time Notes 1. ACT (R) command is ACT command after RST command. 2. The another background operation and same channel foreground operation are illegal while tRAD period. E0027N10 9 MC-45V16AB642 AC characteristics (Foreground to Foreground operation) Parameter READ/WRITE to READ/WRITE Command delay time Symbol tCCD -A75 Unit MIN. MAX. 7.5 − Note ns AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore) Parameter Symbol -A75 Unit MIN. MAX. PFC/PFCA to READ/WRITE Command delay time tPCD 15 − ns ACT(R) to READ/WRITE Command delay time tRCD 30 − ns Note 1 Note 1. ACT (R) command is ACT command after RST command. 10 E0027N10 MC-45V16AB642 Serial PD (1/2) Byte No. 0 Function Described Defines the number of bytes written Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 80H 1 0 0 0 0 0 0 0 128 bytes 08H 0 0 0 0 1 0 0 0 256 bytes into serial PD memory 1 Total number of bytes of serial PD memory Fundamental memory type 08H 0 0 0 0 1 0 0 0 VC DRAM 3 Number of row addresses 0DH 0 0 0 0 1 1 0 1 13 rows 4 Number of column addresses 08H 0 0 0 0 1 0 0 0 8 columns 5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank 6 Data width 40H 0 1 0 0 0 0 0 0 64 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface standard 01H 0 0 0 0 0 0 0 1 LVTTL 9 Read latency (/CAS latency) = 2 -A75 75H 0 1 1 1 0 1 0 1 7.5 ns -A75 54H 0 1 0 1 0 1 0 0 5.4 ns 00H 0 0 0 0 0 0 0 0 None 2 cycle time 10 Read latency (/CAS latency) = 2 access time 11 DIMM configuration type Refresh rate / type 80H 1 0 0 0 0 0 0 0 Normal 13 VC DRAM width 08H 0 0 0 0 1 0 0 0 ×8 14 Error checking DRAM width 00H 0 0 0 0 0 0 0 0 None 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 04H 0 0 0 0 0 1 0 0 4 17 Number of banks on each VC DRAM 02H 0 0 0 0 0 0 1 0 2 banks 18 Read latency (/CAS latency) supported 02H 0 0 0 0 0 0 1 0 2 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 01H 0 21 VC DRAM module attributes 00H 0 22 VC DRAM device attributes : general 0EH 0 00H 0 27 tRP (MIN.) -A75 14H 0 28 tRRD (MIN.) -A75 0FH 0 12 0 0 0 1 29 tAPD (MIN.) -A75 0FH 0 0 0 0 1 30 tRAS (MIN.) -A75 34H 0 0 1 1 0 23-26 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 20 ns 1 1 1 15 ns 1 1 1 15 ns 1 0 0 52.5 ns E0027N10 0 0 11 MC-45V16AB642 (2/2) Byte No. Function Described 31 Module bank density 32 Address and command signal Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 20H 0 0 1 0 0 0 0 0 128M bytes -A75 15H 0 0 0 1 0 1 0 1 1.5 ns -A75 08H 0 0 0 0 1 0 0 0 0.8 ns input setup time 33 Address and command signal input hold time Data signal input setup time -A75 15H 0 0 0 1 0 1 0 1 1.5 ns 35 Data signal input hold time -A75 08H 0 0 0 0 1 0 0 0 0.8 ns 36 Prefetch read latency -A75 04H 0 0 0 0 0 1 0 0 4 clocks 37 tPCD (MIN.) -A75 0FH 0 0 0 0 1 1 1 1 15 ns 38 Number of segment addresses 02H 0 0 0 0 0 0 1 0 2 bits 39 Number of channels 04H 0 0 0 0 0 1 0 0 16 40 Depth of channels 08H 0 0 0 0 1 0 0 0 256 bits 2.0 34 62 63 41-61 64-71 72 SPD revision Checksum for bytes 0 - 62 -A75 02H 0 0 0 0 0 0 1 0 34H 0 0 1 1 0 1 0 0 Manufacture’s JEDEC ID code Manufacturing location 73-90 Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific Timing Charts Please refer to the µPD45V128421, 45V128821, 45V128161 Data sheet (E0025N). 12 E0027N10 MC-45V16AB642 Package Drawing 168 PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) Z1 Z2 Y1 Y2 R2 N F2 F1 Q R1 L A B H S (OPTIONAL HOLES) K C J B I G U T E D A1 (AREA A) M2 (AREA A) M1 (AREA B) M detail of A part detail of B part D2 W V X MILLIMETERS 133.35 133.35±0.13 11.43 36.83 6.35 2.0 3.125 54.61 2.44 3.18 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 34.93±0.13 15.15 19.78 3.0 MAX. 1.0 R2.0 4.0±0.10 9.53 φ 3.0 1.27±0.1 4.0 MIN. 0.2±0.15 1.0±0.05 2.54±0.10 3.0 MIN. P ITEM A A1 B C D D1 D2 E F1 F2 G H I J K L M M1 M2 N P Q R1 R2 S T U V W D1 X Y1 Y2 Z1 Z2 E0027N10 2.26 3.0 MIN. 2.26 13 MC-45V16AB642 Edition / Date Page This edition Description Previous Type of edition edition − − Location NEC Corporation (M15112E) 1st edition / − Sep. 2000 2nd edition / p.1, 2 p.1, 2 Dec. 2000 − Deletion p.6, 8, 9, 10, p.6, 8, 9, 10, 11, 12 11, 12 -A10 -A10 specs Elpida Memory, Inc. (E0027N) 1st edition / − − − Republished by Elpida Memory, Inc. Jan. 2001 14 E0027N10 MC-45V16AB642 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. E0027N10 15 MC-45V16AB642 The names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company. CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. • Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above). M8E 00. 4