TI TAS3208YZPR

TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007
FEATURES
•
•
Audio Input/Output
– Three Synchronous Serial Audio Inputs
(Six Channels)
– Two Synchronous Serial Audio Outputs
(Four Channels)
– Input and Output Data Formats: 16-, 20-, or
24-Bit Data Left, Right, and I2S
– SPDIF Transmitter
– 64 × Fs Bit Clock Rate
– 512 × Fs XTAL Input for Master-Mode
Clock Rates
– 256 × Fs MCLKIN for Slave-Mode Clock
Rates
– Ten Multiplexed Stereo Analog Inputs
Selectable Into One Stereo ADC and Three
Stereo Line Outputs
– High-Quality 93 dB DNR (Typical) ADC
Channel Performance (Two Channels)
– A Single Ended Analog Stereo Line
Driver Output With 1 of 11 Selectable
Inputs, 10-kΩ, 100-pF Drive Capability
(Typical Output Level: 1-V RMS)
– Three Stereo Audio DACs
– High-Quality 96-dB DNR (Typical) DAC
Channel Performance (Six Channels)
– Stereo Headphone Amplifier – 24 mW
Power Output Into 16 Ω, 100 pF
Audio Digital Signal Processor
– Programmable Functionality
–
–
–
–
•
•
135-MHz Operation
48-Bit Data Path With 76-Bit Accumulator
Hardware Single Cycle Multiplier (28 × 48)
Two Memory Loads and One Memory Store
Per Cycle
– Usable 768 Data RAM Words (48 Bit),
Usable 1K Coefficient RAM (28 Bit)
– Usable 2.5K Program RAM
– 360 mS @ 48KHz, 17280 Words 24-Bit
Delay Memory for Video Sync
System Control Processor
– Embedded 8051 WARP Microprocessor
– Programmable Using Standard 8051 C
Compilers
– 16K Words of Program RAM (8 Bit)
– Programmable Using Standard 8051 C
Compilers
– 2048 Words of Data RAM (8 Bit)
– 256 Words of Internal RAM (8 Bit)
– Programmable Functionality
General Features
– Easy to Use Control Interface
– I2C Serial Control Master and Slave
Interface
– Control Interface Operational Without
External MCLK Input
– Single 3.3-V Power Supply
– Integrated Regulators
– 100-Pin TQFP Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007
100DVDD1
99AVDD_OSC
98VR_ANA
97XTAL_OUT
96XTAL_IN
95AVSS_ESD
94AVDD_HP
93HPOUTR
92AVSS_HP
91HPOUTL
90AVDD_HP
89AVDD_DAC
88AVSS_DAC
87DACOUT2R
86DACOUT2L
85DACOUT1R
84DACOUT1L
83LINEOUT1R
82LINEOUT1L
81AVSS_LO
80Test
79Test
78Test
77Test
76AVDD_REF
TQFP PACKAGE
(TOP VIEW)
DVSS1
/VREG_EN
STEST
Test
Test
GPIO4
GPIO3
MCLKOUT
LRCLKOUT
SCLKOUT
SDOUT1
SDOUT 2/ SPDIFOUT
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
44
55
6
7
8
9
10
11
12
13
14
15
16
17
17
18
18
19
19
20
20
21
22
23
24
25
V1P5_REF
BG_REF
BIAS_REF
AVSS_ADC/REF
AVDD_ADC
LINEIN10R
LINEIN10L
AVSS_LI
LINEIN9R
LINEIN9L
AVDD_LI
LINEIN8R
LINEIN8L
AVSS_LI
LINEIN7R
LINEIN7L
AVDD_LI
LINEIN6R
LINEIN6L
AVSS_LI
LINEIN5R
LINEIN5L
AVDD_LI
LINEIN4R
LINEIN4L
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MCLKIN
DVSS3
DVDD3
2IC_SDA2
2IC_SCL2
2IC_SDA1
2IC_SCL1
CS
GPIO1
GPIO2
M
/ UTE
R
/ ESET
DVSS4
DVDD4
DVSS5
VR_DIG2
AVSS_ESD
LINEN
I 1L
LINEN
I 1R
AVDD_LI
LINEN
I 2L
LINEN
I 2R
AVSS_LI
LINEN
I 3L
LINEN
I 3R
26
27
28
29
30
31
32
33
DVDD2
VR_DIG1
DVSS2
SPDIF_IN
Test
Test
Test
Test
SDIN3
SDIN2
SDIN1
LRCLKIN
SCLKIN
1
2
DESCRIPTION/ORDERING INFORMATION
The TAS3208 is an audio SOC designed for digital TV Audio Systems and Mini/Micro Component applications.
TAS3208 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit
filter coefficients, and a single-cycle 28 times 48-bit multiplier. The programmability feature allows users to
customize features in the DSP RAM.
The TAS3208 is composed of seven functional blocks.
• Clock and Serial Data Interface
• Analog Input and Output
• 8051 WARP Controller, Serial Control Interface and Device Control
• Audio DSP – Digital Audio Processing
• Power Supply
• Internal References
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
2
TQFP – YZP
TBD
ORDERABLE PART NUMBER
TAS3208YZPR
TOP-SIDE MARKING
TBD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
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TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007
BLOCK DIAGRAM
AVSS
10 pf
512
AVSSTBD
Fs
512Fs
Rb a
is
Rbia s
TBD
OSC
10 pf
MCLKIN
MCLKOUT
Clock
Control
SCLKIN
LRCLKIN
SCLKOUT
SCLKI
LRCLKI
SDIN 1
SAP
IN
SDIN 2
SDIN 3
MUTEZ
Audio
processing
LRCLKOUT
Control
SDA 1
2
I C
SPDIF OUT /
SDOUT 2
31
:
MUX
SPDIF
SCL 1
SDA 2
SDOUT 1
SAP
OUT
2
SPDIF IN
8051
SCL 2
DAC
Mod
CS
HP AMP
GPIO 1-4
2
HP OUT L /R
47 220
uF
16Ohm
10 K ohm
2
10 ch stereo
Analog line Input
2.8V
10 ch stereo
Analog
Inputs
33K
A-MUX
10:1
RMS
0.8 uF
1V
6CH
DAC
2CH
ADC
2
DACOUT 2L/R
2
DACOUT 1L/R
2
A- MUX
11:1
RMS
10 ch stereo
2
LINEOUT 1L/R
Apply to all Line and
DAC outputs
2.2uF
10K ohm
Line outputs
DAC outputs
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1V
0.9 V
RMS ( MAX
RMS (MAX
)
)
3
TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007
TYPICAL APPLICATIONS
The TAS3208 may be used with an external Asynchronous Sample Rate Converter (ASRC) to
accommodate asynchronous serial inputs at different sampling rates. An example of this is shown in the
block diagram of Figure 2.2.
AVSS
AVSS TBD
10
512
pf
Fs
10
512Fs
Rb ias
Rbias
TBD
OSC
pf
MCLKIN
MCLKOUT
Clock
Control
SCLKIN
LRCLKIN
SCLKOUT
External
ASRC
SCLKI
SDIN1A
SDIN2B
MUX
SDI 1
LRCLKI
SDO 1
SDIN3B
SDIN4B
SDIN 1
SDI 2
SDO 2
SDIN 2
SDI 3
SDO 3
SDIN 3
SAP
IN
Audio
processing
SDOUT 1
SAP
OUT
2
LRCLKOUT
SCLKA
LRCLKA
SCLKB
LRCLKB
MCLKB
SCLKO
SCLKI
MCLKA
MUX
LRCLKI
LRCLKO
MUTEZ
Control
SPDIF OUT
MCLKO
MCLKI
SDA 1
SCL1
SDA 2
2
I C
/
SDOUT 2
3:1
MUX
SPDIF
SPDIF IN
8051
LRCLKOUT
SCLKOUT
MCLKOUT
SCL 2
DAC
Mod
CS
HP AMP
GPIO 1-4
2
HP OUT L / R
2
10 ch stereo
Analog
Inputs
A -MUX
10:1
6CH
DAC
2 CH
ADC
A- MUX
11:1
Figure 1. TAS3208 and interface to external ASRC
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DACOUT 2 L/R
DACOUT 1 L/R
2
LINEOUT 1 L/R
2
10 ch stereo
4
2
2
TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
DVDD
Supply voltage range
–0.5
3.8
V
AVDD
Supply voltage range
–0.5
3.8
V
VI
Input voltage range
Voltage range applied to any output in the high-impedance
or power-off state
VO
3.3-V TTL
–0.5
VDDS + 0.5
3.3-V analog
–0.5
AVDDS + 0.5
1.8-V LVCMOS
–0.5
AVDD + 0.5 (2)
3.3-V TTL
–0.5
VDDS + 0.5
3.3-V analog
–0.5
AVDDS + 0.5
1.8-V LVCMOS
–0.5
DVDD + 0.5 (3)
1.8-V LVCMOS
–0.5
AVDD + 0.5 (4)
UNIT
V
V
IIK
Input clamp current
VI < 0 or VI > DVDD
±20
mA
IOK
Output clamp current
VO < 0 or VO > DVDD
±20
mA
Tstg
Storage temperature range
150
°C
260
°C
–65
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1)
(2)
(3)
(4)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AVDD is an internal 1.8-V supply derived from a regulator in the CXD9890Q chip. Pin XTALI is the only CXD9890Q input that is
referenced to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI.
DVDD is an internal 1.8-V supply derived from regulators in the CXD9890Q chip. DVDD is routed to– DVDD_BYPASS_CAP – to provide
access to external filter capacitors, but should not be used to source power to external devices.
Pin XTALO is the only CXD9890Q output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed
is for reference; only a crystal should be connected to XTALO. AVDD is also routed to – AVDD_BYPASS_CAP – to provide access to
external filter capacitors, but should not be used to source power to external devices.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
3.0
3.3
3.6
V
3.0
3.3
3.6
V
DVDD
Digital supply voltage
AVDD
Analog supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating ambient air temperature (ensuring Parametric)
–20
TJ
Operating junction temperature
–20
3.3-V analog
3.3-V TTL
1.8-V LVCMOS (XTL_IN)
2.0
1.26
1.95
3.3-V TTL
0.8
1.8-V LVCMOS (XTL_IN)
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0.54
25
UNIT
V
V
70
°C
105
°C
5
TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output
voltage
VOL
Low-level output
voltage
IOZ
High-impedance
output current
IIL (1)
Low-level input
current
IIH (2)
IOH = –4 mA
1.8-V LVCMOS
(XTL_OUT)
IOH = –0.55 mA
3.3-V TTL
IOL = 4 mA
1.8-V LVCMOS
(XTL_OUT)
IOL = 0.75 mA
MIN
MAX
V
1.44
0.5
0.396
±20
3.3-V TTL
UNIT
2.4
1.8-V LVCMOS
(XTL_IN)
VI = VIL
±1
3.3-V TTL
VI = VIL
±1
1.8-V LVCMOS
(XTL_IN)
VI = VIH
±1
3.3-V TTL
VI = VIH
±1
V
µA
µA
µA
IDVDD
Digital supply
current
DSP clock = 135-MHz LRCLKIN/LRCLKOUT = 48 KHz,
XTALI = 24.288 MHz
200
mA
IAVDD
Analog supply
current
DSP clock = 135-MHz LRCLKIN/LRCLKOUT = 48 KHz,
XTALI = 24.288 MHz
28
mA
IDVDD
Digital supply
current
RESET = Low
0.1
mA
IAVDD
Analog supply
current
RESET = Low
5
mA
(1)
(2)
6
High-level input
current
TEST CONDITIONS
3.3-V TTL
Value given is for those input pins that connect to an internal pull-up resistor as well as an input buffer. For inputs that have a pull-down
resistor or no resistor, IIL is ± 1 µa.
Value given is for those input pins that connect to an internal pull-down resistor as well as an input buffer. For inputs that have a pull-up
resistor or no resistor, IIH is ± 1 µa.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS3208PZP
ACTIVE
HTQFP
PZP
100
TAS3208PZPR
ACTIVE
HTQFP
PZP
100
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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