EN25Q32A
EN25Q32A
32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
•
-
• 32 M-bit Serial Flash
- 32 M-bit/4096 K-byte/16384 pages
- 256 bytes per programmable page
•
-
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#
Dual SPI: CLK, CS#, DQ0, DQ1, WP#
Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
•
-
High performance
100MHz clock rate for one data bit
80MHz clock rate for two data bits
80MHz clock rate for four data bits
• Lockable 512 byte OTP security sector
• Minimum 100K endurance cycle
•
-
• Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
•
-
High performance program/erase speed
Page program time: 1.3ms typical
Sector erase time: 90ms typical
Block erase time 500ms typical
Chip erase time: 25 seconds typical
Package Options
8 pins SOP 200mil body width
8 contact VDFN
8 pins PDIP
All Pb-free packages are RoHS compliant
• Industrial temperature Range
Uniform Sector Architecture:
1024 sectors of 4-Kbyte
64 blocks of 64-Kbyte
Any sector or block can be erased individually
GENERAL DESCRIPTION
The EN25Q32A is a 32 Megabit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q32A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI),
DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the
Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The EN25Q32A is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25Q32A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure.1 CONNECTION DIAGRAMS
CS#
1
8
VCC
DO (DQ1)
2
7
NC (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD SOP / PDIP
CS#
1
8
VCC
DO (DQ1)
2
7
NC (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD VDFN
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 2. BLOCK DIAGRAM
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 1. Pin Names
Symbol
Pin Name
CLK
Serial Clock Input
DI (DQ0)
Serial Data Input (Data Input Output 0)
DO (DQ1)
Serial Data Output (Data Input Output 1)
CS#
Chip Enable
WP# (DQ2)
Write Protect (Data Input Output 2)
NC(DQ3)
Not Connect (Data Input Output 3)
Vcc
Supply Voltage (2.7-3.6V)
Vss
Ground
NC
No Connect
*1
*1
*2
*2
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25Q32A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
MEMORY ORGANIZATION
The memory is organized as:
z
4,194,304 bytes
z
Uniform Sector Architecture
64 blocks of 64-Kbyte
1024 sectors of 4-Kbyte
z
16384 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 2. Uniform Block Sector Architecture (Continued)
44
43
….
390FFFh
38FFFFh
380FFFh
37FFFFh
370FFFh
36FFFFh
360000h
35F000h
360FFFh
35FFFFh
350000h
34F000h
350FFFh
34FFFFh
340000h
33F000h
340FFFh
33FFFFh
330000h
32F000h
330FFFh
32FFFFh
320000h
31F000h
320FFFh
31FFFFh
784
783
310000h
30F000h
310FFFh
30FFFFh
768
767
300000h
2FF000h
300FFFh
2FFFFFh
752
751
2F0000h
2EF000h
2F0FFFh
2EFFFFh
….
….
….
….
800
799
….
….
816
815
….
….
832
831
….
….
848
847
….
….
864
863
….
….
370000h
36F000h
….
880
879
….
….
380000h
37F000h
….
896
895
….
….
….
….
….
….
….
….
….
390000h
38F000h
….
912
911
….
….
….
….
….
….
….
….
….
….
….
….
….
3A0FFFh
39FFFFh
….
3A0000h
39F000h
736
735
2E0000h
2DF000h
2E0FFFh
2DFFFFh
….
45
928
927
720
719
2D0000h
2CF000h
2D0FFFh
2CFFFFh
….
46
3B0FFFh
3AFFFFh
704
703
2C0000h
2BF000h
2C0FFFh
2BFFFFh
….
47
3B0000h
3AF000h
….
48
944
943
….
49
3C0FFFh
3BFFFFh
….
50
3C0000h
3BF000h
….
51
960
959
….
52
3D0FFFh
3CFFFFh
….
53
3D0000h
3CF000h
….
54
976
975
….
55
3E0FFFh
3DFFFFh
….
56
3E0000h
3DF000h
….
57
992
991
….
58
3F0FFFh
3EFFFFh
….
59
3F0000h
3EF000h
….
60
1008
1007
….
61
3FFFFFh
….
62
Address range
3FF000h
….
63
Sector
1023
….
Block
688
2B0000h
2B0FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 2. Uniform Block Sector Architecture (Continued)
23
22
….
240FFFh
23FFFFh
230FFFh
22FFFFh
220FFFh
21FFFFh
210000h
20F000h
210FFFh
20FFFFh
200000h
1FF000h
200FFFh
1FFFFFh
1F0000h
1EF000h
1F0FFFh
1EFFFFh
1E0000h
1DF000h
1E0FFFh
1DFFFFh
1D0000h
1CF000h
1D0FFFh
1CFFFFh
448
447
1C0000h
1BF000h
1C0FFFh
1BFFFFh
432
431
1B0000h
1AF000h
1B0FFFh
1AFFFFh
416
415
1A0000h
19F000h
1A0FFFh
19FFFF
….
….
….
….
464
463
….
….
480
479
….
….
496
495
….
….
512
511
….
….
528
527
….
….
220000h
21F000h
….
544
543
….
….
230000h
22F000h
….
560
559
….
….
….
….
….
….
….
….
….
240000h
23F000h
….
576
575
….
….
….
….
….
….
….
….
….
….
….
….
….
250FFFh
24FFFFh
….
250000h
24F000h
400
399
190000h
18F000h
190FFFh
18FFFFh
….
24
592
591
384
383
180000h
17F000h
180FFFh
17FFFFh
….
25
260FFFh
25FFFFh
368
367
170000h
16F000h
170FFFh
16FFFFh
….
26
260000h
25F000h
….
27
608
607
….
28
270FFFh
26FFFFh
….
29
270000h
26F000h
….
30
624
623
….
31
280FFFh
27FFFFh
….
32
280000h
27F000h
….
33
640
639
….
34
290FFFh
28FFFFh
….
35
290000h
28F000h
….
36
656
655
….
37
2A0FFFh
29FFFFh
….
38
2A0000h
29F000h
….
39
672
671
….
40
2AFFFFh
….
41
Address range
2AF000h
….
42
Sector
687
….
Block
352
160000
160FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
7
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 2. Uniform Block Sector Architecture (Continued)
3
2
….
0F0FFFh
0EFFFFh
0E0FFFh
0DFFFFh
0D0000h
0CF000h
0D0FFFh
0CFFFFh
0C0000h
0BF000h
0C0FFFh
0BFFFFh
0B0000h
0AF000h
0B0FFFh
0AFFFFh
0A0000h
09F000h
0A0FFFh
09FFFFh
090000h
08F000h
090FFFh
08FFFFh
080000h
07F000h
080FFFh
07FFFFh
112
111
070000h
06F000h
070FFFh
06FFFFh
96
95
060000h
05F000h
060FFFh
05FFFFh
….
….
….
128
127
….
….
144
143
….
….
160
159
….
….
176
175
….
….
192
191
….
….
208
207
….
….
0E0000h
0DF000h
….
224
223
….
….
0F0000h
0EF000h
….
240
239
….
….
….
….
….
….
….
….
100FFFh
0FFFFFh
….
….
….
….
….
….
….
….
….
….
….
….
100000h
0FF000h
….
256
255
80
79
050000h
04F000h
050FFFh
04FFFFh
….
4
110FFFh
10FFFFh
64
63
040000h
03F000h
040FFFh
03FFFFh
….
5
110000h
10F000h
48
47
030000h
02F000h
030FFFh
02FFFFh
….
6
272
271
….
7
120FFFh
11FFFFh
….
8
120000h
11F000h
….
9
288
287
….
10
130FFFh
12FFFFh
….
11
130000h
12F000h
….
12
304
303
….
13
140FFFh
13FFFFh
….
14
140000h
13F000h
….
15
320
319
….
16
150FFFh
14FFFFh
….
17
150000h
14F000h
….
18
336
335
….
19
15FFFFh
….
20
Address range
15F000
….
21
Sector
351
….
Block
32
020000h
020FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 2. Uniform Block Sector Architecture (End)
….
….
16
15
010000h
00F000h
010FFFh
00FFFFh
….
0
01FFFFh
….
1
Address range
01F000h
….
Sector
31
….
Block
4
3
2
1
0
004000h
003000h
002000h
001000h
000000h
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
OPERATING FEATURES
Standard SPI Modes
The EN25Q32A is accessed through a SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as
shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby
and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For
Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising
edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction
The EN25Q32A supports Dual SPI operation when using the “ Dual Output Fast Read and Dual I/O
Fast Read “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the
Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read
instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)
or for application that cache code-segments to RAM for execution. The Dual output feature simply
allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI
instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use
the standard SPI interface with single output signal.
Quad SPI Instruction
The EN25Q32A supports Quad output operation when using the Quad I/O Fast Read (EBh).This
instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate
possible with the standard SPI. The Quad Read instruction offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or for application
that cache code-segments to RAM for execution. The EN25Q32A also supports full Quad Mode
function while using the Enable Quad I/O (EQIO) (38h). When using Quad SPI instruction the DI and
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and NC pins become DQ2 and DQ3
respectively.
Figure 4. Quad SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed
at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page
of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time,
using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read
Device ID (RDI) instruction) is executed.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
10
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Status Register. The Status Register contains a number of status and control bits that can be read or
set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory
default) to enable WP# function or is set to “1” to disable WP# function (It can be floating during SPI
mode.)
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25Q32A provides the following data protection mechanisms:
z
Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z
Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z
The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM).
z
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 3. Protected Area Sizes Sector Organization
Status Register Content
BP3
Bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
Bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Memory Content
Protect Areas
Addresses
None
Block 0 to 62
Block 0 to 61
Block 0 to 59
Block 0 to 55
Block 0 to 47
Block 0 to 31
All
None
Block 63 to 1
Block 63 to 2
Block 63 to 4
Block 63 to 8
Block 63 to 16
Block 63 to 32
All
None
000000h-3EFFFFh
000000h-3DFFFFh
000000h-3BFFFFh
000000h-37FFFFh
000000h-2FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
None
3FFFFFh-010000h
3FFFFFh-020000h
3FFFFFh-040000h
3FFFFFh-080000h
3FFFFFh-100000h
3FFFFFh-200000h
000000h-3FFFFFh
Density(KB)
None
4032KB
3968KB
3840KB
3584KB
3072KB
2048KB
4096KB
None
4032KB
3968KB
3840KB
3584KB
3072KB
2048KB
4096KB
Portion
None
Lower 63/64
Lower 62/64
Lower 60/64
Lower 56/64
Lower 48/64
Lower 32/64
All
None
Upper 63/64
Upper 62/64
Upper 60/64
Upper 56/64
Upper 48/64
Upper 32/64
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID
(RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select
(CS#) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12
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EN25Q32A
Table 4A. Instruction Set
Instruction Name
Byte 1
Code
EQIO
38h
RSTQIO(1)
FFh
Write Enable
Write Disable / Exit
OTP mode
Read Status
Register
Write Status
Register
Page Program
Sector Erase / OTP
erase
Block Erase
06h
Chip Erase
C7h/ 60h
Deep Power-down
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
Manufacturer/
Device ID
Read Identification
Enter OTP mode
B9h
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
04h
05h
(S7-S0)(2)
01h
S7-S0
02h
A23-A16
A15-A8
A7-A0
20h
A23-A16
A15-A8
A7-A0
D8h
A23-A16
A15-A8
A7-A0
continuous(3)
D7-D0
Next byte
continuous
(4)
dummy
dummy
90h
dummy
dummy
9Fh
3Ah
(M7-M0)
(ID15-ID8)
dummy
(ID7-ID0)
00h
01h
(ID7-ID0)
(M7-M0)
(ID7-ID0)
(6)
ABh
(ID7-ID0)
(M7-M0)
(5)
Notes:
1. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode.
2. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin.
3. The Status Register contents will repeat continuously until CS# terminate the instruction.
4. The Device ID will repeat continuously until CS# terminates the instruction.
5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
6. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25Q32A
Table 4B. Instruction Set (Read Instruction)
Instruction Name
Byte 1
Code
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
(Next byte)
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Dual Output Fast
Read
3Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, …) (1)
Dual I/O Fast Read
BBh
A23-A8(2)
A7-A0,
dummy (2)
(D7-D0, …) (1)
Quad I/O Fast Read
EBh
A23-A0,
dummy (4)
(dummy,
D7-D0 ) (5)
(D7-D0, …) (3)
n-Bytes
continuous
(Next Byte)
continuous
(one byte
per 4 clocks,
continuous)
(one byte
per 4 clocks,
continuous)
(one byte
per 2 clocks,
continuous)
Notes:
1. Dual Output data
DQ0 = (D6, D4, D2, D0)
DQ1 = (D7, D5, D3, D1)
2. Dual Input Address
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 ; A6, A4, A2, A0, dummy 6, dummy 4, dummy 2, dummy 0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 ; A7, A5, A3, A1, dummy 7, dummy 5, dummy 3, dummy 1
3. Quad Data
DQ0 = (D4, D0, …… )
DQ1 = (D5, D1, …… )
DQ2 = (D6, D2, …... )
DQ3 = (D7, D3, …... )
4. Quad Input Address
DQ0 = A20, A16, A12, A8, A4, A0, dummy 4, dummy 0
DQ1 = A21, A17, A13, A9, A5, A1, dummy 5, dummy 1
DQ2 = A22, A18, A14, A10, A6, A2, dummy 6, dummy 2
DQ3 = A23, A19, A15, A11, A7, A3, dummy 7, dummy 3
5. Quad I/O Fast Read Data
DQ0 = ( dummy 12, dummy 8, dummy 4, dummy 0, D4, D0 )
DQ1 = ( dummy 13, dummy 9, dummy 5, dummy 1, D5, D1 )
DQ2 = ( dummy 14, dummy 10, dummy 6, dummy 2, D6, D2 )
DQ3 = ( dummy 15, dummy 11, dummy 7, dummy 3, D7, D3 )
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
14
©2004 Eon Silicon Solution, Inc.,
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EN25Q32A
Table 5. Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0)
ABh
(ID7-ID0)
15h
90h
1Ch
9Fh
1Ch
15h
3016h
Enable Quad I/O (EQIO) (38h)
The Enable Quad I/O (EQIO) instruction will enable the flash device for Quad SPI bus operation. Upon
completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a
power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 5. The device did not
support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual Input/Output
FAST_READ (BBh) modes while the Enable Quad I/O (EQIO) (38h) turns on.
Figure 5. Enable Quad I/O Sequence Diagram
Reset Quad I/O (RSTQIO) (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. The device accepts either Standard SPI ( 8 clocks ) or Quad SPI ( 2 clocks) command
cycles. For Standard SPI, DQ [3:1] are don’t care for this command, but should be driven to VIH or VIL.
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EN25Q32A
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase
(BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 7.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 6. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions.
The instruction sequence is shown in Figure 7.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 7. Write Disable Instruction Sequence Diagram
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EN25Q32A
Figure 7.1 Write Enable/Disable Instruction Sequence under EQIO Mode
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 8.
The instruction sequence is shown in Figure 8.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 8. Read Status Register Instruction Sequence Diagram
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EN25Q32A
Figure 8.1 Read Status Register Instruction Sequence under EQIO Mode
Table 6. Status Register Bit Locations
S7
SRP
Status
Register
Protect
1 = status
register write
disable
S6
OTP_LOCK
bit
(note 1)
1 = OTP
sector is
protected
Non-volatile bit
WPDIS
(WP# disable)
1 = WP#
disable
0 = WP#
enable
S5
S4
S3
S2
S1
BP3
BP2
BP1
BP0
WEL
(Block
(Block
(Block
(Block
(Write Enable
Protected bits) Protected bits) Protected bits) Protected bits)
Latch)
(note 2)
(note 2)
(note 2)
(note 2)
S0
WIP
(Write In
Progress bit)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
volatile bit
volatile bit
Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect
(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
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EN25Q32A
The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits
are 0.
WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory
default) to enable WP# function or is set to “1” to disable WP# function (It can be floating during SPI
mode.)
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set
to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register
(SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is
no longer accepted for execution.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 8. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad I/O (EQIO) (38h) command.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN25Q32A
Figure 9. Write Status Register Instruction Sequence Diagram
Figure 9.1 Write Status Register Instruction Sequence under EQIO Mode
Read Data Bytes (READ) (03h)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When
the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
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EN25Q32A
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 10. Read Data Instruction Sequence Diagram
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory
contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a
maximum frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 11. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes
at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad I/O (EQIO) (38h) command.
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EN25Q32A
Figure 11. Fast Read Instruction Sequence Diagram
Figure 11.1 Fast Read Instruction Sequence under EQIO Mode
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EN25Q32A
Dual Output Fast Read (3Bh)
The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from
the EN25Q32A at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is
ideal for quickly downloading code from to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the device’s
internal circuits additional time for setting up the initial address. The input data during the dummy clock
is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data
out clock.
Figure 12. Dual Output Fast Read Instruction Sequence Diagram
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EN25Q32A
Dual Input / Output FAST_READ (BBh)
The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO
pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The
address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on
the falling edge of CLK at a maximum frequency. The first address can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following
address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 13.
Figure 13. Dual Input / Output Fast Read Instruction Sequence Diagram
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EN25Q32A
Quad Input / Output FAST_READ (EBh)
The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins. DQ0, DQ1, DQ2 and
DQ3 and four Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O
pins) shift our on the falling edge of CLK at a maximum frequency FR. The first address can be any
location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->
sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2,
DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad
Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown
in Figure 14.
The instruction sequence is shown in Figure 14.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 14. Quad Input / Output Fast Read Instruction Sequence Diagram
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EN25Q32A
Figure 14.1. Quad Input / Output Fast Read Instruction Sequence under EQIO Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4
dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown
in Figure 15.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And
afterwards CS# is raised, the system then will escape from performance enhance mode and return to
normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 15.1 while using the Enable Quad I/O (EQIO) (38h) command.
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EN25Q32A
Figure 15. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram
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EN25Q32A
Figure 15.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence under EQIO Mode
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EN25Q32A
Page Program (PP) (02h)
The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 16.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 16. Page Program Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
29
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 16.1 Program Instruction Sequence under EQIO Mode
Sector Erase (SE) (20h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 17. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 18.1 while using the Enable Quad I/O (EQIO) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
30
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 17. Sector Erase Instruction Sequence Diagram
Block Erase (BE) (D8h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 18. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 18.1 while using the Enable Quad I/O (EQIO) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
31
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 18. Block Erase Instruction Sequence Diagram
Figure 18.1 Block/Sector Erase Instruction Sequence under EQIO Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
32
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
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EN25Q32A
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 19. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0.
The Chip Erase (CE) instruction is ignored if one, or more blocks are protected.
The instruction sequence is shown in Figure 19.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 19. Chip Erase Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 19.1 Chip Erase Sequence under EQIO Mode
Deep Power-down (DP) (B9h)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 9.)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from
this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the
Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 20. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
34
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 20. Deep Power-down Instruction Sequence Diagram
Release from Deep Power-down and Read Device ID (RDI)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature
that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
When used only to release the device from the power-down state, the instruction is issued by driving
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 21. After
the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 22. The Device ID value for the EN25Q32A are listed in Table 5. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device
was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is
immediate. If the device was previously in the Deep Power-down mode, though, the transition to the
Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2
(max), as specified in Table 11. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
35
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 21. Release Power-down Instruction Sequence Diagram
Figure 22. Release Power-down / Device ID Instruction Sequence Diagram
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Eon (1Ch)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 23. The Device ID values for the EN25Q32A are listed in Table 5. If the 24-bit address
is initially set to 000001h the Device ID will be read first
The instruction sequence is shown in Figure 23.1 while using the Enable Quad I/O (EQIO) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
36
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 23. Read Manufacturer / Device ID Diagram
Figure 23.1. Read Manufacturer / Device ID Diagram under EQIO Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
37
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
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EN25Q32A
Read Identification (RDID) (9Fh)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being
shifted out on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock .
The instruction sequence is shown in Figure 24. The Read Identification (RDID) instruction is
terminated by driving Chip Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
The instruction sequence is shown in Figure 24.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 24. Read Identification (RDID)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
38
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 24.1. Read Identification (RDID) under EQIO Mode
Enter OTP Mode (3Ah)
This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read,
program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 1023,
SRP bit becomes OTP_LOCK bit and can be read with RDSR command. Program / Erase command
will be disabled when OTP_LOCK bit is ‘1’
WRSR command will ignore the input data and program OTP_LOCK bit to 1.
User must clear the protect bits before enter OTP mode.
OTP sector can only be program and erase before OTP_LOCK bit is set to ‘1’ and BP [3:0] = ‘0000’. In
OTP mode, user can read other sectors, but program/erase other sectors only allowed when
OTP_LOCK bit equal to ‘0’.
User can use WRDI (04h) command to exit OTP mode.
The instruction sequence is shown in Figure 25.1 while using the Enable Quad I/O (EQIO) (38h) command.
Erase OTP Command (20h)
User can use Sector Erase (20h) command only to erase OTP data.
Table 7. OTP Sector Address
Sector
Sector Size
Address Range
1023
512 byte
3FF000h – 3FF1FFh
Note: The OTP sector is mapping to sector 1023
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
39
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 25. Enter OTP Mode
Figure 25.1 Enter OTP Mode Sequence under EQIO Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
40
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Power-up Timing
Figure 26. Power-up Timing
Table 8. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
10
tPUW(1)
Time delay to Write instruction
1
10
ms
Write Inhibit Voltage
1
2.5
V
VWI(1)
µs
Note:
1.The parameters are characterized only.
2. VCC (max.) is 3.6V and VCC (min.) is 2.7V
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
The Status Register contains 00h (all Status Register bits are 0).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
41
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 9. DC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Standby Current
ICC2
Deep Power-down Current
ICC3
Operating Current (READ)
ICC4
Operating Current (PP)
ICC5
Operating Current (WRSR)
ICC6
Min.
CS# = VCC, VIN = VSS or VCC
CS# = VCC, VIN = VSS or VCC
CLK = 0.1 VCC / 0.9 VCC at
100MHz, DQ = open
CLK = 0.1 VCC / 0.9 VCC at
80MHz, DQ = open
CS# = VCC
Max.
Unit
±2
µA
±2
µA
20
µA
20
µA
25
mA
20
mA
28
mA
18
mA
Operating Current (SE)
CS# = VCC
CS# = VCC
25
mA
ICC7
Operating Current (BE)
CS# = VCC
25
mA
VIL
Input Low Voltage
– 0.5
0.2 VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.4
V
VOH
Output High Voltage
IOH = –100 µA
VCC-0.2
V
Table 10. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
20/30
Input Rise and Fall Times
Unit
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
Notes:
1.
CL = 20 pF when CLK=100MHz, CL = 30 pF when CLK = 80MHz,
Figure 27. AC Measurement I/O Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
42
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
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EN25Q32A
Table 11. AC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
FR
Alt
fC
fR
tCH
Parameter
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
Serial Clock Frequency for:
RDSR, RDID, Dual Output Fast Read and
Quad I/O Fast Read
Serial Clock Frequency for READ,
1
tCL1
Min
Typ
Max
Unit
D.C.
100
MHz
D.C.
80
MHz
D.C.
50
MHz
Serial Clock High Time
4
ns
Serial Clock Low Time
4
ns
tCLCH
2
Serial Clock Rise Time (Slew Rate)
0.1
V / ns
tCHCL
2
Serial Clock Fall Time (Slew Rate)
0.1
V / ns
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
5
ns
15
50
ns
ns
tSLCH
tCSS
tSHSL
tCSH
CS# High Time for read
CS# High Time for program/erase
tSHQZ 2
tDIS
Output Disable Time
tCLQX
tHO
Output Hold Time
0
ns
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCLQV
tV
Output Valid from CLK
6
8
ns
ns
tWHSL3
Write Protect Setup Time before CS# Low
20
ns
tSHWL3
Write Protect Hold Time after CS# High
100
ns
tDP 2
CS# High to Deep Power-down Mode
tRES1 2
tW
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
tPP
tSE
tBE
tCE
tRES2 2
3
µs
3
µs
1.8
µs
10
15
ms
Page Programming Time
1.3
5
ms
Sector Erase Time
0.09
0.3
s
Block Erase Time
0.5
2
s
Chip Erase Time
25
50
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
43
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 28. Serial Output Timing
Figure 29. Input Timing
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
ABSOLUTE MAXIMUM RATINGS
Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up
to or above these values. Exposure of the device to the maximum rating values for extended periods of
time may adversely affect the device reliability.
Parameter
Value
Unit
Storage Temperature
-65 to +150
°C
Plastic Packages
-65 to +125
°C
Output Short Circuit Current1
200
mA
Input and Output Voltage
(with respect to ground) 2
-0.5 to +4.0
V
Vcc
-0.5 to +4.0
V
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5
V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
RECOMMENDED OPERATING RANGES 1
Parameter
Value
Ambient Operating Temperature
Industrial Devices
-40 to 85
Operating Supply Voltage
Vcc
Full: 2.7 to 3.6
Unit
°C
V
Notes:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Maximum Positive Overshoot Waveform
45
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Table 12. DATA RETENTION and ENDURANCE
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
-40 to 85 °C
100k
cycles
Data Retention Time
Erase/Program Endurance
Table 13. CAPACITANCE
( VCC = 2.7-3.6V)
Parameter Symbol
Parameter Description
Test Setup
Max
Unit
CIN
Input Capacitance
VIN = 0
Typ
6
pF
COUT
Output Capacitance
VOUT = 0
8
pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
46
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
PACKAGE MECHANICAL
Figure 30. SOP 200 mil ( official name = 208 mil )
SYMBOL
DIMENSION IN MM
NOR
1.975
0.15
1.825
5.275
7.90
5.275
1.27
0.425
0.65
MIN.
MAX
A
1.75
2.20
A1
0.05
0.25
A2
1.70
1.95
D
5.15
5.40
E
7.70
8.10
E1
5.15
5.40
e
----b
0.35
0.50
L
0.5
0.80
0
0
0
θ
0
4
8
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
47
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 31. VDFN8 ( 5x6mm )
Controlling dimensions are in millimeters (mm).
DIMENSION IN MM
MIN.
NOR
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.04
A2
--0.20
--D
5.90
6.00
6.10
E
4.90
5.00
5.10
D2
3.30
3.40
3.50
E2
3.90
4.00
4.10
e
--1.27
--b
0.35
0.40
0.45
L
0.55
0.60
0.65
Note : 1. Coplanarity: 0.1 mm
SYMBOL
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
48
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Figure 32. PDIP8
SYMBOL
A
A1
A2
D
E
E1
L
eB
Θ0
DIMENSION IN INCH
MIN.
NOR
MAX
----0.210
0.015
----0.125
0.130
0.135
0.355
0.365
0.400
0.300
0.310
0.320
0.245
0.250
0.255
0.115
0.130
0.150
0.310
0.350
0.375
0
7
15
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
49
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
50
©2004 Eon Silicon Solution, Inc.,
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EN25Q32A
ORDERING INFORMATION
EN25Q32A
-
100
H
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
H = 8-pin 200mil SOP
W = 8-pin VDFN
Q = 8-pin PDIP
SPEED
100 = 100 Mhz
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
25Q = 3V Serial Flash with 4KB Uniform-Sector,
Dual and Quad I/O
32A = 32 Megabit (4096K x 8)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
51
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com
EN25Q32A
Revisions List
Revision No Description
A
B
C
Date
Initial Release
2009/04/28
1. Add Figure 4. Quad SPI Modes on page 10.
2. Add Figure 7.1 Write Enable/Disable Instruction Sequence under
EQIO Mode on page 17.
3. Add Figure 8.1 Read Status Register Instruction Sequence under
EQIO Mode on page 18.
4. Add Figure 9.1 Write Status Register Instruction Sequence under
EQIO Mode on page 20.
5. Add Figure 11.1 Fast Read Instruction Sequence under EQIO Mode
on page 22.
6. Add Figure 14.1. Quad Input / Output Fast Read Instruction Sequence
under EQIO Mode on page 26.
7. Add Figure 15.1 Quad Input/Output Fast Read Enhance Performance
2009/07/27
Mode Sequence under EQIO Mode on page 28.
8. Add Figure 16.1 Program Instruction Sequence under EQIO Mode on
page 30.
9. Add Figure 18.1 Block/Sector Erase Instruction Sequence under
EQIO Mode on page 32.
10. Add Figure 19.1 Chip Erase Sequence under EQIO Mode on page
34.
11. Add Figure 23.1. Read Manufacturer / Device ID Diagram under
EQIO Add Mode on page 37.
12. Add Figure 24.1. Read Identification (RDID) under EQIO Mode on
page 39.
13. Add Figure 25.1 Enter OTP Mode Sequence under EQIO Mode on
page 40.
Modify Table 9. DC Characteristics ICC1 (Standby) and ICC2 (Deep Power2009/10/13
down) Current from 5µA to 20µA on page 42.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
52
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com