EN25F40A - Eon Silicon Solution Inc.

EN25F40A
EN25F40A
4 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
•
•
•
-
Single power supply operation
Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
SPI Compatible: Mode 0 and Mode 3
4 M-bit Serial Flash
4 M-bit/512 K-byte/2,048 pages
256 bytes per programmable page
•
•
•
•
-
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD#
Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
High performance
104MHz clock rate for Standard SPI
104MHz clock rate for two data bits
104MHz clock rate for four data bits
Low power consumption
10mA typical active current
1 μA typical power down current
Uniform Sector Architecture:
128 sectors of 4-Kbyte
16 blocks of 32-Kbyte
8 blocks of 64-Kbyte
Any sector or block can be erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Page program time: 0.8ms typical
- Sector erase time: 30ms typical
- 32KB Block erase time 100ms typical
- 64KB Block erase time 200ms typical
- Chip erase time: 1.5 seconds typical
• Lockable 512 byte OTP security sector
• Support Serial Flash Discoverable
Parameters (SFDP) signature
• Read Unique ID Number
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 150mil body width
- 8 pins VSOP 150mil body width
- 8 contact USON 2x3 mm
- 8 contact VDFN 5x6 mm
- All Pb-free packages are compliant RoHS,
Halogen-Free and REACH.
• Industrial temperature Range
GENERAL DESCRIPTION
The EN25F40A is a 4 Megabit (512 K-byte) Serial Flash memory, with enhanced write protection
mechanisms. The EN25F40A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select,
Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 104MHz are
supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 416MHz
(104MHz x 4) for Quad Output when using the Dual/Quad I/O Fast Read instructions. The memory can
be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The EN25F40A is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25F40A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
1
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
Figure.1 CONNECTION DIAGRAMS
CS#
1
8
VCC
DO (DQ1)
2
7
HOLD# (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD SOP / VSOP
CS#
1
8
VCC
DO (DQ1)
2
7
HOLD# (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD USON / VDFN
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
2
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
Figure 2. BLOCK DIAGRAM
Flash
Memory
X-Decoder
Address
Buffer
And
Latches
Y-Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CS#
CLK
DI (DQ0)
DO (DQ1)
WP# (DQ2)
HOLD# (DQ3)
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
3
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
Table 1. Pin Names
Symbol
Pin Name
CLK
Serial Clock Input
DI (DQ0)
Serial Data Input (Data Input Output 0)
DO (DQ1)
Serial Data Output (Data Input Output 1)
CS#
Chip Select
WP# (DQ2)
Write Protect (Data Input Output 2)
HOLD# (DQ3)
HOLD# pin (Data Input Output 3)
Vcc
Supply Voltage (2.7-3.6V)
Vss
Ground
NC
No Connect
*1
*1
*2
*2
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ2 ~ DQ3 are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25F40A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
4
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
MEMORY ORGANIZATION
The memory is organized as:
z
524,288 bytes
z
Uniform Sector Architecture
16 blocks of 32-Kbyte
8 blocks of 64-Kbyte
128 sectors of 4-Kbyte
z
2,048 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
5
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
Table 2. Uniform Block Sector Architecture
0
4
3
2
1
0
….
….
….
….
….
….
….
….
….
050FFFh
04FFFFh
64
63
040000h
03F000h
040FFFh
03FFFFh
….
5
050000h
04F000h
48
47
030000h
02F000h
030FFFh
02FFFFh
….
6
80
79
32
31
020000h
01F000h
020FFFh
01FFFFh
….
7
060FFFh
05FFFFh
….
8
060000h
05F000h
….
9
96
95
….
10
070FFFh
06FFFFh
….
11
070000h
06F000h
16
15
010000h
00F000h
010FFFh
00FFFFh
….
1
12
112
111
….
2
13
07FFFFh
….
3
14
07F000h
….
4
127
….
5
15
Address range
….
6
Sector
….
7
32KB Block
….
64KB Block
0
000000h
000FFFh
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
OPERATING FEATURES
Standard SPI Modes
The EN25F40A is accessed through a SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as
shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby
and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For
Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising
edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction
The EN25F40A supports Dual SPI operation when using the “Dual Output Fast Read and Dual I/O Fast
Read “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the Serial
Flash memory at two to three times the rate possible with the standard SPI. The Dual Read instructions
are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for
application that cache code-segments to RAM for execution. The Dual output feature simply allows the
SPI input pin to also serve as an output during this instruction. When using Dual SPI instructions the DI
and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use the standard SPI
interface with single output signal.
Quad I/O SPI Modes
The EN25F40A supports Quad input / output operation when using the Quad I/O Fast Read (EBh).This
instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate
possible with the standard SPI. The Quad Read instruction offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or for application
that cache code-segments to RAM for execution. When using Quad SPI instruction the DI and DO pins
become bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD# pins become DQ2 and DQ3
respectively.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
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EN25F40A
Figure 4. Quad I/O SPI Modes
Full Quad SPI Modes (QPI)
The EN25F40A also supports Full Quad SPI Mode (QPI) function while using the Enable Quad
Peripheral Interface mode (EQPI) (38h). When using Quad SPI instruction the DI and DO pins become
bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD# pins become DQ2 and DQ3 respectively.
Figure 5. Full Quad SPI Modes
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
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EN25F40A
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) or Quad Input Page Program (QPP) sequence, which consists of four bytes plus
data. This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) or Quad Input Page Program (QPP) instruction allows
up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in
consecutive addresses on the same page of memory.
Sector Erase, Half Block Erase, Block Erase and Chip Erase
The Page Program (PP) or Quad Input Page Program (QPP) instruction allows bits to be reset from 1 to
0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can
be achieved a sector at a time, using the Sector Erase (SE) instruction, half a block at a time using the
Half Block Erase (HBE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE, tHBE, tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP, QPP) or Erase (SE,
HBE, BE or CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tHBE, tBE or tCE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program can
monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, and Write Status Register). The device then goes into the
Stand-by Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read
Device ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate)
by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
WHDIS bit. The WP# and Hold# Disable bit (WHDIS bit), non-volatile bit, it indicates the WP# and
HOLD# are enabled or not. When it is “0” (factory default), the WP# and HOLD# are enabled. On the
other hand, while WHDIS bit is “1”, the WP# and HOLD# are disabled. No matter WHDIS is “0＂ or
“1＂, the system can executes Quad Input/Output FAST_READ (EBh), Quad Input Page Program (32h)
or EQPI (38h) command directly. User can use Flash Programmer to set WHDIS bit as “1＂ and then
the host system can let WP# and HOLD# keep floating in SPI mode.
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
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EN25F40A
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25F40A
provides the following data protection mechanisms:
z
Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z
Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP), Quad Input Page Program (QPP) instruction completion or
Sector Erase (SE) instruction completion or Half Block Erase (HBE) / Block Erase (BE)
instruction completion or Chip Erase (CE) instruction completion
z
The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM).
z
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register Content
BP3
Bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
Bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Memory Content
Protect Areas
Addresses
Density(KB)
Portion
None
None
None
None
Block 7
Block 6 to 7
Block 4 to 7
Block 2 to 7
Block 1 to 7
All
All
None
Block 0
Block 0 to 1
Block 0 to 3
Block 0 to 5
Block 0 to 6
All
All
070000h-07FFFFh
060000h-07FFFFh
040000h-07FFFFh
020000h-07FFFFh
010000h-07FFFFh
000000h-07FFFFh
000000h-07FFFFh
None
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
000000h-05FFFFh
000000h-06FFFFh
000000h-07FFFFh
000000h-07FFFFh
64KB
128KB
256KB
384KB
448KB
512KB
512KB
None
64KB
128KB
256KB
384KB
448KB
512KB
512KB
Upper 1/8
Upper 2/8
Upper 4/8
Upper 6/8
Upper 7/8
All
All
None
Lower 1/8
Lower 2/8
Lower 4/8
Lower 6/8
Lower 7/8
All
All
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
10
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
www.eonssi.com
EN25F40A
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release
from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is
followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a Page Program (PP), Quad Input Page Program (QPP), Sector Erase (SE), Half Block
Erase (HBE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That
is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being
driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), Quad Input Page Program (QPP) and
Release from Deep Power Down (RES ) minimum number of bytes specified has to be given,
without which, the command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE, HBE and BE, exact 24-bit address is a must,
any less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
©2013 Eon Silicon Solution, Inc.,
11
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
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EN25F40A
Table 4A. Instruction Set
Instruction Name
Byte 1
Code
EQPI
38h
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
RSTQIO(1)
Release Quad I/O or
Fast Read Enhanced
Mode
FFh
RSTEN
66h
RST(2)
99h
Write Enable
Write Disable / Exit
OTP mode
Read Status
Register
Write Status
Register
Page Program
06h
Quad Input Page
Program
04h
05h
(S7-S0)(3)
01h
S7-S0
02h
A23-A16
A15-A8
A7-A0
D7-D0
32h
A23-A16
A15-A8
A7-A0
(D7-D0, …) (5)
20h
A23-A16
A15-A8
A7-A0
continuous(4)
Sector Erase
32KB Half Block
Erase (HBE)
64KB Block Erase
52h
A23-A16
A15-A8
A7-A0
D8h
A23-A16
A15-A8
A7-A0
Chip Erase
C7h/ 60h
Deep Power-down
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
Manufacturer/
Device ID
B9h
Next byte
continuous
(one byte
per 2 clocks,
continuous)
(6)
dummy
dummy
dummy
(ID7-ID0)
90h
dummy
dummy
00h
01h
Read Identification
9Fh
(M7-M0)
(ID15-ID8)
(ID7-ID0)
(8)
Enter OTP mode
Read SFDP mode
and Unique ID
Number
3Ah
A23-A16
A15-A8
A7-A0
dummy
ABh
5Ah
(M7-M0)
(ID7-ID0)
(ID7-ID0)
(M7-M0)
(D7-D0)
(7)
(Next Byte)
continuous
Notes:
1. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode
2. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin
4. The Status Register contents will repeat continuously until CS# terminate the instruction
5. Quad Data
DQ0 = (D4, D0, …… )
DQ1 = (D5, D1, …… )
DQ2 = (D6, D2, …... )
DQ3 = (D7, D3, …... )
6. The Device ID will repeat continuously until CS# terminates the instruction
7. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID
8. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity
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©2013 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
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EN25F40A
Table 4B. Instruction Set (Read Instruction)
Instruction Name
Address
bits
OP Code
Dummy bits / Clocks
(Default)
Data Out
Read Data
03h
24 bits
0
(D7-D0, …)
Fast Read
0Bh
24 bits
8 bits / 8 clocks
(D7-D0, …)
Dual Output Fast Read
3Bh
24 bits
8 bits / 8 clocks
(D7-D0, …)
Dual I/O Fast Read
BBh
24 bits
8 bits / 4 clocks
(D7-D0, …)
Quad I/O Fast Read
EBh
24 bits
24 bits / 6 clocks
(D7-D0, …)
Remark
(Next Byte)
continuous
(Next Byte)
continuous
(one byte
Per 4 clocks,
continuous)
(one byte
Per 4 clocks,
continuous)
(one byte
per 2 clocks,
continuous)
Table 4C. Instruction Set (Read Instruction support mode and dummy cycle setting)
Instruction Name
OP Code
Start From SPI/QPI
Dummy Cycle
SPI
QPI
SPI
QPI
Read Data
03h
Yes
No
N/A
N/A
Fast Read
0Bh
Yes
Yes
8 clocks
6 clocks
Dual Output Fast Read
3Bh
Yes
No
8 clocks
N/A
Dual I/O Fast Read
BBh
Yes
No
4 clocks
N/A
Quad I/O Fast Read
EBh
Yes
Yes
Quad Input/Output Fast Read
Enhance Performance Mode
EBh
Yes
Yes
6 clocks
6 clocks
( 2 clocks are
performance
enhance
indicator)
6 clocks
6 clocks
( 2 clocks are
performance
enhance
indicator)
Note:
1. ‘Start From SPI/QPI' means if this command is initiated from SPI or QPI mode.
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EN25F40A
Table 5. Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0)
ABh
(ID7-ID0)
12h
90h
1Ch
9Fh
1Ch
12h
3113h
Enable Quad Peripheral Interface mode (EQPI) (38h)
The Enable Quad Peripheral Interface mode (EQPI) instruction will enable the flash device for Quad
SPI bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed
input/output until a power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 6. The
device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh), Dual
Input/Output FAST_READ (BBh) and Quad Input Page Program (32h) modes while the Enable Quad
Peripheral Interface mode (EQPI) (38h) turns on.
Figure 6. Enable Quad Peripheral Interface mode Sequence Diagram
Reset Quad I/O (RSTQIO) or Release Quad I/O Fast Read Enhancement Mode (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. This command can’t be used in Standard SPI mode.
User also can use the 0xFFh command to release the Quad I/O Fast Read Enhancement Mode. The
detail description, please see the Quad I/O Fast Read Enhancement Mode section.
Note:
If the system is in the Quad I/O Fast Read Enhance Mode in QPI Mode, it is necessary to execute
0xFFh command by two times. The first 0xFFh command is to release Quad I/O Fast Read Enhance
Mode, and the second 0xFFh command is to release QPI Mode.
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EN25F40A
Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)
The Reset operation is used as a system (software) reset that puts the device in normal operating
Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the EN25F40A the host drives CS# low, sends the Reset-Enable command (66h), and drives
CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any
command other than the Reset command after the Reset-Enable command will disable the ResetEnable.
A successful command execution will reset the Status register and the Information register to data =
00h, see Figure 7 for SPI Mode and Figure 7.1 for QPI Mode. A device reset during an active Program
or Erase operation aborts the operation, which can cause the data of the targeted address range to be
corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write
operation requires more software latency time (tSR) than recovery from other operations. Please Figure
7.2.
Figure 7. Reset-Enable and Reset Sequence Diagram
Figure 7.1 Reset-Enable and Reset Sequence Diagram in QPI Mode
Figure 7.2 Software Reset Recovery
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EN25F40A
Software Reset Flow
Initial
Command
= 66h ?
No
Yes
Reset enable
Command
= 99h ?
No
Yes
Reset start
No
WIP = 0 ?
Embedded
Reset Cycle
Yes
Reset done
Note:
1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or QPI
(Full Quad) mode.
2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST)
(99h) commands.
3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows:
Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h)
-> SPI Reset (RST) (99h) to reset.
4. The reset command could be executed during embedded program and erase process, QPI mode
and Continue EB mode to back to SPI mode.
5. This flow cannot release the device from Deep power down mode.
6. The Status Register Bit and Information register Bit will reset to default value after reset done.
7. If user reset device during erase, the embedded reset cycle software reset latency will take about
28us in worst case.
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EN25F40A
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Quad Input Page Program (QPP),
Sector Erase (SE), Half Block Erase (HBE), Block Erase (BE), Chip Erase (CE) and Write Status
Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 8. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 9) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program (PP), Quad Input Page Program (QPP), Sector Erase, Half Block Erase
(HBE), Block Erase (BE) and Chip Erase instructions.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 9. Write Disable Instruction Sequence Diagram
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EN25F40A
Figure 9.1 Write Enable/Disable Instruction Sequence in QPI Mode
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 10.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 10. Read Status Register Instruction Sequence Diagram
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EN25F40A
Figure 10.1 Read Status Register Instruction Sequence in QPI Mode
Table 6. Status Register Bit Locations
S7
S6
S5
WHDIS
SRP
OTP_LOCK
BP3
WP# &
Status
bit
(Block
Register
Hold#
Protected bits)
(note 1)
Protect
Disable bit
1 = status
register write
disable
1 = OTP
sector is
protected
Non-volatile bit
1 = WP# and
HOLD# disable
0 = WP# and
HOLD# enable
(note 2)
S4
S3
S2
S1
BP2
BP1
BP0
WEL
(Block
(Block
(Block
(Write Enable
Protected bits) Protected bits) Protected bits)
Latch)
(note 2)
(note 2)
(note 2)
Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit
S0
WIP
(Write In
Progress bit)
(Note 3)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
volatile bit
volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP), Quad Input Page Program (QPP), Sector Erase (SE) and , Block Erase
(BE), instructions. The Block Protect (BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is executed if, and only if, all
Block Protect (BP3, BP2, BP1, BP0) bits are 0.
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EN25F40A
WHDIS bit. The WP# and Hold# Disable bit (WHDIS bit), non-volatile bit, it indicates the WP# and
HOLD# are enabled or not. When it is “0” (factory default), the WP# and HOLD# are enabled. On the
other hand, while WHDIS bit is “1”, the WP# and HOLD# are disabled. No matter WHDIS is “0＂ or
“1＂, the system can executes Quad Input/Output FAST_READ (EBh), Quad Input Page Program (32h)
or EQPI (38h) command directly. User can use Flash Programmer to set WHDIS bit as “1＂ and then
the host system can let WP# and HOLD# keep floating in SPI mode.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set
to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register
(SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is
no longer accepted for execution.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
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EN25F40A
Figure 11. Write Status Register Instruction Sequence Diagram
Figure 11.1 Write Status Register Instruction Sequence in QPI Mode
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EN25F40A
Read Data Bytes (READ) (03h)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 12. The first byte addresses can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When
the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 12. Read Data Instruction Sequence Diagram
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EN25F40A
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory
contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a
maximum frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes
at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
The instruction sequence is shown in Figure 13.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 13. Fast Read Instruction Sequence Diagram
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Figure 13.1 Fast Read Instruction Sequence in QPI Mode
Dual Output Fast Read (3Bh)
The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from
the EN25F40A at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is ideal
for quickly downloading code from to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy clocks after the 24-bit address as shown in Figure 14. The dummy clocks allow the device’s
internal circuits additional time for setting up the initial address. The input data during the dummy clock
is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data
out clock.
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EN25F40A
Figure 14. Dual Output Fast Read Instruction Sequence Diagram
Dual Input / Output FAST_READ (BBh)
The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO
pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to
input the Address bits (A23-A0) two bits per clock. This reduced instruction overhead may allow for
code execution (XIP) directly from the Dual SPI in some applications.
The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The
address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on
the falling edge of CLK at a maximum frequency. The first address can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following
address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 15.
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EN25F40A
Figure 15. Dual Input / Output Fast Read Instruction Sequence Diagram
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EN25F40A
Quad Input / Output FAST_READ (EBh)
The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins, DQ0, DQ1, DQ2 and
DQ3 and six dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O
pins) shift our on the falling edge of CLK at a maximum frequency FR. The first address can be any
location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->
sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2,
DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad
Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown
in Figure 16.
The instruction sequence is shown in Figure 16.1 while using the Enable Quad Peripheral Interface mode (EQPI)
(38h) command.
Figure 16. Quad Input / Output Fast Read Instruction Sequence Diagram
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Figure 16.1. Quad Input / Output Fast Read Instruction Sequence in QPI Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4
dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit access address, as shown in
Figure 17.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And
afterwards CS# is raised, the system then will escape from performance enhance mode and return to
normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 17.1 while using the Enable Quad Peripheral Interface mode (EQPI)
(38h) command.
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EN25F40A
Figure 17. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram
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EN25F40A
Figure 17.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence in QPI Mode
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EN25F40A
Page Program (PP) (02h)
The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 18. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 18.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 18. Page Program Instruction Sequence Diagram
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Figure 18.1 Program Instruction Sequence in QPI Mode
Quad Input Page Program (QPP) (32h)
The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at
previously erased (FFh) memory locations using four pins: DQ0, DQ1, DQ2 and DQ3. The Quad Page
Program can improve performance for PROM Programmer and applications that have slow clock
speeds < 5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page
Program instruction since the inherent page program time is much greater than the time it take to clockin the data.
A Write Enable instruction must be executed before the device will accept the Quad Page Program
(QPP) instruction (Status Register-1, WEL=1). The instruction is initiated by driving the CS# pin low
then shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte,
into the IO pins. The CS# pin must be held low for the entire length of the instruction while data is being
sent to the device. All other functions of Quad Page Program (QPP) are identical to standard Page
Program. The Quad Page Program (QPP) instruction sequence is shown in Figure 19.
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EN25F40A
CS#
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
CLK
Command
32h
DQ0
3 Address bytes
(24 clocks)
A23 A22 A21
A3
A2
A1
A0
*
DQ1
DQ2
DQ3
*
= MSB
CS#
31
32
33
34
35
36
37
534 535 536 537 538 539 540 541 542 543
CLK
Data
Byte
1
DQ0
A0
Data
Byte
2
Data
Byte
3
Data
Byte
252
Data
Byte
253
Data
Byte
254
Data
Byte
255
Data
Byte
256
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
DQ1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
DQ2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
DQ3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
*
*
*
*
*
*
*
*
Figure 19. Quad Input Page Program Instruction Sequence Diagram (SPI Mode only)
Sector Erase (SE) (20h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 20. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
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EN25F40A
self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 22.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 20. Sector Erase Instruction Sequence Diagram
32KB Half Block Erase (HBE) (52h)
The Half Block Erase (HBE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Half Block Erase (HBE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Half Block Erase (HBE) instruction. Chip Select (CS#) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 21. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Half Block Erase (HBE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Half Block Erase cycle (whose
duration is tHBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Half Block Erase cycle, and is 0 when it is completed. At some unspecified time before
the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Half Block Erase (HBE) instruction applied to a block which is protected by the Block Protect (BP3,
BP2, BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 22.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25F40A
Figure 21. 32KB Half Block Erase Instruction Sequence Diagram
64KB Block Erase (BE) (D8h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 22. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 22.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25F40A
Figure 22. 64KB Block Erase Instruction Sequence Diagram
Figure 22.1 Half Block/Block/Sector Erase Instruction Sequence in QPI Mode
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EN25F40A
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 23. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0.
The Chip Erase (CE) instruction is ignored if one, or more blocks are protected.
The instruction sequence is shown in Figure 23.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 23. Chip Erase Instruction Sequence Diagram
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EN25F40A
Figure 23.1 Chip Erase Sequence in QPI Mode
Deep Power-down (DP) (B9h)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 12.)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from
this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the
Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 24. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
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EN25F40A
Figure 24. Deep Power-down Instruction Sequence Diagram
Release from Deep Power-down and Read Device ID (RDI)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature
that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
When used only to release the device from the power-down state, the instruction is issued by driving
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 25. After
the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 26. The Device ID value for the EN25F40A are listed in Table 5. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device
was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is
immediate. If the device was previously in the Deep Power-down mode, though, the transition to the
Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2
(max), as specified in Table 14. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
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EN25F40A
Figure 25. Release Power-down Instruction Sequence Diagram
Figure 26. Release Power-down / Device ID Instruction Sequence Diagram
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address of 000000h. After which, the Manufacturer ID for Eon (1Ch) and the
Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 27. The Device ID values for the EN25F40A are listed in Table 5. If the 24-bit address is initially
set to 000001h the Device ID will be read first
The instruction sequence is shown in Figure 27.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25F40A
Figure 27. Read Manufacturer / Device ID Diagram
Figure 27.1. Read Manufacturer / Device ID Diagram in QPI Mode
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EN25F40A
Read Identification (RDID) (9Fh)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being
shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The
instruction sequence is shown in Figure 28. The Read Identification (RDID) instruction is terminated by
driving Chip Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
The instruction sequence is shown in Figure 28.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 28. Read Identification (RDID)
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EN25F40A
Figure 28.1. Read Identification (RDID) in QPI Mode
Enter OTP Mode (3Ah)
This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read,
program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 127, SRP
bit becomes OTP_LOCK bit and can be read with RDSR command. The Chip Erase, Bank Erase and
Half Bank Erase commands are also disabled.
In OTP mode, user can read other sectors, but program/erase other sectors only allowed when
OTP_LOCK bit equal to ‘0’.
WRSR command will ignore the input data and program OTP_LOCK bit to 1.
User can use WRDI (04h) command to exit OTP mode.
The instruction sequence is shown in Figure 28.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Erase OTP Command (20h)
User only can use Sector Erase (20h) command to erase OTP data.
Table 7. OTP Sector Address
Sector
Sector Size
Address Range
127
512 byte
07F000h – 07F1FFh
Note: The OTP sector is mapping to sector 127.
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EN25F40A
Figure 29. Enter OTP Mode Sequence
Figure 29.1 Enter OTP Mode Sequence in QPI Mode
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EN25F40A
Read SFDP Mode and Unique ID Number (5Ah)
Read SFDP Mode
EN25F40A features Serial Flash Discoverable Parameters (SFDP) mode. Host system can retrieve the
operating characteristics, structure and vendor specified information such as identifying information,
memory size, operating voltage and timing information of this device by SFDP mode.
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read SFDP
Mode is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 30. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Serial Flash Discoverable Parameters (SFDP)
instruction. When the highest address is reached, the address counter rolls over to 0x00h, allowing the
read sequence to be continued indefinitely. The Serial Flash Discoverable Parameters (SFDP)
instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at
any time during data output. Any Read Data Bytes at Serial Flash Discoverable Parameters (SFDP)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure 30. Read SFDP Mode and Unique ID Number Instruction Sequence Diagram
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EN25F40A
Table 8. Serial Flash Discoverable Parameters (SFDP) Signature and Parameter Identification
Data Value (Advanced Information)
Description
SFDP Signature
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers (NPH)
Unused
ID Number
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length (in DW)
Parameter Table Pointer (PTP)
Unused
Address (h)
Address (Bit)
(Byte Mode)
Data
Comment
00h
01h
02h
03h
04h
05h
06h
07h
08h
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
53h
46h
44h
50h
00h
01h
00h
FFh
00h
Star from 0x00
Star from 0x01
1 parameter header
Reserved
JEDEC ID
09h
15 : 08
00h
Star from 0x00
0Ah
23 : 16
01h
Star from 0x01
0Bh
0Ch
0Dh
0Eh
0Fh
31 : 24
07 : 00
15 : 08
23 : 16
31 : 24
09h
30h
00h
00h
FFh
9 DWORDs
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Signature [31:0]:
Hex: 50444653
000030h
Reserved
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EN25F40A
Table 9. Parameter ID (0) (Advanced Information) 1/9
Description
Address (h)
(Byte Mode)
Address
(Bit)
Block / Sector Erase sizes
Identifies the erase granularity for all Flash
Components
00
Write Granularity
Write Enable Instruction Required for
Writing to Volatile Status Register
Write Enable Opcode Select for Writing to
Volatile Status Register
02
30h
01b
1b
0 = No, 1 = Yes
00b
00 = N/A
01 = use 50h opcode
11 = use 06h opcode
03
04
31h
Supports (1-1-2) Fast Read
Device supports single input opcode & address
and dual output data Fast Read
05
06
07
08
09
10
11
12
13
14
15
111b
4 KB Erase Support
(FFh = not supported)
1b
0 = not supported
1 = supported
00b
00 = 3-Byte
01 = 3- or 4-Byte (e.g.
defaults to 3-Byte
mode; enters 4-Byte
mode on command)
10 = 4-Byte
11 = reserved
19
0b
0 = not supported
1 = supported
20
1b
0 = not supported
1 = supported
21
1b
0 = not supported
1 = supported
22
0b
0 = not supported
1 = supported
23
24
1b
Reserved
FFh
Reserved
17
Supports Double Transfer Rate (DTR)
Clocking
Indicates the device supports some type of
double transfer rate clocking.
Supports (1-2-2) Fast Read
Device supports single input opcode, dual input
address, and dual output data Fast Read
Supports (1-4-4) Fast Read
Device supports single input opcode, quad input
address, and quad output data Fast Read
Supports (1-1-4) Fast Read
Device supports single input opcode & address
and quad output data Fast Read
Unused
18
32h
Reserved
20h
16
Address Byte
Number of bytes used in addressing for flash arra
write and erase.
Comment
00 = reserved
01 = 4KB erase
10 = reserved
11 = 64KB erase
01
Unused
4 Kilo-Byte Erase Opcode
Data
25
26
Unused
33h
27
28
29
30
31
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EN25F40A
Table 9. Parameter ID (0) (Advanced Information) 2/9
Description
Flash Memory Density
Address (h)
(Byte Mode)
37h : 34h
Address
(Bit)
31 : 00
Data
Comment
003FFFFFh
4 Mbits
Data
Comment
00100b
4 dummy clocks
010b
8 mode bits
Table 9. Parameter ID (0) (Advanced Information) 3/9
Description
(1-4-4) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
38h
Quad Input Address Quad Output (1-44) Fast Read Number of Mode Bits
(1-4-4) Fast Read Opcode
Opcode for single input opcode, quad input
address, and quad output data Fast Read.
(1-1-4) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
39h
3Ah
(1-1-4) Fast Read Number of Mode Bits
(1-1-4) Fast Read Opcode
Opcode for single input opcode & address
and quad output data Fast Read.
3Bh
Address
(Bit)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
31 : 24
EBh
00000b
Not Supported
000b
Not Supported
FFh
Not Supported
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EN25F40A
Table 9. Parameter ID (0) (Advanced Information) 4/9
Description
(1-1-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
3Ch
(1-1-2) Fast Read Number of Mode Bits
(1-1-2) Fast Read Opcode
Opcode for single input opcode & address
and dual output data Fast Read.
(1-2-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
3Dh
15 : 08
3Eh
16
17
18
19
20
21
22
23
(1-2-2) Fast Read Number of Mode Bits
(1-2-2) Fast Read Opcode
Opcode for single input opcode, dual input
address, and dual output data Fast Read.
Address
(Bit)
00
01
02
03
04
05
06
07
3Fh
Data
Comment
01000b
8 dummy clocks
000b
Not Supported
3Bh
00100b
4 dummy clocks
000b
Not Supported
31 : 24
BBh
Address
(Bit)
Data
Supports (2-2-2) Fast Read
Device supports dual input opcode &
address and dual output data Fast Read.
00
0b
Reserved. These bits default to all 1’s
01
02
03
111b
04
1b
Table 9. Parameter ID (0) (Advanced Information) 5/9
Description
Supports (4-4-4) Fast Read
Device supports Quad input opcode &
address and quad output data Fast Read.
Address (h)
(Byte Mode)
40h
Reserved. These bits default to all 1’s
Reserved. These bits default to all 1’s
43h : 41h
05
06
07
31 : 08
Comment
0 = not supported
1 = supported
Reserved
0 = not supported
1 = supported
(QPI Mode)
111b
Reserved
FFh
Reserved
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EN25F40A
Table 9. Parameter ID (0) (Advanced Information) 6/9
Description
Reserved. These bits default to all 1’s
(2-2-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
45h : 44h
46h
(2-2-2) Fast Read Number of Mode Bits
(2-2-2) Fast Read Opcode
Opcode for dual input opcode & address
and dual output data Fast Read.
47h
Address
(Bit)
15 : 00
16
17
18
19
20
21
22
23
31 : 24
Data
Comment
FFh
Reserved
00000b
Not Supported
000b
Not Supported
FFh
Not Supported
Data
Comment
Table 9. Parameter ID (0) (Advanced Information) 7/9
Description
Reserved. These bits default to all 1’s
(4-4-4) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
49h : 48h
4Ah
(4-4-4) Fast Read Number of Mode Bits
(4-4-4) Fast Read Opcode
Opcode for quad input opcode/address,
quad output data Fast Read.
4Bh
Address
(Bit)
15 : 00
16
17
18
19
20
21
22
23
FFh
Reserved
00100b
4 dummy clocks
010b
8 mode bits
31 : 24
EBh
Must Enter QPI Mode
Firstly
Data
Comment
0Ch
20h
0Fh
52h
4 KB
Table 9. Parameter ID (0) (Advanced Information) 8/9
Description
Sector Type 1 Size
Sector Type 1 Opcode
Sector Type 2 Size
Sector Type 2 Opcode
Address (h)
(Byte Mode)
4Ch
4Dh
4Eh
4Fh
Address
(Bit)
07 : 00
15 : 08
23 : 16
31 : 24
32 KB
Table 9. Parameter ID (0) (Advanced Information) 9/9
Description
Sector Type 3 Size
Sector Type 3 Opcode
Sector Type 4 Size
Sector Type 4 Opcode
Address (h)
(Byte Mode)
50h
51h
52h
53h
Address
(Bit)
07 : 00
15 : 08
23 : 16
31 : 24
Data
Comment
10h
D8h
00h
FFh
64 KB
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or modifications due to changes in technical specifications.
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Not Supported
Not Supported
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EN25F40A
Read Unique ID Number
The Read Unique ID Number instruction accesses a factory-set read-only 96-bit number that is unique
to each EN25F40A device. The ID number can be used in conjunction with user software methods to
help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the
CS# pin low and shifting the instruction code “5Ah” followed by a three bytes of addresses, 0x80h, and
one byte of dummy clocks. After which, the 96-bit ID is shifted out on the falling edge of CLK as shown
in Figure 30.
Table 10. Unique ID Number
Description
Address (h)
(Byte Mode)
Address
(Bit)
Data
Unique ID Number
80h : 8Bh
95 : 00
By die
Comment
Power-up Timing
Figure 31. Power-up Timing
Table 11. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
10
tPUW(1)
Time delay to Write instruction
1
10
ms
Write Inhibit Voltage
1
2.2
V
VWI(1)
µs
Note:
1.The parameters are characterized only.
2. VCC (max.) is 3.6V and VCC (min.) is 2.7V
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
The Status Register contains 00h (all Status Register bits are 0).
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or modifications due to changes in technical specifications.
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EN25F40A
Table 12. DC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
ICC2
ICC3
ICC4
Min.
Typ.
Max.
Unit
-
1
±2
µA
-
1
±2
µA
Standby Current
CS# = VCC, VIN = VSS or
VCC
-
1
20
µA
Deep Power-down
Current
CS# = VCC, VIN = VSS or
VCC
-
1
20
µA
CLK = 0.1 VCC / 0.9 VCC at
104MHz, DQ = open
-
8
15
mA
5
8
mA
12
18
mA
6
10
mA
-
10
28
mA
CS# = VCC
-
5
12
mA
CS# = VCC
CS# = VCC
-
10
25
mA
-
10
25
mA
CLK = 0.1 VCC / 0.9 VCC at
33MHz, DQ = open
CLK = 0.1 VCC / 0.9 VCC at
104MHz in Quad mode,
DQ = open
CLK = 0.1 VCC / 0.9 VCC at
33MHz in Quad mode,
DQ = open
CS# = VCC
Operating Current
(READ)
-
ICC6
Operating Current (PP)
Operating Current
(WRSR)
Operating Current (SE)
ICC7
Operating Current (BE)
VIL
Input Low Voltage
– 0.5
0.2 VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
-
0.4
V
VCC-0.2
-
V
ICC5
VOL
Output Low Voltage
IOL = 1.6 mA
VOH
Output High Voltage
IOH = –100 µA
Note : Typical condition at VCC 3.3V, T = 25℃. as our design target
Table 13. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Max.
Load Capacitance
30
Input Rise and Fall Times
Unit
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
Figure 32. AC Measurement I/O Waveform
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or modifications due to changes in technical specifications.
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EN25F40A
Table 14. AC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Alt
Parameter
Min
Typ
Max
Unit
D.C.
-
104
MHz
D.C.
-
104
MHz
MHz
fR
Serial Clock Frequency for:
FAST_READ, PP, QPP, SE, HBE, BE, DP, RES,
WREN, WRDI, WRSR, RDSR
Serial Clock Frequency for:
RDID, Dual Output Fast Read and Quad I/O Fast
Read
Serial Clock Frequency for READ
D.C.
-
50
tCH 1
Serial Clock High Time
4
-
-
ns
tCL1
Serial Clock Low Time
4
-
-
ns
tCLCH2
Serial Clock Rise Time (Slew Rate)
0.1
-
-
V / ns
tCHCL 2
Serial Clock Fall Time (Slew Rate)
0.1
-
-
V / ns
FR
fC
tSLCH
tCSS
CS# Active Setup Time (Relative to CLK)
5
-
-
ns
tCHSH
CS# Active Hold Time (Relative to CLK)
5
-
-
ns
tSHCH
CS# Not Active Setup Time (Relative to CLK)
5
-
-
ns
tCHSL
CS# Not Active Hold Time (Relative to CLK)
5
-
-
ns
CS# High Time for read
CS# High Time for program/erase
7
30
-
-
ns
ns
tSHSL
tCSH
tSHQZ 2
tDIS
Output Disable Time
-
-
6
ns
tCLQX
tHO
Output Hold Time
0
-
-
ns
tDVCH
tDSU
Data In Setup Time
2
-
-
ns
tCHDX
tDH
Data In Hold Time
5
-
-
ns
tHLCH
HOLD# Low Setup Time ( relative to CLK )
5
ns
tHHCH
HOLD# High Setup Time ( relative to CLK )
5
ns
tCHHH
HOLD# Low Hold Time ( relative to CLK )
5
ns
tCHHL
HOLD# High Hold Time ( relative to CLK )
5
ns
tHLQZ
2
tHZ
HOLD# Low to High-Z Output
6
ns
tHHQX
2
tLZ
HOLD# High to Low-Z Output
6
ns
tV
Output Valid from CLK for 30 pF
Output Valid from CLK for 15 pF
tCLQV
-
-
8
6
ns
tWHSL3
Write Protect Setup Time before CS# Low
20
-
-
ns
tSHWL3
Write Protect Hold Time after CS# High
100
-
-
ns
-
-
3
µs
-
-
3
µs
-
-
1.8
µs
tW
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
-
2
15
ms
tPP
tDP
2
tRES1 2
tRES2 2
Page Programming Time
-
0.8
3
ms
tSE
Sector Erase Time
-
0.03
0.2
s
tHBE
32KB Block Erase Time
0.1
0.8
s
tBE
64KB Block Erase Time
-
0.2
1
s
tCE
Chip Erase Time
-
1.5
7.5
s
tSR
Software Reset
Latency
WIP = write operation
-
-
28
µs
WIP = not in write operation
-
-
0
µs
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
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or modifications due to changes in technical specifications.
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EN25F40A
Figure 33. Serial Output Timing
Figure 34. Input Timing
Figure 35. Hold Timing
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Rev. A, Issue Date: 2013/11/18
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EN25F40A
ABSOLUTE MAXIMUM RATINGS
Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up
to or above these values. Exposure of the device to the maximum rating values for extended periods of
time may adversely affect the device reliability.
Parameter
Value
Unit
Storage Temperature
-65 to +150
C
Plastic Packages
-65 to +125
C
Output Short Circuit Current1
200
mA
Input and Output Voltage
(with respect to ground) 2
-0.5 to +4.0
V
Vcc
-0.5 to +4.0
V
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V.
During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
RECOMMENDED OPERATING RANGES 1
Parameter
Value
Ambient Operating Temperature
Industrial Devices
-40 to 85
Operating Supply Voltage
Vcc
Full: 2.7 to 3.6
Unit
C
V
Notes:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
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EN25F40A
Table 15. DATA RETENTION and ENDURANCE
Parameter Description
Test Conditions
Min
Unit
Data Retention Time
85°C
20
Years
Erase/Program Endurance
-40 to 85 °C
100k
cycles
Table 16. CAPACITANCE
( VCC = 2.7-3.6V)
Parameter Symbol
Parameter Description
Test Setup
Max
Unit
CIN
Input Capacitance
VIN = 0
6
pF
COUT
Output Capacitance
VOUT = 0
8
pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
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EN25F40A
PACKAGE MECHANICAL
b
E
E1
Figure 36. SOP 8 ( 150 mil )
e
Detail A
Detail A
DIMENSION IN MM
NOR
MAX
A
--1.75
A1
--0.25
A2
--1.50
D
--5.00
E
--6.20
E1
--4.00
e
1.27
--b
--0.51
L
--1.27
0
0
θ
--0
8
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
SYMBOL
MIN.
1.35
0.10
--4.80
5.80
3.80
--0.33
0.4
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EN25F40A
Figure 37. VSOP 8 ( 150 mil )
A
DIMENSION IN MM
MIN.
NOR
MAX
--0.90
A1
A2
D
E
E1
e
b
L
0.05
0.65
4.80
5.80
3.80
--0.33
0.40
SYMBOL
0.10
0.70
4.90
6.00
3.90
1.27
0.41
0.71
0.15
0.75
5.00
6.20
4.00
--0.51
1.27
θ
0
-10
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
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EN25F40A
Figure 38. USON (8L 2x3mm)
SYMBOL
A
A1
A2
A3
D
E
J
K
e
b
L
L1
L2
MIN.
0.50
0.00
--2.95
1.95
0.10
1.50
0.20
0.30
0.40
---
DIMENSION IN MM
NOR
MAX
0.55
0.60
0.035
0.05
0.40
0.425
0.152 REF
3.00
3.05
2.00
2.05
0.20
0.30
1.60
1.70
0.5 BSC
0.25
0.30
----0.45
0.50
--0.15
Notice: This package can’t contact
to metal trace or pad on board due
to expose metal pad underneath the
package.
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EN25F40A
Figure 39. VDFN8 ( 5x6mm )
Controlling dimensions are in millimeters (mm).
DIMENSION IN MM
MIN.
NOR
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.04
A2
--0.20
--D
5.90
6.00
6.10
E
4.90
5.00
5.10
D2
3.30
3.40
3.50
E2
3.90
4.00
4.10
e
--1.27
--b
0.35
0.40
0.45
L
0.55
0.60
0.65
Note : 1. Coplanarity: 0.1 mm
SYMBOL
Notice: This package can’t contact
to metal trace or pad on board due
to expose metal pad underneath the
package.
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EN25F40A
ORDERING INFORMATION
EN25F40A
-
104
G
I
P
PACKAGING CONTENT
P = RoHS, Halogen-Free and REACH compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
G = 8-pin 150mil SOP
RB = 8-pin 150mil VSOP
X = 8-pin USON (2x3 mm)
W = 8-pin VDFN (5x6 mm)
SPEED
104 = 104 MHz
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
25F = 3V Serial Flash with 4KB Uniform-Sector,
Dual and Quad I/O
40 = 4 Megabit (512K x 8)
A = version identifier
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EN25F40A
Revisions List
Revision No Description
Date
Preliminary 0.0
2013/02/06
Preliminary 0.1
Preliminary 0.2
Preliminary 0.3
A
Initial Release
1. Update Table 12. DC Characteristics on page 52.
2. Update Table 14. AC Characteristics on page 53.
Update Table 3. Protected Area Sizes Sector Organization on page 10.
1. Update Table 12. DC Characteristics on page on page 52.
(1) Update ICC3 (READ / in SPI mode) from 10 to 8 mA (typ.)
(2) Update ICC5 (WRSR) from 10 / 18 mA to 5 / 12 mA (typ. / max.)
2. Update Table 14. AC Characteristics on page 53.
(1) Update Page Program Time (tPP) from 0.7 to 0.8ms (typ.)
(2) Update 32K Half Block Erase Time (tHBE) from 0.5 to 0.8s (max.)
Release A version.
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2013/11/18
2013/03/07
2013/03/18
2013/10/31
2013/11/18
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