TI PCM5100A

PCM5100A, PCM5101A, PCM5102A
www.ti.com
SLAS859 – MAY 2012
2VRMS DirectPath™, 112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface
Check for Samples: PCM5100A, PCM5101A, PCM5102A
FEATURES
1
112 / 106 / 100dB
Dynamic Range
112 / 106 / 100dB
THD+N @ - 1dBFS
–93 / –92 / –90dB
Full Scale Output
2.1VRMS (GND center)
Normal 8× Oversampling Digital Filter Latency: 20tS
Low Latency 8× Oversampling Digital Filter Latency: 3.5tS
Sampling Frequency
8kHz to 384kHz
System Clock Multiples (fSCK): 64, 128, 192, 256, 384, 512,
768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz
Current
Segment
DAC
Current
Segment
DAC
I/V
Zero
Data
Detector
SNR
I/V
DIN (i2s)
PCM5102 / PCM5101 /
PCM5100
Analog
Mute
•
•
Typical Performance (3.3V Power Supply)
Parameter
Analog
Mute
•
32bit ∆Σ Modulator
•
8x Interpolation Filter
•
•
•
Market-Leading Low Out-of-Band Noise
Selectable Digital-Filter Latency &
Performance
No DC Blocking Capacitors Required
Integrated Negative Charge Pump
Internal Pop-Free Control For Sample-Rate
Changes Or Clock Halts
Intelligent Muting System; Soft Up/Down Ramp
& Analog Mute For 120dB Mute SNR With
Popless Operation.
Integrated High-Performance Audio PLL With
BCK Reference To Generate SCK Internally
Supports 1.8V Digital Input Interface
Small 20-pin TSSOP Package
Audio Interface
•
•
23
LINE OUT
Advanced Mute Control
Clock Halt
Detection
PCM510xA
LRCK
BCK
Power
Supply
PLL Clock
MCK
UVP/Reset
POR
Ch. Pump
CPVDD (3.3V)
AVDD (3.3V)
DVDD (1.8V or 3.3V)
GND
CAPP
CAPM
VNEG
Figure 1. PCM510xA Functional Block Diagram
OTHER KEY FEATURES
•
•
•
•
Accepts 16-, 24-, And 32-Bit Audio Data
PCM Data Formats: I2S, Left-Justified
Automatic Power-Save Mode When LRCK And
BCK Are Deactivated.
1.8V or 3.3V Failsafe LVCMOS Digital Inputs
•
•
•
Hardware Configuration
Single Supply Operation:
– 3.3V Analog, 1.8V or 3.3V Digital
Integrated Power-On Reset
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two Cascade, Audio Precision are trademarks of Audio Precision.
DirectPath is a trademark of Texas, Instruments, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
PCM5100A, PCM5101A, PCM5102A
SLAS859 – MAY 2012
www.ti.com
APPLICATIONS
•
•
•
•
A/V Receivers
DVD, BD Players
HDTV Receivers
Applications Requiring 2VRMS Audio Output
DESCRIPTION
The PCM510xA devices are a family of monolithic
CMOS integrated circuits that include a stereo digitalto-analog converter and additional support circuitry in
a small TSSOP package. The PCM510xA uses the
latest generation of TI’s advanced segment-DAC
architecture
to
achieve
excellent
dynamic
performance and improved tolerance to clock jitter.
The PCM510xA provides 2.1VRMS ground centered
outputs, allowing designers to eliminate DC blocking
capacitors on the output, as well as external muting
circuits traditionally associated with single supply line
drivers.
The integrated line driver surpasses all other chargepump based line drivers by supporting loads down to
1kΩ. By supporting loads down to 1kΩ, the
PCM510xA can essentially drive up to 10 products in
parallel. (LCD TV, DVDR, AV Receivers etc).
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock). This allows a 3-wire I2S connection,
along with reduced system EMI.
Intelligent clock error and PowerSense under voltage
protection utilizes a two level mute system for popfree performance. Upon clock error or system power
failure, the device digitally attenuates the data (or last
known good data), then mutes the analog circuit
Compared with existing DAC technology, the
PCM510xA family offers up to 20dB lower out-ofband noise, reducing EMI and aliasing in downstream
amplifiers/ADCs. (from traditional 100kHz OBN
measurements all the way to 3MHz)
The PCM510xA accepts industry-standard audio data
formats with 16- to 32-bit data. Sample rates up to
384kHz are supported.
Table 1. Differences Between PCM510xA Devices
Part Number
Dynamic Range
SNR
THD
PCM5102A
112dB
112dB
–93dB
PCM5101A
106dB
106dB
–92dB
PCM5100A
100dB
100dB
–90dB
spacer
2
Copyright © 2012, Texas Instruments Incorporated
PCM5100A, PCM5101A, PCM5102A
www.ti.com
SLAS859 – MAY 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION
TERMINAL FUNCTIONS, PCM510xA
PCM510xA (top view)
Table 2. TERMINAL FUNCTIONS, PCM510xA
TERMINAL
I/O
DESCRIPTION
1
—
Charge pump power supply, 3.3V
2
O
Charge pump flying capacitor terminal for positive rail
CPGND
3
—
Charge pump ground
CAPM
4
O
Charge pump flying capacitor terminal for negative rail
VNEG
5
O
Negative charge pump rail terminal for decoupling, -3.3V
OUTL
6
O
Analog output from DAC left channel
OUTR
7
O
Analog output from DAC right channel
AVDD
8
-—
Analog power supply, 3.3V
AGND
9
—
Analog ground
DEMP
10
I
De-emphasis control for 44.1kHz sampling rate (1): Off (Low) / On (High)
FLT
11
I
Filter select : Normal latency (Low) / Low latency (High)
SCK
12
I
System clock input (1)
BCK
13
I
Audio data bit clock input (1)
DIN
14
I
Audio data input (1)
LRCK
15
I
Audio data word clock input (1)
FMT
16
I
Audio format selection : I2S (Low) / Left justified (High)
XSMT
17
I
Soft mute control (1): Soft mute (Low) / soft un-mute (High)
LDOO
18
—
Internal logic supply rail terminal for decoupling, or external 1.8V supply
terminal
DGND
19
—
Digital ground
DVDD
20
—
Digital power supply, 1.8V or 3.3V
NAME
NO.
CPVDD
CAPP
(1)
Failsafe LVCMOS Schmitt trigger input
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
Supply Voltage
Digital Input Voltage
UNIT
AVDD, CPVDD, DVDD
–0.3 to 3.9
LDOO wtih DVDD at 1.8V (See 1.8V application circuit)
–0.3 to 2.25
DVDD at 1.8V
–0.3 to 2.25
DVDD at 3.3V
–0.3 to 3.9
Analog Input Voltage
V
–0.3 to 3.9
Operating Temperature Range
–25 to 85
Storage Temperature Range
–65 to 150
°C
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
θJA
Theta JA
ψJT
Psi JT
1.0
ψJB
Psi JB
41.5
θJC
Theta JC
θJB
Theta JB
High K
MAX
UNIT
91.2
Top
ºC/W
25.3
42.0
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
16
24
32
UNIT
Bits
384
kHz
Data Format (PCM Mode)
fS
(1)
Audio data interface format
I2S, left justified
Audio data bit length
16, 24, 32-bit acceptable
Audio data format
MSB First, 2’s Complement
Sampling frequency
8
System clock frequency
64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or
3072
fSCK, up to 50Mhz
Digital Input/Output
Logic Family: 3.3V LVCMOS compatible
VIH
VIL
IIH
IIL
VOH
VOL
0.7×DVDD
Input logic level
0.3×DVDD
Input logic current
VIN = VDD
10
VIN = 0V
–10
IOH = –4mA
Output logic level
0.8×DVDD
IOL = 4mA
0.22×DVDD
V
µA
V
Logic Family 1.8V LVCMOS compatible
VIH
VIL
IIH
IIL
VOH
VOL
(1)
4
0.7×DVDD
Input logic level
0.3×DVDD
Input logic current
VIN = VDD
10
VIN = 0V
–10
IOH = –2mA
Output logic level
0.8×DVDD
IOL = 2mA
0.22×DVDD
V
µA
V
One sample time si defined as the reciprocal of the sampling frequency. 1tS = 1/fS
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SLAS859 – MAY 2012
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic Performance (PCM Mode) (2) (3) (Values shown for three devices PCM5102/PCM5101/PCM5100)
THD+N at –1 dBFS (3)
fS = 48kHz
–93/–92/–90
fS = 96kHz
–93/–92/–90
fS = 192kHz
Dynamic range (3)
EIAJ, A-weighted, fS = 48kHz
Signal-to-noise ratio (3)
–93/–92/–90
106/ 100/ 95
112/106/100
EIAJ, A-weighted, fS = 96kHz
112/106/100
EIAJ, A-weighted, fS = 192kHz
112/106/100
EIAJ, A-weighted, fS = 48kHz
112/106/100
EIAJ, A-weighted, fS = 96kHz
112/106/100
EIAJ, A-weighted, fS = 192kHz
Signal to noise ratio with
analog mute (3) (4)
EIAJ, A-weighted, fS = 48kHz
123
123
EIAJ, A-weighted, fS = 192kHz
fS = 48 kHz
dB
112/106/100
113
EIAJ, A-weighted, fS = 96kHz
Channel Separation
-83/ -82/ -80
123
100/ 95/ 90
109/103/97
fS = 96kHz
109/103/97
fS = 192kHz
109/103/97
Analog Output
Output voltage
2.1
VRMS
Gain error
–6
±2.0
6
Gain mismatch, channel-tochannel
–6
±2.0
6
–5
±1.0
5
Bipolar zero error
At bipolar zero
Load impedance
% of FSR
% of FSR
1
mV
kΩ
Filter Characteristics–1: Normal
Pass band
0.45fS
Stop band
0.55fS
Stop band attenuation
–60
Pass-band ripple
±0.02
Delay time
20tS
dB
s
Filter Characteristics–2: Low Latency
Pass band
0.47fS
Stop band
0.55fS
Stop band attenuation
–52
Pass-band ripple
±0.0001
Delay time
(2)
(3)
(4)
3.5tS
dB
s
Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise
ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications
are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter).
Assert XSMT or both L-ch and R-ch PCM data are BPZ
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDC
Power Supply Requirements
DVDD
Digital supply voltage
Target DVDD = 1.8V
1.65
1.8
1.95
DVDD
Digital supply voltage
Target DVDD = 3.3V
3.0
3.3
3.6
AVDD
Analog supply voltage
3.0
3.3
3.6
CPVDD
Charge-pump suply voltage
3.0
3.3
3.6
fS = 48kHz
7
IDD
DVDD supply current at 1.8V (5) fS = 96kHz
8
IDD
fS = 192kHz
9
fS = 48kHz
7
DVDD supply current at 1.8V (6) fS = 96kHz
8
fS = 192kHz
IDD
IDD
IDD
ICC
DVDD supply current at 1.8V (7)
ICC
7
DVDD supply current at 3.3V (5) fS = 96kHz
8
fS = 192kHz
9
fS = 48kHz
8
DVDD supply current at 3.3V (6) fS = 96kHz
9
ICC
AVDD / CPVDD Supply
Current (7)
Power Dissipation, DVDD =
1.8V (5)
Power Dissipation, DVDD =
1.8V (6)
Power Dissipation, DVDD =
1.8V (7)
Power Dissipation, DVDD =
3.3V (6)
Power Dissipation, DVDD =
3.3V (7)
(5)
(6)
(7)
6
mA
13
mA
0.5
0.8
fS = 48kHz
11
16
fS = 96kHz
11
fS = 192kHz
11
fS = 48kHz
22
fS = 96kHz
22
fS = 192kHz
22
fS = n/a
0.2
0.4
fS = 48kHz
48.9
185
fS = 96kHz
50.7
fS = 192kHz
52.5
fS = 48kHz
85.2
fS = 96kHz
87.0
fS = 192kHz
88.8
fS = n/a (Power Down Mode)
Power Dissipation, DVDD =
3.3V (5)
mA
12
10
DVDD supply current at 3.3V (7)
AVDD / CPVDD Supply
Current (6)
mA
0.3
fS = 48kHz
AVDD / CPVDD Supply
Current (5)
mA
9
fS = 192kHz
IDD
VDC
mA
32
mA
59.4
fS = 96kHz
62.7
fS = 192kHz
66.0
fS = 48kHz
99.0
fS = 96kHz
102.3
fS = 192kHz
105.6
fS = n/a (Power Down Mode)
2.3
mA
mW
187
mW
1.2
fS = 48kHz
mA
mW
92.4
mW
148.5
mW
4.0
mW
Input is Bipolar Zero data.
Input is 1kHz -1dBFS data
Power Down Mode
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SLAS859 – MAY 2012
TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100A THD+N
vs
Input Level
PCM5101A THD+N
vs
Input Level
10
-10
-10
-30
-30
THD+N [dB]
THD+N [dB]
10
-50
-50
-70
-70
-90
-90
-110
-100
-110
-80
-60
-40
Input Level [dBFS]
-20
-100
0
-80
-60
-40
Input Level [dBFS]
Figure 2.
-20
0
Figure 3.
PCM5102A THD+N
vs
Input Level
10
-10
THD+N [dB]
-30
-50
-70
-90
-110
-100
-80
-60
-40
Input Level [dBFS]
-20
0
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5101A FFT Plot at BPZ With AMUTE
-20
-40
-40
-60
-60
-80
-80
Amplitude [dB]
Amplitude [dB]
PCM5100A FFT Plot at BPZ With AMUTE
-20
-100
-120
-100
-120
-140
-140
-160
-160
-180
-180
0
5
10
Frequency [kHz]
15
0
20
5
10
Frequency [kHz]
Figure 5.
15
20
Figure 6.
PCM5102A FFT Plot at BPZ With AMUTE
-20
-40
-60
Amplitude [dB]
-80
-100
-120
-140
-160
-180
0
5
10
Frequency [kHz]
15
20
Figure 7.
8
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SLAS859 – MAY 2012
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5101A FFT Plot at –60dB To 300kHz
0
-20
-20
-40
-40
-60
-60
Amplitude [dB]
Amplitude [dB]
PCM5100A FFT Plot at –60dB To 300kHz
0
-80
-100
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
Frequency [kHz]
250
0
300
50
100
150
200
Frequency [kHz]
Figure 8.
250
300
Figure 9.
PCM5102A FFT Plot at –60dB To 300kHz
0
-20
-40
Amplitude [dB]
-60
-80
-100
-120
-140
-160
0
50
100
150
200
Frequency [kHz]
250
300
Figure 10.
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APPLICATION INFORMATION
Reset and System Clock Functions
Power-On Reset Function
The PCM510xA includes a power-on reset function shown in Figure 11. With VDD > 2.8V, the power-on reset
function is enabled. After the initialization period, the PCM510xA is set to its default reset state.
3.3V
2.8V
AVDD, DVDD,
CPVDD
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 11. Power-On Reset Timing, DVDD = 3.3V
The PCM510xA includes a power-on reset function shown in Figure 12 operating at DVDD=1.8V. With AVDD
greater than approximately 2.8V, and PVDD greater than approximately 2.8 V, and DVDD greater than
approximately 1.5V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to
its default reset state.
3.3V
2.8V
AVDD, CPVDD
1.8V
1.5V
DVDD, LDOO
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 12. Power-On Reset Timing, DVDD = 1.8V
10
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System Clock Input
The PCM510xA requires a system clock to operate the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 12) and supports up to 50MHz. The PCM510xA
system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling
frequencies of 8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.4kHz -192kHz, and 384kHz with
±4% tolerance are supported. The sampling frequency detector sets the clock for the digital filter, Delta Sigma
Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 3 shows examples of system clock
frequencies for common audio sampling rates.
SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in
software mode, available only in the PCM512x and PCM514x devices, by configuring various PLL and clockdivider registers. This allows the device to become a clock master and drive the host serial port with LRCK and
BCK, from a non-audio related clock (e.g. using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) ).
Figure 13 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise.
Table 3. System Master Clock Inputs for Audio Related Clocks
System Clock Frequency (fSCK) (MHz)
Sampling
Frequency
64 fS
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1024 fS
1152 fS
1536 fS
2048 fS
3072 fS
8 kHz
– (1)
1.0240 (2)
1.5360 (2)
2.0480
3.0720
4.0960
6.1440
8.1920
9.2160
12.2880
16.3840
24.5760
16 kHz
– (1)
2.0480 (2)
3.0720 (2)
4.0960
6.1440
8.1920
12.2880
16.3840
18.4320
24.5760
36.8640
49.1520
32 kHz
–
(1)
4.0960
(2)
6.1440 (2)
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
49.1520
– (1)
– (1)
–
(1)
5.6488
(2)
8.4672
(2)
–
(1)
– (1)
–
(1)
6.1440
(2)
9.2160
(2)
–
(1)
– (1)
–
(1)
–
(1)
– (1)
–
(1)
–
(1)
– (1)
–
(1)
–
(1)
– (1)
–
(1)
–
(1)
– (1)
–
(1)
– (1)
44.1 kHz
48 kHz
88.2 kHz
96 kHz
176.4 kHz
192 kHz
384 kHz
(1)
(2)
11.2896
(2)
12.2880
(2)
22.5792
24.5760
24.5760
49.1520
16.9344
18.4320
33.8688
36.8640
–
(1)
11.2896
12.2880
22.5792
24.5760
45.1584
49.1520
–
(1)
16.9344
18.4320
33.8688
36.8640
–
(1)
–
(1)
–
(1)
22.5792
24.5760
45.1584
49.1520
–
(1)
–
(1)
–
(1)
33.8688
36.8640
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
45.1584
49.1520
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
–
(1)
This system clock rate is not supported for the given sampling frequency.
This system clock rate is supported by PLL mode.
tSCKH
"H"
0.7*DVDD
System Clock
(SCK)
0.3*DVDD
"L"
tS CK L
tSCY
Figure 13. Timing Requirements for SCK Input
Table 4. Timing Requirements for SCK Input
Parameters
Min
Max
Unit
tSCY
System clock pulse cycle time
20
1000
ns
tSCKH
System clock pulse width, High
tSCKL
System clock pulse width, Low
Copyright © 2012, Texas Instruments Incorporated
DVDD=1.8V
8
DVDD=3.3V
9
DVDD=1.8V
8
DVDD=3.3V
9
ns
ns
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System Clock PLL Mode
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC.
This reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency
electromagnetic interference.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. The PCM510xA disables the internal PLL when an external SCK is supplied;
specific BCK rates are required to generate an appropriate master clock. describes the minimum and maximum
BCK per LRCK for the integrated PLL to automatically generate an internal SCK.
Table 5. BCK Rates (MHz) by LRCK Sample Rate for
PCM510xA PLL Operation
BCK (fS)
Sample f (kHz)
32
64
8
-
-
16
-
1.024
32
1.024
2.048
44.1
1.4112
2.8224
48
1.536
3.072
96
3.072
6.144
192
6.144
12.288
384
12.288
24.576
Audio Data Interface
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is
the serial audio bit clock, and it is used to clock the serial data present on DIN into the serial shift register of the
audio interface. Serial data is clocked into the PCM510xA on the rising edge of BCK. LRCK is the serial audio
left/right word clock.
Table 6. PCM510xA Audio Data Formats, Bit Depths and Clock Rates
CONTROL MODE
FORMAT
DATA BITS
Hardware Control
I2S/LJ
32, 24, 20, 16
MAX LRCK
FREQUENCY [fS]
SCK RATE [x fS]
BCK RATE [x fS]
Up to 192kHz
128 – 3072
(≤50MHz)
64, 48, 32
384kHz
64, 128
64, 48, 32
The PCM510xA requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
12
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PCM Audio Data Formats and Timing
The PCM510xA supports industry-standard audio data formats, including standard I2S and left-justified. Data
formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified.
All formats require binary 2s complement, MSB-first audio data. Figure 14 shows a detailed timing diagram for
the serial audio interface.
LRCK
0. 5 * DVDD
(Input)
tBCH
t BCL
tLB
BCK
0. 5 * DVDD
(Input)
tBCY
tBL
DATA
0. 5 * DVDD
(Input)
tDS
tDH
Figure 14. PCM510xA Serial Audio Timing - Slave
Table 7. Audio Interface Slave Timing
Parameters
Min
Max
Units
tBCY
BCK Pulse Cycle Time
40
ns
tBCL
BCK Pulse Width LOW
16
ns
tBCH
BCK Pulse Width HIGH
16
ns
tBL
BCK Rising Edge to LRCK Edge
8
ns
tLB
LRCK Edge to BCK Rising Edge
8
ns
ns
tDS
DATA Set Up Time
8
tDH
DATA Hold Time
8
fBCK
BCK frequency @ DVDD=3.3V
24.576
MHz
fBCK
BCK frequency @ DVDD=1.8V
12.288
MHz
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1tS
R-channel
L-channel
LRCK
BCK
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15
16
1
2
15
16
DATA
MSB
LSB
MSB
LSB
2
23
Audio data word = 24-bit, BCK = 48, 64fS
- ,
1
2
2
24
1
24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31
32
1
2
31
32
DATA
MSB
LSB
MSB
LSB
Left Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 15. Left Justified Audio Data Format
1tS
LRCK
L- channel
R- channel
BCK
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15
16
1
2
15
16
DATA
MSB
LSB
MSB
LSB
Audio data word = 24-bit, BCK = 48, 64fS
1
2
23
1
24
2
23
24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31
32
1
2
31
32
DATA
MSB
LSB
MSB
LSB
2
I S Data Format; L-channel = LOW, R-channel = HIGH
Figure 16. I2S Audio Data Format
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Function Descriptions
Interpolation Filter
The PCM510xA provides 2 types of interpolation filter. Users can select which filter to use by using the FLT pin
(pin11)
Table 8. Digital Interpolation Filter Options
FLT Pin
Description
0
FIR Normal x8/x4/x2/x1 Interpolation Filters
1
IIR Low Latency x8/x4/x2/x1 Interpolation Filters
The Normal x8/x4/x2/x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sampling frequency (fS) for
from 8kHz to 384kHz.
Table 9. Normal x8 Interpolation Filter
Parameter
Condition
Filter Gain Pass Band
0 ……. 0.45fS
Value (Typ)
Filter Gain Stop Band
0.55fS ….. 7.455fS
Filter Group Delay
Value (Max)
Units
±0.02
dB
–60
dB
22tS
s
space
1.0
0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
4
−0.4
0
50
100
150
200
250
Samples
300
350
G023
G012
Figure 17. Normal x8 Interpolation Filter Frequency
Response
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400
Figure 18. Normal x8 Interpolation Filter Impulse
Response
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0.05
0.04
0.03
Amplitude (dB)
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.1
0.2
0.3
Frequency (x fS)
0.4
0.5
G034
Figure 19. Normal x8 Interpolation Filter Passband Ripple
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The Normal x4/x2/x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sample time (tS) for sample
rates from 8kHz to 384kHz.
Table 10. Normal x4 Interpolation Filter
Parameter
Condition
Value (Typ)
Filter Gain Pass Band
0 ……. 0.45fS
Filter Gain Stop Band
0.55fS ….. 7.455fS
Filter Group Delay
Value (Max)
Units
±0.02
dB
–60
dB
22tS
s
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
−0.4
4
0
20
40
60
80
100
Samples
120
140
G009
Figure 20. Normal x4 Interpolation Filter Frequency
Response
160
G020
Figure 21. Normal x4 Interpolation Filter Impulse
Response
0.05
0.04
0.03
Amplitude (dB)
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
Frequency (x fS)
1.0
G031
Figure 22. Normal x4 Interpolation Filter Passband Ripple
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Normal x2 / x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sample time (tS) for sample rates
from 8kHz to 384kHz.
Table 11. Normal x2 Interpolation Filter
Parameter
Condition
Value (Typ)
Filter Gain Pass Band
0 ……. 0.45fS
Filter Gain Stop Band
0.55fS ….. 7.455fS
Filter Group Delay
Value (Max)
Units
±0.02
dB
–60
dB
22tS
s
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
−0.4
4
0
10
20
30
40
50
60
Samples
G006
Figure 23. Normal x2 Interpolation Filter Frequency
Response
70
80
90
100
G017
Figure 24. Normal x2 Interpolation Filter Impulse
Response
0.05
0.04
0.03
Amplitude (dB)
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
1.0
Frequency (x fS)
1.5
2.0
G028
Figure 25. Normal x2 Interpolation Filter Passband Ripple
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The low-latency x8 / x4 / x2 / x1(bypass) Interpolation filter is programmed in 256 cycles 1 sample time (tS) for
sample rates from 8kHz to 384kHz.
Table 12. Low latency x8 Interpolation Filter
Parameter
Condition
Filter Gain Pass Band
0 ……. 0.45fS
Filter Gain Stop Band
0.55fS ….. 7.455fS
Value (Typ)
Units
±0.0001
dB
–52
dB
3.5tS
s
Filter Group Delay
space
1.0
0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
0.0
−80
−0.2
−100
−0.4
−120
0
1
2
Frequency (x fS)
3
4
−0.6
0
50
100
150
200
250
Samples
300
350
G011
Figure 26. Low latency x8 Interpolation Filter
Frequency Response
400
G022
Figure 27. Low latency x8 Interpolation Filter
Impulse Response
0.00010
0.00008
0.00006
Amplitude (dB)
0.00004
0.00002
0.00000
−0.00002
−0.00004
−0.00006
−0.00008
−0.00010
0.0
0.1
0.2
0.3
Frequency (x fS)
0.4
0.5
G033
Figure 28. Low latency x8 Interpolation Filter Passband Ripple
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Table 13. Low latency x4 Interpolation Filter
Parameter
Condition
Filter Gain Pass Band
0 ……. 0.45fS
Filter Gain Stop Band
0.55fS ….. 3.455fS
Value (Typ)
Units
±0.0001
dB
–52
dB
3.5tS
s
Filter Group Delay
space
1.0
0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
0.0
−80
−0.2
−100
−0.4
−120
0
1
2
Frequency (x fS)
3
4
−0.6
0
20
40
60
80
100
Samples
G008
Figure 29. Low latency x4 Interpolation Filter
Frequency Response
120
140
160
180
G019
Figure 30. Low latency x4 Interpolation Filter
Impulse Response
0.0001
0.00008
0.00006
Amplitude (dB)
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 31. Low latency x4 Interpolation Filter Passband Ripple
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Table 14. Low latency x2 Interpolation Filter
Parameter
Condition
Filter Gain Pass Band
0 ……. 0.45fS
Filter Gain Stop Band
0.55fS ….. 1.455fS
Value (Typ)
Units
±0.0001
dB
–52
dB
3.5tS
s
Filter Group Delay
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
4
−0.4
0
10
20
30
40
50
60
Samples
70
80
90
G005
Figure 32. Low latency x2 Interpolation Filter
Frequency Response
100
G016
Figure 33. Low latency x2 Interpolation Filter
Impulse Response
0.0001
0.00008
0.00006
Amplitude (dB)
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 34. Low latency x2 Interpolation Filter Passband Ripple
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Zero Data Detect
The PCM510xA has a zero-data detect function. When the device detects continuous zero data, it enters a full
analog mute condition.
The PCM510xA counts zero data over 1024LRCKs (21ms @ 48kHz) before setting analog mute.
Power Save Mode
When any kind of clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA enters Stand-by
mode automatically. The current-segment DAC and Line driver are also powered down.
When BCK and LRCK halt to a low level for more than 1 second, the PCM510xA enters Power down mode
automatically. Power-down mode includes the negative charge pump and Bias/Reference circuit power-down in
addition to stand-by.
Whenever expected Audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA, the device starts its
powerup sequence automatically.
XSMT Pin (Soft Mute / Soft Un-Mute)
For external digital control of the PCM510xA, the XSMT pin must be driven by an external digital host with a
specific/minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM510xA requires tr/tf times
of less than 20ns. In the majority of applications, this shouldn’t be a problem, however, traces with high
capacitance may have issues.
When the XSMT pin is shifted from high to low (3.3V to 0V), a soft digital attenuation ramp is started. –1dB
attenuation will be applied every 1tS from 0dBFS to –∞. This takes 104 sample times.
When the XSMT pin is shifted from low to high (0V to 3.3V), a soft digital “un-mute” is started. 1dB gain steps are
applied every tS from –∞ to 0dBFS. This takes 104 sample times.
0.9 * DVDD
XSMT
0.1 * DVDD
Tr < 20ns
Tf <20ns
Figure 35. XSMT Timing for Soft Mute and Soft Un-Mute
Table 15. XSMT Timing Parameters
Parameters
22
Max
Unit
Rise time (tR)
20
ns
Fall time (tF)
20
ns
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External Power Sense Undervoltage Protection mode (supported only when DVDD = 3.3V)
The XSMT pin can also be used to monitor a system voltage, such as the 24VDC LCD TV backlight, or 12VDC
system supply using a potential divider created with two resistors. (See Figure 36 )
• If the XSMT pin makes a transition from 1 to 0 over 6ms or more, the device will switch into external undervoltage protection mode. In this mode, two trigger levels are used.
• When XSMT pin level reaches 2V, soft mute process begins.
• When XSMT pin level reaches 1.2V, analog mute will engage, regardless of digital audio level, and analog
shut down will begin. (i.e. DAC circuitry will power down etc).
A timing diagram to show this is shown in Figure 37.
NOTE
The XSMT input pins voltage range is from –0.3V to DVDD + 0.3V.The ratio of external
resistors must be considered within this input range. Any increase in power supply (such
as power supply positive noise/ripple) can pull the XSMT pin higher than DVDD+0.3V.
For example, if the PCM510xA is monitoring a 12V input, and dividing the voltage by 4, then the voltage at
XSMT during ideal power supply conditions will be 3V. If the voltage spikes any higher than 14.4V, then XSMT
will see a voltage in excess of 3.6V (DVDD+0.3), potentially damaging the device.
Providing the divider is set appropriately, any DC voltage can be monitored.
System
VDD
12V
supply
7.25kO
XSMT
2.75kO
Figure 36. XSMT in External UVP Mode
Digital Attenuation Followed by Analog Mute
0.9 * DVDD
2.0 V
Analog Mute
XSMT
1.2 V
0.1 * DVDD
tf
Figure 37. XSMT Timing for Undervoltage Protection
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Recommended Powerdown Sequence
With inadequate system design, the PCM510x can exhibit some pop on power down. This is caused by the
device not having enough time to detect power loss and start the muting process.
On the PCM51xx evaluation board, this is compensated for with an electrolytic decoupling capacitor. This
capacitor provides enough time between data loss from USB or S/PDIF and power supply loss for the muting
process to take place.
The PCM51xx has two auto-mute functionalities that can be used to mute the device upon power loss (intentional
or unintentional)
XSMT = 0
When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog
mute. This process takes 150 sample times (ts) + 0.2mS
As this mute time is mainly dominated by the sampling frequency, systems sampling at 192kHz will mute much
faster than a 48kHz system.
Clock Error Detect
When clock error is detected on the incoming data clock, the PCM51xx family switches to an internal oscillator,
and continues to the drive the DAC, while attenuating the data from the last known value. Once this process is
complete, the PCM51xx outputs will be hard muted to ground.
Planned Shutdown
These auto-muting processes can be manipulated by system designs to mute before power loss in the following
ways
1. Assert XSMT low 150tS + 0.2mS before power is removed.
3.3V
VDD
0V
150tS + 0.2ms
High
XSMT
Low
High
I2 S Clocks
SCK, BCK, LRCK
Low
Time
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2. Stop I2S clocks (SCK, BCK, LRCK) 3ms before powerdown as shown below:
3.3V
VDD
0V
High
XSMT
Low
3msec
High
I2S Clocks
SCK, BCK, LRCK
Low
Time
Unplanned Shutdown
Many systems use a low-noise regulator to provide an AVDD 3.3V supply for the DAC. The XSMT Pin can take
advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the DAC before
the entire SMPS discharges. shows how to configure such a system to use the XSMT pin. The XSMT pin can
also be used in parallel with a GPIO pin from the system microcontroller/DSP or Power Supply.
MCU GPIO
“mute” signal
GND
XSMT
Linear
Regulator
110V / 220V
SMPS
6V
PCM51xx
Audio DAC
3V3
10 F
GND
GND
Figure 38. Using the XSMT Pin
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Typical Application Circuits
Figure 39. PCM510xA Standard PCM Audio Operation, 3.3V
Figure 40. PCM510xA Standard PCM Audio Operation, 1.8V
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PCM Audio
Source
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PCM Audio
Source
Figure 41. PCM510xA PLL Operation, 3.3V
Figure 42. PCM510xA PLL Operation, 1.8V
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Recommended Output Filter for the PCM510xA
The diagram in Figure 43 shows the recommended output filter for the PCM510xA. The new PCM510xA next
generation current segment architecture offers excellent out of band noise, making a traditional 20kHz low pass
filter a thing of the past.
The RC settings below offer a –3dB filter point at 153kHz (approx), giving the DAC the ability to reproduce
virtually all frequencies through to it’s maximum sampling rate of 384kHz.
LINE
LOUT
470Ω
2.2nF
Output voltage is2 VRMS
With a10K Ω Load
ROUT
470Ω
2. 2nF
OUT
Figure 43. Recommended Output Lowpass Filter for 10kΩ Operation
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PACKAGE OPTION ADDENDUM
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15-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
PCM5100APW
PREVIEW
TSSOP
PW
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM5101APW
PREVIEW
TSSOP
PW
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM5102APW
PREVIEW
TSSOP
PW
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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