EXAR XRT86VX38_0906

XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JUNE 2009
REV. 1.0.1
GENERAL DESCRIPTION
The XRT86VX38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology
(Relayless, Reconfigurable, Redundancy) and BITS
Timing element. The physical interface is optimized
with internal impedance, and with the patented pad
structure, the XRT86VX38 provides protection from
power failures and hot swapping.
The XRT86VX38 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VX38 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
FIGURE 1. XRT86VX38 8-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
Local PCM
Highway
External Data
Link Controller
XRT86VX38
Tx Overhead In
Rx Overhead Out
1 of 8-channels
Tx Serial
Data In
1:2 Turns Ratio
2-Frame
Slip Buffer
Elastic Store
TTIP
Tx LIU
Interface
Tx Framer
Tx Serial
Clock
ST-BUS
LLB
Rx Serial
Clock
TRING
LB
RTIP
Rx Serial
Data Out
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Rx LIU
Interface
PRBS
Generator &
Analyser
Performance
Monitor
HDLC/LAPD
Controllers
LIU &
Loopback
Control
RRING
RxLOS
Line Side
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
1:1 Turns Ratio
Signaling &
Alarms
Microprocessor
Interface
DMA
Interface
JTAG
3
INT
System (Terminal) Side
TxON
Memory
D[7:0]
A[14:0]
P
Select
WR
4 ALE_AS
RD
RDY_DTACK
Intel/Motorola µP
Configuration , Control &
Status Monitor
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
APPLICATIONS
 High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems
 SONET/SDH terminal or Add/Drop multiplexers (ADMs)
 T1/E1/J1 add/drop multiplexers (MUX)
 Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
 BITS Timing
 Digital Access Cross-connect System (DACs)
 Digital Cross-connect Systems (DCS)
 Frame Relay Switches and Access Devices (FRADS)
 ISDN Primary Rate Interfaces (PRA)
 PBXs and PCM channel bank
 T3 channelized access concentrators and M13 MUX
 Wireless base stations
 ATM equipment with integrated DS1 interfaces
 Multichannel DS1 Test Equipment
 T1/E1/J1 Performance Monitoring
 Voice over packet gateways
 Routers
FEATURES
 Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths
 Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path
 Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path
 Supports BITS timing generation on the Transmit Outputs
 Supports BITS timing extraction from NRZ data on the Analog Receive Path
 DS-0 Monitoring on both Transmit and Receive Time Slots
 Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704
 Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz
 Independent, full duplex DS1 Tx and Rx Framer/LIUs
 Each channel has full featured Long-haul/Short-haul LIU
 Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
 Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
 Programmable output clocks for Fractional T1/E1/J1
 Supports Channel Associated Signaling (CAS)
 Supports Common Channel Signalling (CCS)
 Supports ISDN Primary Rate Interface (ISDN PRI) signaling
2
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
 Extracts and inserts robbed bit signaling (RBS)
 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /
buffer 1)
 HDLC Controllers Support SS7
 Timeslot assignable HDLC
 V5.1 or V5.2 Interface
 Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface
every 1 second or for a single transmission
 Supports SPRM and NPRM
 Alarm Indication Signal with Customer Installation signature (AIS-CI)
 Remote Alarm Indication with Customer Installation (RAI-CI)
 Gapped Clock interface mode for Transmit and Receive.
 Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
 Parallel search algorithm for fast frame synchronization
 Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)
 Direct access to D and E channels for fast transmission of data link information
 Full BERT Controller for generation and detection on system and line side of the chip
 PRBS, QRSS, and Network Loop Code generation and detection
 Seven Independent, simultaneous Loop Code Detectors per Channel
 Programmable Interrupt output pin
 Supports programmed I/O and DMA modes of Read-Write access
 The framer block encodes and decodes the T1/E1/J1 Frame serial data
 Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
 Detects OOF, LOF, LOS errors and COFA conditions
 Loopbacks: Local (LLB) and Line remote (LB)
 Facilitates Inverse Multiplexing for ATM
 Performance monitor with one second polling
 Boundary scan (IEEE 1149.1) JTAG test port
 Accepts external 8kHz Sync reference
 1.8V Inner Core
 3.3V CMOS operation with 5V tolerant inputs
 256-pin fpBGA and 329-pin fpBGA package with -40C to +85C operation
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT86VX38IB329
329 Fine Pitch Ball Grid Array
-40C to +85C
XRT86VX38IB256
256 Fine Pitch Ball Grid Array
-40C to +85C
3
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
329 BALL - FINE PITCH BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
O O O O O O O O O O O O O O O O O O O
A
O O O O O O O O O O O O O O O O O O O
B
O O O O O O O O O O O O O O O O O O O
C
O O O O O O O O O O O O O O O O O O O
D
O O O O O O O O O O O O O O O O O O O
E
O O O O O
O O O O O
F
O O O O O
O O O O O O O
O O O O O
G
O O O O O
O O O O O O O
O O O O O
H
O O O O O
O O O O O O O
O O O O O
J
O O O O O
O O O O O O O
O O O O O
K
O O O O O
O O O O O O O
O O O O O
L
O O O O O
O O O O O O O
O O O O O
M
O O O O O
O O O O O O O
O O O O O
N
O O O O O
P
O O O O O O O O O O O O O O O O O O O
R
O O O O O O O O O O O O O O O O O O O
T
O O O O O O O O O O O O O O O O O O O
U
O O O O O O O O O O O O O O O O O O O
V
O O O O O O O O O O O O O O O O O O O
W
O O O O O
4
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
256 BALL - FINE PITCH BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
O O O O O O O O O O O O O O O O
A
O O O O O O O O O O O O O O O O
B
O O O O O O O O O O O O O O O O
C
O O O O O O O O O O O O O O O O
D
O O O O O O O O O O O O O O O O
E
O O O O O O O O O O O O O O O O
F
O O O O O O O O O O O O O O O O
G
O O O O O O O O O O O O O O O O
H
O O O O O O O O O O O O O O O O
J
O O O O O O O O O O O O O O O O
K
O O O O O O O O O O O O O O O O
L
O O O O O O O O O O O O O O O O
M
O O O O O O O O O O O O O O O O
N
O O O O O O O O O O O O O O O O
P
O O O O O O O O O O O O O O O O
R
O O O O O O O O O O O O O O O O
T
5
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
LIST OF PARAGRAPHS
1.0 PIN LISTS .................................................................................................................................................6
2.0 PIN DESCRIPTIONS ..............................................................................................................................12
I
XRT86VX38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VX38 8-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................ 1
Figure 2.: ITU G.703 Pulse Template .............................................................................................................................. 43
Figure 3.: ITU G.703 Section 13 Synchronous Interface Pulse Template ....................................................................... 44
Figure 4.: DSX-1 Pulse Template (normalized amplitude) .............................................................................................. 45
II
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
LIST OF TABLES
Table 1:: 329 Ball List by Ball Number ............................................................................................................................... 6
Table 2:: 256 Ball List by Ball Number ............................................................................................................................... 9
Table 3:: Pin Description Structure .................................................................................................................................. 12
Table 4:: E1 Receiver Electrical Characteristics .............................................................................................................. 40
Table 5:: T1 Receiver Electrical Characteristics .............................................................................................................. 41
Table 6:: E1 Transmitter Electrical Characteristics .......................................................................................................... 41
Table 7:: E1 Transmit Return Loss Requirement ............................................................................................................. 42
Table 8:: T1 Transmitter Electrical Characteristics .......................................................................................................... 42
Table 9:: Transmit Pulse Mask Specification ................................................................................................................... 43
Table 10:: E1 Synchronous Interface Transmit Pulse Mask Specification ....................................................................... 44
Table 11:: DSX1 Interface Isolated pulse mask and corner points .................................................................................. 45
Table 12:: AC Electrical Characteristics ........................................................................................................................... 46
III
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
1.0 PIN LISTS
TABLE 1: 329 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
A1
VDD
A2
VDDPLL18
A3
VSS
A4
DGND
A5
TDI
A6
VSS
A7
RXSIG0
A8
RXSYNC0
A9
TXSYNC0
A10
TXSIG0
A11
RXSERCLK1
A12
VDD
A13
TXSYNC1
A14
TXSER1
A15
VSS
A16
RXCASYNC2
A17
RXCRCSYNC2
A18
RxSCLK2
A19
VDD
B1
GNDPLL
B2
VDDPLL18
B3
VDDPLL18
B4
DVDD18
B5
RXTSEL
B6
VDD
B7
TMS
B8
RXLOS0
B9
VDD
B10
TXMSYNC0
B11
TXSERCLK0
B12
RXSIG1
TABLE 1: 329 BALL LIST
BY BALL NUMBER
TABLE 1: 329 BALL LIST
BY BALL NUMBER
TABLE 1: 329 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
B13
RXLOS1
D7
TDO
F1
RRING1
B14
TXMSYNC1
D8
RXSER0
F2
VSS
B15
TXSIG1
D9
RXSERCLK0
F3
TTIP1
B16
RXSERCLK2
D10
RXCRCSYNC0
F4
TRING1
B17
RXSER2
D11
TXSER0
F5
VDD
B18
TXSIG2
D12
RXCRCSYNC1
F15
VDD18
B19
RXSER3
D13
VDD18
F16
RXSERCLK3
C1
RTIP0
D14
TXSERCLK1
F17
RxSCLK3
C2
RVDD0
D15
RXLOS2
F18
TXSERCLK3
C3
GNDPLL
D16
TXSYNC2
F19
TXSER3
C4
VDDPLL18
D17
TXSER2
G1
RVDD2
C5
VSS
D18
RXSIG3
G2
RGND1
C6
AGND
D19
RXCASYNC3
G3
TGND1
C7
aTEST
E1
RTIP1
G4
TVDD1
C8
MCLKIN
E2
RVDD1
G5
VDD18
C9
TRST
E3
TRING0
G7
VDD18
C10
TCK
E4
TGND0
G8
VSS
C11
RxSCLK0
E5
ANALOG
G9
VDD18
C12
RXSER1
E6
VDD18
G10
VSS
C13
RXSYNC1
E7
VSS
G11
VDD18
C14
RXCASYNC1
E8
VDD18
G12
VSS
C15
RXSYNC2
E9
VDD18
G13
VDD18
C16
RXSIG2
E10
RXCASYNC0
G15
DATA7
C17
TXSERCLK2
E11
VDD18
G16
TXMSYNC3
C18
TXMSYNC2
E12
VDD18
G17
WR / R/W
C19
RXCRCSYNC3
E13
VDD18
G18
TXSIG3
D1
RRING0
E14
RxSCLK1
G19
CS
D2
RGND0
E15
VDD18
H1
RTIP2
D3
TTIP0
E16
VDD
H2
RGND2
D4
TVDD0
E17
RXSYNC3
H3
TRING2
D5
GNDPLL
E18
RXLOS3
H4
TTIP2
D6
AVDD18
E19
TXSYNC3
H5
VSS
6
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 1: 329 BALL LIST
BY BALL NUMBER
TABLE 1: 329 BALL LIST
BY BALL NUMBER
TABLE 1: 329 BALL LIST
BY BALL NUMBER
REV. 1.0.1
TABLE 1: 329 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
H7
VSS
K4
TTIP3
M2
RGND4
N19
ADDR0
H8
VSS
K5
TVDD3
M3
TGND4
P1
RTIP5
H9
VSS
K7
VSS
M4
TVDD4
P2
VSS
H10
VSS
K8
VSS
M5
VDD18
P3
TGND5
H11
VSS
K9
VSS
M7
VSS
P4
RVDD6
H12
VSS
K10
VSS
M8
VSS
P5
TGND6
H13
VSS
K11
VSS
M9
VSS
P15
VDD18
H15
ADDR12
K12
VSS
M10
VSS
P16
VDD
H16
DATA6
K13
VSS
M11
VSS
P17
PTYPE0
H17
ADDR14
K15
ADDR8
M12
VSS
P18
PCLK
H18
DATA5
K16
DATA2
M13
VSS
P19
DATA1
H19
ADDR13
K17
ALE / AS
M15
ADDR3
R1
RRING5
J1
RRING2
K18
ADDR10
M16
RDY / DTACK
R2
RGND5
J2
RVDD3
K19
PTYPE2
M17
ADDR1
R3
TVDD6
J3
TGND2
L1
RRING3
M18
ADDR2
R4
TRING6
J4
TVDD2
L2
RVDD4
M19
ADDR5
R5
TTIP6
J5
VDD18
L3
TTIP4
N1
RRING4
R6
VSS
J7
VDD18
L4
TRING4
N2
RVDD5
R7
RXCRCSYNC7
J8
VSS
L5
TGND3
N3
TTIP5
R8
TXMSYNC6
J9
VSS
L7
VDD18
N4
TRING5
R9
VDD18
J10
VSS
L8
VSS
N5
TVDD5
R10
VDD18
J11
VSS
L9
VSS
N7
VDD18
R11
VDD
J12
VSS
L10
VSS
N8
VSS
R12
VDD18
J13
VDD18
L11
VSS
N9
VDD18
R13
VDD
J15
ADDR11
L12
VSS
N10
VSS
R14
VDD18
J16
ADDR9
L13
VDD18
N11
VDD18
R15
VDD
J17
VDD
L15
VDD18
N12
VSS
R16
REQ1
J18
INT
L16
ADDR4
N13
VDD18
R17
RXSERCLK4
J19
DATA4
L17
ADDR6
N15
VSS
R18
VDD
K1
RTIP3
L18
DATA3
N16
DATA0
R19
ACK1
K2
RGND3
L19
ADDR7
N17
RD / DS / WE
T1
RTIP6
K3
TRING3
M1
RTIP4
N18
PTYPE1
T2
RGND6
7
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TABLE 1: 329 BALL LIST
BY BALL NUMBER
TABLE 1: 329 BALL LIST
BY BALL NUMBER
TABLE 1: 329 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
T3
TTIP7
U16
TXMSYNC4
W10
RXCASYNC6
T4
TVDD7
U17
RXCASYNC4
W11
VDD
T5
8KEXTOSC
U18
RXSIG4
W12
RXSER6
T6
VDD18
U19
RXLOS4
W13
TXSIG5
T7
VDD
V1
VDD
W14
RXSIG5
T8
RXSYNC7
V2
TGND7
W15
VDD
T9
RXCASYNC7
V3
RGND7
W16
RXCRCSYNC5
T10
RXSYNC6
V4
RESET
W17
TXSER4
T11
TXSERCLK5
V5
E1OSCCLK
W18
RxSCLK4
T12
RXSERCLK6
V6
TXMSYNC7
W19
VSS
T13
TXMSYNC5
V7
RXLOS7
T14
RxSCLK5
V8
RXSER7
T15
RXSERCLK5
V9
TXSYNC6
T16
TXSYNC4
V10
RXCRCSYNC6
T17
RXSYNC4
V11
RXLOS6
T18
ACK0
V12
RXSIG6
T19
REQ0
V13
TXSER5
U1
RRING6
V14
RXSER5
U2
RVDD7
V15
RXCASYNC5
U3
TRING7
V16
TXSIG4
U4
VDD
V17
TXSERCLK4
U5
TXSERCLK7
V18
RXSER4
U6
TXSIG7
V19
RXCRCSYNC4
U7
RXSERCLK7
W1
VSS
U8
RxSCLK7
W2
RTIP7
U9
RXSIG7
W3
RRING7
U10
TXSIG6
W4
TXON
U11
RxSCLK6
W5
T1OSCCLK
U12
VSS
W6
TXSER7
U13
TXSYNC5
W7
TXSYNC7
U14
RXSYNC5
W8
TXSERCLK6
U15
RXLOS5
W9
TXSER6
8
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 2: 256 BALL LIST
BY BALL NUMBER
TABLE 2: 256 BALL LIST
BY BALL NUMBER
TABLE 2: 256 BALL LIST
BY BALL NUMBER
REV. 1.0.1
TABLE 2: 256 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
B16
RXSER3
D16
RXLOS3
F16
ADDR13
A1
GNDPLL
C1
RRING0
E1
RRING1
G1
RRING2
A2
GNDPLL
C2
RGND0
E2
RGND1
G2
RGND2
A3
VDDPLL18
C3
TTIP0
E3
TTIP1
G3
TTIP2
A4
VDDPLL18
C4
GNDPLL
E4
TRING1
G4
TRING2
A5
RxTSEL
C5
AVDD18
E5
TGND0
G5
TGND2
A6
TMS
C6
DVDD18
E6
MCLKIN
G6
VDD18
A7
RXLOS0
C7
aTEST
E7
VSS
G7
VSS
A8
RXCRCSYNC0
C8
TDI
E8
VDD
G8
VSS
A9
RXCASYNC0
C9
TXSYNC0
E9
VSS
G9
VSS
A10
RXSERCLK1
C10
RXCRCSYNC1
E10
TXSER0
G10
VSS
A11
RXSYNC1
C11
RXLOS1
E11
VDD
G11
ADDR14
A12
TXMSYNC1
C12
TXSER1
E12
RXCRCSYNC3
G12
DATA6
A13
RXSYNC2
C13
RXSERCLK2
E13
RXCASYNC3
G13
DATA7
A14
TXSYNC2
C14
RXCRCSYNC2
E14
TXMSYNC3
G14
DATA5
A15
RxSCLK2
C15
TXMSYNC2
E15
TXSYNC3
G15
VDD
A16
VDD
C16
RXSYNC3
E16
TXSERCLK3
G16
ADDR12
B1
RTIP0
D1
RTIP1
F1
RTIP2
H1
RTIP3
B2
RVDD0
D2
RVDD1
F2
RVDD2
H2
RVDD3
B3
VDDPLL18
D3
TRING0
F3
TGND1
H3
TTIP3
B4
ANALOG
D4
TVDD0
F4
TVDD1
H4
TRING3
B5
AGND
D5
VDDPLL18
F5
TVDD2
H5
TVDD3
B6
TDO
D6
DGND
F6
VSS
H6
VDD18
B7
RXSER0
D7
TRST
F7
VSS
H7
VSS
B8
RXSERCLK0
D8
TCK
F8
VDD18
H8
VSS
B9
RXSYNC0
D9
TXMSYNC0
F9
VDD18
H9
VSS
B10
RxSCLK0
D10
TXSERCLK0
F10
VDD18
H10
VSS
B11
RXSER1
D11
RXCASYNC1
F11
RXLOS2
H11
VDD18
B12
TXSYNC1
D12
RxSCLK1
F12
RxSCLK3
H12
PTYPE2
B13
TXSERCLK1
D13
RXCASYNC2
F13
WR / R/W
H13
DATA4
B14
RXSER2
D14
TXSER2
F14
CS
H14
ADDR10
B15
TXSERCLK2
D15
RXSERCLK3
F15
TXSER3
H15
INT
9
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TABLE 2: 256 BALL LIST
BY BALL NUMBER
TABLE 2: 256 BALL LIST
BY BALL NUMBER
TABLE 2: 256 BALL LIST
BY BALL NUMBER
TABLE 2: 256 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
H16
ADDR11
K16
ADDR5
M16
PCLK
P16
RXLOS4
J1
RRING3
L1
RRING4
N1
RRING5
R1
RRING6
J2
RGND3
L2
RGND4
N2
RGND5
R2
RGND6
J3
TTIP4
L3
TTIP5
N3
TGND6
R3
RGND7
J4
TRING4
L4
TRING5
N4
TVDD7
R4
RESET
J5
TGND3
L5
TGND5
N5
TGND7
R5
E1OSCCLK
J6
VDD18
L6
8KEXTOSC
N6
TXMSYNC7
R6
RXSERCLK7
J7
VSS
L7
VDD18
N7
RXCRCSYNC7
R7
RXSYNC7
J8
VSS
L8
VDD18
N8
TXSYNC6
R8
TXMSYNC6
J9
VSS
L9
VDD18
N9
RXCASYNC6
R9
RXCRCSYNC6
J10
VSS
L10
VDD18
N10
TXSERCLK5
R10
RXLOS6
J11
VDD18
L11
ADDR3
N11
RXSYNC5
R11
TXMSYNC5
J12
DATA3
L12
DATA1
N12
TXSER4
R12
RXCASYNC5
J13
ADDR9
L13
ADDR0
N13
RXSYNC4
R13
RXCRCSYNC5
J14
ADDR8
L14
ADDR1
N14
VDD
R14
RXCASYNC4
J15
ADDR7
L15
RD / DS / WE
N15
ACK0
R15
RXCRCSYNC4
J16
ALE / AS
L16
RDY / DTACK
N16
REQ0
R16
REQ1
K1
RTIP4
M1
RTIP5
P1
RTIP6
T1
RVDD7
K2
RVDD4
M2
RVDD5
P2
RVDD6
T2
RTIP7
K3
TGND4
M3
TTIP6
P3
TTIP7
T3
RRING7
K4
TVDD4
M4
TRING6
P4
TRING7
T4
TXON
K5
TVDD5
M5
TVDD6
P5
TXSER7
T5
T1OSCCLK
K6
VDD18
M6
VDD
P6
TXSERCLK7
T6
TXSYNC7
K7
VSS
M7
RxSCLK7
P7
RXLOS7
T7
TXSERCLK6
K8
VSS
M8
RXCASYNC7
P8
RXSER7
T8
TXSER6
K9
VSS
M9
VDD
P9
RxSCLK6
T9
RXSYNC6
K10
VSS
M10
RXSERCLK6
P10
TXSER5
T10
RXSER6
K11
VDD18
M11
TXSYNC5
P11
RXSER5
T11
RxSCLK5
K12
DATA2
M12
PTYPE1
P12
RXLOS5
T12
RXSERCLK5
K13
ADDR4
M13
PTYPE0
P13
TXMSYNC4
T13
TXSYNC4
K14
ADDR6
M14
DATA0
P14
RXSERCLK4
T14
TXSERCLK4
K15
ADDR2
M15
ACK1
P15
RXSER4
T15
RxSCLK4
10
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TABLE 2: 256 BALL LIST
BY BALL NUMBER
PIN
PIN NAME
T16
VDD
11
REV. 1.0.1
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
2.0 PIN DESCRIPTIONS
There are six types of pins defined throughout this pin description and the corresponding symbol is presented
in table below. The per-channel pin is indicated by the channel number or the letter ’n’ which is appended at the
end of the signal name, for example, TxSERn, where "n" indicates channels 0 to 7. All output pins are "tristated" upon hardware RESET.
SYMBOL
PIN TYPE
I
Input
O
Output
I/O
Bidirectional
GND
Ground
PWR
Power
NC
No Connect
The structure of the pin description is divided into eleven groups, as presented in the table below
TABLE 3: PIN DESCRIPTION STRUCTURE
SECTION
PAGE NUMBER
Transmit System Side Interface
page 13
Receive System Side Interface
page 18
Receive Line Interface
page 23
Transmit Line Interface
page 24
Timing Interface
page 25
JTAG Interface
page 26
Microprocessor Interface
page 26
Power Pins (3.3V)
page 35
Power Pins (1.8V)
page 36
Ground Pins
page 37
No Connect Pins
page 38
12
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
TxSER0/
TxPOS0
TxSER1/
TxPOS1
TxSER2/
TxPOS2
TxSER3/
TxPOS3
TxSER4/
TxPOS4
TxSER5/
TxPOS5
TxSER6/
TxPOS6
TxSER7/
TxPOS7
329 PKG 256 PKG
BALL#
BALL #
D11
E10
A14
C12
D17
D14
F19
F15
W17
N12
V13
P10
W9
T8
W6
P5
TYPE
OUTPUT
DRIVE(MA)
I
-
DESCRIPTION
Transmit Serial Data Input (TxSERn)/Transmit Positive
Digital Input (TxPOSn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Mode - TxSERn
These pins function as the transmit serial data input on the
system side interface, which are latched on the rising edge of
the TxSERCLKn pin. Any payload data applied to this pin will
be inserted into an outbound DS1/E1 frame and output to the
line. In DS1 mode, the framing alignment bits, facility data link
bits, CRC-6 bits, and signaling information can also be
inserted from this input pin if configured appropriately. In E1
mode, all data intended to be transported via Time Slots 1
through 15 and Time slots 17 through 31 must be applied to
this input pin. Data intended for Time Slots 0 and 16 can also
be applied to this input pin If configured accordingly.
DS1 or E1 High-Speed Multiplexed Mode* - TxSERn
In this mode, these pins are used as the high-speed multiplexed data input pin on the system side. High-speed multiplexed data of channels 0-3 must be applied to TxSER0 and
high-speed multiplexed data of channels 4-7 must be applied
to TxSER4 in a byte or bit-interleaved way. The framer latches
in the multiplexed data on TxSER0 and TxSER4 using TxMSYNC/TxINCLK and demultiplexes this data into 4 serial
streams. The LIU block will then output the data to the line
interface using TxSERCLKn.
DS1 or E1 Framer Bypass Mode - TxPOSn
In this mode, TxSERn is used for the positive digital input pin
(TxPOSn) to the LIU.
NOTE:
1. *High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-multiplexed modes,
and (For T1 only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3. These 8 pins are internally pulled “High” for each
channel.
13
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
TxSERCLK0/
TxLINECLK0
TxSERCLK1/
TxLINECLK1
TxSERCLK2/
TxLINECLK2
TxSERCLK3/
TxLINECLK3
TxSERCLK4/
TxLINECLK4
TxSERCLK5/
TxLINECLK5
TxSERCLK6/
TxLINECLK6
TxSERCLK7/
TxLINECLK7
329 PKG 256 PKG
BALL#
BALL #
B11
D10
D14
B13
C17
B15
F18
E16
V17
T14
T11
N10
W8
T7
U5
P6
TYPE
OUTPUT
DRIVE(MA)
I/O
12
DESCRIPTION
Transmit Serial Clock (TxSERCLKn)/Transmit Line Clock
(TxSERCLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLKn:
This clock signal is used by the transmit serial interface to
latch the contents on the TxSERn pins into the T1/E1 framer
on the rising edge of the TxSERCLKn. These pins can be configured as input or output as described below.
When TxSERCLKn is configured as Input:
These pins will be inputs if the TxSERCLK is chosen as the
timing source for the transmit framer. Users must provide a
1.544MHz clock rate to this input pin for T1 mode of operation,
and 2.048MHz clock rate in E1 mode.
When TxSERCLKn is configured as Output:
These pins will be outputs if either the recovered line clock or
the MCLK PLL is chosen as the timing source for the T1/E1
transmit framer. The transmit framer will output a 1.544MHz
clock rate in T1 mode of operation, and a 2.048MHz clock rate
in E1 mode.
DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as
INPUT ONLY
In this mode, TxSERCLK is an optional clock signal input
which is used as the timing source for the transmit line interface, and is only required if TxSERCLK is chosen as the timing source for the transmit framer. If TxSERCLK is chosen as
the timing source, system equipment should provide
1.544MHz (For T1 mode) or 2.048MHz (For E1 mode) to the
TxSERCLKn pins on each channel. TxSERCLK is not
required if either the recovered clock or MCLK PLL is chosen
as the timing source of the device.
High speed or multiplexed data is latched into the device using
the TxMSYNC/TxINCLK high-speed clock signal.
DS1 or E1 Framer Bypass Mode - TxLINECLKn
In this mode, TxSERCLKn is used as the transmit line clock
(TxLINECLK) to the LIU.
NOTE:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE:
14
These 8 pins are internally pulled “High” for each
channel.
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
TxSYNC0/
TxNEG0
TxSYNC1/
TxNEG1
TxSYNC2/
TxNEG2
TxSYNC3/
TxNEG3
TxSYNC4/
TxNEG4
TxSYNC5/
TxNEG5
TxSYNC6/
TxNEG6
TxSYNC7/
TxNEG7
329 PKG 256 PKG
BALL#
BALL #
A9
C9
A13
B12
D16
A14
E19
E15
T16
T13
U13
M11
V9
N8
W7
T6
TYPE
OUTPUT
DRIVE(MA)
I/O
12
DESCRIPTION
Transmit Single Frame Sync Pulse (TxSYNCn) / Transmit
Negative Digital Input (TxNEGn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNCn:
These TxSYNCn pins are used to indicate the single frame
boundary within an outbound T1/E1 frame. In both DS1 or E1
mode, the single frame boundary repeats every 125 microseconds (8kHz).
In DS1/E1 base rate, TxSYNCn can be configured as either
input or output as described below.
When TxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for one
period of TxSERCLK during the first bit of an outbound DS1/
E1 frame. It is imperative that the TxSYNC input signal be synchronized with the TxSERCLK input signal.
When TxSYNCn is configured as an Output:
The transmit T1/E1 framer will output a signal which pulses
"High" for one period of TxSERCLK during the first bit of an
outbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - TxSYNCn as
INPUT ONLY:
In this mode, TxSYNCn must be an input regardless of the
clock source that is chosen to be the timing source for the
transmit framer. In 2.048MVIP/4.096/8.192MHz high-speed
modes, TxSYNCn pins must be pulsed ’High’ for one period of
TxSERCLK during the first bit of the outbound T1/E1 frame. In
HMVIP mode, TxSYNC0 and TxSYNC4 must be pulsed ’High’
for 4 clock cycles of the TxMSYNC/TxINCLK signal in the
position of the first two and the last two bits of a multiplexed
frame. In H.100 mode, TxSYNC0 and TxSYNC4 must be
pulsed ’High’ for 2 clock cycles of the TxMSYNC/TxINCLK signal in the position of the first and the last bit of a multiplexed
frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this mode, TxSYNCn is used as the negative digital input
pin (TxNEG) to the LIU.
NOTE:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE:
15
These 8 pins are internally pulled “Low” for each
channel.
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
TxMSYNC0/
TxINCLK0
TxMSYNC1/
TxINCLK1
TxMSYNC2/
TxINCLK2
TxMSYNC3/
TxINCLK3
TxMSYNC4/
TxINCLK4
TxMSYNC5/
TxINCLK5
TxMSYNC6/
TxINCLK6
TxMSYNC7/
TxINCLK7
329 PKG 256 PKG
BALL#
BALL #
B10
D9
B14
A12
C18
C15
G16
E14
U16
P13
T13
R11
R8
R8
V6
N6
TYPE
OUTPUT
DRIVE(MA)
I/O
12
DESCRIPTION
Multiframe Sync Pulse (TxMSYNCn) / Transmit Input
Clock (TxINCLKn)
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxMSYNCn
In this mode, these pins are used to indicate the multi-frame
boundary within an outbound DS1/E1 frame.
In DS1 ESF mode, TxMSYNCn repeats every 3ms.
In DS1 SF mode, TxMSYNCn repeats every 1.5ms.
In E1 mode, TxMSYNCn repeats every 2ms.
If TxMSYNCn is configured as an input, TxMSYNCn must
pulse "High" for one period of TxSERCLK during the first bit of
an outbound DS1/E1 multi-frame. It is imperative that the
TxMSYNC input signal be synchronized with the TxSERCLK
input signal.
If TxMSYNCn is configured as an output, the transmit section
of the T1/E1 framer will output and pulse TxMSYNC "High" for
one period of TxSERCLK during the first bit of an outbound
DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - (TxINCLKn as
INPUT ONLY)
In this mode, this pin must be used as the high-speed input
clock pin (TxINCLKn) for the backplane interface to latch in
high-speed or multiplexed data on the TxSERn pin. The frequency of TxINCLK is presented in the table below.
OPERATION MODE
FREQUENCY OF
TXINCLK(MHZ)
2.048MVIP non-multiplexed
2.048
4.096MHz non-multiplexed
4.096
8.192MHz non-multiplexed
8.192
12.352MHz Bit-multiplexed
(DS1 ONLY)
12.352
16.384MHz Bit-multiplexed
16.384
16.384 HMVIP Byte-multiplexed
16.384
16.384 H.100 Byte-multiplexed
16.384
NOTES:
1. *High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
2. In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
3. These 8 pins are internally pulled “Low” for each
channel.
16
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
TxSIG0
TxSIG1
TxSIG2
TxSIG3
TxSIG4
TxSIG5
TxSIG6
TxSIG7
329 PKG 256 PKG
BALL#
BALL #
A10
B15
B18
G18
V16
W13
U10
U6
TYPE
OUTPUT
DRIVE(MA)
I/O
8
DESCRIPTION
Transmit Time Slot Octet Identifier Output 0 (TxCHNn_0) /
Transmit Serial Signaling Input (TxSIGn):
The exact function of these pins depends on whether or not
the transmit framer enables the transmit fractional/signaling
interface, as described below:
If transmit fractional/signaling interface is disabled - No function
If transmit fractional/signaling interface is enabled TxSIGn:
These pins can be used to input robbed-bit signaling data to
be inserted within an outbound DS1 frame or to input Channel
Associated Signaling (CAS) data within an outbound E1
frame, as described below.
T1 Mode: Signaling data (A,B,C,D) of each channel must be
provided on bit 4,5,6,7 of each time slot on the TxSIG pin if 16code signaling is used. If 4-code signaling is selected, signaling data (A,B) of each channel must be provided on bit 4, 5 of
each time slot on the TxSIG pin. If 2-code signaling is
selected, signaling data (A) of each channel must be provided
on bit 4 of each time slot on the TxSIG pin.
E1 Mode: Signaling data in E1 mode can be provided on the
TxSIGn pins on a time-slot-basis as in T1 mode, or it can be
provided on time slot 16 only via the TxSIGn input pins. In the
latter case, signaling data (A,B,C,D) of channel 1 and channel
17 must be inserted on the TxSIGn pin during time slot 16 of
frame 1, signaling data (A,B,C,D) of channel 2 and channel 18
must be inserted on the TxSIGn pin during time slot 16 of
frame 2...etc. The CAS multiframe Alignments bits (0000 bits)
and the extra bits/alarm bit (xyxx) must be inserted on the
TxSIGn pin during time slot 16 of frame 0.
NOTE:
Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
NOTE:
These 8 pins are internally pulled “Low” for each
channel.
17
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
RxSYNC0/
RxNEG0
RxSYNC1/
RxNEG1
RxSYNC2/
RxNEG2
RxSYNC3/
RxNEG3
RxSYNC4/
RxNEG4
RxSYNC5/
RxNEG5
RxSYNC6/
RxNEG6
RxSYNC7/
RxNEG7
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
A8
B9
I/O
12
C13
A11
C15
A13
E17
C16
T17
N13
U14
N11
T10
T9
T8
R7
DESCRIPTION
Receive Single Frame Sync Pulse (RxSYNCn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) RxSYNCn:
These RxSYNCn pins are used to indicate the single
frame boundary within an inbound T1/E1 frame. In both
DS1 or E1 mode, the single frame boundary repeats
every 125 microseconds (8kHz).
In DS1/E1 base rate, RxSYNCn can be configured as
either input or output depending on the slip buffer configuration as described below.
When RxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for
one period of RxSERCLK and repeats every 125S. The
receive serial Interface will output the first bit of an
inbound DS1/E1 frame during the provided RxSYNC
pulse.
NOTE: It is imperative that the RxSYNC input signal be
synchronized with the RxSERCLK input signal.
When RxSYNCn is configured as an Output:
The receive T1/E1 framer will output a signal which
pulses "High" for one period of RxSERCLK during the first
bit of an inbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - RxSYNCn as
INPUT ONLY:
In this mode, RxSYNCn must be an input regardless of
the slip buffer configuration. In 2.048MVIP/4.096/
8.192MHz high-speed modes, RxSYNCn pins must be
pulsed ’High’ for one period of RxSERCLK during the first
bit of the inbound T1/E1 frame. In HMVIP mode,
RxSYNCn must be pulsed ’High’ for 4 clock cycles of the
RxSERCLK signal in the position of the first two and the
last two bits of a multiplexed frame. In H.100 mode,
RxSYNCn must be pulsed ’High’ for 2 clock cycles of the
RxSERCLK signal in the position of the first and the last
bit of a multiplexed frame.
DS1 or E1 Framer Bypass Mode - RxNEGn
In this mode, RxSYNCn is used as the Receive negative
digital output pin (RxNEG) from the LIU.
NOTE: *High-speed backplane modes include (For T1/
E1)
2.048MVIP,
4.096MHz,
8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bitmultiplexed mode.
NOTE:
In DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every fourth
time slot (don’t care).
NOTE: These 8 pins are internally pulled “Low” for each
channel.
18
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
RxCRCSYNC0
RxCRCSYNC1
RxCRCSYNC2
RxCRCSYNC3
RxCRCSYNC4
RxCRCSYNC5
RxCRCSYNC6
RxCRCSYNC7
D10
D12
A17
C19
V19
W16
V10
R7
A8
C10
C14
E12
R15
R13
R9
N7
TYPE
OUTPUT
DRIVE (MA)
O
12
DESCRIPTION
Receive Multiframe Sync Pulse (RxCRCSYNCn):
The RxCRCSYNCn pins are used to indicate the receive
multi-frame boundary. These pins pulse "High" for one
period of RxSERCLK when the first bit of an inbound
DS1/E1 Multi-frame is being output on the RxCRCSYNCn
pin.
• In DS1 ESF mode, RxCRCSYNCn repeats every 3ms
• In DS1 SF mode, RxCRCSYNCn repeats every 1.5ms
• In E1 mode, RxCRCSYNCn repeats every 2ms.
RxCASYNC0
RxCASYNC1
RxCASYNC2
RxCASYNC3
RxCASYNC4
RxCASYNC5
RxCASYNC6
RxCASYNC7
E10
C14
A16
D19
U17
V15
W10
T9
A9
D11
D13
E13
R14
R12
N9
M8
O
12
Receive CAS Multiframe Sync Pulse (RxCASYNCn):
- E1 Mode Only
The RxCASYNCn pins are used to indicate the E1 CAS
Multif-frame boundary. These pins pulse "High" for one
period of RxSERCLK when the first bit of an E1 CAS
Multi-frame is being output on the RxCASYNCn pin.
19
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
D9
B8
I/O
12
A11
A10
B16
C13
F16
D15
R17
P14
T15
T12
T12
M10
U7
R6
DESCRIPTION
Receive Serial Clock Signal (RxSERCLKn) / Receive
Line Clock (RxLINECLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - RxSERCLKn:
These pins are used as the receive serial clock on the
system side interface which can be configured as either
input or output. The receive serial interface outputs data
on RxSERn on the rising edge of RxSERCLKn.
When RxSERCLKn is configured as Input:
These pins will be inputs if the slip buffer on the Receive
path is enabled. System side equipment must provide a
1.544MHz clock rate to this input pin for T1 mode of operation, and 2.048MHz clock rate in E1 mode.
When RxSERCLKn is configured as Output:
These pins will be outputs if slip buffer is bypassed. The
receive framer will output a 1.544MHz clock rate in T1
mode of operation, and a 2.048MHz clock rate in E1
mode.
DS1/E1 High-Speed Backplane Modes* - (RxSERCLK
as INPUT ONLY)
In this mode, this pin must be used as the high-speed
input clock for the backplane interface to output highspeed or multiplexed data on the RxSERn pin. The frequency of RxSERCLK is presented in the table below.
OPERATION MODE
FREQUENCY OF
RXSERCLK(MHZ)
2.048MVIP non-multiplexed
2.048
4.096MHz non-multiplexed
4.096
8.192MHz non-multiplexed
8.192
12.352MHz Bit-multiplexed
(DS1 ONLY)
12.352
16.384MHz Bit-multiplexed
16.384
16.384 HMVIP Byte-multiplexed
16.384
16.384 H.100 Byte-multiplexed
16.384
NOTES:
1. *High-speed backplane modes include (For T1/
E1)
2.048MVIP,
4.096MHz,
8.192MHz,
16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bitmultiplexed mode.
2. For DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every
fourth time slot (don’t care).
20
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
RxSER0/
RxPOS0
RxSER1/
RxPOS1
RxSER2/
RxPOS2
RxSER3/
RxPOS3
RxSER4/
RxPOS4
RxSER5/
RxPOS5
RxSER6/
RxPOS6
RxSER7/
RxPOS7
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
D9
B8
I/O
12
A11
A10
B16
C13
F16
D15
R17
P14
T15
T12
T12
M10
U7
R6
D8
B7
C12
B11
B17
B14
B19
B16
V18
P15
V14
P11
W12
T10
V8
P8
DESCRIPTION
(Continued)
DS1 or E1 Framer Bypass Mode - RxLINECLKn
In this mode, RxSERCLKn is used as the Receive Line
Clock output pin (RxLineClk) from the LIU.
NOTE: These 8 pins are internally pulled “High” for each
channel.
O
12
Receive Serial Data Output (RxSERn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Mode - RxSERn
These pins function as the receive serial data output on
the system side interface, which are updated on the rising
edge of the RxSERCLKn pin. All the framing alignment
bits, facility data link bits, CRC bits, and signaling information will also be extracted to this output pin.
DS1 or E1 High-Speed Multiplexed Mode* - RxSERn
In this mode, these pins are used as the high-speed multiplexed data output pin on the system side. High-speed
multiplexed data of channels 0-3 will output on RxSER0
and high-speed multiplexed data of channels 4-7 will output on RxSER4 in a byte or bit-interleaved way. The
framer outputs the multiplexed data on RxSER0 and
RxSER4 using the high-speed input clock (RxSERCLKn).
DS1 or E1 Framer Bypass Mode
In this mode, RxSERn is used as the positive digital output pin (RxPOSn) from the LIU.
NOTE: *High-speed multiplexed modes include (For T1/
E1) 16.384MHz HMVIP, H.100, Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bitmultiplexed mode.
NOTE:
21
In DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every fourth
time slot (don’t care).
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
RxSig0
RxSig1
RxSig2
RxSig3
RxSig4
RxSig5
RxSig6
RxSig7
A7
B12
C16
D18
U18
W14
V12
U9
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
O
8
DESCRIPTION
Receive Serial Signaling Output (RxSIGn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/signaling interface, as described below:
If receive fractional/signaling interface is disabled :
-No function
If receive fractional/signaling interface is enabled RxSIGn:
These pins can be used to output robbed-bit signaling
data within an inbound DS1 frame or to output Channel
Associated Signaling (CAS) data within an inbound E1
frame, as described below.
T1 Mode: Signaling data (A,B,C,D) of each channel will
be output on bit 4,5,6,7 of each time slot on the RxSIG pin
if 16-code signaling is used. If 4-code signaling is
selected, signaling data (A,B) of each channel will be output on bit 4, 5 of each time slot on the RxSIG pin. If 2code signaling is selected, signaling data (A) of each
channel will be output on bit 4 of each time slot on the
RxSIG pin.
E1 Mode: Signaling data in E1 mode will be output on the
RxSIGn pins on a time-slot-basis as in T1 mode, or it can
be output on time slot 16 only via the RxSIGn output pins.
In the latter case, signaling data (A,B,C,D) of channel 1
and channel 17 will be output on the RxSIGn pin during
time slot 16 of frame 1, signaling data (A,B,C,D) of channel 2 and channel 18 will be output on the RxSIGn pin
during time slot 16 of frame 2...etc. The CAS multiframe
Alignments bits (0000 bits) and the extra bits/alarm bit
(xyxx) will be output on the RxSIGn pin during time slot 16
of frame 0.
NOTE:
RxSCLK0
RxSCLK1
RxSCLK2
RxSCLK3
RxSCLK4
RxSCLK5
RxSCLK6
RxSCLK7
C11
E14
A18
F17
W18
T14
U11
U8
B10
D12
A15
F12
T15
T11
P9
M7
O
8
Receive Fractional/signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
Receive Recovered Line Clock Output (RxSCLKn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/signaling interface, as described below:
If receive fractional/signaling interface is disabled -No function
If receive fractional/signaling interface is enabled Receive Recovered Line Clock Output (RxSCLKn):
These pins output the recovered T1/E1 line clock
(1.544MHz in T1 mode and 2.048MHz in E1 mode) for
each channel.
NOTE:
22
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE LINE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
C1
E1
H1
K1
M1
P1
T1
W2
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
RxLOS0
RxLOS1
RxLOS2
RxLOS3
RxLOS4
RxLOS5
RxLOS6
RxLOS7
TYPE
OUTPUT
DRIVE (MA)
B1
D1
F1
H1
K1
M1
P1
T2
I
-
Receive Positive Analog Input (RTIPn):
RTIP is the positive differential input from the line interface. This input pin, along with the RRING input pin, functions as the “Receive DS1/E1 Line Signal” input for the
XRT86VX38 device.
The user is expected to connect this signal and the
RRING input signal to a 1:1 transformer for proper operation. The center tap of the receive transformer should have
a bypass capacitor of 0.1F to ground (Chip Side) to
improve long haul application receive capabilities.
D1
F1
J1
L1
N1
R1
U1
W3
C1
E1
G1
J1
L1
N1
R1
T3
I
-
Receive Negative Analog Input (RRINGn):
RRING is the negative differential input from the line interface. This input pin, along with the RTIP input pin, functions as the “Receive DS1/E1 Line Signal” input for the
XRT86VX38 device.
The user is expected to connect this signal and the RTIP
input signal to a 1:1 transformer for proper operation. The
center tap of the receive transformer should have a
bypass capacitor of 0.1F to ground (Chip Side) to
improve long haul application receive capabilities.
B8
B13
D15
E18
U19
U15
V11
V7
A7
C11
F11
D16
P16
P12
R10
P7
O
4
Receive Loss of Signal Output Indicator (RLOSn):
The XRT86VX38 device will assert this output pin (i.e.,
toggle it “high”) anytime (and for the duration that) the
Receive DS1/E1 Framer or LIU block declares the LOS
defect condition.
Conversely, the XRT86VX38 will "TRI-State" this pin anytime (and for the duration that) the Receive DS1/E1
Framer or LIU block is NOT declaring the LOS defect condition.
DESCRIPTION
NOTE: Since the XRT86VX38 tri-states this output pin
(anytime the channel is not declaring the LOS
defect condition), the user MUST connect a "pulldown" resistor (ranging from 1K to 10K) to each
RxLOS output pin, to pull this output pin to the
logic "LOW" condition, whenever the Channel is
NOT declaring the LOS defect condition.
This output pin will toggle “High” (declare LOS) if the
Receive Framer or the Receive LIU block associated with
Channel N determines that an RLOS condition occurs. In
other words, this pin is OR-ed with the LIU RLOS and the
Framer RLOS bit. If either the LIU RLOS or the Framer
RLOS bit associated with channel N pulses high, the corresponding RLOS pin of that particular channel will be set
to “High”.
23
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
RECEIVE LINE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
RxTSEL
B5
A5
I
-
DESCRIPTION
Receive Termination Control (RxTSEL):
Upon power up, the receivers are in "High" impedance.
Switching to internal termination can be selected through
the microprocessor interface by programming the appropriate channel register. However, to switch control to the
hardware pin, RxTCNTL must be programmed to "1" in the
appropriate global register (0x0FE2). Once control has
been granted to the hardware pin, it must be pulled "High"
to switch to internal termination.
NOTE: Internally pulled "Low" with a 50kresistor.
RxTSEL (pin)
Rx Termination
0
External
1
Internal
Note: RxTCNTL (bit) must be set to "1"
TRANSMIT LINE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
D3
F3
H4
K4
L3
N3
R5
T3
C3
E3
G3
H3
J3
L3
M3
P3
TYPE
DESCRIPTION
O
Transmit Positive Analog Output (TTIPn):
TTIP is the positive differential output to the line interface. This output pin, along with the corresponding TRING output pin, function as
the Transmit DS1/E1 output signal drivers for the XRT86VX38
device.
The user is expected to connect this signal and the corresponding
TRING output signal to a 1:2 step up transformer for proper operation.
This output pin will be tri-stated whenever the user sets the “TxON”
input pin or register bit (0xnF02, bit 3) to “0”.
NOTE: This pin should have a series line capacitor of 0.68F for DC
blocking purposes.
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
E3
F4
H3
K3
L4
N4
R4
U3
D3
E4
G4
H4
J4
L4
M4
P4
O
Transmit Negative Analog Output (TRINGn):
TRING is the negative differential output to the line interface. This
output pin, along with the corresponding TTIP output pin, function as
the Transmit DS1/E1 output signal drivers for the XRT86VX38
device.
The user is expected to connect this signal and the corresponding
TRING output signal to a 1:2 step up transformer for proper operation.
NOTE: This output pin will be tri-stated whenever the user sets the
“TxON” input pin or register bit (0xnF02, bit 3) to “0”.
24
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TRANSMIT LINE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
DESCRIPTION
TxON
W4
T4
I
Transmitter On
This input pin permits the user to either enable or disable the Transmit Output Driver within the Transmit DS1/E1 LIU Block. If the TxON
pin is pulled “Low”, all 8 Channels are tri-stated. When this pin is
pulled ‘High’, turning on or off the transmitters will be determined by
the appropriate channel registers (address 0x0Fn2, bit 3)
LOW = Disables the Transmit Output Driver within the Transmit DS1/
E1 LIU Block. In this setting, the TTIP and TRING output pins of all 8
channels will be tri-stated.
HIGH = Enables the Transmit Output Driver within the Transmit DS1/
E1 LIU Block. In this setting, the corresponding TTIP and TRING output pins will be enabled or disabled by programming the appropriate
channel register. (address 0x0Fn2, bit 3)
NOTE:
Whenever the transmitters are turned off, the TTIP and
TRING output pins will be tri-stated.
TIMING INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
MCLKIN
C8
E6
I
-
Master Clock Input:
This pin is used to provide the timing reference for the internal master clock of the device. The frequency of this clock
is programmable from 8kHz to 16.384MHz in register
0x0FE9.
E1OSCCLK
V5
R5
O
8
Framer E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be programmed to 65.536MHz in register 0x011E.
T1OSCCLK
W5
T5
O
8
Framer T1 Output Clock Reference
This output pin is defaulted to 1.544MHz, but can be programmed to output 49.408MHz in register 0x011E.
8KEXTOSC
T5
L6
I
-
External Oscillator Select
For normal operation, this pin should not be used, or pulled
“Low”.
This pin is internally pulled “Low” with a 50k resistor.
ANALOG
E5
B4
O
DESCRIPTION
Factory Test Mode Pin
NOTE: For Internal Use Only
25
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
JTAG INTERFACE
The XRT86VX38 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry
specification for additional information on boundary scan operations.
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
TCK
C10
D8
I
-
Test clock: Boundary Scan Test clock input:
The TCLK signal is the clock for the TAP controller, and it
generates the boundary scan data register clocking. The
data on TMS and TDI is loaded on the positive edge of
TCK. Data is observed at TDO on the falling edge of TCK.
TMS
B7
A6
I
-
Test Mode Select: Boundary Scan Test Mode Select
input.
The TMS signal controls the transitions of the TAP controller in conjunction with the rising edge of the test clock
(TCK).
DESCRIPTION
NOTE:
TDI
A5
C8
I
-
For normal operation this pin must be pulled
’High’.
Test Data In: Boundary Scan Test data input
The TDI signal is the serial test data input.
NOTE: This pin is internally pulled ’high’.
TDO
D7
B6
O
8
Test Data Out: Boundary Scan Test data output
The TDO signal is the serial test data output.
TRST
C9
D7
I
-
Test Reset Input:
The TRST signal (Active Low) asynchronously resets the
TAP controller to the Test-Logic-Reset state.
NOTE: This pin is internally pulled ’high’
aTEST
C7
C7
I
-
Factory Test Mode Pin
NOTE: This pin is internally pulled ’low’, and should be
pulled ’low’ for normal operation.
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
N16
P19
K16
L18
J19
H18
H16
G15
M14
L12
K12
J12
H13
G14
G12
G13
TYPE
OUTPUT
DRIVE (MA)
I/O
8
DESCRIPTION
Bidirectional Microprocessor Data Bus
These pins are used to drive and receive data over the bidirectional data bus, whenever the Microprocessor performs READ or WRITE operations with the Microprocessor
Interface of the XRT86VX38 device.
When DMA interface is enabled, these 8-bit bidirectional
data bus is also used by the T1/E1 Framer or the external
DMA Controller for storing and retrieving information.
26
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
REQ0
T19
N16
O
8
DMA Cycle Request Output—DMA Controller 0 (Write):
These output pins are used to indicate that DMA transfers
(Write) are requested by the T1/E1 Framer.
On the transmit side (i.e., To transmit data from external
DMA controller to HDLC buffers within the XRT86VX38),
DMA transfers are only requested when the transmit buffer
status bits indicate that there is space for a complete message or cell.
The DMA Write cycle starts by T1/E1 Framer asserting the
DMA Request (REQ0) ‘low’, then the external DMA controller should drive the DMA Acknowledge (ACK0) ‘low’ to indicate that it is ready to start the transfer. The external DMA
controller should place new data on the Microprocessor
data bus each time the Write Signal is Strobed low if the
WR is configured as a Write Strobe. If WR is configured as
a direction signal, then the external DMA controller would
place new data on the Microprocessor data bus each time
the Read Signal (RD) is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
at least one of the Transmit HDLC buffers are empty and
can receive one more HDLC message.
The Framer negates this output pin (toggles it “High”) when
the HDLC buffer can no longer receive another HDLC message.
REQ1
R16
R16
O
8
DMA Cycle Request Output—DMA Controller 1 (Read):
These output pins are used to indicate that DMA transfers
(Read) are requested by the T1/E1 Framer.
On the receive side (i.e., To transmit data from HDLC buffers within the XRT86VX38 to external DMA Controller),
DMA transfers are only requested when the receive buffer
contains a complete message or cell.
The DMA Read cycle starts by T1/E1 Framer asserting the
DMA Request (REQ1) ‘low’, then the external DMA controller should drive the DMA Acknowledge (ACK1) ‘low’ to indicate that it is ready to receive the data. The T1/E1 Framer
should place new data on the Microprocessor data bus
each time the Read Signal is Strobed low if the RD is configured as a Read Strobe. If RD is configured as a direction
signal, then the T1/E1 Framer would place new data on the
Microprocessor data bus each time the Write Signal (WR)
is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
one of the Receive HDLC buffer contains a complete
HDLC message that needs to be read by the µC/µP.
The Framer negates this output pin (toggles it “High”) when
the Receive HDLC buffers are depleted.
DESCRIPTION
27
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
INT
J18
H15
O
8
Interrupt Request Output:
This active-low output signal will be asserted when the
XRT86VX38 device is requesting interrupt service from the
Microprocessor. This output pin should typically be connected to the “Interrupt Request” input of the Microprocessor.
The Framer will assert this active "Low" output (toggles it
"Low"), to the local µP, anytime it requires interrupt service.
PCLK
P18
M16
I
-
Microprocessor Clock Input:
This clock input signal is only used if the Microprocessor
Interface has been configured to operate in the Synchronous Modes (e.g., Power PC 403 Mode). If the Microprocessor Interface is configured to operate in this mode, then
it will use this clock signal to do the following.
DESCRIPTION
1. To sample the CS, WR/R/W, A[14:0], D[7:0], RD/DS
and DBEN input pins, and
2. To update the state of the D[7:0] and the RDY/
DTACK output signals.
NOTES:
1.
The Microprocessor Interface can work with
PCLK frequencies ranging up to 33MHz.
2.
This pin is inactive if the user has configured the
Microprocessor Interface to operate in either the
Intel-Asynchronous
or
the
MotorolaAsynchronous Modes. In this case, the user
should tie this pin to GND.
When DMA interface is enabled, the PCLK input pin is also
used by the T1/E1 Framer to latch in or latch out receive or
output data respectively.
I
-
Microprocessor Type Input:
These input pins permit the user to specify which type of
Microprocessor/Microcontroller to be interfaced to the
XRT86VX38 device. The following table presents the three
different microprocessor types that the XRT86VX38 supports.
PType0
M13
M12
H12
PType1
P17
N18
K19
PType2
PTYPE0
PTYPE1
PTYPE2
MICROPROCESSOR
TYPE
0
0
0
68HC11, 8051, 80C188
0
0
1
MOTOROLA 68K
1
0
1
IBM POWER PC 403
NOTE: These pins are internally pulled “Low” with a 50k
resistor.
28
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
RDY/DTACK
M16
L16
O
12
DESCRIPTION
Ready/Data Transfer Acknowledge Output:
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel Asynchronous Mode - RDY - Ready Output
Tis output pin will function as the “active-low” READY output.
During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level,
ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “high”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being
toggled to the logic low level.
Motorola Asynchronous Mode - DTACK - Data Transfer
Acknowledge Output
Tis output pin will function as the “active-low” DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level,
ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once
the Microprocessor has determined that this input pin has
toggled to the logic “low” level, then it is now safe for it to
move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “high”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being
toggled to the logic low level.
29
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
RDY/DTACK
M16
L16
O
12
DESCRIPTION
(Con’t)
Power PC 403 Mode - RDY Ready Output:
This output pin will function as the “active-high” READY
output.
During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic high level,
ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once
the Microprocessor has sampled this signal being at the
logic “high” level upon the rising edge of PCLK, then it is
now safe for it to move on and execute the next READ or
WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “low”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it samples this output pin
being at the logic low level.
NOTE: The Microprocessor Interface will update the state
of this output pin upon the rising edge of PCLK.
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
N19
M17
M18
M15
L16
M19
L17
L19
K15
J16
K18
J15
H15
H19
H17
L13
L14
K15
L11
K13
K16
K14
J15
J14
J13
H14
H16
G16
F16
G11
I
-
Microprocessor Interface Address Bus Input
These pins permit the Microprocessor to identify on-chip
registers and Buffer/Memory locations within the
XRT86VX38 device whenever it performs READ and
WRITE operations with the XRT86VX38 device.
NOTE: These pins are internally pulled “Low” with a 50k
resistor, except ADDR[8:14].
30
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
ALE / AS
K17
J16
I
-
Address Latch Enable Input Address Strobe
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel-Asynchronous Mode - ALE
This active-high input pin is used to latch the address
(present at the Microprocessor Interface Address Bus pins
(A[14:0]) into the XRT86VX38 Microprocessor Interface
block and to indicate the start of a READ or WRITE cycle.
Pulling this input pin “high” enables the input bus drivers for
the Address Bus input pins (A[14:0]). The contents of the
Address Bus will be latched into the XRT86VX38 Microprocessor Interface circuitry, upon the falling edge of this input
signal.
Motorola-Asynchronous (68K) Mode - AS
This active-low input pin is used to latch the data residing
on the Address Bus, A[14:0] into the Microprocessor Interface circuitry of the XRT86VX38 device.
Pulling this input pin “low” enables the input bus drivers for
the Address Bus input pins. The contents of the Address
Bus will be latched into the Microprocessor Interface circuitry, upon the rising edge of this signal.
Power PC 403 Mode - No Function -Tie to GND:
This input pin has no role nor function and should be tied to
GND.
CS
G19
F14
I
-
Microprocessor Interface—Chip Select Input:
The user must assert this active low signal in order to
select the Microprocessor Interface for READ and WRITE
operations between the Microprocessor and the
XRT86VX38 on-chip registers and buffer/memory locations.
DESCRIPTION
31
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
RD/DS/WE
N17
L15
I
-
Microprocessor Interface—Read Strobe Input:
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the Framer has been configured to operate in, as defined by the PTYPE[2:0] pins.
Intel-Asynchronous Mode - RD - READ Strobe Input:
This input pin will function as the RD (Active Low Read
Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the XRT86VX38 device
will place the contents of the addressed register (or buffer
location) on the
Microprocessor Interface Bi-directional data bus (D[7:0]).
When this signal is negated, then the Data Bus will be tristated.
Motorola-Asynchronous (68K) Mode - DS - Data
Strobe:
This input pin will function as the DS (Data Strobe) input
signal.
Power PC 403 Mode - WE - Write Enable Input:
This input pin will function as the WE (Write Enable) input
pin.
Anytime the Microprocessor Interface samples this activelow input signal (along with CS and WR/R/W) also being
asserted (at a logic low level) upon the rising edge of
PCLK, then the Microprocessor Interface will (upon the
very same rising edge of PCLK) latch the
contents on the Bi-Directional Data Bus (D[7:0]) into the
“target” on-chip register or buffer location within the
XRT86VX38 device.
WR / R/W
G17
F13
I
-
Microprocessor Interface—Write Strobe Input
The exact behavior of this pin depends upon the type of
Microprocessor/Microcontroller the XRT86VX38 has been
configured to operate in, as defined by the PTYPE[2:0]
pins.
Intel-Asynchronous Mode - WR - Write Strobe Input:
This input pin functions as the WR (Active Low WRITE
Strobe) input signal from the Microprocessor. Once this
active-low signal is asserted, then the input buffers (associated with the Bi-Directional Data Bus pin, D[7:0]) will be
enabled.
The Microprocessor Interface will latch the contents on the
Bi-Directional Data Bus (into the “target” register or
address location, within the XRT86VX38) upon the rising
edge of this input pin.
Motorola-Asynchronous Mode - R/W - Read/Write
Operation Identification Input Pin:
This pin is functionally equivalent to the “R/W” input pin. In
the Motorola Mode, a “READ” operation occurs if this pin is
held at a logic “1”, coincident to a falling edge of the RD/DS
(Data Strobe) input pin. Similarly a WRITE operation
occurs if this pin is at a logic “0”, coincident to a falling edge
of the RD/DS (Data Strobe) input pin.
DESCRIPTION
32
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
WR / R/W
G17
F13
I
-
DESCRIPTION
(Con’t)
Power PC 403 Mode - R/W - Read/Write Operation Identification Input:
This input pin will function as the “Read/Write Operation
Identification Input” pin.
Anytime the Microprocessor Interface samples this input
signal at a logic "High" (while also sampling the CS input
pin “Low”) upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of
PCLK) latch the contents of the Address Bus (A[14:0]) into
the Microprocessor Interface circuitry, in preparation for this
forthcoming READ operation. At some point (later in this
READ operation) the Microprocessor will also assert the
DBEN/OE input pin, and the Microprocessor Interface will
then place the contents of the “target” register (or address
location within the XRT86VX38 device) upon the Bi-Directional Data Bus pins (D[7:0]), where it can be read by the
Microprocessor.
Anytime the Microprocessor Interface samples this input
signal at a logic "Low" (while also sampling the CS input
pin a logic “Low”) upon the rising edge of PCLK, then the
Microprocessor Interface will (upon the very same rising
edge of PCLK) latch the contents of the Address Bus
(A[14:0]) into the Microprocessor Interface circuitry, in
preparation for the forthcoming WRITE operation. At some
point (later in this WRITE operation) the Microprocessor
will also assert the RD/DS/WE input pin, and the Microprocessor Interface will then latch the contents of the Bi-Directional Data Bus (D[7:0]) into the contents of the “target”
register or buffer location (within the XRT86VX38).
33
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
MICROPROCESSOR INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
ACK0
T18
N15
I
-
DESCRIPTION
DMA Cycle Acknowledge Input—DMA Controller 0
(Write):
The external DMA Controller will assert this input pin “Low”
when the following two conditions are met:
1. After the DMA Controller, within the Framer has
asserted (toggled “Low”), the Req_0 output signal.
2. When the external DMA Controller is ready to
transfer data from external memory to the selected
Transmit HDLC buffer.
ACK1
R19
At this point, the DMA transfer between the external memory and the selected Transmit HDLC buffer may begin.
After completion of the DMA cycle, the external DMA Controller will negate this input pin after the DMA Controller
within the Framer has negated the Req_0 output pin. The
external DMA Controller must do this in order to acknowledge the end of the DMA cycle.
DMA Cycle Acknowledge Input—DMA Controller 1
(Read):
The external DMA Controller asserts this input pin “Low”
when the following two conditions are met:
M15
1. After the DMA Controller, within the Framer has
asserted (toggled "Low"), the Req_1 output signal.
2. When the external DMA Controller is ready to
transfer data from the selected Receive HDLC buffer
to external memory.
At this point, the DMA transfer between the selected
Receive HDLC buffer and the external memory may begin.
After completion of the DMA cycle, the external DMA Controller will negate this input pin after the DMA Controller
within the Framer has negated the Req_1 output pin. The
external DMA Controller will do this in order to acknowledge the end of the DMA cycle.
NOTE:
RESET
V4
R4
I
-
This pin is internally pulled “High” with a 50k
resistor.
Hardware Reset Input
Reset is an active low input. If this pin is pulled “Low” for
more than 10S, the device will be reset. When this occurs,
all output will be ‘tri-stated’, and all internal registers will be
reset to their default values.
34
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
POWER SUPPLY PINS (3.3V)
329 PKG
BALL#
256 PKG
BALL #
VDD
A1
A12
A19
B6
B9
E16
F5
J17
P16
R11
R13
R15
R18
T7
U4
V1
W11
W15
A16
E8
E11
G15
M6
M9
N14
T16
PWR
Framer Block Power Supply (I/O)
RVDD
C2
E2
G1
J2
L2
N2
P4
U2
B2
D2
F2
H2
K2
M2
P2
T1
PWR
Receiver Analog Power Supply for LIU Section
TVDD
D4
G4
J4
K5
M4
N5
R3
T4
D4
F4
F5
H5
K4
K5
M5
N4
PWR
Transmitter Analog Power Supply for LIU Section
SIGNAL NAME
TYPE
DESCRIPTION
35
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
POWER SUPPLY PINS (1.8V)
329 PKG
BALL#
256 PKG
BALL #
VDD18
D13
E6
E8
E9
E11
E12
E13
E15
F15
G5
G7
G9
G11
G13
J5
J7
J13
L7
L13
L15
M5
N7
N9
N11
N13
P15
R9
R10
R12
R14
T6
F8
F9
F10
G6
H6
H11
J6
J11
K6
K11
L7
L8
L9
L10
PWR
Framer Block Power Supply
DVDD18
B4
C6
PWR
Digital Power Supply for LIU Section
AVDD18
D6
C5
PWR
Analog Power Supply for LIU Section
VDDPLL18
A2
B2
B3
C4
A3
A4
B3
D5
PWR
Analog Power Supply for PLL
SIGNAL NAME
TYPE
DESCRIPTION
36
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
GROUND PINS
329 PKG
BALL#
256 PKG
BALL #
VSS
A3, A6
A15, C5
E7, F2
G8, G10
G12, H5
H7, H8
H9, H10
H11, H12
H13, J8
J9, J10
J11, J12
K7, K8
K9, K10
K11, K12
K13, L8
L9, L10
L11, L12
M7, M8
M9, M10
M11, M12
M13, N8
N10, N12
N15, P2
R6, U12
W1, W19
E7
E9
F6
F7
G7
G8
G9
G10
H7
H8
H9
H10
J7
J8
J9
J10
K7
K8
K9
K10
GND
Framer Block Ground
DGND
A4
D6
GND
Digital Ground for LIU Section
AGND
C6
B5
GND
Analog Ground for LIU Section
RGND
D2
G2
H2
K2
M2
R2
T2
V3
C2
E2
G2
J2
L2
N2
R2
R3
GND
Receiver Analog Ground for LIU Section
TGND
E4
G3
J3
L5
M3
P3
P5
V2
E5
F3
G5
J5
K3
L5
N3
N5
GND
Transmitter Analog Ground for LIU Section
SIGNAL NAME
TYPE
DESCRIPTION
37
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
GROUND PINS
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
B1
C3
D5
A1
A2
C4
329 PKG
BALL#
256 PKG
BALL #
GNDPLL
TYPE
GND
DESCRIPTION
Analog Ground for PLL
NO CONNECT PINS
SIGNAL NAME
NC
F6
F7
F8
F9
F10
F11
F12
F13
F14
G6
G14
H6
H14
J6
J14
K6
K14
L6
L14
M6
M14
N6
N14
P6
P7
P8
P9
P10
P11
P12
P13
P14
TYPE
NC
DESCRIPTION
No Connection
38
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
ELECTRICAL CHARACTERISTICS
Absolute Maximums
Power Supply.....................................................................
VDDIO .. ................................................ -0.5V to +3.465V
Power Rating fpBGA Package.................. 2.4
VDDCORE...............................................-0.5V to +1.890V
Storage Temperature ...............................-65°C to 150°C
Input Logic Signal Voltage (Any Pin) .........-0.5V to + 5.5V
Operating Temperature Range.................-40°C to 85°C
ESD Protection (HBM)...........................................>2000V
Supply Voltage ...................... GND-0.5V to +VDD + 0.5V
Input Current (Any Pin) ...................................... + 100mA
DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN.
TYP.
-10
MAX.
UNITS
+10
µA
0.8
V
CONDITIONS
ILL
Data Bus Tri-State Bus Leakage Current
VIL
Input Low voltage
VIH
Input High Voltage
2.0
VDD
V
VOL
Output Low Voltage
0.0
0.4
V
IOL = -1.6mA
VOH
Output High Voltage
2.4
VDD
V
IOH = 40µA
IOC
Open Drain Output Leakage Current
µA
IIH
Input High Voltage Current
-10
10
µA
VIH = VDD
IIL
Input Low Voltage Current
-10
10
µA
VIL = GND
XRT86VX38 POWER CONSUMPTION
Test Conditions: TA = 25°C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, Internal termination, unless otherwise
specified
MODE
IMPEDANCE
T1
100
E1
E1
MIN.
TYP.
UNITS
CONDITIONS
2.02
1.54
W
All ones Pattern
PRBS Pattern
75
1.95
1.57
W
All ones Pattern
PRBS Pattern
120
1.77
1.44
W
All ones Pattern
PRBS Pattern
39
MAX.
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TABLE 4: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA= -40° to 85°C, unless otherwise specified
PARAMETER
MIN.
TYP.
MAX.
UNIT
Receiver loss of signal:
Cable attenuation @1024kHz
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS De-asserted
TEST CONDITIONS
32
15
20
dB
ITU-G.775, ETSI 300 233
12.5
% ones
Receiver Sensitivity
(Short Haul with cable loss)
11
dB
With nominal pulse amplitude of 3.0V
for 120 and 2.37V for 75 application.
Receiver Sensitivity
(Long Haul with cable loss)
0
dB
With nominal pulse amplitude of 3.0V
for 120 and 2.37V for 75 application.
Input Impedance
Input Jitter Tolerance:
1 Hz
10kHz-100kHz
43
k
15
37
0.3
UIpp
UIpp
ITU G.823
kHz
dB
ITU G.736
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
-
Jitter Attenuator Corner Frequency (-3dB curve) (JABW=0)
(JABW=1)
-
10
1.5
-
Hz
Hz
ITU G.736
12
8
8
-
-
dB
dB
dB
ITU-G.703
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
20
0.5
40
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TABLE 5: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless otherwise specified
PARAMETER
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Receiver loss of signal:
Number of consecutive zeros before
RLOS is set
Input signal level at RLOS
RLOS Clear
Receiver Sensitivity
(Short Haul with cable loss)
Receiver Sensitivity
(Long Haul with cable loss)
Normal
Extended
175
15
20
-
dB
12.5
-
-
% ones
12
-
dB
Cable attenuation @772kHz
ITU-G.775, ETSI 300 233
With nominal pulse amplitude of 3.0V
for 100 termination
0
0
dB
dB
15
-
k
138
0.4
-
-
UIpp
AT&T Pub 62411
-
10
0.1
KHz
dB
TR-TSY-000499
-
6
Hz
AT&T Pub 62411
-
14
20
16
Input Impedance
Jitter Tolerance:
1Hz
10kHz - 100kHz
Recovered Clock Jitter
Transfer Corner Frequency
Peaking Amplitude
Jitter Attenuator Corner Frequency
(-3dB curve)
Return Loss:
51kHz - 102kHz
102kHz - 2048kHz
2048kHz - 3072kHz
With nominal pulse amplitude of 3.0V
for 100 termination
36
45
-
dB
dB
dB
TABLE 6: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless otherwise specified
PARAMETER
MIN.
TYP.
MAX.
UNIT
120 Application
2.13
2.70
2.37
3.00
2.60
3.30
V
V
Output Pulse Width
224
244
264
ns
Output Pulse Width Ratio
0.95
-
1.05
-
ITU-G.703
Output Pulse Amplitude Ratio
0.95
-
1.05
-
ITU-G.703
AMI Output Pulse Amplitude:
75 Application
TEST CONDITIONS
1:2 transformer
41
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TABLE 6: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless otherwise specified
PARAMETER
Jitter Added by the Transmitter Output
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
MIN.
TYP.
MAX.
UNIT
-
0.025
0.05
UIpp
15
9
8
-
-
dB
dB
dB
TEST CONDITIONS
Broad Band with jitter free TCLK
applied to the input.
ETSI 300 166
TABLE 7: E1 TRANSMIT RETURN LOSS REQUIREMENT
FREQUENCY
RETURN LOSS
ETS 300166
51-102kHz
6dB
102-2048kHz
8dB
2048-3072kHz
8dB
TABLE 8: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40° to 85°C, unless otherwise specified
PARAMETER
MIN.
TYP.
MAX.
UNIT
AMI Output Pulse Amplitude:
2.4
3.0
3.60
V
1:2 transformer measured at DSX-1.
Output Pulse Width
338
350
362
ns
ANSI T1.102
Output Pulse Width Imbalance
-
-
20
-
ANSI T1.102
Output Pulse Amplitude Imbalance
-
-
+200
mV
ANSI T1.102
Jitter Added by the Transmitter Output
-
0.025
0.05
UIpp
Output Return Loss:
51kHz -102kHz
102kHz-2048kHz
2048kHz-3072kHz
-
17
12
10
-
dB
dB
dB
42
TEST CONDITIONS
Broad Band with jitter free TCLK
applied to the input.
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
FIGURE 2. ITU G.703 PULSE TEMPLATE
10%
20%
269 ns
(244 + 25)
194 ns
(244 – 50)
20%
10%
V = 100%
Nominal pulse
50%
20%
10%
0%
10%
10%
219 ns
(244 – 25)
10%
244 ns
488 ns
(244 + 244)
Note – V corresponds to the nominal peak value.
TABLE 9: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance
75 Resistive (Coax)
120 Resistive (twisted Pair)
2.37V
3.0V
0 + 0.237V
0 + 0.3V
244ns
244ns
0.95 to 1.05
0.95 to 1.05
Nominal Peak Voltage of a Mark
Peak voltage of a Space (no Mark)
Nominal Pulse width
Ratio of Positive and Negative Pulses Imbalance
43
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
FIGURE 3. ITU G.703 SECTION 13 SYNCHRONOUS INTERFACE PULSE TEMPLATE
T T
30 30
T T
30 30
T T
30 30
+V
+V1
0
–V1
T
4
T
4
T
4
T
4
T
Shaded area in which
signal should be
monotonic
–V
T1818900-92
T Average period of
synchronizing signal
TABLE 10: E1 SYNCHRONOUS INTERFACE TRANSMIT PULSE MASK SPECIFICATION
75 Resistive (Coax)
120 Resistive (twisted Pair)
Maximum Peak Voltage of a Mark
1.5V
1.9V
Minimum Peak Voltage of a Mark
0.75V
1.0V
Nominal Pulse width
244ns
244ns
Test Load Impedance
44
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
FIGURE 4. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
TABLE 11: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE
MAXIMUM CURVE
TIME (UI)
NORMALIZED AMPLITUDE
TIME (UI)
NORMALIZED AMPLITUDE
-0.77
-.05V
-0.77
.05V
-0.23
-.05V
-0.39
.05V
-0.23
0.5V
-0.27
.8V
-0.15
0.95V
-0.27
1.15V
0.0
0.95V
-0.12
1.15V
0.15
0.9V
0.0
1.05V
0.23
0.5V
0.27
1.05V
0.23
-0.45V
0.35
-0.07V
0.46
-0.45V
0.93
0.05V
0.66
-0.2V
1.16
0.05V
0.93
-0.05V
1.16
-0.05V
45
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
TABLE 12: AC ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
MCLKIN Clock Duty Cycle
40
-
60
%
MCLKIN Clock Tolerance
-
±50
-
ppm
46
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
86VX38
ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT86VX38IB329
329 Fine Pitch Ball Grid Array
-40C to +85C
XRT86VX38IB256
256 Fine Pitch Ball Grid Array
-40C to +85C
PACKAGE DIMENSIONS FOR 329 FINE PITCH BALL GRID ARRAY
329 Fine Pitch Ball Grid Array
(17.0 mm x 17.0 mm, fpBGA)
Rev. 1.00
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A1 corner
A
B
C
D
E
F
G
H
J
D
K
D1
L
M
N
P
R
T
U
V
W
D1
D
(A1 corner feature is mfger option)
Seating
Plane
A
A1
b
A2
e
Note: The control dimension is in millimeter.
SYMBOL
A
A1
A2
D
D1
b
e
INCHES
MIN
MAX
0.056
0.067
0.010
0.014
0.046
0.053
0.663
0.675
0.567 BSC
0.014
0.018
0.031 BSC
47
MILLIMETERS
MIN
MAX
1.43
1.71
0.26
0.36
1.17
1.35
16.85
17.15
14.40 BSC
0.36
0.46
0.80 BSC
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
4
PACKAGE DIMENSIONS FOR 256 FINE PITCH BALL GRID ARRAY
256 Fine Pitch Ball Grid Array
(17.0 mm x 17.0 mm, fpBGA)
Rev. 1.00
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
A1 corner
A
B
C
D
E
F
G
H
D1
D
J
K
L
M
N
P
R
T
D1
D
(A1 corner feature is mfger option)
Seating
Plane
A
A1
b
A2
e
Note: The control dimension is in millimeter.
SYMBOL
A
A1
A2
D
D1
b
e
INCHES
MIN
MAX
0.058
0.070
0.013
0.017
0.045
0.053
0.661
0.677
0.591 BSC
0.020
0.024
0.039 BSC
48
MILLIMETERS
MIN
MAX
1.48
1.78
0.33
0.43
1.15
1.35
16.80
17.20
15.00 BSC
0.50
0.60
1.00 BSC
XRT86VX38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2009 EXAR Corporation
Datasheet June 2009.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
49
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OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.1
P4.
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
1.0.0
May. 01, 2009
Initial release of Hardware Description
1.0.1
June 15, 2009
Update packaging name to fpBGA, add BITS functionality to general description,
updated features and applications and updates to eletrical tables
50