Product Brief OPTICAL TRANSPORT & DATACOM PRODUCTS SMI4039 SMI4039 40-45 Gbps 2:16 DQPSK CDR/Demultiplexer Product Description 4Adjustable input threshold and sample clock phase for each input channel SMI4039 accepts single-ended or differential 40 to 45 Gbps NRZ serial data streams and demultiplexes the data into sixteen parallel output channels consistent with the SFI-5 standard. 4Reference clock input port at 1/4th of the SFI-5.1 baud rate Product Highlights 42:16 CDR/Demultiplexer with Integrated DQPSK decoder function 4Control interfaces support wide range of logic families 41.2V or 1.8V LVCMOS 4Temperature sense output voltage 4BiCMOS Silicon Germanium technology for high reliability 4Power supplies: 1.2 to 1.8V, and - 2.8V 4CML for dual serial input ports (differential) each operating at rates from 19.9 to 22.3 Gbaud/s 4Lower power consumption: 2.2 Watts 4Full BGA package including the serial input ports Applications 4SFI-5.1 compatible data and clock interfaces 4Dual on-chip Clock and Data Recovery (CDR) units with full-rate recovered clock output from 19.9 to 22.3 GHz 4 OC768/OTU3 Modules and Transponders 4 MSPP, ADM and Cross-connects 4 IP Routers and Switches 4CDR lock status indicators 4On-chip PRBS error checker and pattern generator 440 mVp-p input sensitivity for NRZ input signal 4100 mVp-p input sensitivity for RZ input signal W W W .SE MTE CH .COM SIERRA MONOLITHICS Product Brief SMI4039 Block Diagram RXLOS1 Status Control Logic CDR_LOCK_ERR1 CDR_LOCK_ERR0 > LOS_TH1[7:0] RXLF_N[1] DAC DSC_DELAY[3:0] Data Select Frame Generator RXDSCP/N RXDATA_EN RXDATAIN_DELAY0[5:0] CDR Block SWAP_01 DAC PH_ADJ0[4:0] C1 INVERT[1:0] LOCK_TO_DATA0 Fixed Data PRBS Pattern 27 /231 OUTPUT_DELAY[15:0][3:0] CDR . . . DECODER_EN Peak Det DAC C2 PRBS Error Checker DQPSK Decoder TH_ADJ0[P,N][7:0] + CDR Peak Det TH_ADJ1[P,N][7:0] RXLF_P[0] SFI-5 Block LOCK_TO_DATA1 + DAC RXDATAIN[0]P/N RXDATAIN _DELAY1[5:0] Line Side Deskew RXDATAIN[1]P/N GTEMP_P GTEMP_N Diode Temp. Sensor PRBS Block PH _ADJ1[4:0] 1.0 K RESN Select Resistor LOS_TH0[7:0] ADC R RXS0 PEAKDET 0[7:0] ADC C1 C2 RXS1 RXS_SEL0[1:0] > PEAKDET 1[7:0] Bias Current Control RXDATA_ SEL[1:0] RXLF_P[1] RESP Detector & Status RXS_SEL1[1:0] RXLOS0 RXDATA[15] P/N . . . RXDATA[0] P/N RXDCK_EN RXDCKP/N FRAME_EPOCH FRAME_EPOCH_EN R RESET_N Data Control Level Shift RXLF_N[0] RXREFCLK P/N Status SPI Subsystem RXCKSRCP/N RXCLKSRC _EN RXMCLKP/N VDD_Control RXMCLK_EN SPI_EN_N SPI_CLK SPI_DIN SPI_DOUT VCC_Digital -1.6V Reference REFN16_OUT REFN16_IN VDD_Digital VEE VEE_Digital -1.6V Regulator TEMP[7:0] VCC VDD_SFI5 ADC VCC_VCO_1 VEE_VCO_1 VEE_VCO_0 RX_TEMP VCC_VCO_0 PTAT Temp. Sensor Control DACs Control logic Interface Definitions SFI5 compatabile I/O LVCMOS (1.2, 1.8V) GND referenced CML AC coupled CML Sierra Monolithics Inc. is now part of Semtech Incorporated. To view the most current product specifications and datasheets, contact your local Semtech Field Applications Engineer. W W W .SE MTE CH .COM SIERRA MONOLITHICS SMI4039-PB