SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 D D D D Member of the Texas Instruments Widebus+ Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Packaged in Plastic Fine-Pitch Ball Grid Array Package description This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH32374 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus+ are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 6 A A 1Q2 1Q1 1OE 1CLK 1D1 1D2 B B 1Q4 1Q3 GND GND 1D3 1D4 C C 1Q6 1Q5 1D6 D 1Q8 1Q7 VCC GND 1D5 D VCC GND 1D7 1D8 E 2Q2 2Q1 GND GND 2D1 2D2 F 2Q4 2Q3 2D4 2Q6 2Q5 VCC GND 2D3 G VCC GND 2D5 2D6 H 2Q8 2Q7 2OE 2CLK 2D7 2D8 E F G H J 3Q2 3Q1 3OE 3CLK 3D1 3D2 J K 3Q4 3Q3 GND GND 3D3 3D4 K L 3Q6 3Q5 3D6 M 3Q8 3Q7 VCC GND 3D5 L VCC GND 3D7 3D8 M N 4Q2 4Q1 GND GND 4D1 4D2 N P 4Q4 4Q3 4Q6 4Q5 VCC GND 4D4 R VCC GND 4D3 P 4D5 4D6 R T 4Q7 4Q8 4OE 4CLK 4D8 4D7 T logic diagram (positive logic) A3 H3 1OE 2OE A4 H4 1CLK 2CLK A5 1D1 C1 A2 1D C1 1Q1 2D1 E5 To Seven Other Channels J3 2Q1 T3 4OE J4 T4 3CLK 4CLK J5 C1 J2 1D 3Q1 N5 4D1 To Seven Other Channels 2 1D To Seven Other Channels 3OE 3D1 E2 POST OFFICE BOX 655303 C1 1D To Seven Other Channels • DALLAS, TEXAS 75265 N2 4Q1 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 2 0.35 × VCC VI VO Input voltage 0 Output voltage 0 IOL ∆t/∆v 0.7 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V Low level output current Low-level V 1.7 Low-level input voltage High level output current High-level V 0.8 VCC VCC VCC = 1.65 V VCC = 2.3 V –4 VCC = 2.7 V VCC = 3 V –12 –8 V V mA –24 VCC = 1.65 V VCC = 2.3 V 4 VCC = 2.7 V VCC = 3 V 12 Input transition rise or fall rate V 0.65 × VCC VIL IOH UNIT 8 mA 24 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA IOH = –8 mA VOH 12 mA IOH = –12 IOH = –24 mA IOL = 100 µA VOL II II(hold) ( ) 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2.2 MAX 0.2 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 VI = VCC or GND VI = 0.58 V 3.6 V ±5 1.65 V 25 VI = 1.07 V VI = 0.7 V 1.65 V –25 2.3 V 45 VI = 1.7 V VI = 0.8 V 2.3 V –45 3V 75 3V –75 ∆ICC One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND VI = VCC or GND UNIT V 1.65 V VO = VCC or GND VI = VCC or GND, Data inputs 1.65 V VCC–0.2 1.2 1.65 V to 3.6 V IOZ ICC Ci TYP† IOL = 4 mA IOL = 8 mA VI = 2 V VI = 0 to 3.6 V‡ Control inputs MIN V µA µA 3.6 V ±500 3.6 V ±10 µA 40 µA 750 µA 3.6 V 3 V to 3.6 V 3 33V 3.3 pF 6 Co Outputs VO = VCC or GND 3.3 V 7 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V ± 0.15 V MIN fclock tw Clock frequency tsu th MAX § VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 UNIT MAX 150 MHz Pulse duration, CLK high or low § 3.3 3.3 3.3 ns Setup time, data before CLK↑ § 2.1 2.2 1.9 ns Hold time, data after CLK↑ § This information was not available at the time of publication. § 0.6 0.5 0.5 ns 4 • DALLAS, TEXAS 75265 POST OFFICE BOX 655303 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) VCC = 1.8 V ± 0.15 V TO (OUTPUT) MIN † MAX † VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX fmax tpd CLK Q † 1 5.3 4.9 1 4.2 ns ten OE Q † † 1 6.2 5.9 1 4.8 ns † † 1 5.3 4.7 1.2 4.3 ns tdis Q OE † This information was not available at the time of publication. 150 VCC = 2.7 V 150 MHz operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF VCC = 1.8 V TYP † f = 10 MHz † VCC = 2.5 V TYP VCC = 3.3 V TYP 31 30 16 18 UNIT pF † This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES283 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 1.5 V Input 0V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V tsu th 2.7 V Data Input 1.5 V 1.5 V 0V Output Control (low-level enabling) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V 0V tPLZ 1.5 V Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V VOL + 0.3 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 2 S1 at GND (see Note B) VOL tPHZ tPZH tPHL VOH Output 2.7 V tPZL 2.7 V Input 1.5 V 2.7 V Timing Input 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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