CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com 16 LVPECL Output, High-Performance Clock Buffer Check for Samples: CDCLVP2108 FEATURES DESCRIPTION • • • The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications. 1 2 • • • • • • • • • • • Dual 1:8 Differential Buffer Two Clock Inputs Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL 16 LVPECL Outputs Maximum Clock Frequency: 2 GHz Maximum Core Current Consumption: 115 mA Very Low Additive Jitter: <100 fs,rms in 10-kHz to 20-MHz Offset Range 2.375 V to 3.6 V Device Power Supply Maximum Propagation Delay: 550 ps Maximum Within Bank Output Skew: 25 ps LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs Industrial Temperature Range: –40°C to +85°C Available in 7-mm × 7-mm QFN-48 (RGZ) Package ESD Protection Exceeds 2 kV (HBM) APPLICATIONS • • • • The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a QFN-48, 7-mm × 7-mm package. Wireless Communications Telecommunications/Networking Medical Imaging Test and Measurement Equipment VCC The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL. VCC VCC VCC VCC INP0 LVPECL INN0 8 8 INP1 LVPECL INN1 VAC_REF[1, 0] VCC 8 8 2 OUTP[7...0] OUTN[7...0] OUTP[15...8] OUTN[15...8] Reference Generator GND GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. AVAILABLE OPTIONS (1) TA PACKAGED DEVICES FEATURES CDCLVP2108RGZT 48-pin QFN (RGZ) package, small tape and reel CDCLVP2108RGZR 48-pin QFN (RGZ) package, tape and reel –40°C to +85°C (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) Supply voltage range (2) VCC (3) CDCLVP2108 UNIT –0.5 to 4.6 V –0.5 to VCC + 0.5 V VIN Input voltage range VOUT Output voltage range IIN Input current IOUT Output current TA Specified free-air temperature range (no airflow) TSTG Storage temperature range –65 to +150 °C TJ Maximum junction temperature +125 °C ESD Electrostatic discharge (HBM) 2 kV (1) (2) (3) (3) –0.5 to VCC + 0.5 V 20 mA 50 mA –40 to +85 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltages must be supplied simultaneously. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). CDCLVP2108 PARAMETER VCC Supply voltage TA Ambient temperature MIN TYP MAX UNIT 2.375 2.50/3.30 3.60 V +85 °C –40 PACKAGE DISSIPATION RATINGS (1) (2) VALUE PARAMETER θJA θJP (1) (2) (3) 2 Thermal resistance, junction-to-ambient (3) TEST CONDITIONS 4 × 4 VIAS ON PAD UNIT 0 LFM 33.8 °C/W 150 LFM 22.6 °C/W 400 LFM 19.2 °C/W 3.67 °C/W Thermal resistance, junction-to-pad The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board). Connected to GND with 16 thermal vias (0.3-mm diameter). θJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN package. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS: LVCMOS Input (1) At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted). CDCLVP2108 PARAMETER fIN TEST CONDITIONS TYP MAX UNIT 200 MHz 1.8 V Vth + 0.1 VCC V 0 Vth – 0.1 V 40 μA Input frequency External threshold voltage applied to complementary input Vth Input threshold voltage VIH Input high voltage VIL Input low voltage IIH Input high current VCC = 3.6 V, VIH = 3.6 V IIL Input low current VCC = 3.6 V, VIL = 0 V ΔV/ΔT Input edge rate ICAP Input capacitance (1) MIN 20% to 80% 1.1 –40 1.5 μA V/ns 5 pF Figure 3 and Figure 4 show dc test setup. ELECTRICAL CHARACTERISTICS: Differential Input (1) At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted). CDCLVP2108 PARAMETER fIN Input frequency TEST CONDITIONS TYP Clock input MAX UNIT 2000 MHz fIN ≤ 1.5 GHz 0.1 1.5 V 1.5 GHz ≤ fIN ≤ 2 GHz 0.2 1.5 V 1.0 VCC – 0.3 V 40 μA VIN, DIFF, PP Differential input peak-peak voltage VICM Input common-mode level IIH Input high current VCC = 3.6 V, VIH = 3.6 V IIL Input low current VCC = 3.6 V, VIL = 0 V ΔV/ΔT Input edge rate ICAP Input capacitance (1) MIN 20% to 80% –40 1.5 μA V/ns 5 pF Figure 5 and Figure 6 show dc test setup. Figure 7 shows ac test setup. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 3 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS: LVPECL Output (1) At VCC = 2.375 V to 2.625 V and TA = –40°C to +85°C (unless otherwise noted). CDCLVP2108 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Output high voltage VCC – 1.26 VCC – 0.9 V VOL Output low voltage VCC – 1.7 VCC – 1.3 V VOUT, DIFF, PP Differential output peak-peak voltage 0.5 1.35 V VAC_REF Input bias voltage (2) VCC – 1.6 VCC – 1.1 V VIN, DIFF, PP = 0.1V 550 ps VIN, DIFF, PP = 0.3V 550 ps 150 ps tPD Propagation delay tSK,PP Part-to-part skew tSK,O_WB Within bank output skew tSK,O_BB Bank-to-bank output skew tSK,P Pulse skew (with 50% duty cycle input) Random additive jitter (with 50% duty cycle input) tRJIT PSPUR Coupling on differential OUT8 from OUT7 in the frequency spectrum of fOUT, 8 ±(fOUT, 8/2) with synchronous inputs tR/tF Output rise/fall time IEE Supply internal current ICC Output and internal supply current (1) (2) 4 fIN ≤ 2 GHz IAC_REF = 2 mA 25 Both inputs have equal skew Crossing-point-to-crossing-point distortion, fOUT = 100 MHz –50 30 ps 50 ps fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.25 V, 10 kHz to 20 MHz 0.124 ps, RMS fOUT = 100 MHz, VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz 0.178 ps, RMS fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz 0.061 ps, RMS fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz 0.119 ps, RMS fOUT = 100 MHz, VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz 0.104 ps, RMS fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 –46.6 dBc fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V –49.1 dBc fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 –61 dBc fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V –62.5 dBc 20% to 80% 200 ps Outputs unterminated 115 mA All outputs terminated, 50 Ω to VCC – 2 620 mA Figure 8 and Figure 9 show dc and ac test setup. Internally generated bias voltage (VAC_REF) is for 3.3-V operation only. It is recommended to apply externally generated bias voltage for VCC < 3.0 V. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS: LVPECL Output (1) At VCC = 3.0 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted). CDCLVP2108 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Output high voltage VCC – 1.26 VCC – 0.9 V VOL Output low voltage VCC – 1.7 VCC – 1.3 V VOUT, DIFF, PP Differential output peak-peak voltage 0.65 1.35 V VAC_REF Input bias voltage VCC – 1.6 VCC – 1.1 V VIN, DIFF, PP = 0.1V 550 ps VIN, DIFF, PP = 0.3V 550 ps 150 ps 25 ps 30 ps 50 ps tPD Propagation delay tSK,PP Part-to-part skew tSK,O_WB Within bank output skew tSK,O_BB Bank-to-bank output skew tSK,P Pulse skew (with 50% duty cycle input) IAC_REF = 2 mA Both inputs have equal skew Crossing-point-to-crossing-point distortion, fOUT = 100 MHz Random additive jitter (with 50% duty cycle input) tRJIT PSPUR Coupling on differential OUT8 from OUT7 in the frequency spectrum of fOUT, 8 ±(fOUT, 8/2) with synchronous inputs tR/tF Output rise/fall time IEE Supply internal current ICC Output and internal supply current (1) fIN ≤ 2 GHz –50 fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.65 V, 10 kHz to 20 MHz 0.121 ps, RMS fOUT = 100 MHz, VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz 0.185 ps, RMS fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz 0.077 ps, RMS fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz 0.122 ps, RMS fOUT = 100 MHz, VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz 0.105 ps, RMS fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 –48.5 dBc fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SIFF,PP,1 = 1 V, VICM, 1 = 1 V –50.6 dBc fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 –60.5 dBc fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V –60.9 dBc 20% to 80% 200 ps Outputs unterminated 115 mA All outputs terminated, 50 Ω to VCC – 2 620 mA Figure 8 and Figure 9 show dc and ac test setup. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 5 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com OUTN10 OUTP10 OUTN9 OUTP9 OUTN8 OUTP8 OUTN7 OUTP7 OUTN6 OUTP6 OUTN5 OUTP5 36 35 34 33 32 31 30 29 28 27 26 25 RGZ PACKAGE QFN-48 (TOP VIEW) VCC 37 24 VCC OUTP11 38 23 OUTN4 OUTN11 39 22 OUTP4 OUTP12 40 21 OUTN3 CDCLVP2108 (1) 6 OUTN12 41 20 OUTP3 OUTP13 42 19 OUTN2 OUTN13 43 18 OUTP2 OUTP14 44 17 OUTN1 OUTN14 45 16 OUTP1 OUTP15 46 15 OUTN0 OUTN15 47 14 OUTP0 VCC 48 13 VCC 5 6 7 8 9 10 VAC_REF1 VCC VCC VAC_REF0 INN0 INP0 12 4 INN1 GND 3 INP1 11 2 NC NC 1 (1) GND Thermal Pad Thermal pad must be soldered to ground. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com PIN DESCRIPTIONS CDCLVP2108 Pin Descriptions TERMINAL NAME TERMINAL NO. VCC 6, 7, 13, 24, 37, 48 Power 2.5-/3.3-V supplies for the device Device grounds TYPE DESCRIPTION GND 1, 12 Ground INP0, INN0 10, 9 Input Differential input pair or single-ended input no. 0 INP1, INN1 3, 4 Input Differential input pair or single-ended input no. 1 OUTP15, OUTN15 46, 47 Output Differential LVPECL output pair no. 15 OUTP14, OUTN14 44, 45 Output Differential LVPECL output pair no. 14 OUTP13, OUTN13 42, 43 Output Differential LVPECL output pair no. 13 OUTP12, OUTN12 40, 41 Output Differential LVPECL output pair no. 12 OUTP11, OUTN11 38, 39 Output Differential LVPECL output pair no. 11 OUTP10, OUTN10 35, 36 Output Differential LVPECL output pair no. 10 OUTP9, OUTN9 33, 34 Output Differential LVPECL output pair no. 9 OUTP8, OUTN8 31, 32 Output Differential LVPECL output pair no. 8 OUTP7, OUTN7 29, 30 Output Differential LVPECL output pair no. 7 OUTP6, OUTN6 27, 28 Output Differential LVPECL output pair no. 6 OUTP5, OUTN5 25, 26 Output Differential LVPECL output pair no. 5 OUTP4, OUTN4 22, 23 Output Differential LVPECL output pair no. 4 OUTP3, OUTN3 20, 21 Output Differential LVPECL output pair no. 3 OUTP2, OUTN2 18, 19 Output Differential LVPECL output pair no. 2 OUTP1, OUTN1 16, 17 Output Differential LVPECL output pair no. 1 OUTP0 OUTN0 14, 15 Output Differential LVPECL output pair no. 0 VAC_REF0 8 Output Bias voltage output for capacitive coupled input pair no. 0. Do not use VAC_REF at VCC < 3.0 V. If used, it is recommended to use a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA. VAC_REF1 5 Output Bias voltage output for capacitive coupled input pair no. 1. Do not use VAC_REF at VCC < 3.0 V. If used, it is recommended to use a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA. NC 2, 11 — Do not connect Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 7 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = –40°C to +85°C (unless otherwise noted). Differential Output Peak-toPeak Voltage (V) DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE vs FREQUENCY 1.0 VCC = 2.375 V TA = -40°C to +85°C VICM = 1 V VIN,DIFF,PP = Min 0.9 0.8 0.7 0.6 0.5 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Frequency (GHz) Figure 1. Differential Output Peak-to-Peak Voltage (V) DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE vs FREQUENCY 1.1 1.2 1.3 1.0 0.9 0.8 0.7 VCC = 3.0 V TA = -40°C to +85°C VICM = 1 V VIN,DIFF,PP = Min 0.6 0.5 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Frequency (GHz) Figure 2. 8 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com TEST CONFIGURATIONS This section describes the function of each block for the CDCLVP2108. Figure 3 through Figure 9 illustrate how the device should be setup for a variety of test configurations. IN VIH Vth VIL IN Vth Figure 3. DC-Coupled LVCMOS Input During Device Test VCC VIHmax Vthmax VILmax VIH Vth Vth VIL VIHmin Vthmin VILmin GND Figure 4. Vth Variation over LVCMOS Levels VCC VCC 130 W 130 W CDCLVP2108 LVPECL 82 W 82 W Figure 5. DC-Coupled LVPECL Input During Device Test Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 9 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com 100 W LVDS CDCLVP2108 Figure 6. DC-Coupled LVDS Input During Device Test VCC VCC 82 W 82 W CDCLVP2108 Differential 130 W 130 W Figure 7. AC-Coupled Differential Input to Device Oscilloscope LVPECL 50 W 50 W VCC - 2 V Figure 8. LVPECL Output DC Configuration During Device Test Phase Noise Analyzer LVPECL 150 W 150 W 50 W Figure 9. LVPECL Output AC Configuration During Device Test 10 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com Figure 10 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 11. VOH OUTNx VOD VOL OUTPx 80% VOUT,DIFF,PP (= 2 ´ VOD) 20% 0V tR tF Figure 10. Output Voltage and Rise/Fall Time INNx INPx tPLH0 tPLH0 tPLH1 tPLH1 OUTN0 OUTP0 OUTN1 OUTP1 tPLH2 tPLH2 OUTN2 OUTP2 tPLH15 tPLH15 OUTN15 OUTP15 (1) Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn (n = 0, 1, 2....15), or as the difference between the fastest and the slowest tPHLn (n = 0, 1, 2....15). (2) Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn (n = 0, 1, 2....15) across multiple devices, or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2....15) across multiple devices. Figure 11. Output and Part-to-Part Skew Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 11 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION Thermal Management Power consumption of the CDCLVP2108 can be high enough to require attention to thermal management. For reliability and performance reasons, the die temperature should be limited to a maximum of +125°C. That is, as an estimate, ambient temperature (TA) plus device power consumption times θJA should not exceed +125°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. Figure 12 shows a recommended land and via pattern. 5,0 mm (min) 0,33 mm (typ) 1,2 mm (typ) Figure 12. Recommended PCB Layout Power-Supply Filtering High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with very low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. 12 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com Figure 13 illustrates this recommended power-supply decoupling method. VCC Board Supply Chip Supply Ferrite Bead C 10 mF C 1 mF C 0.1 mF (x6) Figure 13. Power-Supply Decoupling LVPECL Output Termination The CDCLVP2108 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC –2) V, but this dc voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled configurations. These configurations are shown in Figure 14a and b for VCC = 2.5 V and Figure 15a and b for VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, ac coupling is required. VCC VCC 250 W 250 W CDCLVP2108 LVPECL 62.5 W 62.5 W (a) Output DC Termination VBB CDCLVP2108 LVPECL 86 W 86 W 50 W 50 W (b) Output AC Termination Figure 14. LVPECL Output DC and AC Termination for VCC = 2.5 V Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 13 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com VCC VCC 130 W 130 W CDCLVP2108 LVPECL 82 W 82 W (a) Output DC Termination VBB CDCLVP2108 150 W LVPECL 150 W 50 W 50 W (b) Output AC Termination Figure 15. LVPECL Output DC and AC Termination for VCC = 3.3 V Input Termination The CDCLVP2108 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 16 illustrates how to dc couple an LVCMOS input to the CDCLVP2108. The series resistance (RS) should be placed close to the LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver output impedance. VIH Vth VIL RS LVCMOS CDCLVP2108 Vth = VIH + VIL 2 Figure 16. DC-Coupled LVCMOS Input to CDCLVP2108 14 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com Figure 17 shows how to dc couple LVDS inputs to the CDCLVP2108. Figure 18 and Figure 19 describe the method of dc coupling LVPECL inputs to the CDCLVP2108 for VCC = 2.5 V and VCC = 3.3 V, respectively. 100 W LVDS CDCLVP2108 Figure 17. DC-Coupled LVDS Inputs to CDCLVP2108 VCC VCC 250 W 250 W CDCLVP2108 LVPECL 62.5 W 62.5 W Figure 18. DC-Coupled LVPECL Inputs to CDCLVP2108 (VCC = 2.5 V) VCC VCC 130 W 130 W CDCLVP2108 LVPECL 82 W 82 W Figure 19. DC-Coupled LVPECL Inputs to CDCLVP2108 (VCC = 3.3 V) Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 15 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com Figure 20 and Figure 21 show the technique of ac coupling differential inputs to the CDCLVP2108 for VCC = 2.5 V and VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, ac coupling is required. VCC VCC 96 W 96 W CDCLVP2108 Differential 105 W 105 W Figure 20. AC-Coupled Differential Inputs to CDCLVP2108 (VCC = 2.5 V) VCC VCC 82 W 82 W CDCLVP2108 Differential 130 W 130 W Figure 21. AC-Coupled Differential Inputs to CDCLVP2108 (VCC = 3.3 V) 16 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 CDCLVP2108 SCAS878B – MAY 2009 – REVISED AUGUST 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July, 2009) to Revision B Page • Corrected VIL parameter description in Electrical Characteristics table for LVCMOS input ................................................. 3 • Added footnote (2) to Electrical Characteristics table for LVPECL Output, VCC = 2.375 V to 2.625 V ................................ 4 • Revised descriptions of pins 8 and 5 .................................................................................................................................... 7 • Changed recommended resistor values in Figure 14(a) .................................................................................................... 13 • Changed recommended resistor values in Figure 18 ......................................................................................................... 15 Changes from Original (May, 2009) to Revision A Page • Changed LVPECL output condition voltage range from 3 V to 2.625 V ............................................................................... 4 • Changed LVPECL output at VCC = 2.375 V to 3.6 V random additive jitter specification (at fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz) from 0.007 ps, RMS to 0.061 ps, RMS .................................................................... 4 • Changed LVPECL output at VCC = 3.0 V to 3.6 V random additive jitter specification (at fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz) from 0.011 ps, RMS to 0.077 ps, RMS .................................................................... 5 • Corrected Figure 5 ................................................................................................................................................................ 9 • Corrected Figure 7 .............................................................................................................................................................. 10 • Added Input Termination section ........................................................................................................................................ 14 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVP2108 17 PACKAGE OPTION ADDENDUM www.ti.com 31-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) CDCLVP2108RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CDCLVP2108RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CDCLVP2108RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CDCLVP2108RGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVP2108RGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CDCLVP2108RGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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