CDCLVD1213 www.ti.com SCAS897 – JULY 2010 1:4 Low Additive Jitter LVDS Buffer With Divider Check for Samples: CDCLVD1213 FEATURES 1 • • • • • • • • • • • 1:4 Differential Buffer Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz Low Output Skew of 20 ps (Max) Selectable Divider Ratio 1, /2, /4 Universal Input Accepts LVDS, LVPECL, and CML 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible Clock Frequency up to 800 MHz 2.375 V–2.625 V Device Power Supply Industrial Temperature Range: –40°C to 85°C Packaged in 3 mm × 3 mm 16-Pin QFN (RGT) ESD Protection Exceeds 3 kV HBM, 1 kV CDM APPLICATIONS • • • • • DESCRIPTION The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML. The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2, or 4. The CDCLVD1213 is specifically designed for driving 50 Ω transmission lines. The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 2.5 V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1213 is packaged in small 16-pin, 3-mm × 3-mm QFN package. Telecommunications/Networking Medical Imaging Test and Measurement Equipment Wireless Communications General Purpose Clocking ASIC 156.25 MHz PHY1 CDCLVD1213 LVDS Buffer with Divider DIV PHY2 FPGA Figure 1. Application Example 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CDCLVD1213 SCAS897 – JULY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. QP0 QN0 INP QP1 INN QN1 QP2 70 W 70 W QN2 VT VCC QDP /1 /2 /4 200 kW QDN DIV 200 kW GND Figure 2. CDCLVD1213 Block Diagram QP1 QN0 QP0 VCC GND RGT PACKAGE (TOP VIEW) 12 11 10 9 13 QN1 14 QP2 15 3mm x 3mm 16 pin QFN (RGT) 8 VT 7 INP 6 INN 5 VCC Thermal Pad 2 1 2 3 4 QDP QDN DIV 16 GND QN2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 CDCLVD1213 www.ti.com SCAS897 – JULY 2010 PIN DESCRIPTIONS CDCLVD1213 Pin Descriptions PIN TYPE DESCRIPTION NAME NO. VCC 5, 10 Power 2.5 V supply for the device GND 1, 9 Ground Device ground INP, INN 7, 6 Input Differential input pair Input for threshold voltage VT 8 Input QDP, QDN 2,3 Output Differential divided LVDS output pair QP0, QN0 11,12 Output Differential LVDS output pair no. 0 QP1, QN1 13,14 Output Differential LVDS output pair no. 1 QP2, QN2 15,16 Output Differential LVDS output pair no. 2 4 Input with an internal 200kΩ pull-up and pull-down DIV Thermal Pad Divider selection – selects divider ratio for QD output; (See Table 1) See thermal management recommendations Table 1. Divider Selection Table DIV DIVIDER RATIO 0 /1 open /2 1 /4 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) VALUE UNIT –0.3 to 2.8 V Input voltage range, VI –0.2 to VCC +0.2 V Output voltage range, VO –0.2 to VCC+0.2 V Supply voltage range, VCC See Note (2) Driver short circuit current , IOSD Electrostatic discharge (Human Body Model 1.5 kΩ, 100 pF) (1) (2) >3000 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The output can handle the permanent short. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). Device supply voltage, VCC Ambient temperature, TA MIN TYP MAX 2.375 2.5 2.625 V 85 °C –40 UNIT Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 3 CDCLVD1213 SCAS897 – JULY 2010 www.ti.com THERMAL INFORMATION CDCLVD1213 THERMAL METRIC (1) qJA Junction-to-ambient thermal resistance 51.3 qJC(top) Junction-to-case(top) thermal resistance 85.4 qJB Junction-to-board thermal resistance 20.1 yJT Junction-to-top characterization parameter 1.3 yJB Junction-to-board characterization parameter 19.4 qJC(bottom) Junction-to-case(bottom) thermal resistance 6 (1) UNITS RGT(16 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIVIDER CONTROL INPUT (DIV) CHARACTERISTICS VdI3 3-State VdIH Input high voltage Open VdIL Input low voltage IdIH Input high current VCC = 2.625 V, VIH = 2.625 V IdIL Input low current VCC = 2.625 V, VIL = 0 V Rpull(DIV) Input pull-up/ pull-down resistor 0.5×VCC V 0.7×VCC V 0.2×VCC V 30 mA –30 mA 200 kΩ DIFFERENTIAL INPUTS (INP, INN) CHARACTERISTICS fIN VIN, DIFF Input frequency Clock input Differential input voltage peak-to-peak VICM = 1.25 V VICM Input common-mode voltage range RIN Input termination INP, INN to VT, DC IIH Input high current VCC = 2.625 V, VIH = 2.625 V IIL Input low current VCC = 2.625 V, VIL = 0 V ΔV/ΔT Input edge rate 20% to 80% CIN Input capacitance 4 0.3 1 MHz 1.6 VPP VCC – 0.3 10 –10 0.75 V Ω 70 mA mA V/ns 2.5 Submit Documentation Feedback 800 pF Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 CDCLVD1213 www.ti.com SCAS897 – JULY 2010 ELECTRICAL CHARACTERISTICS (continued) At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250 450 mV –15 15 mV 1.1 1.375 –15 15 LVDS OUTPUT CHARACTERISTICS |VOD| Differential output voltage magnitude ΔVOD Change in differential output voltage magnitude VOC(SS) Steady-state common mode output voltage ΔVOC(SS) Steady-state common mode output voltage VIN, DIFF, PP = 0.6V, RL = 100 Ω IOS Short-circuit output current VOD = 0 V VOS Output ac common mode VIN, DIFF, PP = 0.6V, RL = 100 Ω Vring Output overshoot and undershoot Percentage of output amplitude VOD tPD Propagation delay VIN, DIFF, PP = 0.3 V tSK, PP Part-to-part skew VIN, DIFF, PP = 0.3V, RL = 100 Ω 25 V mV ±24 mA 70 mVPP 10% 1.5 (1) 2.5 ns 600 ps 20 ps 50 ps tSK, O Output skew tSK,P Pulse skew (with 50% duty cycle input) Crossing-point-to-crossing-point distortion tRJIT Random additive jitter (with 50% duty cycle input) Edge speed 0.75V/ns 10 kHz – 20 MHz tR/tF Output rise/fall time 20% to 80%,100 Ω, 5 pF 300 ps ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 17 28 mA ICC100 Supply current All outputs, RL = 100 Ω, f = 100 MHz 40 58 mA ICC800 Supply current All outputs, RL = 100 Ω, f = 800 MHz 60 85 mA (1) –50 0.3 ps, RMS 50 Undivided outputs only. Typical Additive Phase Noise Characteristics for 100 MHz Clock PARAMETER MIN TYP MAX UNIT phn100 Phase noise at 100 Hz offset -132.9 dBc/Hz phn1k Phase noise at 1 kHz offset -138.8 dBc/Hz phn10k Phase noise at 10 kHz offset -147.4 dBc/Hz phn100k Phase noise at 100 kHz offset -153.6 dBc/Hz phn1M Phase noise at 1 MHz offset -155.2 dBc/Hz phn10M Phase noise at 10 MHz offset -156.2 dBc/Hz phn20M Phase noise at 20 MHz offset -156.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS Typical Additive Phase Noise Characteristics for 737.27 MHz Clock PARAMETER MIN TYP MAX UNIT phn100 Phase noise at 100 Hz offset -80.2 dBc/Hz phn1k Phase noise at 1 kHz offset -114.3 dBc/Hz phn10k Phase noise at 10 kHz offset phn100k Phase noise at 100 kHz offset -138 dBc/Hz -143.9 phn1M Phase noise at 1 MHz offset -145.2 dBc/Hz dBc/Hz phn10M Phase noise at 10 MHz offset -146.5 dBc/Hz phn20M Phase noise at 20 MHz offset -146.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 5 CDCLVD1213 SCAS897 – JULY 2010 www.ti.com TYPICAL CHARACTERISTICS INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES vs FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V) Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs Figure 3. 100 MHz Input and Output Phase Noise Plot Differential Output Voltage vs Frequency VOD − Differential Output Voltage − mV 350 TA = 25oC 340 2.625V 330 320 2.5V 310 300 2.375V 290 280 270 260 250 0 100 200 300 400 500 600 700 800 Frequency − MHz Figure 4. 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 CDCLVD1213 www.ti.com SCAS897 – JULY 2010 TEST CONFIGURATIONS Oscilloscope 100 W LVDS Figure 5. LVDS Output DC Configuration During Device Test Phase Noise Analyzer LVDS 50 W Figure 6. LVDS Output AC Configuration During Device Test VOH OUTNx VOD OUTPx VOL 80% VOUT,DIFF,PP (= 2 x VOD) 20% 0V tR tF Figure 7. Output Voltage and Rise/Fall Time INN INP tPLH0 tPHL0 tPLH1 tPHL1 QN0 QP0 QN1 QP1 tPLH2 tPHL2 QN2 QP2 (1) Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2). (2) Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2). Figure 8. Output and Part-to-Part Skew Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 7 CDCLVD1213 SCAS897 – JULY 2010 www.ti.com Vring QNx VOD 0V Differential QPx Figure 9. Output Overshoot and Undershoot VOS GND Figure 10. Output AC Common Mode APPLICATION INFORMATION THERMAL MANAGEMENT For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure adequate heat conduction to the package. Figure 11 shows a recommended land and via pattern. Figure 11. Recommended PCB Layout 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 CDCLVD1213 www.ti.com SCAS897 – JULY 2010 POWER-SUPPLY FILTERING High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is critical to applications. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1 µF) bypass capacitors as there are supply pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. Ferrite Bead 1 µF 10 µF 0.1 µF Figure 12. Power-Supply Decoupling LVDS OUTPUT TERMINATION The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is recommended to place termination resister close to the receiver. If the receiver is internally biased, ac-coupling should be used. If the LVDS receiver has internal 100 Ω termination, external termination is not required. Unused outputs can be left open without connecting any traces to the output pins. Z = 50 W 100 W CDCLVD1213 LVDS Z = 50 W Figure 13. Output DC Termination 100 nF Z = 50 W 100 W CDCLVD1213 LVDS Z = 50 W 100 nF Figure 14. Output AC Termination (With Receiver Internally Biased) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 9 CDCLVD1213 SCAS897 – JULY 2010 www.ti.com INPUT TERMINATION The CDCLVD1213 input has internal 140 Ω terminations, and an external 350 Ω resistor is required for a 50 Ω transmission line. It can be interfaced with LVDS, LVPECL, or CML drivers. LVDS input can be connected directly, dc or ac coupled. With ac coupling, external bias (VCC/2) must be provided to VT pin. Figure 16 illustrates how to connect CML input to CDCLVD1213 input buffer. The input does not have internal biasing, so external biasing (VCC/2 to VT) is required for ac coupling. If the CML output swing is >1.6 VPP, then signal swing needs to be reduced to meet VIN, DIF, PP ≤ 1.6 VPP. Z = 50 W 350 W LVDS CDCLVD1213 Z = 50 W Figure 15. LVDS Clock Driver Connected to CDCLVD1213 Input 100 nF Z = 50 W 350 W CML CDCLVD1213 Z = 50 W 100 nF VT = 1.25V Figure 16. CML Clock Driver Connected to CDCLVD1213 Input Figure 17 shows how to connect LVPECL input to the CDCLVD1213 input buffer. The input does not have internal biasing, so external biasing (VCC/2 to VT) is required for ac coupling. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 Vpp. 75 W 100 nF Z = 50 W 350 W LVPECL CDCLVD1213 Z = 50 W 75 W 150 W 150 W 100 nF VT = 1.25V Figure 17. LVPECL Clock Driver Connected to CDCLVD1213 Input 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1213 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CDCLVD1213RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples CDCLVD1213RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CDCLVD1213RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 CDCLVD1213RGTT QFN RGT 16 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD1213RGTR QFN RGT 16 3000 338.1 338.1 20.6 CDCLVD1213RGTT QFN RGT 16 250 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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