TI MSP430F5308IRGZ

MSP430F530x, MSP430F5310
www.ti.com
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
23
•
•
•
•
Low Supply-Voltage Range, 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode (AM)
All System Clocks Active
– 195 µA/MHz at 8 MHz, 3 V, Flash
Program Execution (Typical)
– 115 µA/MHz at 8 MHz, 3 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3)
– Real-Time Clock With Crystal,
Watchdog, and Supply Supervisor
Operational, Full RAM Retention, Fast
Wake-Up:
1.9 µA at 2.2 V, 2.1 µA at 3 V (Typical)
– Low-Power Oscillator (VLO), GeneralPurpose Counter, Watchdog, and
Supply Supervisor Operational, Full
RAM Retention, Fast Wake-Up:
1.4 µA at 3 V (Typical)
– Off Mode (LPM4)
Full RAM Retention, Supply Supervisor
Operational, Fast Wake-Up:
1.1 µA at 3 V (Typical)
– Shutdown Mode (LPM4.5)
0.18 µA at 3 V (Typical)
Wake-Up From Standby Mode in Less Than
5 µs
16-Bit RISC Architecture, Extended Memory,
Up to 25-MHz System Clock
Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring,
and Brownout
Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Watch Crystals (XT1)
– High-Frequency Crystals up to 32 MHz
(XT2)
16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TA2, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TB0, Timer_B With Seven
Capture/Compare Shadow Registers
Two Universal Serial Communication
Interfaces
– USCI_A0 and USCI_A1 Each Support:
– Enhanced UART With Auto-Baudrate
Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1 Each Support:
– I2CTM
– Synchronous SPI
Integrated 3.3-V Power System
10-Bit Analog-to-Digital (A/D) Converter With
Window Comparator
Comparator
Hardware Multiplier Supporting 32-Bit
Operations
Serial Onboard Programming, No External
Programming Voltage Needed
Three Channel Internal DMA
Basic Timer With Real-Time Clock Feature
Family Members are summarized in
For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F530x, MSP430F5310
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 µs.
The MSP430F5310, MSP430F5309, and MSP430F5308 devices are microcontroller configurations with 3.3-V
LDO, four 16-bit timers, a high-performance 10-bit analog-to-digital converter (ADC), two universal serial
communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities and
31 or 47 I/O pins.
The MSP430F5304 device is a configuration 3.3-V LDO, four 16-bit timers, a high-performance 10-bit analog-todigital converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, realtime clock module with alarm capabilities, and 31 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, and hand-held meters.
Table 1. Family Members
USCI
DEVICE
PROGRAM
MEMORY
(KB)
SRAM
(KB)
Timer_A (1)
Timer_B (2)
MSP430F5310
32
6
5, 3, 3
7
MSP430F5309
MSP430F5308
MSP430F5304
(1)
(2)
24
16
8
6
6
6
5, 3, 3
5, 3, 3
5, 3, 3
CHANNEL A: CHANNEL B:
UART, LIN,
SPI, I2C
IrDA, SPI
ADC10_A
(CH)
Comp_B
(CH)
I/O
PACKAGE
TYPE
2
2
10 ext, 2 int
8
47
64 RGC,
80 ZQE
1
1
6 ext, 2 int
4
31
48 PT,
48 RGZ
2
2
10 ext, 2 int
8
47
64 RGC,
80 ZQE
1
1
6 ext, 2 int
4
31
48 PT,
48 RGZ,
2
2
10 ext, 2 int
8
47
64 RGC,
80 ZQE
1
1
6 ext, 2 int
4
31
48 PT,
48 RGZ,
1
1
6 ext, 2 int
-
31
48 PT,
48 RGZ
7
7
7
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Table 2. Ordering Information (1)
PACKAGED DEVICES
TA
–40°C to 85°C
(1)
(2)
2
(2)
PLASTIC 64-PIN VQFN
(RGC)
PLASTIC 80-BALL BGA
(ZQE)
PLASTIC 48-PIN VQFN
(RGZ)
PLASTIC 48-PIN LQFP
(PT)
MSP430F5310IRGC
MSP430F5310IZQE
MSP430F5310IRGZ
MSP430F5310IPT
MSP430F5309IRGC
MSP430F5309IZQE
MSP430F5309IRGZ
MSP430F5309IPT
MSP430F5308IRGC
MSP430F5308IZQE
MSP430F5308IRGZ
MSP430F5308IPT
MSP430F5304IRGZ
MSP430F5304IPT
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
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Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F530x, MSP430F5310
www.ti.com
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Functional Block Diagram – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRG,
MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
MCLK
CPUXV2
and
Working
Registers
32KB
24KB
16KB
6KB
Flash
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
1×5 I/Os
1×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1×8 I/Os
PA
1×16 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
REF
COMP_B
ADC10_A
10 Bit
200 KSPS
12 Channels
(10 ext, 2 int)
Window
Comparator
MAB
DMA
MDB
3 Channel
EEM
(S:3+1)
JTAG,
SBW
Interface
TA0
MPY32
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TA2
Timer_A
3 CC
Registers
USCI0,1
PU Port
Ax: UART,
IrDA, SPI
LDO
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
Bx: SPI, I2C
PU.0, PU.1
Copyright © 2010–2012, Texas Instruments Incorporated
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MSP430F530x, MSP430F5310
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
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Pin Designation – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRGC
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
NC
LDOO
LDOI
PU.1
NC
PU.0
VSSU
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
2
47
3
46
4
45
5
44
6
43
7
8
9
42
MSP430F530xIRGC
MSP430F5310IRGC
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P4.7/PM_NONE
P4.6/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVCC2
DVSS2
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
VCORE
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2
P6.3/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P5.0/A8/VeREF+
P5.1/A9/VeREF−
AVCC1
P5.4/XIN
P5.5/XOUT
AVSS1
DVCC1
DVSS1
NOTE: Connection of exposed thermal pad to VSS is recommended.
4
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MSP430F530x, MSP430F5310
www.ti.com
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Pin Designation – MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE
ZQE PACKAGE
(TOP VIEW)
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
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MSP430F530x, MSP430F5310
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
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Functional Block Diagram – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,
MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
MCLK
CPUXV2
and
Working
Registers
32KB
24KB
16KB
6KB
Flash
RAM
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
I/O Ports
P1, P2
1×8 I/Os
1×1 I/Os
Interrupt,
Wakeup
PA
1×9 I/Os
P3.x
PB
P4.x
P5.x
PC
P6.x
I/O Ports
P4
1×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1×4 I/Os
PB
1×8 I/Os
PC
1×10 I/Os
REF
COMP_B
ADC10_A
10 Bit
200 KSPS
8 Channels
(6 ext, 2 int)
Window
Comparator
MAB
DMA
MDB
3 Channel
EEM
(S:3+1)
JTAG,
SBW
Interface
TA0
MPY32
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TA2
Timer_A
3 CC
Registers
USCI
PU Port
A1: UART,
IrDA, SPI
LDO
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
B1: SPI, I2C
PU.0, PU.1
6
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Pin Designation – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,
MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT
PU.0
VSSU
NC
PU.1
LDOI
NC
LDOO
P5.2/XT2IN
AVSS2
P5.3/XT2OUT
TEST/SBWTCK
RST/NMI/SBWTDIO
RGZ OR PT PACKAGE
(TOP VIEW)
1
48 47 46 45 44 43 42 41 40 39 38 37
36
P4.7/PM_NONE
2
35
P4.6/PM_NONE
P6.2/CB2/A2
3
34
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P6.3/CB3/A3
4
33
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P5.0/A8/VeREF+
5
32
P4.3/PM_UCB1CLK/PM_UCA1STE
P5.1/A9/VeREF-
6
31
P4.2/PM_UCB1SOMI/PM_UCB1SCL
AVCC1
7
30
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P5.4/XIN
8
29
P4.0/PM_UCB1STE/PM_UCA1CLK
P5.5/XOUT
9
28
DVCC2
AVSS1
10
27
DVSS2
DVCC1
11
26
PJ.3/TCK
DVSS1
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PJ.2/TMS
PJ.0/TDO
P2.0/TA1.1
P1.7/TA1.0
P1.6/TA1CLK/CBOUT
P1.5/TA0.4
P1.4/TA0.3
P1.3/TA0.2
P1.2/TA0.1
P1.1/TA0.0
VCORE
P1.0/TA0CLK/ACLK
MSP430F530x
MSP430F5310
PJ.1/TDI/TCLK
P6.0/CB0/A0
P6.1/CB1/A1
NOTE: For RGZ package, connection of exposed thermal pad to VSS is recommended.
Copyright © 2010–2012, Texas Instruments Incorporated
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Functional Block Diagram – MSP430F5304IRGZ, MSP430F5304IPT
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS
P1.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
8KB
Flash
6KB
RAM
MCLK
CPUXV2
and
Working
Registers
Power
Management
LDO
SVM/SVS
Brownout
SYS
Watchdog
Port Map
Control
(P4)
PA
P2.x
I/O Ports
P1, P2
1×8 I/Os
1×1 I/Os
Interrupt,
Wakeup
PA
1×9 I/Os
P3.x
PB
P4.x
P5.x
PC
P6.x
I/O Ports
P4
1×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1×4 I/Os
PB
1×8 I/Os
PC
1×10 I/Os
REF
ADC10_A
10 Bit
200 KSPS
8 Channels
(6 int, 2 ext)
Window
Comparator
MAB
DMA
MDB
3 Channel
EEM
(S:3+1)
JTAG,
SBW
Interface
TA0
MPY32
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TA2
Timer_A
3 CC
Registers
USCI
PU Port
A1: UART,
IrDA, SPI
LDO
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
B1: SPI, I2C
PU.0, PU.1
8
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Pin Designation – MSP430F5304IRGZ, MSP430F5304IPT
P6.0/A0
P6.1/A1
PU.0
VSSU
PU.1
NC
LDOI
NC
LDOO
AVSS2
P5.2/XT2IN
TEST/SBWTCK
P5.3/XT2OUT
RST/NMI/SBWTDIO
RGZ OR PT PACKAGE
(TOP VIEW)
1
48 47 46 45 44 43 42 41 40 39 38 37
36
P4.7/PM_NONE
2
35
P4.6/PM_NONE
P6.2/A2
3
34
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P6.3/A3
4
33
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P5.0/A8/VeREF+
5
32
P4.3/PM_UCB1CLK/PM_UCA1STE
P5.1/A9/VeREF-
6
31
P4.2/PM_UCB1SOMI/PM_UCB1SCL
AVCC1
7
30
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P5.4/XIN
8
29
P4.0/PM_UCB1STE/PM_UCA1CLK
P5.5/XOUT
9
28
DVCC2
MSP430F5304
PJ.0/TDO
PJ.1/TDI/TCLK
P2.0/TA1.1
P1.7/TA1.0
P1.6/TA1CLK/CBOUT
PJ.2/TMS
P1.5/TA0.4
25
12
13 14 15 16 17 18 19 20 21 22 23 24
P1.4/TA0.3
DVSS1
P1.3/TA0.2
PJ.3/TCK
P1.2/TA0.1
DVSS2
26
P1.1/TA0.0
27
11
P1.0/TA0CLK/ACLK
10
VCORE
AVSS1
DVCC1
NOTE: For RGZ package, connection of exposed thermal pad to VSS is recommended.
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Table 3. Terminal Functions
TERMINAL
NO.
NAME
I/O (1)
DESCRIPTION
RGZ,
RGC
ZQE
PT
P6.4/CB4/A4
5
N/A
C1
I/O
General-purpose digital I/O
Comparator_B input CB4 (not available on RGZ or PT package devices)
Analog input A4 – ADC (not available on RGZ or PT package devices)
P6.5/CB5/A5
6
N/A
D2
I/O
General-purpose digital I/O
Comparator_B input CB5 (not available on RGZ or PT package devices)
Analog input A5 – ADC (not available on RGZ or PT package devices)
P6.6/CB6/A6
7
N/A
D1
I/O
General-purpose digital I/O
Comparator_B input CB6 (not available on RGZ or PT package devices)
Analog input A6 – ADC (not available on RGZ or PT package devices)
P6.7/CB7/A7
8
N/A
D3
I/O
General-purpose digital I/O
Comparator_B input CB7 (not available on RGZ or PT package devices)
Analog input A7 – ADC (not available on RGZ or PT package devices)
P5.0/A8/VeREF+
9
5
E1
I/O
General-purpose digital I/O
Analog input A8 – ADC
Input for an external reference voltage to the ADC
P5.1/A9/VeREF-
10
6
E2
I/O
General-purpose digital I/O
Analog input A9 – ADC
Negative terminal for an externally provided ADC reference
AVCC1
11
7
F2
P5.4/XIN
12
8
F1
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
P5.5/XOUT
13
9
G1
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS1
14
10
G2
Analog ground supply
DVCC1
15
11
H1
Digital power supply
DVSS1
16
12
J1
Digital ground supply
17
13
J2
Regulated core power supply output (internal use only, no external current
loading)
P1.0/TA0CLK/ACLK
18
14
H2
I/O
General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0
19
15
H3
I/O
General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1
20
16
J3
I/O
General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2
21
17
G4
I/O
General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3
22
18
H4
I/O
General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4
23
19
J4
I/O
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT
24
20
G5
I/O
General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0
25
21
H5
I/O
General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1
26
22
J5
I/O
General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
VCORE
(1)
(2)
10
(2)
Analog power supply
I = input, O = output, N/A = not available
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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Table 3. Terminal Functions (continued)
TERMINAL
NO.
NAME
I/O (1)
DESCRIPTION
RGZ,
RGC
ZQE
PT
P2.1/TA1.2
27
N/A
G6
I/O
General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.2/TA2CLK/SMCLK
28
N/A
J6
I/O
General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input ; SMCLK output
P2.3/TA2.0
29
N/A
H6
I/O
General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
P2.4/TA2.1
30
N/A
J7
I/O
General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
P2.5/TA2.2
31
N/A
J8
I/O
General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
P2.6/RTCCLK/DMAE0
32
N/A
J9
I/O
General-purpose digital I/O with port interrupt
RTC clock output for calibration
DMA external trigger input
P2.7/UCB0STE/UCA0CLK
33
N/A
H7
I/O
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/UCB0SDA
34
N/A
H8
I/O
General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL
35
N/A
H9
I/O
General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE
36
N/A
G8
I/O
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/UCA0SIMO
37
N/A
G9
I/O
General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.4/UCA0RXD/UCA0SOMI
38
N/A
G7
I/O
General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.0/PM_UCB1STE/
PM_UCA1CLK
41
29
E8
P4.1/PM_UCB1SIMO/
PM_UCB1SDA
42
30
E7
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/
PM_UCB1SCL
43
31
D9
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
P4.3/PM_UCB1CLK/
PM_UCA1STE
44
32
DVSS2
39
27
F9
Digital ground supply
DVCC2
40
28
E9
Digital power supply
D7
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.4/PM_UCA1TXD/
PM_UCA1SIMO
45
33
D8
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I/O
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Table 3. Terminal Functions (continued)
TERMINAL
NO.
NAME
I/O (1)
DESCRIPTION
RGZ,
RGC
ZQE
PT
P4.5/PM_UCA1RXD/
PM_UCA1SOMI
46
34
C9
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE
47
35
C8
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: no secondary function.
P4.7/PM_NONE
48
36
C7
I/O
General-purpose digital I/O with reconfigurable port mapping secondary
function
Default mapping: no secondary function.
VSSU
49
37
B8,
B9
PU.0
50
38
A9
I/O
General-purpose digital I/O - controlled by PU control register
NC
51
39
B7
I/O
No connect.
PU.1
52
40
A8
I/O
General-purpose digital I/O - controlled by PU control register
LDOI
53
41
A7
LDO input
LDOO
54
42
A6
LDO output
NC
55
43
B6
No connect.
AVSS2
56
44
A5
Analog ground supply
P5.2/XT2IN
57
45
B5
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT
58
46
B4
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK
59
47
A4
I
PJ.0/TDO
60
23
C5
I/O
General-purpose digital I/O
Test data output port
PJ.1/TDI/TCLK
61
24
C4
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/TMS
62
25
A3
I/O
General-purpose digital I/O
Test mode select
PJ.3/TCK
63
26
B3
I/O
General-purpose digital I/O
Test clock
RST/NMI/SBWTDIO
64
48
A2
I/O
Reset input active low
Non-maskable interrupt input
Spy-bi-wire data input/output
P6.0/CB0/A0
1
1
A1
I/O
General-purpose digital I/O
Comparator_B input CB0 (not available on F5304 device)
Analog input A0 – ADC
P6.1/CB1/A1
2
2
B2
I/O
General-purpose digital I/O
Comparator_B input CB1 (not available on F5304 device)
Analog input A1 – ADC
P6.2/CB2/A2
3
3
B1
I/O
General-purpose digital I/O
Comparator_B input CB2 (not available on F5304 device)
Analog input A2 – ADC
P6.3/CB3/A3
4
4
C2
I/O
General-purpose digital I/O
Comparator_B input CB3 (not available on F5304 device)
Analog input A3 – ADC
Reserved
N/A
N/A
(3)
Thermal Pad
Pad
Pad
N/A
(3)
12
PU ground supply
Test mode pin – select digital I/O on JTAG pins
Spy-bi-wire input clock
Exposed thermal pad on QFN packages. Connection to VSS is recommended
(not available on PT package devices).
C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
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SHORT-FORM DESCRIPTION
CPU (Link to User's Guide)
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST/NMI, P1, and P2.
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
(Non)maskable
0FFFCh
62
(Non)maskable
0FFFAh
61
Maskable
0FFF8h
60
Maskable
0FFF6h
59
TB0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV) (1) (3)
Maskable
0FFF4h
58
Watchdog Timer_A Interval Timer
Mode
WDTIFG
Maskable
0FFF2h
57
Maskable
0FFF0h
56
Maskable
0FFEEh
55
Maskable
0FFECh
54
Maskable
0FFEAh
53
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Comp_B
INTERRUPT FLAG
WDTIFG, KEYV (SYSRSTIV)
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)
(1) (2)
Comparator B interrupt flags (CBIV)
TB0
TB0CCR0 CCIFG0
UCA0RXIFG, UCA0TXIFG (UCA0IV)
USCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (UCAB0IV)
ADC10IFG0
TA0
(1) (3)
(1) (3)
(1) (3) (4)
TA0CCR0 CCIFG0
(3)
TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFE8h
52
LDO-PWR
LDOOFFIG, LDOONIFG, LDOOVLIFG
Maskable
0FFE6h
51
Maskable
0FFE4h
50
Maskable
0FFE2h
49
Maskable
0FFE0h
48
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
TA1
TA1
TA1CCR0 CCIFG0
(1) (3)
(3)
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
(1) (3)
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
0FFDEh
47
USCI_A1 Receive or Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)
(1) (3)
Maskable
0FFDCh
46
USCI_B1 Receive or Transmit
UCB1RXIFG, UCB1TXIFG (UCB1IV)
(1) (3)
Maskable
0FFDAh
45
Maskable
0FFD8h
44
Maskable
0FFD6h
43
Maskable
0FFD4h
42
Maskable
0FFD2h
41
0FFD0h
40
TA2
TA2
I/O Port P2
RTC_A
TA2CCR0 CCIFG0
(3)
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1) (3)
P2IFG.0 to P2IFG.7 (P2IV)
(1) (3)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)
Reserved
(3)
(4)
(5)
(1) (3)
(3)
USCI_A0 Receive or Transmit
ADC10_A
(1)
(2)
(1) (2)
Reserved
(5)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Only on devices with ADC, otherwise reserved.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
Table 5. Memory Organization (1)
Memory (flash)
Main: interrupt vector
Main: code memory
RAM
Information memory
(flash)
Bootstrap loader (BSL)
memory (flash)
Peripherals
(1)
16
MSP430F5304
MSP430F5308
MSP430F5309
MSP430F5310
Total Size
8 KB
00FFFFh–00FF80h
00FFFFh-00E000h
16 KB
00FFFFh–00FF80h
00FFFFh-00C000h
24 KB
00FFFFh–00FF80h
00FFFFh-00A000h
32 KB
00FFFFh–00FF80h
00FFFFh-008000h
Sector 1
2 KB
0033FFh–002C00h
2 KB
0033FFh–002C00h
2 KB
0033FFh–002C00h
2 KB
0033FFh–002C00h
Sector 0
2 KB
002BFFh–002400h
2 KB
002BFFh–002400h
2 KB
002BFFh–002400h
2 KB
002BFFh–002400h
Sector 7
2 KB
0023FFh–001C00h
2 KB
0023FFh–001C00h
2 KB
0023FFh–001C00h
2 KB
0023FFh–001C00h
Info A
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
128 B
0019FFh–001980h
Info B
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
128 B
00197Fh–001900h
Info C
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info D
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
Size
N/A = Not available
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory via the BSL is protected by user-defined password. Use of the UART BSL requires external
access to the six pins shown in Table 6. For complete description of the features of the BSL and its
implementation, see MSP430 Programming Via the Bootstrap Loader (SLAU319).
Table 6. BSL Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.1
Data transmit
P1.2
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 8. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
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Flash Memory (Link to User's Guide)
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
RAM Memory (Link to User's Guide)
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.
• Each sector 0 to n can be completely disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Digital I/O (Link to User's Guide)
There are up to six 8-bit I/O ports implemented: For 64 pin options, P1, P2, P4, and P6 are complete, P5 is
reduced to 6-bit I/O, and P3 is reduced to 5-bit I/O. For 48 pin options, P6 is reduced to 4-bit I/O, P2 is reduced
to 1-bit I/O, and P3 is completely removed. Port PJ contains four individual I/O ports, common to all devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC).
Port Mapping Controller (Link to User's Guide)
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.
Table 9. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT0
-
Comparator_B output
PM_TB0CLK
TB0 clock input
PM_ADC10CLK
-
PM_DMAE0
DMAE0 input
1
2
PM_SVMOUT
-
PM_TB0OUTH
TB0 high impedance input TB0OUTH
4
PM_TB0CCR0A
TB0 CCR0 capture input CCI0A
TB0 CCR0 compare output Out0
5
PM_TB0CCR1A
TB0 CCR1 capture input CCI1A
TB0 CCR1 compare output Out1
6
PM_TB0CCR2A
TB0 CCR2 capture input CCI2A
TB0 CCR2 compare output Out2
7
PM_TB0CCR3A
TB0 CCR3 capture input CCI3A
TB0 CCR3 compare output Out3
3
18
ADC10CLK
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SVM output
Copyright © 2010–2012, Texas Instruments Incorporated
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Table 9. Port Mapping, Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
8
PM_TB0CCR4A
TB0 CCR4 capture input CCI4A
TB0 CCR4 compare output Out4
9
PM_TB0CCR5A
TB0 CCR5 capture input CCI5A
TB0 CCR5 compare output Out5
10
PM_TB0CCR6A
TB0 CCR6 capture input CCI6A
TB0 CCR6 compare output Out6
11
12
13
14
15
16
USCI_A1 UART RXD (Direction controlled by USCI - input)
PM_UCA1SOMI
USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD
USCI_A1 UART TXD (Direction controlled by USCI - output)
PM_UCA1SIMO
USCI_A1 SPI slave in master out (direction controlled by USCI)
PM_UCA1CLK
USCI_A1 clock input/output (direction controlled by USCI)
PM_UCB1STE
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
PM_UCB1SOMI
USCI_B1 SPI slave out master in (direction controlled by USCI)
PM_UCB1SCL
USCI_B1 I2C clock (open drain and direction controlled by USCI)
PM_UCB1SIMO
USCI_B1 SPI slave in master out (direction controlled by USCI)
PM_UCB1SDA
USCI_B1 I2C data (open drain and direction controlled by USCI)
PM_UCB1CLK
USCI_B1 clock input/output (direction controlled by USCI)
PM_UCA1STE
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17
PM_CBOUT1
None
Comparator_B output
18
PM_MCLK
None
MCLK
None
RTCCLK output
19
20
21
22
23
24
25
(1)
PM_UCA1RXD
PM_RTCCLK
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
26 - 30
Reserved
31 (0FFh) (1)
PM_ANALOG
None
DVSS
Disables the output driver as well as the input Schmitt-trigger to prevent
parasitic cross currents when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
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Table 10. Default Mapping
PIN
20
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P4.0/P4MAP0
PM_UCB1STE/PM_UCA1CLK
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.1/P4MAP1
PM_UCB1SIMO/PM_UCB1SDA
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.2/P4MAP2
PM_UCB1SOMI/PM_UCB1SCL
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
P4.3/P4MAP3
PM_UCB1CLK/PM_UCA1STE
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
P4.4/P4MAP4
PM_UCA1TXD/PM_UCA1SIMO
USCI_A1 UART TXD (Direction controlled by USCI - output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
P4.5/P4MAP5
PM_UCA1RXD/PM_UCA1SOMI
USCI_A1 UART RXD (Direction controlled by USCI - input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6
PM_NONE
None
DVSS
P4.7/P4MAP7
PM_NONE
None
DVSS
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Oscillator and System Clock (Link to User's Guide)
The clock system in the MSP430F530x family of devices is supported by the Unified Clock System (UCS)
module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode not supported),
an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO),
an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS
module is designed to meet the requirements of both low system cost and low power consumption. The UCS
module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally
controlled oscillator (DCO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM) (Link to User's Guide)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Hardware Multiplier (Link to User's Guide)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
Real-Time Clock (RTC_A) (Link to User's Guide)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated realtime clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that
can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode
integrates an internal calendar which compensates for months with less than 31 days and includes leap year
correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
Watchdog Timer (WDT_A) (Link to User's Guide)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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System Module (SYS) (Link to User's Guide)
The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap
loader entry mechanisms, as well as configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 11. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
SYSRSTIV, System Reset
019Eh
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
PMMSWBOR (BOR)
06h
Wakeup from LPMx.5
08h
SYSSNIV, System NMI
SYSUNIV, User NMI
22
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019Ch
019Ah
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
PMMSWPOR (POR)
14h
WDT timeout (PUC)
16h
WDT password violation (PUC)
18h
KEYV flash password violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM password violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
06h
SVSMHDLYIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
04h
ACCVIFG
06h
Reserved
08h
Reserved
0Ah to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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DMA Controller (Link to User's Guide)
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC10_A conversion register to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
Table 12. DMA Trigger Assignments
TRIGGER
CHANNEL
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
TA2CCR2 CCIFG
TA2CCR2 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
21
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
22
UCB1RXIFG
UCB1RXIFG
UCB1RXIFG
23
(1)
(2)
(1)
UCB1TXIFG
(2)
UCB1TXIFG
ADC10IFG0
(2)
UCB1TXIFG
24
ADC10IFG0
ADC10IFG0
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
reserved
reserved
reserved
(2)
28
reserved
reserved
reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
If a reserved trigger source is selected, no Trigger1 is generated.
Only on devices with ADC. Reserved on devices without ADC.
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Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C
Mode)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430F53xx series includes one or two complete USCI modules.
TA0 (Link to User's Guide)
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 13. TA0 Signal Connections
INPUT PIN NUMBER
RGC, ZQE
RGZ, PT
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
18, H2-P1.0
14-P1.0
TA0CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
18, H2-P1.0
14-P1.0
TA0CLK
TACLK
19, H3-P1.1
15-P1.1
TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
20, J3-P1.2
21, G4-P1.3
22, H4-P1.4
23, J4-P1.5
(1)
24
16-P1.2
17-P1.3
18-P1.4
19-P1.5
DVCC
VCC
TA0.1
CCI1A
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
TA0
OUTPUT PIN NUMBER
RGC, ZQE
RGZ, PT
19, H3-P1.1
15-P1.1
TA0.0
20, J3-P1.2
16-P1.2
ADC10 (internal)
ADC10 (internal)
ADC10SHSx =
{1}
ADC10SHSx =
{1}
21, G4-P1.3
17-P1.3
22, H4-P1.4
18-P1.4
23, J4-P1.5
19-P1.5
(1)
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA0.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
TA0.3
CCI3A
DVSS
CCI3B
DVSS
GND
DVCC
VCC
TA0.4
CCI4A
DVSS
CCI4B
DVSS
GND
DVCC
VCC
CCR1
CCR2
CCR3
CCR4
TA1
TA2
TA3
TA4
TA0.1
(1)
TA0.2
TA0.3
TA0.4
Only on devices with ADC.
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TA1 (Link to User's Guide)
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 14. TA1 Signal Connections
INPUT PIN NUMBER
RGC, ZQE
RGZ, PT
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
24, G5-P1.6
20-P1.6
TA1CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
24, G5-P1.6
20-P1.6
TA1CLK
TACLK
25, H5-P1.7
21-P1.7
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
26, J5-P2.0
27, G6-P2.1
22-P2.0
DVCC
VCC
TA1.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
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MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
TA0
TA1
OUTPUT PIN NUMBER
RGC, ZQE
RGZ, PT
25, H5-P1.7
21-P1.7
26, J5-P2.0
22-P2.0
TA1.0
TA1.1
27, G6-P2.1
CCR2
TA2
TA1.2
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TA2 (Link to User's Guide)
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 15. TA2 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
TA2CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
28, J6-P2.2
TA2CLK
TACLK
29, H6-P2.3
TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
RGC, ZQE
28, J6-P2.2
30, J7-P2.4
31, J8-P2.5
26
RGZ, PT
DVCC
VCC
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
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BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
OUTPUT PIN NUMBER
RGC, ZQE
RGZ, PT
29, H6-P2.3
CCR0
TA0
TA2.0
30, J7-P2.4
CCR1
TA1
TA2.1
31, J8-P2.5
CCR2
TA2
TA2.2
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TB0 (Link to User's Guide)
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 16. TB0 Signal Connections
INPUT PIN NUMBER
RGC, ZQE
(1)
(2)
(1)
RGZ, PT
(1)
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
TB0CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
TB0CLK
TBCLK
TB0.0
CCI0A
TB0.0
CCI0B
DVSS
GND
DVCC
VCC
TB0.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TB0.2
CCI2A
TB0.2
CCI2B
DVSS
GND
DVCC
VCC
TB0.3
CCI3A
TB0.3
CCI3B
DVSS
GND
DVCC
VCC
TB0.4
CCI4A
TB0.4
CCI4B
DVSS
GND
DVCC
VCC
TB0.5
CCI5A
TB0.5
CCI5B
DVSS
GND
DVCC
VCC
TB0.6
CCI6A
ACLK
(internal)
CCI6B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
TB0
TB0.0
CCR1
TB1
TB0.1
CCR2
TB2
TB0.2
CCR3
TB3
TB0.3
CCR4
TB4
TB0.4
CCR5
TB5
TB0.5
CCR6
TB6
TB0.6
OUTPUT PIN NUMBER
RGC, ZQE (1)
RGZ, PT (1)
ADC10
(internal) (2)
ADC10SHSx =
{2}
ADC10
(internal) (2)
ADC10SHSx =
{2}
ADC10 (internal)
ADC10SHSx =
{3}
ADC10 (internal)
ADC10SHSx =
{3}
Timer functions selectable via the port mapping controller.
Only on devices with ADC.
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Comparator_B (Link to User's Guide)
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
ADC10_A (Link to User's Guide)
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and a conversion result buffer. A window comparator with a
lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags.
CRC16 (Link to User's Guide)
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
REF Voltage Reference (Link to User's Guide)
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
LDO and Port U
The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire
MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.
Alternatively, the power system can supply power only to other components within the system, or it can be
unused altogether. The Port U Pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These
pins can only be configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If
the 3.3-V LDO is not being used in the system (disabled), the LDOO pin can be supplied externally.
Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM
implemented on all devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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Peripheral File Map
Table 17. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 18)
0100h
000h-01Fh
PMM (see Table 19)
0120h
000h-01Fh
Flash Control (see Table 20)
0140h
000h-00Fh
CRC16 (see Table 21)
0150h
000h-007h
RAM Control (see Table 22)
0158h
000h-001h
Watchdog (see Table 23)
015Ch
000h-001h
UCS (see Table 24)
0160h
000h-01Fh
SYS (see Table 25)
0180h
000h-01Fh
Shared Reference (see Table 26)
01B0h
000h-001h
Port Mapping Control (see Table 27)
01C0h
000h-002h
Port Mapping Port P4 (see Table 27)
01E0h
000h-007h
Port P1/P2 (see Table 28)
0200h
000h-01Fh
Port P3/P4 (see Table 29)
0220h
000h-00Bh
Port P5/P6 (see Table 30)
0240h
000h-00Bh
Port PJ (see Table 31)
0320h
000h-01Fh
TA0 (see Table 32)
0340h
000h-02Eh
TA1 (see Table 33)
0380h
000h-02Eh
TB0 (see Table 34)
03C0h
000h-02Eh
TA2 (see Table 35)
0400h
000h-02Eh
Real-Time Clock (RTC_A) (see Table 36)
04A0h
000h-01Bh
32-bit Hardware Multiplier (see Table 37)
04C0h
000h-02Fh
DMA General Control (see Table 38)
0500h
000h-00Fh
DMA Channel 0 (see Table 38)
0510h
000h-00Ah
DMA Channel 1 (see Table 38)
0520h
000h-00Ah
DMA Channel 2 (see Table 38)
0530h
000h-00Ah
USCI_A0 (see Table 39)
05C0h
000h-01Fh
USCI_B0 (see Table 40)
05E0h
000h-01Fh
USCI_A1 (see Table 41)
0600h
000h-01Fh
USCI_B1 (see Table 42)
0620h
000h-01Fh
ADC10_A (see Table 43)
0740h
000h-01Fh
Comparator_B (see Table 44)
08C0h
000h-00Fh
LDO-PWR and Port U configuration (see Table 45)
0900h
000h-014h
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Table 18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM Power mode 5 control
PMM5CTL
10h
Table 20. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 22. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 23. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 24. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
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Table 25. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootstrap loader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 26. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 27. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password register
PMAPPWD
00h
Port mapping control register
PMAPCTL
02h
Port P4.0 mapping register
P4MAP0
00h
Port P4.1 mapping register
P4MAP1
01h
Port P4.2 mapping register
P4MAP2
02h
Port P4.3 mapping register
P4MAP3
03h
Port P4.4 mapping register
P4MAP4
04h
Port P4.5 mapping register
P4MAP5
05h
Port P4.6 mapping register
P4MAP6
06h
Port P4.7 mapping register
P4MAP7
07h
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Table 28. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 29. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
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Table 30. Port P5/P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 31. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Table 32. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 3
TA0CCR3
18h
Capture/compare register 4
TA0CCR4
1Ah
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
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Table 33. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 34. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 register
TB0R
10h
Capture/compare register 0
TB0CCR0
12h
Capture/compare register 1
TB0CCR1
14h
Capture/compare register 2
TB0CCR2
16h
Capture/compare register 3
TB0CCR3
18h
Capture/compare register 4
TB0CCR4
1Ah
Capture/compare register 5
TB0CCR5
1Ch
Capture/compare register 6
TB0CCR6
1Eh
TB0 expansion register 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Table 35. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
Capture/compare control 2
TA2CCTL2
06h
TA2 counter register
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
Capture/compare register 2
TA2CCR2
16h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
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Table 36. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter register 1
RTCSEC/RTCNT1
10h
RTC minutes/counter register 2
RTCMIN/RTCNT2
11h
RTC hours/counter register 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter register 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
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Table 37. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
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Table 38. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Ah
Table 39. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA0CTL1
00h
USCI control 1
UCA0CTL0
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
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Table 40. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB0CTL1
00h
USCI synchronous control 1
UCB0CTL0
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Table 41. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA1CTL1
00h
USCI control 1
UCA1CTL0
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
UCA1MCTL
08h
USCI status
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
UCA1IE
1Ch
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt vector word
UCA1IV
1Eh
Table 42. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB1CTL1
00h
USCI synchronous control 1
UCB1CTL0
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
USCI interrupt enable
UCB1IE
1Ch
USCI interrupt flags
UCB1IFG
1Dh
USCI interrupt vector word
UCB1IV
1Eh
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Table 43. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A Control register 0
ADC10CTL0
00h
ADC10_A Control register 1
ADC10CTL1
02h
ADC10_A Control register 2
ADC10CTL2
04h
ADC10_A Window Comparator Low Threshold
ADC10LO
06h
ADC10_A Window Comparator High Threshold
ADC10HI
08h
ADC10_A Memory Control Register 0
ADC10MCTL0
0Ah
ADC10_A Conversion Memory Register
ADC10MEM0
12h
ADC10_A Interrupt Enable
ADC10IE
1Ah
ADC10_A Interrupt Flags
ADC10IGH
1Ch
ADC10_A Interrupt Vector Word
ADC10IV
1Eh
Table 44. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control register 0
CBCTL0
00h
Comp_B control register 1
CBCTL1
02h
Comp_B control register 2
CBCTL2
04h
Comp_B control register 3
CBCTL3
06h
Comp_B interrupt register
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 45. LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LDO key/ID register
LDOKEYPID
00h
PU port control
PUCTL
04h
LDO power control
LDOPWRCTL
08h
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE, LDOI)
(2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
±2 mA
(3)
–55°C to 150°C
Maximum junction temperature, TJ
(1)
(2)
(3)
95°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
(1)
PARAMETER
θJA
Junction-to-ambient thermal resistance, still air
θJC(TOP)
θJC(BOTTOM)
θJB
(1)
(2)
(3)
(4)
(5)
40
Junction-to-case (top) thermal resistance
(5)
(2)
(3)
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
VALUE
(4)
VQFN (RGC)
30
VQFN (RGZ)
28.6
LQFP (PT)
62.8
BGA (ZQE)
55.5
VQFN (RGC)
15.6
VQFN (RGZ)
14.4
LQFP (PT)
18.2
BGA (ZQE)
21.2
VQFN (RGC)
1.6
VQFN (RGZ)
1.6
LQFP (PT)
N/A
BGA (ZQE)
N/A
VQFN (RGC)
8.9
VQFN (RGZ)
5.5
LQFP (PT)
28.3
BGA (ZQE)
19.3
UNIT
°C/W
°C/W
°C/W
°C/W
N/A = not applicable
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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Recommended Operating Conditions
MIN
V
PMMCOREVx = 0, 1
2.0
3.6
V
PMMCOREVx = 0, 1, 2
2.2
3.6
V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
V
85
°C
VSS
Supply voltage (AVSS = DVSS1/2 = DVSS)
TA
Operating free-air temperature
I version
–40
TJ
Operating junction temperature
I version
-40
CVCORE
Capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
(2)
(3)
UNIT
3.6
Supply voltage during program execution and flash
programming(AVCC = DVCC1/2 = DVCC) (1) (2)
(1)
MAX
1.8
VCC
fSYSTEM
NOM
PMMCOREVx = 0
0
V
85
470
°C
nF
10
Processor frequency (maximum MCLK frequency)
Figure 1)
(3)
(see
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
25.0
MHz
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 1. Maximum System Frequency
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)
(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
IAM,
IAM,
(1)
(2)
(3)
42
Flash
RAM
EXECUTION
MEMORY
Flash
RAM
VCC
3V
3V
PMMCOREVx
1 MHz
8 MHz
12 MHz
TYP
MAX
1.74
2.58
2.78
1.91
20 MHz
TYP
MAX
TYP
MAX
0
0.25
0.27
1.55
1.68
1
0.28
2
0.30
3
0.32
0
0.17
1
0.19
1.03
1.54
2
0.20
1.16
1.73
2.84
3
0.21
1.24
1.87
3.1
2.09
0.19
0.91
TYP
MAX
2.84
4.68
5.06
3.10
5.13
25 MHz
TYP
UNIT
MAX
mA
6.0
6.5
1.00
1.67
mA
3.11
3.9
4.3
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing. LDO disabled (LDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
LPM0,1MHz
Low-power mode 0
(3) (4)
ILPM2
Low-power mode 2
(5) (4)
ILPM4
0
73
77
85
80
80
97
3V
3
79
83
92
88
95
105
2.2 V
0
6.5
6.5
8
7.5
8
11
3V
3
7.0
7.0
9
7.9
8.9
13
0
1.60
1.90
2.6
3.4
1
1.65
2.00
2.7
3.6
2
1.75
2.15
2.9
3.8
0
1.8
2.1
2.8
3.6
1
1.9
2.3
2.9
3.8
2
2.0
2.4
3.0
4.0
3
2.0
2.5
3.0
3.1
4.0
6.5
0
1.1
1.3
1.8
1.9
2.7
5.0
1
1.1
1.4
2.0
2.8
2
1.2
1.5
2.1
2.9
3
1.3
1.5
2.0
2.2
3.0
5.5
0
0.9
1.1
1.5
1.8
2.5
4.8
1
1.1
1.2
2.0
2.6
2
1.2
1.2
2.1
2.7
3
1.3
1.3
1.6
2.2
2.8
5.0
ILPM4.5
0.15
0.18
0.35
0.26
0.45
0.8
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
3V
Low-power mode 4 (8) (4)
Low-power mode 4.5
(9)
85°C
2.2 V
Low-power mode 3,
crystal mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
60°C
PMMCOREVx
3V
ILPM3,VLO
25°C
VCC
2.2 V
ILPM3,XT1LF
-40°C
(1) (2)
3V
3V
TYP
MAX
TYP
MAX
2.6
TYP
MAX
TYP
MAX
6.0
UNIT
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
LDO disabled (LDOEN = 0).
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
LDO disabled (LDOEN = 0)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
LDO disabled (LDOEN = 0)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
LDO disabled (LDOEN = 0)
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
LDO disabled (LDOEN = 0)
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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Schmitt-Trigger Inputs – General Purpose I/O (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
TYP
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.85
3V
0.4
1.0
20
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
External interrupt timing
(2)
TEST CONDITIONS
VCC
Port P1, P2: P1.x to P2.x, External trigger pulse width to
set interrupt flag
2.2 V, 3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
1.8 V, 3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA
VOH
High-level output voltage
I(OHmax) = –10 mA
I(OHmax) = –5 mA
OL
Low-level output voltage
(2)
44
(2)
3V
(2)
1.8 V
(1)
I(OLmax) = 15 mA
(1)
1.8 V
(1)
I(OLmax) = 10 mA
I(OLmax) = 5 mA
(2)
(1)
I(OHmax) = –15 mA
I(OLmax) = 3 mA
VCC
(1)
(2)
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
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Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
(1)
(2)
(3)
TEST CONDITIONS
Low-level output voltage
I(OHmax) = –1 mA
(2)
I(OHmax) = –3 mA
(3)
I(OHmax) = –2 mA
(2)
I(OHmax) = –6 mA
(3)
I(OLmax) = 1 mA
(2)
I(OLmax) = 3 mA
(3)
I(OLmax) = 2 mA
(2)
I(OLmax) = 6 mA
(3)
VCC
1.8 V
3V
(1)
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
1.8 V
3V
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1) (2)
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
Clock output frequency
ACLK
SMCLK
MCLK
CL = 20 pF
(2)
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 3
25
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 3
25
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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MSP430F530x, MSP430F5310
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Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
8.0
VCC = 3.0 V
Px.y
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
TA = 85°C
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.0
3.5
1.0
1.5
Figure 2.
Figure 3.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
IOH – Typical High-Level Output Current – mA
VCC = 3.0 V
Px.y
-5.0
-10.0
-15.0
TA = 85°C
-20.0
2.0
0.0
0.0
IOH – Typical High-Level Output Current – mA
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
TA = 25°C
VCC = 1.8 V
Px.y
-1.0
-2.0
-3.0
-4.0
TA = 85°C
-5.0
-6.0
TA = 25°C
-7.0
-8.0
-25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 4.
46
TA = 25°C
VCC = 1.8 V
Px.y
7.0
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3.5
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
2.0
Figure 5.
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Crystal Oscillator, XT1, Low-Frequency Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1
CL,eff
fFault,LF
tSTART,LF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(2) (3)
32.768
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Oscillator fault frequency,
LF mode (7)
XTS = 0
(8)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C,
CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C,
CL,eff = 12 pF
µA
Hz
50
kHz
2
XTS = 0, XCAPx = 1
Duty cycle, LF mode
UNIT
kΩ
(6)
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Startup time, LF mode
10
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, XCAPx = 0
Integrated effective load
capacitance, LF mode (5)
0.170
32768
XTS = 0, XT1BYPASS = 0
OALF
3V
0.290
XT1 oscillator crystal frequency,
LF mode
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals (4)
TYP
pF
30
70
%
10
10000
Hz
1000
3V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C
IDVCC.XT2
XT2 oscillator crystal current
consumption
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25°C
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C
(1) (2)
TYP
MAX
UNIT
200
260
3V
µA
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C
450
fXT2,HF0
XT2 oscillator crystal
frequency, mode 0
XT2DRIVEx = 0, XT2BYPASS = 0
(3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal
frequency, mode 1
XT2DRIVEx = 1, XT2BYPASS = 0
(3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal
frequency, mode 2
XT2DRIVEx = 2, XT2BYPASS = 0
(3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal
frequency, mode 3
XT2DRIVEx = 3, XT2BYPASS = 0
(3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level
square-wave input frequency,
bypass mode
XT2BYPASS = 1
0.7
32
MHz
Oscillation allowance for
HF crystals (5)
OAHF
tSTART,HF
CL,eff
Startup time
Integrated effective load
capacitance, HF mode (6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
48
Oscillator fault frequency
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Ω
3V
ms
0.3
1
(1)
Duty cycle
fFault,HF
(4) (3)
(7)
Measured at ACLK, fXT2,HF2 = 20 MHz
40
(8)
30
XT2BYPASS = 1
50
pF
60
%
300
kHz
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-Trigger Inputs section of this datasheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
Measured at ACLK (2)
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
MIN
TYP
MAX
6
9.4
14
0.5
kHz
%/°C
4
40
UNIT
%/V
50
60
TYP
MAX
%
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MIN
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
3
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Full temperature range
1.8 V to 3.6 V
±3.5
3V
±1.5
REFO absolute tolerance calibrated
TA = 25°C
UNIT
µA
Hz
%
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO startup time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
(1)
(2)
40
50
60
25
%
µs
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
dfDCO/dT
dfDCO/dVCC
(1)
(2)
DCO frequency temperature drift
(1)
DCO frequency voltage drift
(2)
40
50
60
%
fDCO = 1 MHz,
0.1
%/°C
fDCO = 1 MHz
1.9
%/V
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 6. Typical DCO frequency
50
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PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage,
DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage,
DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
Pulse duration required at RST/NMI
pin to accept a reset
MIN
0.80
TYP
1.30
60
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.80
V
VCORE1(AM)
Core voltage, active mode,
PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.60
V
VCORE0(AM)
Core voltage, active mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.40
V
VCORE3(LPM)
Core voltage, low-current mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE2(LPM)
Core voltage, low-current mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.84
V
VCORE1(LPM)
Core voltage, low-current mode,
PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.64
V
VCORE0(LPM)
Core voltage, low-current mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.44
V
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PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
tpd(SVSH)
t(SVSH)
52
SVSH off voltage level (1)
SVSH propagation delay
SVSH on or off delay time
dVDVCC/dt
(1)
SVSH on voltage level (1)
DVCC rise time
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.57
1.68
1.78
SVSHE = 1, SVSHRVL = 1
1.79
1.88
1.98
SVSHE = 1, SVSHRVL = 2
1.98
2.08
2.21
SVSHE = 1, SVSHRVL = 3
2.10
2.18
2.31
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.85
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.07
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.28
SVSHE = 1, SVSMHRRL = 3
2.20
2.30
2.42
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.55
SVSHE = 1, SVSMHRRL = 5
2.52
2.70
2.88
SVSHE = 1, SVSMHRRL = 6
2.90
3.10
3.23
SVSHE = 1, SVSMHRRL = 7
2.90
3.10
3.23
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
20
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
SVSHE = 0 → 1
SVSHFP = 1
12.5
SVSHE = 0 → 1
SVSHFP = 0
100
µs
0
1000
V/s
The SVSH settings that are available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for recommended settings and use.
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PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
0
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
V(SVMH)
SVMH on or off voltage level
1.5
tpd(SVMH)
t(SVMH)
(1)
SVMH propagation delay
SVMH on or off delay time
µA
SVMHE = 1, SVSMHRRL = 0
1.62
1.74
1.85
SVMHE = 1, SVSMHRRL = 1
1.88
1.94
2.07
SVMHE = 1, SVSMHRRL = 2
2.07
2.14
2.28
SVMHE = 1, SVSMHRRL = 3
2.20
2.30
2.42
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.55
SVMHE = 1, SVSMHRRL = 5
2.52
2.70
2.88
SVMHE = 1, SVSMHRRL = 6
2.90
3.10
3.23
SVMHE = 1, SVSMHRRL = 7
2.90
3.10
3.23
SVMHE = 1, SVMHOVPE = 1
UNIT
nA
200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
(1)
MAX
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
20
µs
SVMHE = 0 → 1
SVMHFP = 1
12.5
SVMHE = 0 → 1
SVMHFP = 0
100
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
tpd(SVSL)
t(SVSL)
SVSL current consumption
SVSL propagation delay
SVSL on or off delay time
TYP
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
2.0
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
UNIT
nA
µA
µs
SVSLE = 0 → 1
SVSLFP = 1
12.5
SVSLE = 0 → 1
SVSLFP = 0
100
µs
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on or off delay time
Copyright © 2010–2012, Texas Instruments Incorporated
TYP
MAX
0
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0 → 1, SVMLFP = 1
12.5
SVMLE = 0 → 1, SVMLFP = 0
100
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UNIT
nA
µA
µs
µs
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Wake-Up from Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tWAKE-UP-FAST
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode (2)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-LPM5
tWAKE-UP-RESET
(1)
(2)
(3)
MIN
TYP
MAX
fMCLK ≥ 4.0 MHz
5
fMCLK < 4.0 MHz
6
UNIT
µs
150
165
µs
Wake-up time from LPM4.5
to active mode (3)
2
3
ms
Wake-up time from RST or
BOR event to active mode (3)
2
3
ms
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
This value represents the time from the wakeup event to the reset vector execution.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V, 3 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ± 10%
1.8 V, 3 V
tTB,cap
Timer_B capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V, 3 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
USCI (UART Mode) Recommended Operating Conditions
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
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CONDITIONS
Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
VCC
MIN
TYP
MAX
UNIT
fSYSTEM
MHz
1
MHz
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tτ
(1)
UART receive deglitch time
TEST CONDITIONS
(1)
VCC
MIN
TYP
MAX
2.2 V
50
600
3V
50
600
UNIT
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
fUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
USCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
MAX
UNIT
fSYSTEM
MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 7 and Figure 8)
PARAMETER
fUSCI
TEST CONDITIONS
USCI input clock frequency
PMMCOREV = 0
tSU,MI
SOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,MI
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
SIMO output data valid time
SIMO output data hold time
(2)
(2)
(3)
1.8 V
55
3V
38
2.4 V
30
3V
25
1.8 V
0
3V
0
2.4 V
0
3V
0
TYP
ns
ns
ns
ns
1.8 V
20
3V
18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
16
3V
15
(3)
CL = 20 pF, PMMCOREV = 3
(1)
MIN
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 0
tHD,MO
VCC
SMCLK, ACLK
Duty cycle = 50% ± 10%
1.8 V
-10
3V
-8
2.4 V
-10
3V
-8
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 7 and Figure 8.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 7
and Figure 8.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 7. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 8. SPI Master Mode, CKPH = 1
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USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1), Figure 9 and Figure 10)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, Last clock to STE high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
tHD,SO
(1)
(2)
(3)
SOMI output data valid time
SOMI output data hold time
(2)
(3)
VCC
MIN
1.8 V
11
3V
8
2.4 V
7
3V
6
1.8 V
3
3V
3
2.4 V
3
3V
3
TYP
MAX
ns
ns
ns
ns
1.8 V
66
3V
50
2.4 V
36
3V
30
1.8 V
30
3V
23
2.4 V
16
3V
13
1.8 V
5
3V
5
2.4 V
2
3V
2
1.8 V
5
3V
5
2.4 V
5
3V
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 0
1.8 V
76
3V
60
UCLK edge to SOMI valid,
CL = 20 pF
PMMCOREV = 3
2.4 V
44
3V
40
CL = 20 pF
PMMCOREV = 0
1.8 V
18
3V
12
CL = 20 pF
PMMCOREV = 3
2.4 V
10
3V
8
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 7 and Figure 8.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 7
and Figure 8.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 9. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 10. SPI Slave Mode, CKPH = 1
58
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 11)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STO
Setup time for STOP
tSP
Pulse duration of spikes suppressed by input
filter
fSCL > 100 kHz
tSU,STA
tHD,STA
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 11. I2C Mode Timing
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10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog supply voltage
V(Ax)
Analog input voltage range
TEST CONDITIONS
VCC
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
(2)
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
P3.7 terminals
Operating supply current into
AVCC terminal. REF module
and reference buffer off.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 00
Operating supply current into
AVCC terminal. REF module
on, reference buffer on.
MIN
(1)
TYP
MAX
UNIT
1.8
3.6
V
0
AVCC
V
2.2 V
60
100
3V
75
110
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 01
3V
113
150
µA
Operating supply current into
AVCC terminal. REF module
off, reference buffer on.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 10, VEREF = 2.5 V
3V
105
140
µA
Operating supply current into
AVCC terminal. REF module
off, reference buffer off.
fADC10CLK = 5 MHz, ADC10ON = 1, REFON =
0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 11, VEREF = 2.5 V
3V
70
110
µA
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad.
2.2 V
3.5
RI
Input MUX ON resistance
IADC10_A
(1)
(2)
µA
pF
AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC
36
1.8 V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC
96
kΩ
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ().
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A linearity
parameters
2.2 V, 3 V
0.45
5
5.5
MHz
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.2
4.8
5.4
MHz
2.2 V, 3 V
2.4
Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
µs
External fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSEL ≠ 0
tADC10ON
Turn on settling time of
the ADC
tSample
Sampling time
(1)
(2)
(3)
(4)
60
See
3.0
(2)
(3)
100
ns
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF
(4)
1.8 V
3
µs
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF
(4)
3V
1
µs
The ADC10OSC is sourced directly from MODOSC inside the UCS.
12 × ADC10DIV × 1/fADC10CLK
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB
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10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral
linearity error
1.4 V ≤ (VeREF+ – VeREF–)min ≤ 1.6 V
ED
Differential
linearity error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
EO
Offset error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
Internal impedance of source RS < 100 Ω, CVeREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
EG
Gain error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
ET
Total unadjusted
error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V
±2.0
LSB
MAX
UNIT
1.4
AVCC
V
0
1.2
V
1.4
AVCC
V
1.6 V < (VeREF+ – VeREF–)min ≤ VAVCC
±1.0
2.2 V, 3 V
±1.0
±1.0
LSB
REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VeREF+
Positive external
reference voltage input
VeREF+ > VeREF– (2)
VeREF–
Negative external
reference voltage input
VeREF+ > VeREF–
(VeREF+ –
VeREF–)
Differential external
reference voltage input
VeREF+ > VeREF– (4)
IVeREF+
IVeREF–
CVREF+/(1)
(2)
(3)
(4)
(5)
Static input current
Capacitance at VeREF+/terminal
(3)
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
1.4 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
(5)
VCC
MIN
(1)
TYP
±8.5
±26
2.2 V, 3 V
µA
±1
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
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REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage
VREF+
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal (2)
IREF+
TEST CONDITIONS
VCC
MIN
(1)
TYP
MAX
REFVSEL = {2} for 2.5 V,
REFON = 1
3V
2.51
±1.5%
REFVSEL = {1} for 2.0 V,
REFON = 1
3V
1.99
±1.5%
REFVSEL = {0} for 1.5 V,
REFON = 1
2.2 V, 3 V
UNIT
V
1.5 ±1.5%
REFVSEL = {0} for 1.5 V
2.2
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
V
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3V
18
24
µA
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
3V
15.5
21
µA
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5V
3V
13.5
21
µA
30
50
ppm/
°C
TCREF+
Temperature coefficient of
built-in reference (3)
IVREF+ = 0 A,
REFVSEL = (0, 1, 2}, REFON = 1
ISENSOR
Operating supply current
into AVCC terminal (4)
REFON = 0, INCH = 0Ah,
ADC10ON = N A, TA = 30°C
2.2 V
20
22
3V
20
22
VSENSOR
See
ADC10ON = 1, INCH = 0Ah,
TA = 30°C
2.2 V
770
3V
770
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is approximately 0.5 × VAVCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tSENSOR(sample)
Sample time required if
channel 10 is selected (6)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
µs
tVMID(sample)
Sample time required if
channel 11 is selected (7)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
1
µs
PSRR_DC
Power supply rejection ratio
(dc)
AVCC = AVCC (min) - AVCC(max),
TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1
120
µV/V
PSRR_AC
Power supply rejection ratio
(ac)
AVCC = AVCC (min) - AVCC(max),
TA = 25 °C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = {0, 1, 2}, REFON = 1
6.4
mV/V
tSETTLE
Settling time of reference
voltage (8)
AVCC = AVCC (min) - AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
75
µs
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
62
(5)
µA
mV
V
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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Comparator B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
IAVCC_COMP
IAVCC_REF
CBPWRMD = 00, CBON = 1, CBRSx = 00
Comparator operating
supply current into AVCC.
Excludes reference
CBPWRMD = 01, CBON = 1, CBRSx = 00
resistor ladder.
Quiescent current of
resistor ladder into AVCC.
Including REF module
current.
VIC
Common mode input
range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
tPD
tPD,filter
tEN_CMP
Series input resistance
Propagation delay,
response time
Propagation delay with
filter active
Comparator enable time
MAX
UNIT
V
40
2.2 V
30
50
3V
40
65
2.2 V,
3V
10
17
CBPWRMD = 10, CBON = 1, CBRSx = 00
2.2 V,
3V
0.1
0.5
CBREFACC = 0, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V,
3V
10
17
µA
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V,
3V
22
µA
VCC-1
V
µA
0
CBPWRMD = 00
CBPWRMD = 01, 10
±20
mV
±10
mV
4
kΩ
5
ON - switch closed
OFF - switch opened
3
pF
50
MΩ
CBPWRMD = 00, CBF = 0
450
ns
CBPWRMD = 01, CBF = 0
600
ns
CBPWRMD = 10, CBF = 0
50
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.35
0.6
1.0
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
0.6
1.0
1.8
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
1.0
1.8
3.4
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
1.8
3.4
6.5
µs
1
2
µs
1.5
µs
1
1.5
µs
VIN ×
(n+1)
/32
VIN ×
(n+1.5)
/32
V
CBON = 0 to CBON = 1
CBPWRMD = 00, 01
CBON = 0 to CBON = 1
CBPWRMD = 10
tEN_REF
Resistor reference enable
CBON = 0 to CBON = 1
time
VCB_REF
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
Copyright © 2010–2012, Texas Instruments Incorporated
VIN ×
(n+0.5)
/32
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Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VLDOO = 3.3 V ± 10%, IOH = -25 mA.
See Figure 13 for typical
characteristics.
VOL
Low-level output voltage
VLDOO = 3.3 V ± 10%, IOL = 25 mA.
See Figure 12 for typical
characteristics.
VIH
High-level input voltage
VLDOO = 3.3 V ± 10%
See Figure 14 for typical
characteristics.
VIL
Low-level input voltage
VLDOO = 3.3 V ± 10%
See Figure 14 for typical
characteristics.
64
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VCC
MIN
TYP
MAX
2.4
UNIT
V
0.4
2.0
V
V
0.8
V
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
90
VCC = 3.0 V
TA = 25 ºC
IOL - Typical Low-Level Output Current - mA
80
VCC = 3.0 V
TA = 85 ºC
VCC = 1.8 V
TA = 25 ºC
70
60
50
VCC = 1.8 V
TA = 85 ºC
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VOL - Low-Level Output Voltage - V
Figure 12. Ports PU.0, PU.1 Typical Low-Level Output Characteristics
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
IOH - Typical High-Level Output Current - mA
-10
-20
-30
VCC = 1.8 V
TA = 85 ºC
-40
-50
VCC = 3.0 V
TA = 85 ºC
-60
VCC = 1.8 V
TA = 25 ºC
-70
VCC = 3.0 V
TA = 25 ºC
-80
-90
0.5
1
1.5
2
2.5
3
VOH - High-Level Output Voltage - V
Figure 13. Ports PU.0, PU.1 Typical High-Level Output Characteristics
TYPICAL PU.0, PU.1 INPUT THRESHOLD
2.0
T A = 25 °C, 85 °C
1.8
VIT+ , postive-going input threshold
Input Threshold - V
1.6
1.4
1.2
VIT- , negative-going input threshold
1.0
0.8
0.6
0.4
0.2
0.0
1.8
2.2
2.6
3
3.4
LDOO Supply Voltage, VLDOO - V
Figure 14. Ports PU.0, PU.1 Typical Input Threshold Characteristics
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LDO-PWR (LDO Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VLAUNCH
LDO input detection threshold
VLDOI
LDO input voltage
VLDO
LDO output voltage
VLDO_EXT
LDOO terminal input voltage with
LDO disabled
LDO disabled
ILDOO
Maximum external current from
LDOO terminal
LDO is on
VCC
TYP
3.76
3.3
1.8
LDO current overload detection
IDET
MIN
60
(1)
MAX
UNIT
3.75
V
5.5
V
±9%
V
3.6
V
20
mA
100
mA
CLDOI
LDOI terminal recommended
capacitance
4.7
µF
CLDOO
LDOO terminal recommended
capacitance
220
nF
tENABLE
Settling time VLDO
(1)
Within 2%, recommended
capacitances
2
ms
A current overload will be detected when the total current supplied from the LDO exceeds this value.
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
tREADMARGIN
Read access time during margin mode
IPGM
Supply current from DVCC during program
IERASE
Supply current from DVCC during erase
IMERASE, IBANK
Supply current from DVCC during mass erase or bank erase
tCPT
Cumulative program time
MIN
TYP
1.8
See
Program and erase endurance
10
UNIT
3.6
V
200
ns
3
5
mA
2
6.5
mA
2.5
mA
16
ms
(1)
4
MAX
5
10
cycles
tRetention
Data retention duration
TJ = 25°C
100
tWord
Word or byte program time
See
(2)
64
85
years
µs
0
Block program time for first byte or word
See
(2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
tBlock,
N
Block program time for last byte or word
See
(2)
55
73
µs
Erase time for segment, mass erase, and bank erase when
available.
See
(2)
23
32
ms
tBlock,
tErase
(1)
(2)
66
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the flash controller's state machine.
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V, 3 V
0.025
15
µs
tSBW,
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3 V
1
µs
En
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency - 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
2.2 V
15
100
0
5
MHz
10
MHz
80
kΩ
3V
0
2.2 V, 3 V
45
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
From module
1
P1OUT.x
0
From module
1
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
To module
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
68
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Interrupt
Edge
Select
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Table 46. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
x
0
1
2
3
4
FUNCTION
P1DIR.x
P1SEL.x
P1.0 (I/O)
I: 0; O: 1
0
TA0CLK
0
1
ACLK
1
1
I: 0; O: 1
0
TA0.CCI0A
0
1
TA0.0
1
1
I: 0; O: 1
0
TA0.CCI1A
0
1
TA0.1
1
1
I: 0; O: 1
0
TA0.CCI2A
0
1
TA0.2
1
1
I: 0; O: 1
0
0
1
P1.1 (I/O)
P1.2 (I/O)
P1.3 (I/O)
P1.4 (I/O)
TA0.CCI3A
TA0.3
P1.5/TA0.4
5
P1.5 (I/O)
TA0.CCI4A
TA0.4
P1.6/TA1CLK/CBOUT
6
7
1
1
I: 0; O: 1
0
0
1
1
1
P1.6 (I/O)
I: 0; O: 1
0
TA1CLK
0
1
CBOUT comparator B
P1.7/TA1.0
CONTROL BITS AND SIGNALS
1
1
I: 0; O: 1
0
TA1.CCI0A
0
1
TA1.0
1
1
P1.7 (I/O)
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Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
0
From module
1
P2OUT.x
0
From module
1
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
To module
DVSS
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UB0STE/UCA0CLK
D
P2IE.x
EN
To module
Q
P2IFG.x
P2SEL.x
P2IES.x
70
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Table 47. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.3/TA2.0
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
x
0
1
2
3
4
5
6
FUNCTION
P2.0 (I/O)
7
P2SEL.x
I: 0; O: 1
0
0
1
TA1.1
1
1
P2.1 (I/O)
I: 0; O: 1
0
TA1.CCI2A
0
1
TA1.2
1
1
P2.2 (I/O)
I: 0; O: 1
0
TA2CLK
0
1
SMCLK
1
1
I: 0; O: 1
0
TA2.CCI0A
0
1
TA2.0
1
1
I: 0; O: 1
0
TA2.CCI1A
0
1
TA2.1
1
1
I: 0; O: 1
0
TA2.CCI2A
0
1
TA2.2
1
1
I: 0; O: 1
0
0
1
RTCCLK
1
1
P2.7 (I/O)
I: 0; O: 1
0
X
1
P2.3 (I/O)
P2.4 (I/O)
P2.5 (I/O)
P2.6 (I/O)
UCB0STE/UCA0CLK (2)
(1)
(2)
(3)
P2DIR.x
TA1.CCI1A
DMAE0
P2.7/UCB0STE/UCA0CLK
CONTROL BITS AND
SIGNALS (1)
(3)
X = Don't care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
0
From module
1
P3OUT.x
0
From module
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
EN
To module
D
Table 48. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
P3.0/UCB0SIMO/UCB0SDA
x
0
FUNCTION
P3.0 (I/O)
UCB0SIMO/UCB0SDA (2)
P3.1/UCB0SOMI/UCB0SCL
1
P3.1 (I/O)
UCB0SOMI/UCB0SCL (2)
P3.2/UCB0CLK/UCA0STE
2
3
4
(4)
P3.3 (I/O)
UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
(2)
P3.4 (I/O)
UCA0RXD/UCA0SOMI (2)
(1)
(2)
(3)
(4)
72
(3)
P3.2 (I/O)
UCB0CLK/UCA0STE (2)
P3.3/UCA0TXD/UCA0SIMO
(3)
CONTROL BITS AND
SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
0
from Port Mapping Control
1
P4OUT.x
0
from Port Mapping Control
1
0
DVCC
1
1
Direction
0: Input
1: Output
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
to Port Mapping Control
DVSS
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
D
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Table 49. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
P4.0/P4MAP0
x
0
FUNCTION
P4.0 (I/O)
Mapped secondary digital function
P4.1/P4MAP1
1
P4.1 (I/O)
Mapped secondary digital function
P4.2/P4MAP2
2
P4.2 (I/O)
Mapped secondary digital function
P4.3/P4MAP3
3
P4.4/P4MAP4
4
P4.3 (I/O)
Mapped secondary digital function
P4.4 (I/O)
Mapped secondary digital function
P4.5/P4MAP5
5
P4.5 (I/O)
Mapped secondary digital function
P4.6/P4MAP6
6
P4.6 (I/O)
Mapped secondary digital function
P4.7/P4MAP7
7
P4.7 (I/O)
Mapped secondary digital function
(1)
74
CONTROL BITS AND SIGNALS
P4DIR.x (1)
P4SEL.x
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
≤ 30
P4MAPx
X
1
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
The direction of some mapped secondary functions are controlled directly by the module. See Table 9 for specific direction control
information of mapped secondary functions.
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Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Pad Logic
to/from Reference
to ADC10
INCHx = x
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
From module
1
P5.0/(A8/VeREF+)
P5.1/(A9/VeREF–)
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
To module
D
Table 50. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
P5.0/A8/VeREF+ (2)
x
0
FUNCTION
P5.0 (I/O) (3)
A8/VeREF+
P5.1/A9/VeREF– (5)
1
(4)
P5.1 (I/O) (3)
A9/VeREF– (6)
(1)
(2)
(3)
(4)
(5)
(6)
CONTROL BITS AND SIGNALS (1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
VeREF+ available on devices with ADC10_A.
Default condition
Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A when available.
VeREF- available on devices with ADC10_A.
Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A when available.
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Port P5, P5.2, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.2
P5DIR.2
DVSS
0
DVCC
1
1
0
1
P5OUT.2
0
Module X OUT
1
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5.2/XT2IN
P5IN.2
EN
Module X IN
76
Bus
Keeper
D
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Port P5, P5.3, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.3
P5DIR.3
DVSS
0
DVCC
1
1
0
1
P5OUT.3
0
Module X OUT
1
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
P5SEL.3
P5IN.3
Bus
Keeper
EN
Module X IN
D
Table 51. Port P5 (P5.2, P5.3) Pin Functions
PIN NAME (P5.x)
P5.2/XT2IN
P5.3/XT2OUT
(1)
(2)
(3)
x
2
3
FUNCTION
P5.2 (I/O)
CONTROL BITS AND SIGNALS (1)
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
XT2IN crystal mode (2)
X
1
X
0
XT2IN bypass mode (2)
X
1
X
1
I: 0; O: 1
0
X
X
XT2OUT crystal mode (3)
X
1
X
0
P5.3 (I/O) (3)
X
1
X
1
P5.3 (I/O)
X = Don't care
Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.4
P5DIR.4
DVSS
0
DVCC
1
1
0
1
P5OUT.4
0
Module X OUT
1
P5DS.4
0: Low drive
1: High drive
P5SEL.4
P5.4/XIN
P5IN.4
EN
Module X IN
78
Bus
Keeper
D
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Pad Logic
to XT1
P5REN.5
P5DIR.5
DVSS
0
DVCC
1
1
0
1
P5OUT.5
0
Module X OUT
1
P5.5/XOUT
P5DS.5
0: Low drive
1: High drive
P5SEL.5
XT1BYPASS
P5IN.5
Bus
Keeper
EN
Module X IN
D
Table 52. Port P5 (P5.4 and P5.5) Pin Functions
PIN NAME (P7.x)
P5.4/XIN
x
4
FUNCTION
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
X
X
XOUT crystal mode (3)
X
1
X
0
P5.5 (I/O) (3)
X
1
X
1
P5.4 (I/O)
XIN crystal mode
(2)
XIN bypass mode (2)
P5.5/XOUT
(1)
(2)
(3)
5
CONTROL BITS AND SIGNALS (1)
P5.5 (I/O)
X = Don't care
Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
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Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Pad Logic
to ADC10
INCHx = x
to Comparator_B
from Comparator_B
CBPD.x
P6REN.x
P6DIR.x
0
0
From module
1
0
DVCC
1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
EN
To module
80
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
D
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Bus
Keeper
P6.0/CB0/(A0)
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Table 53. Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)
P6.0/CB0/(A0)
x
0
FUNCTION
P6.0 (I/O)
A0 (only on devices with ADC)
CB0 (1)
P6.1/CB1/(A1)
P6.2/CB2/(A2)
P6.3/CB3/(A3)
P6.4/CB4/(A4)
1
2
3
4
P6.1 (I/O)
(1)
X
X
X
1
I: 0; O: 1
0
0
1
X
1
I: 0; O: 1
0
0
P6.2 (I/O)
A2 (only on devices with ADC)
X
1
X
CB2 (1)
X
X
1
I: 0; O: 1
0
0
P6.3 (I/O)
A3 (only on devices with ADC)
X
1
X
CB3 (1)
X
X
1
I: 0; O: 1
0
0
X
1
X
1
P6.4 (I/O)
P6.5 (I/O)
P6.6 (I/O)
CB6 (1)
7
0
1
X
A6 (only on devices with ADC)
P6.7/CB7/(A7)
0
X
X
CB5 (1)
6
I: 0; O: 1
X
A5 (only on devices with ADC)
P6.6/CB6/(A6)
CBPD
CB1 (1)
CB4 (1)
5
P6SEL.x
A1 (only on devices with ADC)
A4 (only on devices with ADC)
P6.5/CB5/(A5)
CONTROL BITS AND SIGNALS
P6DIR.x
X
X
I: 0; O: 1
0
0
X
1
X
1
X
X
I: 0; O: 1
0
0
X
1
X
1
X
X
I: 0; O: 1
0
0
A7 (only on devices with ADC)
X
1
X
CB7 (1)
X
X
1
P6.7 (I/O)
Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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Port PU.0, PU.1 Ports
LDOO
VSSU
Pad Logic
PUOPE
PU.0
PUOUT0
PUIN0
PUIPE
PUIN1
PU.1
PUOUT1
Table 54. Port PU.0, PU.1 Output Functions (1)
CONTROL BITS
(1)
PIN NAME
PUOPE
PUOUT1
PUOUT0
PU.1/DM
PU.0/DP
0
X
X
Output disabled
Output disabled
1
0
0
Output low
Output low
1
0
1
Output low
Output high
1
1
0
Output high
Output low
1
1
1
Output high
Output high
PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device
using the integrated 3.3-V LDO when enabled. LDOO can also be supplied externally when the 3.3-V
LDO is not being used and is disabled.
Table 55. Port PU.0, PU.1 Input Functions (1)
CONTROL BITS
(1)
82
PIN NAME
PUIPE
PU.1/DM
PU.0/DP
0
Input disabled
Input disabled
1
Input enabled
Input enabled
PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO
can be generated by the device using the integrated 3.3-V LDO
when enabled. LDOO can also be supplied externally when the 3.3V LDO is not being used and is disabled.
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Copyright © 2010–2012, Texas Instruments Incorporated
MSP430F530x, MSP430F5310
www.ti.com
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
1
PJDS.x
0: Low drive
1: High drive
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
To JTAG
D
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
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Table 56. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS/
SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
(2)
I: 0; O: 1
PJ.1 (I/O) (2)
I: 0; O: 1
PJ.0 (I/O)
TDO (3)
PJ.1/TDI/TCLK
1
X
TDI/TCLK (3)
PJ.2/TMS
2
PJ.2 (I/O)
TMS (3)
PJ.3/TCK
3
(1)
(2)
(3)
(4)
84
X
I: 0; O: 1
(4)
PJ.3 (I/O)
TCK (3)
(4)
(2)
X
(2)
I: 0; O: 1
(4)
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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MSP430F530x, MSP430F5310
www.ti.com
SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
DEVICE DESCRIPTORS
Table 57 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.
Table 57. Device Descriptor Table
Info Block
Die Record
ADC10
Calibration
REF
Calibration
Peripheral
Descriptor
(1)
(1)
'F5304
'F5308
RGC
'F5308
RGZ
'F5309
RGC
'F5309
RGZ
'F5310
RGC
'F5310
RGZ
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
06h
06h
06h
06h
06h
06h
06h
1
06h
06h
06h
06h
06h
06h
06h
01A02h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
1
12h
13h
13h
14h
14h
15h
15h
Device ID
01A05h
1
81h
81h
81h
81h
81h
81h
81h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
DESCRIPTION
ADDRESS
SIZE
(bytes)
Info length
01A00h
1
CRC length
01A01h
CRC value
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC10 Calibration Tag
01A14h
1
13h
13h
13h
13h
13h
13h
13h
ADC10 Calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC Offset
01A18h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF Calibration Tag
01A26h
1
12h
12h
12h
12h
12h
12h
12h
REF Calibration length
01A27h
1
06h
06h
06h
06h
06h
06h
06h
REF 1.5-V Reference
Factor
01A28h
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 2.0-V Reference
Factor
01A2Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 2.5-V Reference
Factor
01A2Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Peripheral Descriptor Tag
01A2Eh
1
02h
02h
02h
02h
02h
02h
02h
Peripheral Descriptor
Length
01A2Fh
1
5Ch
60h
60h
61h
61h
60h
60h
Memory 1
2
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 3
2
0Eh
2Dh
0Eh
2Dh
0Eh
2Dh
0Eh
2Dh
0Eh
2Dh
0Eh
2Dh
0Eh
2Dh
Memory 4
2
2Ah
70h
2Ah
60h
2Ah
60h
2Ah
50h
2Ah
50h
2Ah
40h
2Ah
40h
N/A = Not applicable
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Table 57. Device Descriptor Table (1) (continued)
DESCRIPTION
86
ADDRESS
SIZE
(bytes)
'F5304
'F5308
RGC
'F5308
RGZ
'F5309
RGC
'F5309
RGZ
'F5310
RGC
'F5310
RGZ
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
91h
8Eh
92h
92h
8Eh
90h
90h
91h
8Eh
1
00h
00h
00h
00h
00h
00h
00h
1
1Eh
20h
20h
20h
20h
20h
20h
MSP430CPUXV2
2
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
JTAG
2
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
00h
09h
SBW
2
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
EEM-S
2
00h
03h
00h
03h
00h
03h
00h
03h
00h
03h
00h
03h
00h
03h
TI BSL
2
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
SFR
2
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
PMM
2
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
FCTL
2
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
CRC16
2
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16_RB
2
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
RAMCTL
2
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
WDT_A
2
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
UCS
2
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
SYS
2
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
REF
2
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
Port Mapping
2
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
01h
10h
Port 1/2
2
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
04h
51h
Port 3/4
2
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
Port 5/6
2
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
JTAG
2
0Eh
5Fh
0Eh
5Fh
0Eh
5Fh
0Eh
5Fh
0Eh
5Fh
0Eh
5Fh
0Eh
5Fh
TA0
2
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA1
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TB0
2
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
TA2
2
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
RTC
2
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
0Ah
68h
MPY32
2
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
DMA-3
2
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
USCI_A/B
2
10h
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
Memory 5
2/1
delimiter
Peripheral count
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SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012
Table 57. Device Descriptor Table (1) (continued)
DESCRIPTION
Interrupts
ADDRESS
SIZE
(bytes)
'F5304
'F5308
RGC
'F5308
RGZ
'F5309
RGC
'F5309
RGZ
'F5310
RGC
'F5310
RGZ
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
USCI_A/B
2
N/A
04h
90h
ADC10_A
2
14h
D3h
14h
D3h
14h
D3h
14h
D3h
14h
D3h
14h
D3h
14h
D3h
COMP_B
2
N/A
18h
A8h
18h
A8h
18h
A8h
18h
A8h
18h
A8h
18h
A8h
LDO
2
1Ch
5Ch
04h
5Ch
04h
5Ch
04h
5Ch
04h
5Ch
04h
5Ch
04h
5Ch
COMP_B
1
01h
A8h
A8h
A8h
A8h
A8h
A8h
TB0.CCIFG0
1
64h
64h
64h
64h
64h
64h
64h
TB0.CCIFG1..6
1
65h
65h
65h
65h
65h
65h
65h
WDTIFG
1
40h
40h
40h
40h
40h
40h
40h
USCI_A0
1
01h
90h
90h
90h
90h
90h
90h
USCI_B0
1
01h
91h
91h
91h
91h
91h
91h
ADC10_A
1
D0h
D0h
D0h
D0h
D0h
D0h
D0h
TA0.CCIFG0
1
60h
60h
60h
60h
60h
60h
60h
TA0.CCIFG1..4
1
61h
61h
61h
61h
61h
61h
61h
LDO-PWR
1
5Ch
5Ch
5Ch
5Ch
5Ch
5Ch
5Ch
DMA
1
46h
46h
46h
46h
46h
46h
46h
TA1.CCIFG0
1
62h
62h
62h
62h
62h
62h
62h
TA1.CCIFG1..2
1
63h
63h
63h
63h
63h
63h
63h
P1
1
50h
50h
50h
50h
50h
50h
50h
USCI_A1
1
92h
92h
92h
92h
92h
92h
92h
USCI_B1
1
93h
93h
93h
93h
93h
93h
93h
TA1.CCIFG0
1
66h
66h
66h
66h
66h
66h
66h
TA1.CCIFG1..2
1
67h
67h
67h
67h
67h
67h
67h
P2
1
51h
51h
51h
51h
51h
51h
51h
RTC_A
1
68h
68h
68h
68h
68h
68h
68h
delimiter
1
00h
00h
00h
00h
00h
00h
00h
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MSP430F530x, MSP430F5310
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REVISION HISTORY
REVISION
88
COMMENTS
SLAS677
Product Preview release
SLAS677A
Production Data release
SLAS677B
Released BGA package.
Corrected VCB_REF min and max values by swapping them as they were backward.
Added IUSB_LDO and IVBUS_DETECT to USB-PWR table.
Added QFN thermal pad connection to pinout drawing and terminal function table.
Added LDO and Port U description.
Updated pin diagrams to show A8 and A9 muxed with P5.0/VeREF+ and P5.1/VeREF- pins, respectively.
Updated tEN_REF typ value; changed from 0.3 to 1.
SLAS677C
Table 1 and Functional Block Diagrams, Corrected number of USCI modules for PT and RGZ packages.
Table 3, Changed ACLK description (added dividers up to 32).
Short-Form Description, Added links to family user's guide chapters to section titles.
Table 11, Changed SYSRSTIV interrupt event at 1Ch to Reserved.
Recommended Operating Conditions, Added note regarding interaction between minimum VCC and SVS.
Table 47, Table 48, Corrected notes regarding USCI CLK functions taking precedence over USCI STE functions.
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Copyright © 2010–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
(Requires Login)
MSP430F5304IPT
ACTIVE
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5304IPTR
ACTIVE
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5304IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5304IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IPT
ACTIVE
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IPTR
ACTIVE
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IRGZT
PREVIEW
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5308IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5308IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5309IPT
ACTIVE
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5309IPTR
ACTIVE
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5309IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5309IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Aug-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F5309IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5309IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5309IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5309IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5310IPT
ACTIVE
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5310IPTR
ACTIVE
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5310IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5310IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5310IRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5310IRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F5310IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430F5310IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2012
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This may also be a thermally enhanced plastic package with leads conected to the die pads.
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