HT1626 RAM Mapping 48´16 LCD Controller for I/O MCU PATENTED PAT No. : 099352 Technical Document · Application Note Features · Operating voltage: 2.7V~5.2V · Built-in LCD display RAM · Built-in RC oscillator · R/W address auto increment · External 32.768kHz crystal or 32kHz frequency · Two selection buzzer frequencies (2kHz or 4kHz) source input · Power down command reduces power consumption · 1/5 bias, 1/16 duty, frame frequency is 64Hz · Software configuration feature · Max. 48´16 patterns, 16 commons, 48 segments · Data mode and Command mode instructions · Built-in internal resistor type bias generator · Three data accessing modes · 3-wire serial interface · VLCD pin to adjust LCD operating voltage · 8 kinds of time base or WDT selection · 100-pin QFP package · Time base or WDT overflow output General Description HT1626 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1626. The HT162X series have many kinds of products that match various applications. HT1626 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 768 patterns (48´16). It also supports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1626 is a memory mapping and multi-function LCD controller. The software configuration feature of the Selection Table HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 COM 4 4 8 8 8 8 16 SEG 32 32 32 32 48 64 48 Built-in Osc. ¾ Ö Ö ¾ Ö Ö Ö Crystal Osc. Ö Ö ¾ Ö Ö Ö Ö Rev. 1.50 1 June 9, 2009 PATENTED HT1626 Block Diagram D is p la y R A M O S C O O S C I C S C o n a n T im C ir c R D W R tro l d in g u it C O M 0 C O M 1 5 L C D D r iv e r / B ia s C ir c u it D A T A S E G 0 S E G 4 7 V D D V L C D V S S B Z W a tc h d o g T im e r a n d T im e B a s e G e n e r a to r T o n e F re q u e n c y G e n e ra to r B Z IR Q Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 C S R D O C C C W R D A T A N C N C V S S O S C I S C O V D D V L C D IR Q B Z B Z T 1 T 2 T 3 T 4 C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 N C C O M 5 C O M 6 C O M 7 C O M 8 C O M 9 O M 1 0 O M 1 1 O M 1 2 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 1 8 0 2 7 9 3 7 8 4 7 7 5 7 6 6 7 5 7 7 4 8 7 3 9 7 2 1 0 7 1 1 1 7 0 1 2 6 9 1 3 6 8 1 4 6 7 H T 1 6 2 6 1 0 0 Q F P -A 1 5 1 6 6 6 6 5 1 7 6 4 1 8 6 3 1 9 6 2 2 0 6 1 2 1 6 0 2 2 5 9 2 3 5 8 2 4 5 7 2 5 5 6 2 6 5 5 2 7 5 4 2 8 5 3 2 9 5 2 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 S E G S E G S E G S E G S E G S E G N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C S E G S E G S E G S E G S E G S E G S E G 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 1 5 2 8 7 6 5 4 3 2 1 0 1 4 1 3 Rev. 1.50 June 9, 2009 PATENTED HT1626 Pad Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 7 1 7 0 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 7 2 4 1 7 3 4 2 7 4 4 3 4 4 7 5 4 5 7 6 4 6 7 7 4 7 D A T A C S R D W R V S S 7 8 6 9 6 8 5 3 5 2 4 9 5 0 5 1 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 3 6 3 7 3 9 4 0 4 1 4 2 4 4 4 5 4 6 4 7 4 8 2 V D D 3 V L C D 4 5 B Z 6 B Z 7 T 1 7 9 1 O S C I O S C O IR Q 8 0 (0 , 0 ) 8 T 2 9 T 3 1 0 T 4 C O M 0 1 2 1 1 C O M 1 C O M 2 1 3 C O M 3 C O M 4 1 5 1 4 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 8 4 3 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 5 1 0 9 8 7 6 5 4 3 2 1 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 C O M 5 Chip size: 148 ´ 123 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork. Rev. 1.50 3 June 9, 2009 PATENTED HT1626 Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y 1 2 -1745.115 1195.533 41 729.836 -1455.425 -1745.115 1096.513 42 828.935 -1455.425 3 -1744.679 775.806 43 927.956 -1455.425 4 -1744.765 651.256 44 1027.055 -1455.425 5 -1751.917 505.882 45 1126.075 -1455.425 6 -1746.120 308.253 46 1225.175 -1455.425 7 -1746.120 19.855 47 1324.196 -1455.425 8 -1744.765 -131.999 48 1423.294 -1455.425 9 -1744.765 -317.380 49 1522.315 -1455.425 10 -1744.765 -416.479 50 1621.415 -1455.425 11 -1744.765 -601.860 51 1720.436 12 -1744.765 -700.959 52 1766.902 -1455.425 1453.104 13 -1744.765 -886.341 53 1667.883 1453.104 14 -1744.765 -985.440 54 1568.782 1453.104 15 -1744.765 -1170.821 55 1469.762 1453.104 16 -1744.765 -1269.919 56 1370.662 1453.104 17 -1744.765 -1455.300 57 1271.642 1453.104 18 -1548.505 -1455.425 58 1172.542 1453.104 19 -1449.484 -1455.425 59 1073.522 1453.104 20 -1350.385 -1455.425 60 974.422 1453.104 21 -1251.365 -1455.425 61 875.402 1453.104 22 -1152.266 -1455.425 62 776.302 1453.104 23 -1053.245 -1455.425 63 677.282 1453.104 24 -954.146 -1455.425 64 578.182 1453.104 25 -855.125 -1455.425 65 479.163 1453.104 26 -756.026 -1455.425 66 380.062 1453.104 27 -657.005 -1455.425 67 281.042 1453.104 28 -557.906 -1455.425 68 181.943 1453.104 29 -458.885 -1455.425 69 82.923 1453.104 30 -359.786 -1455.425 70 -16.177 1453.104 31 -260.764 -1455.425 71 -115.197 1453.104 32 -161.665 -1455.425 72 -214.298 1453.104 33 -1455.425 -313.318 1453.104 34 -62.645 36.454 73 -1455.425 74 -412.417 1453.104 35 135.475 -1455.425 75 -511.438 1453.104 36 234.574 -1455.425 76 -610.536 1453.104 37 333.596 -1455.425 77 -709.557 1453.104 38 432.695 -1455.425 78 -808.656 1453.104 39 531.716 -1455.425 79 -977.680 1453.104 40 630.815 -1455.425 80 -1207.287 1453.629 Rev. 1.50 4 June 9, 2009 PATENTED HT1626 Pad Description Pad No. Pad Name I/O Description The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. 1 OSCI I 2 OSCO O 3 VDD ¾ 4 VLCD I LCD operating voltage input pad. 5 IRQ O Time base or Watchdog Timer overflow flag, NMOS open drain output 6, 7 BZ, BZ O 2kHz or 4kHz tone frequency output pair 8~11 T1~T4 I Not connected 12~27 COM0~COM15 O LCD common outputs 28~75 SEG0~SEG47 O LCD segment outputs I Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1626 are disabled. The serial interface circuit is also reset. But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1626 are all enabled. 76 CS Positive power supply 77 RD I READ clock input with pull-high resistor. Data in the RAM of the HT1626 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. 78 WR I WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1626 on the rising edge of the WR signal. 79 DATA I/O Serial data input or output with pull-high resistor 80 VSS ¾ Negative power supply, ground Absolute Maximum Ratings Supply Voltage .........................................-0.3V to 5.5V Storage Temperature ............................-50°C to 125°C Input Voltage.............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-25°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.50 5 June 9, 2009 PATENTED HT1626 D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current IDD2 Operating Current IDD11 Operating Current IDD22 Operating Current ISTB Standby Current VIL Input Low Voltage VIH Input High Voltage IOL1 BZ, BZ, IRQ IOH1 BZ, BZ IOL2 DATA IOH2 DATA IOL3 LCD Common Sink Current Test Conditions VDD Conditions ¾ ¾ 3V 5V 3V 5V 3V 5V 3V 5V No load or LCD ON On-chip RC oscillator No load or LCD ON Crystal oscillator No load or LCD OFF On-chip RC oscillator No load or LCD OFF Crystal oscillator 3V No load, Power down mode 5V 3V 3V IOL4 LCD Segment Sink Current IOH4 LCD Segment Source Current RPH Pull-high Resistor Typ. Max. Unit 2.7 ¾ 5.2 V ¾ 155 310 mA ¾ 260 420 mA ¾ 150 310 mA ¾ 250 420 mA ¾ 8 30 mA ¾ 20 60 mA ¾ ¾ 20 mA ¾ ¾ 35 mA ¾ 1 12 mA ¾ 2 24 mA 0 ¾ 0.6 V 0 ¾ 1.0 V 2.4 ¾ 3.0 V 4.0 ¾ 5.0 V DATA, WR, CS, RD 5V LCD Common Source Current Min. DATA, WR, CS, RD 5V IOH3 Rev. 1.50 Ta=25°C 3V VOL=0.3V 0.9 1.8 ¾ mA 5V VOL=0.5V 1.7 3.0 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -1.7 -3.0 ¾ mA 3V VOL=0.3V 0.9 1.8 ¾ mA 5V VOL=0.5V 1.7 3.0 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -1.7 -3.0 ¾ mA 3V VOL=0.3V 80 160 ¾ mA 5V VOL=0.5V 180 360 ¾ mA 3V VOH=2.7V -40 -80 ¾ mA 5V VOH=4.5V -90 -180 ¾ mA 3V VOL=0.3V 50 100 ¾ mA 5V VOL=0.5V 120 240 ¾ mA 3V VOH=2.7V -30 -60 ¾ mA 5V VOH=4.5V -70 -140 ¾ mA 100 200 300 kW 50 100 150 kW 3V DATA, WR, CS, RD 5V 6 June 9, 2009 PATENTED HT1626 A.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit fSYS1 System Clock 5V On-chip RC oscillator 24 32 40 kHz fSYS2 System Clock ¾ External clock source ¾ 32 ¾ kHz fLCD1 LCD Frame Frequency 5V On-chip RC oscillator 48 64 80 Hz fLCD2 External clock source ¾ 64 ¾ Hz n: Number of COM ¾ n/fLCD ¾ sec 4 ¾ 150 kHz 4 ¾ 300 kHz ¾ ¾ 75 kHz ¾ ¾ 150 kHz CS 500 600 ¾ ns Write mode 3.34 ¾ 125 Read mode 6.67 ¾ ¾ Write mode 1.67 ¾ 125 Read mode 3.34 ¾ ¾ LCD Frame Frequency ¾ tCOM LCD Common Period ¾ fCLK1 Serial Data Clock (WR Pin) 3V Duty cycle 50% 5V 3V fCLK2 Serial Data Clock (RD Pin) tCS Serial Interface Reset Pulse Width (Figure 3) Duty cycle 50% 5V ¾ 3V WR, RD Input Pulse Width (Figure 1) tCLK 5V ms ms t r, t f Rise or Fall Time Serial Data Clock Width (Figure 1) ¾ ¾ ¾ 120 160 ns tsu Setup Time for DATA to WR, RD Clock Width (Figure 2) ¾ ¾ 60 120 ¾ ns tsu1 Setup Time for CS to WR, RD Clock Width (Figure 3) ¾ ¾ 500 600 ¾ ns th Hold Time for DATA to WR, RD Clock Width (Figure 2) ¾ ¾ 500 600 ¾ ns th1 Hold Time for CS to WR, RD Clock Width (Figure 3) ¾ ¾ 50 100 ¾ ns 1.5 2.0 2.5 kHz 3.0 4.0 5.0 kHz 20 ¾ ¾ ms 0.05 ¾ ¾ V/ms Tone Frequency (2kHz) fTONE 5V On-chip RC oscillator Tone Frequency (4kHz) tOFF VDD OFF Times (Figure 4) ¾ VDD drop down to 0V tSR VDD Rising Slew Rate (Figure 4) ¾ ¾ Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage. Rev. 1.50 7 June 9, 2009 PATENTED tf W R , R D C lo c k 9 0 % 5 0 % 1 0 % tr tC V tC L K HT1626 V A L ID D A T A D D D B G N D L K ts Figure 1 V D D 5 0 % G N D th u V W R , R D C lo c k 5 0 % D D G N D Figure 2 tC C S ts W R , R D C lo c k S V D D 5 0 % th u 1 G N D 1 V 5 0 % F IR S T C lo c k V D D tS 0 V D D tO G N D L A S T C lo c k R F F Figure 4. Power-on Reset Timing Figure 3 Functional Description Display Memory - RAM Structure If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. The static display RAM is organized into 192´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Buzzer Tone Output A simple tone generator is implemented in the HT1626. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Time Base and Watchdog Timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued. C O M 1 5 C O M 1 4 C O M 1 3 Command Format The HT1626 can be configured by the software setting. There are two mode commands to configure the HT1626 resource and to transfer the LCD display data. C O M 3 C O M 1 2 C O M 2 C O M 1 C O M 0 S E G 0 3 0 S E G 1 7 4 S E G 2 1 1 8 S E G 3 1 5 1 2 S E G 4 7 1 9 1 1 8 8 D 3 D 2 D 1 D 0 A d d r D 3 D a ta D 2 D 1 D 0 A d d r e s s 8 B its (A 7 , A 6 , ...., A 0 ) A d d r D a ta D a ta 4 B its (D 3 , D 2 , D 1 , D 0 ) RAM Mapping Rev. 1.50 8 June 9, 2009 PATENTED HT1626 T im e B a s e T IM E R /2 5 6 C lo c k S o u r c e V C L R T im e r D D Q D W D T /4 C K C L R IR Q E N /D IS W D T E N /D IS IR Q E N /D IS R W D T Timer and WDT Configurations The following are the data mode ID and the command mode ID: Mode ID READ Operation Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 Command 100 COMMAND Name If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1², and the previous operation mode will be reset also. The CS pin returns to ²0², a new operation mode ID should be issued first. Command Code Function TONE OFF 0000-1000-X Turn-off tone output TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz Timing Diagrams READ Mode (Command Code : 1 1 0) C S W R R D D A T A 1 0 1 A 7 A 5 A 6 A 3 A 4 A 2 A 1 A 0 D 0 D 1 D 2 D 3 1 A 7 0 1 A 5 A 6 D a ta (M A 1 ) M e m o ry A d d re s s 1 (M A 1 ) A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 2 (M A 2 ) D 1 D 2 D 3 D a ta (M A 2 ) READ Mode (Successive Address Reading) C S W R R D D A T A 1 1 0 A 7 A 6 A 5 A 4 A 3 A 2 M e m o ry A d d re s s (M A ) Rev. 1.50 A 1 A 0 D 0 D 1 D 2 D a ta (M A ) 9 D 3 D 0 D 1 D 2 D 3 D a ta (M A + 1 ) D 0 D 1 D 2 D a ta (M A + 2 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 3 ) June 9, 2009 PATENTED HT1626 WRITE Mode (Command Code : 1 0 1) C S W R 1 D A T A 1 0 A 7 A 5 A 6 A 3 A 4 A 2 A 1 A 0 D 0 D 2 D 1 M e m o ry A d d re s s 1 (M A 1 ) D 3 1 1 0 A 7 A 6 D a ta (M A 1 ) A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 2 D 1 M e m o ry A d d re s s 2 (M A 2 ) D 3 D a ta (M A 2 ) WRITE Mode (Successive Address Writing) C S W R 1 D A T A A 7 1 0 A 5 A 6 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s (M A ) D 2 D 1 D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 1 ) D a ta (M A ) D 1 D 2 D 3 D 0 D a ta (M A + 2 ) D 2 D 1 D 3 D 0 D a ta (M A + 3 ) READ-MODIFY-WRITE Mode (Command Code : 1 0 1) C S W R R D D A T A 1 1 0 A 6 A 7 A 5 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 1 (M A 1 ) D 1 D 2 D 3 D 0 D 1 D 2 D 3 1 0 1 A 7 D a ta (M A 1 ) D a ta (M A 1 ) A 6 A 1 A 0 D 0 M e m o ry A d d re s s 2 (M A 2 ) D 1 D 2 D 3 D a ta (M A 2 ) READ-MODIFY-WRITE Mode (Successive Address Accessing) C S W R R D D A T A 1 0 1 A 7 A 6 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) Rev. 1.50 A 0 D 0 D 1 D 2 D 3 D a ta (M A ) 10 D 0 D 1 D 2 D a ta (M A ) D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 2 ) June 9, 2009 PATENTED HT1626 Command Mode (Command Code : 1 0 0) C S W R D A T A 1 0 0 C 8 C 7 C 6 C 5 C 4 C 3 C o m m a n d 1 C 2 C 1 C 8 C 0 C o m m a n d ... C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C o m m a n d i C o m m a n d o r D a ta M o d e Mode (Data And Command Mode) C S W R D A T A C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta R D Rev. 1.50 11 June 9, 2009 PATENTED HT1626 Application Circuits C S * V D D R D *V R W R V L C D D A T A M C U H T 1 6 2 6 *R B Z P ie z o IR Q B Z O S C I C lo c k O u t O S C O C O M 0 ~ C O M 1 5 S E G 0 ~ S E G 4 7 E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) 1 /5 B ia s , 1 /1 6 D u ty O n - c h ip O S C L C D P a n e l C ry s ta l 3 2 7 6 8 H z The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. Note: The volatage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%. Adjust R (external pull-high resistance) to fit user¢s time base clock. Instruction Set Summary Name ID Command Code D/C Function Def. READ 1 1 0 A7A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 1 0 1 A7A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READ-MODIFY1 0 1 A7A6A5A4A3A2A1A0D0D1D2D3 WRITE D Read and Write data to the RAM SYS DIS 1 0 0 0000-0000-X C Turn off both system oscillator and LCD Yes bias generator SYS EN 1 0 0 0000-0001-X C Turn on system oscillator LCD OFF 1 0 0 0000-0010-X C Turn off LCD display LCD ON 1 0 0 0000-0011-X C Turn on LCD display TIMER DIS 1 0 0 0000-0100-X C Disable time base output Yes WDT DIS 1 0 0 0000-0101-X C Disable WDT time-out flag output Yes TIMER EN 1 0 0 0000-0110-X C Enable time base output WDT EN 1 0 0 0000-0111-X C Enable WDT time-out flag output TONE OFF 1 0 0 0000-1000-X C Turn off tone outputs CLR TIMER 1 0 0 0000-1101-X C Clear the contents of the time base generator CLR WDT 1 0 0 0000-1111-X C Clear the contents of the WDT stage RC 32K 1 0 0 0001-10XX-X C System clock source, on-chip RC oscillator Rev. 1.50 12 Yes Yes Yes June 9, 2009 PATENTED Name D/C Function EXT (XTAL) 32K 1 0 0 0001-11XX-X C System clock source, external 32kHz cl o ck so u r ce o r cr yst a l o sci l l a t o r 32.768kHz TONE 4K 1 0 0 010X-XXXX-X C Tone frequency output: 4kHz TONE 2K 1 0 0 0110-XXXX-X C Tone frequency output: 2kHz IRQ DIS 1 0 0 100X-0XXX-X C Disable IRQ output IRQ EN 1 0 0 100X-1XXX-X C Enable IRQ output F1 1 0 0 101X-0000-X C Time base clock output: 1Hz The WDT time-out flag after: 4s F2 1 0 0 101X-0001-X C Time base clock output: 2Hz The WDT time-out flag after: 2s F4 1 0 0 101X-0010-X C Time base clock output: 4Hz The WDT time-out flag after: 1s F8 1 0 0 101X-0011-X C Time base clock output: 8Hz The WDT time-out flag after: 1/2s F16 1 0 0 101X-0100-X C Time base clock output: 16Hz The WDT time-out flag after: 1/4s F32 1 0 0 101X-0101-X C Time base clock output: 32Hz The WDT time-out flag after: 1/8s F64 1 0 0 101X-0110-X C Time base clock output: 64Hz The WDT time-out flag after: 1/16s F128 1 0 0 101X-0111-X C Time base clock output: 128Hz The WDT time-out flag after: 1/32s TEST 1 0 0 1110-0000-X C Test mode, user don¢t use. NORMAL 1 0 0 1110-0011-X C Normal mode Note: ID Command Code HT1626 Def. Yes Yes Yes X : Don¢t care A7~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1626 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1626. Rev. 1.50 13 June 9, 2009 PATENTED HT1626 Package Information 100-pin QFP (14mm´20mm) Outline Dimensions C H D 8 0 G 5 1 I 5 0 8 1 F A B E 3 1 1 0 0 K = J 1 Symbol Rev. 1.50 3 0 Dimensions in mm Min. Nom. Max. A 18.50 ¾ 19.20 B 13.90 ¾ 14.10 C 24.50 ¾ 25.20 D 19.90 ¾ 20.10 E ¾ 0.65 ¾ F ¾ 0.30 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 1 ¾ 1.40 K 0.10 ¾ 0.20 a 0° ¾ 7° 14 June 9, 2009 PATENTED HT1626 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 15 June 9, 2009