SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 • FEATURES • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree(1) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) • • • Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors D OR PW PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y GND Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y DESCRIPTION/ORDERING INFORMATION This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA –40°C to 125°C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC – D Tape and reel SN74LVT125QDREP LVT125E TSSOP – PW Tape and reel SN74LVT125QPWREP LVT125E Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 3 1Y 4 5 6 2Y 10 9 8 3Y 13 12 11 4Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high or power-off IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current IOK Output clamp current θJA Package thermal impedance (4) Tstg Storage temperature range (5) (1) (2) (3) (4) (5) 2 state (2) –0.5 7 UNIT V 128 mA 64 mA VI < 0 –50 mA VO < 0 –50 mA D package 86 PW package 113 –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 Recommended Operating Conditions (1) MIN MAX 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 5.5 V IOH High-level output current –32 mA IOL Low-level output current 32 mA ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature 125 °C (1) V 2 V 0.8 Outputs enabled –40 V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 2.7 V, II = –18 mA VCC = MIN to MAX (2), IOH = –100 µA VCC = 2.7 V, IOH = –8 mA VCC = 3 V, IOH = –32 mA VCC = 2.7 V VOL VCC = 3 V VCC = 0 or MAX (2), II VCC = 0, –1.2 V VCC – 0.2 2.4 V 2 0.5 IOL = 16 mA 0.4 IOL = 32 mA 0.5 VI = 5.5 V VI = VCC ±1 1 Data inputs VCC = 3 V IOZH VCC = 3.6 V, VO = 3 V IOZL VCC = 3.6 V, VO = 0.5 V ICC VCC = 3.6 V, VI = VCC or GND, IO = 0 VI = 2 V Data inputs µA –5 ±450 VI or VO = 0 to 4.5 V VI = 0.8 V V 40 Control inputs 75 µA µA –75 5 µA –5 µA Outputs high 0.12 Outputs low 4.5 7 0.12 0.4 Outputs disabled (1) (2) (3) UNIT 0.2 II(hold) ∆ICC (3) MAX IOL = 24 mA VI = 0 Ioff TYP (1) IOL = 100 µA VI = VCC or GND VCC = 3.6 V MIN VCC = 3 V to 3.6 V, One input at VCC – 0.6, Other inputs at VCC or GND 0.35 0.2 mA mA Ci VI = 3 V or 0 4 pF Co VO = 3 V or 0 8 pF All typical values are at VCC = 3.3 V, TA = 25°C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 3 SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ (1) 4 FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y All typical values are at VCC = 3.3 V, TA = 25°C. VCC = 3.3 V ± 0.3 V MIN VCC = 2.7 V TYP (1) MAX UNIT MIN MAX 1 2.7 4.2 4.7 1 2.9 4.1 5.1 1 3.4 4.9 6.2 1.1 3.4 4.9 6.7 1.8 3.7 5.3 5.9 1.3 2.6 4.7 4.2 ns ns ns SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 1.5 V 0V VOH 1.5 V Output 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPHL tPLH 2.7 V Output Control tPLZ Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V VOL + 0.3 V 3V VOL tPHZ tPZH 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 5 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVT125QPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04705-01XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LVT125-EP : SN74LVT125 • Catalog: • Automotive: SN74LVT125-Q1 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVT125QPWREP Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT125QPWREP TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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