240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply • All inputs and outputs are compatible with SSTL_1.8 interface • 8 Bank architecture • Posted CAS • Programmable CAS Latency 3 ,4 ,5, 6 • OCD (Off-Chip Driver Impedance Adjustment) • ODT (On-Die Termination) • Fully differential clock operations (CK & CK) • Programmable Burst Length 4 / 8 with both sequential and interleave mode • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA(128Mx8), 84ball FBGA(64Mx16) • 133.35 x 30.00 mm form factor • RoHS compliant ORDERING INFORMATION Density Org. # of DRAMs # of ranks Materials ECC HYMP164U64CP6-C4/Y5/S6/S5 512MB 64Mx64 4 1 Lead-free None HYMP164U64CR6-C4/Y5/S6/S5 512MB 64Mx64 4 1 Halogen-free None HYMP112U64CP8-C4/Y5/S6/S5 1GB 128Mx64 8 1 Lead-free None HYMP112U64CR8-C4/Y5/S6/S5 1GB 128Mx64 8 1 Halogen-free None HYMP112U72CP8-C4/Y5/S6/S5 1GB 128Mx72 9 1 Lead-free ECC HYMP125U64CP8-C4/Y5/S6/S5 2GB 256Mx64 16 2 Lead-free None HYMP125U64CR8-C4/Y5/S6/S5 2GB 256Mx64 16 2 Halogen-free None HYMP125U72CP8-C4/Y5/S6/S5 2GB 256Mx72 18 2 Lead-free ECC Part Name This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Jul. 2008 1 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Y5 (DDR2-667) S6 (DDR2-800) S5 (DDR2-800) Unit Speed@CL3 400 400 - 400 Mbps Speed@CL4 533 533 533 533 Mbps Speed@CL5 - 667 667 800 Mbps Speed@CL6 - - 800 - Mbps CL-tRCD-tRP 4-4-4 5-5-5 6-6-6 5-5-5 tCK ADDRESS TABLE Density Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 512MB 64M x 64 1 64Mb x 16 4 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 1GB 128M x 64 1 128Mb x 8 8 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 1GB 128M x 72 1 128Mb x 8 9 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 2GB 256M x 64 2 128Mb x 8 16 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 2GB 256M x 72 2 128Mb x 8 18 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms Rev. 0.6 / Jul. 2008 2 1240pin DDR2 SDRAM Unbuffered DIMMs Input/Output Functional Description Symbol CK[2:0], CK[2:0] CKE[1:0] Type SSTL SSTL Polarity Differential Crossing Active High Pin Description CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data is reference to the crossing of CK and /CK (Both directions of crossing) Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the S[1:0] SSTL Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 RAS, CAS, SSTL Active Low ODT[1:0] SSTL Active High Vref Supply SDRAM mode register. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immu- VDDQ Supply nity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane BA[2:0] SSTL WE /RAS,/CAS and /WE(ALONG WITH S) define the command being entered. Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 as VDD pins. - Selects which DDR2 SDRAM internal bank of four or eight is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA15) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to A[9:0], A10/AP, A[13:11] SSTL - the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ[63:0], CB[7:0] SSTL - Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled DM[8:0] VDD,VSS DQS[8:0], DQS[8:0] SSTL Active High pins are tied to VDD/VDDQ planes on these modules. Differential crossing SA[2:0] - SDA - SCL - VDDSPD Supply Rev. 0.6 / Jul. 2008 of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ Supply SSTL High coincident with that input data during a write access. DM is sampled on both edges Data strobe for input and output data. For Rawcards using x16 organized DRAMs, DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of the DRAM These signals are tied at the system planar to either VSS or VDD to configure the serial SPD EEPROM. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. 3 1240pin DDR2 SDRAM Unbuffered DIMMs PIN CONFIGURATION Front Side 1 pin 64 pin 65 pin 121 pin 184 pin 185 pin 120 pin 240 pin Back Side PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 41 VSS 81 DQ33 121 VSS 161 NC(CB4)* 201 VSS 2 VSS 42 NC(CB0)* 82 VSS 122 DQ4 162 NC(CB5)* 202 DM4 3 DQ0 43 NC(CB1)* 83 DQS4 123 DQ5 163 VSS 203 NC 4 DQ1 44 VSS 84 DQS4 124 VSS 164 NC(DM8)* 204 VSS 5 VSS 45 NC(DQS8)* 85 VSS 125 DM0 165 NC 205 DQ38 6 DQS0 46 NC(DQS8)* 86 DQ34 126 NC 166 VSS 206 DQ39 7 DQS0 47 VSS 87 DQ35 127 VSS 167 NC(CB6)* 207 VSS 8 VSS 48 NC(CB2)* 88 VSS 128 DQ6 168 NC(CB7)* 208 DQ44 9 DQ2 49 NC(CB3)* 89 DQ40 129 DQ7 169 VSS 209 DQ45 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 CKE1 211 DM5 12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 NC 13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15 213 VSS 14 VSS 54 BA2 94 VSS 134 DM1 174 A14 214 DQ46 15 DQS1 55 NC 95 DQ42 135 NC 175 VDDQ 215 DQ47 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS 17 VSS 57 A11 97 VSS 137 CK1 177 A9 217 DQ52 18 NC 58 A7 98 DQ48 138 CK1 178 VDD 218 DQ53 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 CK2 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 CK2 22 DQ11 62 VDDQ 102 NC,TEST1 142 VSS 182 A3 222 VSS * The pin names in parenthesises are applied to DIMM with ECC only. Rev. 0.6 / Jul. 2008 4 1240pin DDR2 SDRAM Unbuffered DIMMs PIN ASSIGNMENT(Continued) Pin Name Pin Name Pin Name Pin Name Pin 23 VSS 63 A2 103 VSS 143 DQ20 183 DQ21 184 Name Pin Name A1 223 DM6 VDD 224 NC 24 DQ16 64 VDD 104 DQS6 144 25 DQ17 65 VSS 105 DQS6 145 VSS 185 CK0 225 VSS 26 VSS 66 VSS 106 VSS 146 DM2 186 CK0 226 DQ54 27 DQS2 67 VDD 107 DQ50 147 NC 187 VDD 227 DQ55 28 DQS2 68 NC 108 DQ51 148 VSS 188 A0 228 VSS 29 VSS 69 VDD 109 VSS 149 DQ22 189 VDD 229 DQ60 30 DQ18 70 A10/AP 110 DQ56 150 DQ23 190 BA1 230 DQ61 31 DQ19 71 BA0 111 DQ57 151 VSS 191 VDDQ 231 VSS DM7 32 VSS 72 VDDQ 112 VSS 152 DQ28 192 RAS 232 33 DQ24 73 WE 113 DQS7 153 DQ29 193 S0 233 NC 34 DQ25 74 CAS 114 DQS7 154 VSS 194 VDDQ 234 VSS 35 VSS 75 VDDQ 115 VSS 155 DM3 195 ODT0 235 DQ62 S1 116 DQ58 156 NC 196 A13 236 DQ63 36 DQS3 76 37 DQS3 77 ODT1 117 DQ59 157 VSS 197 VDD 237 VSS 38 VSS 78 VDDQ 118 VSS 158 DQ30 198 VSS 238 VDDSPD 39 DQ26 79 VSS 119 SDA 159 DQ31 199 DQ36 239 SA0 40 DQ27 80 DQ32 120 SCL 160 VSS 200 DQ37 240 SA1 *NC=No connect Note : 1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products(DIMMs). 2. NC Pins should not be connected to anything, including bussing within the NC group. Rev. 0.6 / Jul. 2008 5 1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx64) : HYMP164U64CP(R)6 /S 0 / DQS 0 / LD Q S DQS 0 LD Q S / CS LD M DM 0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 / DQS 1 DQS 1 D0 / UDQS / DQS 5 UDQS DQS 5 / LDQS / DQS 2 DQS 2 / CS LD M DM 2 D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23 I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 / DQS 3 DQS 3 D1 VD D S P D LDQS UDQS DQS 7 SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS D0-D 3 D0-D 3 D0-D 3 D0-D 3 D0-D 3 D0-D 3 D0-D 3 S erial P D D O -D 3 V REF D O -D 3 VS S D O -D 3 / CS LD M I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 D3 / UDQS UDQS UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15 DM 7 D Q 56 D Q 57 D Q 58 D Q 59 D Q 60 D Q 61 D Q 62 D Q 63 VD D / V D D Q Rev. 0.6 / Jul. 2008 / LDQ S DQS 6 / DQS 7 SCL BA 0- BA 2 A 0 - A 12 / RAS / CAS CKE 0 /WE ODT 0 UDQS UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15 / DQS 6 / UDQS D2 / UDQS DM 6 D Q 48 D Q 49 D Q 50 D Q 51 D Q 52 D Q 53 D Q 54 D Q 55 UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15 DM 3 D Q 24 D Q 25 D Q 26 D Q 27 D Q 28 D Q 29 D Q 30 D Q 31 LD M I/ O 0 I/ O 1 I/ O 2 I/ O 3 I/ O 4 I/ O 5 I/ O 6 I/ O 7 DM 5 D Q 40 D Q 41 D Q 42 D Q 43 D Q 44 D Q 45 D Q 46 D Q 47 LDQS / CS LDQS DM 4 D Q 32 D Q 33 D Q 34 D Q 35 D Q 36 D Q 37 D Q 38 D Q 39 UDM I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 I/ O 15 DM 1 DQ 8 DQ 9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15 / LDQ S / DQS 4 DQS 4 SCL WP A0 S A0 SDA S erial P D A1 S A1 A1 S A2 C lock S ignal Loads C lock Input SDRAMs C K 0, /C K 0 NC C K 1, /C K 1 2 C K 2, /C K 2 2 N otes: 1. D Q ,D M ,D Q S ,/D Q S resistors : 22 Ω +/- 5 % . 2. B ax,A x,/R A S ,/C A S ,/W E resistors : 10 Ω +/- 5 % . 6 1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx64) : HYMP112U64CP(R)8 /S0 /DQS0 DQS0 /DQS4 DQS4 DM0 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CS DM DQS /DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS1 DQS1 /CS I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS6 DQS6 DM6 DM /CS DM DQS /DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS3 DQS3 /CS DQS /DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS7 DQS7 DM3 DM7 DM /CS DM DQS /DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 D3 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL DQS /DQS I/O 1 I/O 2 D7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SDA Serial PD A0 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 SDRAMS D0-7 /CS I/O 0 Clock Signal Loads SCL WP Rev. 0.6 / Jul. 2008 I/O 3 DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 DM2 BA0-BA2 A0-A13 /RAS /CAS CKE0 /WE ODT0 D4 I/O 2 DQS /DQS /DQS2 DQS2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 1 DM5 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS /DQS /DQS5 DQS5 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CS I/O 0 SA0 VDD SPD Serial PD VDD /VDDQ DO-D7 VREF DO-D7 VSS DO-D7 A1 SA1 A1 SA2 Clock Input SDRAMs CK0, /CK0 2 CK1, /CK1 3 CK2, /CK2 3 Notes: 1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 Ω +/- 5 %. 7 1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx72) - HYMP112U72CP8 /S0 /DQS0 DQS0 /DQS4 DQS4 DM0 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CS DM DQS /DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS1 /DQS5 DQS1 DQS5 DM1 /CS DQS /DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CS DM DQS /DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS2 DQS2 /CS DQS /DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS6 DQS6 DM2 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CS DM DQS /DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS3 /DQS7 DQS3 DQS7 DM3 /CS DQS /DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /CS DM DQS /DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS DQS /DQS I/O 0 I/O 1 I/O 2 D7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /DQS8 DQS8 DM8 Clock Signal Loads DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0-BA2 A0-A13 /RAS /CAS CKE0 /WE ODT0 /CS DQS /DQS I/O 0 SCL D8 I/O 3 I/O 4 SDA Serial PD WP I/O 1 I/O 2 SCL Clock Input SDRAMs CK0, /CK0 3 A0 A1 A1 CK1, /CK1 3 SA0 SA1 SA2 CK2, /CK2 3 A1 I/O 5 I/O 6 I/O 7 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 SDRAMS D0-7,D8 Rev. 0.6 / Jul. 2008 V DD SPD Serial PD V DD /V DDQ DO-D8 V REF DO-D8 V SS DO-D8 Notes: 1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 Ω +/- 5 %. 8 1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx64) - HYMP125U64CP(R)8 /S1 /S0 / DQS0 DQS0 / DQS4 DQS4 DM0 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CS DQS /DQS / I/ O 0 I/ O 3 /CS DM DQS /DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/ O 0 I/ O 1 I/ O 2 DM I/ O 1 D0 I/ O 2 D8 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / DQS1 DQS1 DQS /DQS /CS DM I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 /CS DQS /DQS I/ O 2 D4 I/ O 3 D12 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / DQS5 DQS5 DM1 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CS I/ O 0 I/ O 3 /CS DQS /DQS DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/ O 0 I/ O 1 I/ O 2 DM DQS /DQS I/ O 1 D1 I/ O 2 D9 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / DQS2 DQS2 /CS DQS /DQS DM /CS DQS /DQS I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D5 I/ O 3 D13 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / DQS6 DQS6 DM2 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CS DM DQS /DQS I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 I/ O 3 D2 /CS I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 I/ O 3 I/ O 4 DM DQS /DQS / DQS3 DQS3 / DQS7 DQS7 DM3 DM7 I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 I/ O 1 I/ O 1 I/ O 2 I/ O 2 I/ O 3 D3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 BA0-BA2 A0-A15 CKE0 CKE1 /CAS /RAS /WE ODT0 ODT1 Rev. 0.6 / Jul. 2008 D11 I/ O 3 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D7 SDRAMS D8-D15 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D15 SDRAMS D0-D7 SDRAMS D8-D15 SCL SCL WP A0 A1 A1 SA0 SA1 SA2 VDD SPD Serial PD VDD /V DDQ DO-D15 V REF DO-D15 VSS DO-D15 DM I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 3 /CS DQS /DQS I/ O 2 D7 D15 I/ O 3 I/ O 4 SDA Serial PD DQS /DQS I/ O 0 DQS /DQS D14 I/ O 3 I/ O 4 /CS /CS I/ O 2 D6 I/ O 3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/ O 0 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS /DQS /CS I/ O 0 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 Clock Signal Loads Clock Input SDRAMs CK0, /CK0 4 CK1, /CK1 6 CK2, /CK2 6 Notes: 1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %. 2. Bax,Ax,/RAS,/CAS,/WE resistors : 7.5 Ω +/- 5 %. 9 1240pin DDR2 SDRAM Unbuffered DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx72) - HYMP125U72CP8 /S1 /S0 / DQS0 DQS0 / D QS4 D QS4 DM0 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 / CS DM DQ S / DQS I/ O 0 / CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 D Q 39 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D0 I/ O 3 D9 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM DQ S / DQ S / DQS1 DQS1 / CS DM DQS / DQ S / CS DQ S / DQ S I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D4 I/ O 3 D13 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / D QS5 D QS5 DM1 DM5 DM DQ8 DQ9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 / CS DM DQ S / DQS I/ O 0 / CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 D Q 47 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D1 I/ O 3 D10 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM DQ S / DQ S / DQS2 DQS2 / CS DM DQS / DQ S I/ O 0 / CS DQ S / DQ S I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D5 I/ O 3 D14 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / DQS6 DQS6 DM2 D M6 / CS DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DM DQ S / DQS I/ O 0 / CS DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D2 I/ O 3 D 11 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM DQ S / DQ S / DQS3 DQS3 / CS DM DQ S / DQ S I/ O 0 / CS DQ S / DQ S I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D6 I/ O 3 D15 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / D QS7 D QS7 DM3 DM7 DM DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 / CS DM DQ S / DQS I/ O 0 / CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 D Q 63 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 2 D3 I/ O 3 D12 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM DQ S / DQ S / CS DM DQS / DQ S I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 DQ S / DQ S I/ O 2 D7 I/ O 3 / CS I/ O 3 D16 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 / DQS8 DQS8 DM8 DM C B0 C B1 C B2 C B3 C B4 C B5 C B6 CB7 / CS DM DQ S / DQS I/ O 0 I/ O 0 I/ O 1 I/ O 1 I/ O 2 I/ O 3 I/ O 3 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 Rev. 0.6 / Jul. 2008 V DD SP D S erial PD V D D /V D D Q DO-D 17 C lock Signal Loads D 17 C lock Input SD RAM s CK0, /C K0 6 V RE F DO-D 17 CK1, /C K1 6 V SS DO-D 17 CK2, /C K2 6 I/ O 4 I/ O 5 /W E ODT0 ODT1 DQ S / DQ S I/ O 2 D8 I/ O 4 BA0-BA2 A0-A13 CKE0 CKE1 /CAS /RAS / CS SDR AM S D 0-D17 SDR AM S D 0-D17 SD RAM S D0-D8 SD RAM S D 9-D17 SDR AM S D 0-D17 SDR AM S D 0-D17 SD RAM S D 0-D17 SDR AM S D0-D 8 SDR AM S D 9-D17 SCL SCL WP S DA Serial PD A0 A1 A1 S A0 SA1 SA2 N otes: 1. DQ ,D M ,DQ S,/DQ S resistors : 22 Ω +/- 5 % . 2. Bax,Ax,/RAS,/CAS,/W E resistors : 7.5 Ω +/- 5 % . 10 1240pin DDR2 SDRAM Unbuffered DIMMs ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Note VDD - 1.0 ~ 2.3 V 1 Voltage on VDD pin relative to Vss VDDQ - 0.5 ~ 2.3 V 1 VIN, VOUT - 0.5 ~ 2.3 V 1 Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Operation Conditions and Environmental Parameters Parameter Symbol TOPR Rating 0 ~ +55 Units oC Notes TSTG -50 ~ +100 oC 1 Storage Humidity(without condensation) HSTG 5 to 95 % 1 DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal 2 DRAM Component Case Temperature Range TCASE 0 ~+95 oC 3 DIMM Operating temperature(ambient) Storage Temperature Note : 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. 2. Up to 9850 ft. 3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. DC OPERATING CONDITIONS (SSTL_1.8) Symbol Parameter Rating Min. Typ. Max. Units Notes VDD Supply Voltage 1.7 1.8 1.9 V 1 VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1,2 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1,2 VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4 VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 5 1.7 - 3.6 V VDDSPD EEPROM Supply Voltage Note: 1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device. Rev. 0.6 / Jul. 2008 11 1240pin DDR2 SDRAM Unbuffered DIMMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit dc Input logic HIGH VIH(DC) VREF + 0.125 VDDQ + 0.3 V dc Input logic LOW VIL(DC) -0.30 VREF - 0.125 V DDR2 400, 533 DDR2 667, 800 Note INPUT AC LOGIC LEVEL Parameter Symbol Unit Min Max Min Max AC Input logic High VIH(AC) VREF + 0.250 - VREF + 0.200 - V AC Input logic Low VIL(AC) - VREF - 0.250 - VREF - 0.200 V Note AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes 0.5 * VDDQ V 1 Input signal maximum peak to peak swing 1.0 V 1 Input signal minimum slew rate 1.0 V/ns 2, 3 VREF Input reference voltage VSWING(MAX) SLEW Note: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges 3. and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS VSWING(MAX) delta TF Falling Slew = delta TR VREF - VIL(ac) max Rising Slew = delta TF VIH(ac) min - VREF delta TR < Figure : AC Input Test Signal Waveform > Rev. 0.6 / Jul. 2008 12 1240pin DDR2 SDRAM Unbuffered DIMMs Differential Input AC logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential cross point voltage Min. Max. Units Note 0.5 VDDQ + 0.6 V 1 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC). VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ < Differential signal levels > Note: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. DIFFERENTIAL AC OUTPUT PARAMETERS Symbol VOX (ac) Parameter ac differential cross point voltage Min. Max. Units Note 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 0.6 / Jul. 2008 13 1240pin DDR2 SDRAM Unbuffered DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol VOTR Parameter Output Timing Measurement Reference Level SSTL_18 Units Notes 0.5 * VDDQ V 1 Note: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current SSTl_18 Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 Note: 1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Rev. 0.6 / Jul. 2008 14 1240pin DDR2 SDRAM Unbuffered DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C) 512MB : HYMP164U64CP(R)6 Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol Min Max Unit CCK CI1 CI2 CIO 18 57 42 7 22 63 48 9 pF Symbol Min Max Unit CCK CI1 CI2 CIO 22 62 42 6 30 84 64 9 pF Symbol Min Max Unit CCK CI1 CI2 CIO 22 63 43 6 30 85 66 9 pF Symbol Min Max Unit CCK CI1 CI2 CIO 22 64 50 8 35 87 88 13 pF Symbol Min Max Unit CCK CI1 CI2 CIO 23 65 52 9 35 89 92 13 pF pF pF pF 1GB : HYMP112U64CP(R)8 Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS pF pF pF 1GB : HYMP112U72CP8 Pin CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS pF pF pF 2GB : HYMP125U64CP(R)8 Pin CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS pF pF pF 2GB : HYMP125U72CP8 Pin CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS pF pF pF Note : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Rev. 0.6 / Jul. 2008 15 1240pin DDR2 SDRAM Unbuffered DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95°C) 512MB, 64M x 64 U-DIMM : HYMP164U64CP(R)6 Symbol C4 (DDR2 533@CL 4) Y5 (DDR2 667@CL 5) S5/S6 (DDR2 800@CL5&6) Unit IDD0 340 360 380 mA IDD1 440 460 480 mA IDD2P 40 40 40 mA IDD2Q 108 120 128 mA IDD2N 140 160 180 mA IDD3P(F) 80 100 100 mA IDD3P(S) 48 48 48 mA IDD3N 180 200 220 mA IDD4R 640 780 900 mA IDD4W 640 840 960 mA IDD5B 660 700 700 mA IDD6 40 40 40 mA IDD7 1040 1060 1180 mA Note 1 Note : 1. IDD6 current values are guaranted up to Tcase of 85°C max. Rev. 0.6 / Jul. 2008 16 1240pin DDR2 SDRAM Unbuffered DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95°C) 1GB, 128M x 64 U-DIMM : HYMP112U64CP(R)8 Symbol C4 (DDR2 533@CL 4) Y5 (DDR2 667@CL 5) S5/S6 (DDR2 800@CL5&6) Unit IDD0 520 560 600 mA IDD1 600 640 680 mA IDD2P 80 80 80 mA IDD2Q 216 240 256 mA IDD2N 280 320 360 mA IDD3P(F) 200 200 200 mA IDD3P(S) 96 96 96 mA IDD3N 360 400 440 mA IDD4R 1000 1200 1360 mA IDD4W 1000 1240 1440 mA IDD5B 1320 1400 1400 mA IDD6 80 80 80 mA IDD7 1400 1600 1880 mA Note 1 1GB, 128M x 72 ECC U-DIMM : HYMP112U72CP8 Symbol C4 (DDR2 533@CL 4) Y5 (DDR2 667@CL 5) S5/S6 (DDR2 800@CL 5) Unit IDD0 585 630 675 mA IDD1 675 720 765 mA IDD2P 90 90 90 mA IDD2Q 243 270 288 mA IDD2N 315 360 405 mA IDD3P(F) 225 225 225 mA IDD3P(S) 108 108 108 mA IDD3N 360 450 495 mA IDD4R 1125 1350 1530 mA IDD4W 1125 1395 1620 mA IDD5B 1485 1575 1575 mA IDD6 90 90 90 mA IDD7 1575 1800 2115 mA Note 1 Note : 1. IDD6 current values are guaranted up to Tcase of 85°C max. Rev. 0.6 / Jul. 2008 17 1240pin DDR2 SDRAM Unbuffered DIMMs 2GB, 256M x 64 U - DIMM : HYMP125U64CP(R)8 Symbol C4 (DDR2 533@CL 4) Y5 (DDR2 667@CL 5) S5/S6 (DDR2 800@CL5&6) Unit IDD0 800 880 960 mA IDD1 880 960 1040 mA IDD2P 160 160 160 mA IDD2Q 432 480 512 mA IDD2N 560 640 720 mA IDD3P(F) 400 400 400 mA IDD3P(S) 192 192 192 mA IDD3N 720 800 880 mA IDD4R 1280 1520 1720 mA IDD4W 1280 1560 1800 mA IDD5B 1600 1720 1760 mA IDD6 160 160 160 mA IDD7 1680 1920 2240 mA Note 1 2GB, 256M x 72 ECC U-DIMM : HYMP125U72CP8 Symbol C4 (DDR2 533@CL 4) Y5 (DDR2 667@CL 5) S5/S6 (DDR2 800@CL5&6) Unit IDD0 900 990 1080 mA IDD1 990 1080 1170 mA IDD2P 180 180 180 mA IDD2Q 486 540 576 mA IDD2N 630 720 810 mA IDD3P(F) 450 450 450 mA IDD3P(S) 216 216 216 mA IDD3N 810 900 990 mA IDD4R 1440 1710 1935 mA IDD4W 1440 1755 2025 mA IDD5B 1800 1935 1980 mA IDD6 180 180 180 mA IDD7 1890 2160 2520 mA Note 1 Note : 1. IDD6 current values are guaranted up to Tcase of 85°C max. Rev. 0.6 / Jul. 2008 18 1240pin DDR2 SDRAM Unbuffered DIMMs IDD MEASUREMENT CONDITIONS Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 mA Slow PDN Exit MRS(12) = 1 mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max. mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Normal Low Power mA Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.6 / Jul. 2008 19 1240pin DDR2 SDRAM Unbuffered DIMMs Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-800 (S5) DDR2-800 (S6) DDR2-667 (Y5) DDR2-533 (C4) DDR2-400 (E3) Unit Bin(CL-tRCD-tRP) 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Parameter min min min min min CAS Latency 5 6 5 4 3 ns tRCD 12.5 15 15 15 15 ns tRP 12.5 15 15 15 15 ns tRC 57.5 45 60 60 55 ns tRAS 45 60 45 45 40 ns AC Timing Parameters by Speed Grade DDR2-400 Parameter DDR2-533 Symbol Unit Note Min Max Min Max Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps DQS-Out edge to Clock edge Skew tDQSCK -500 500 -500 450 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) - ns System Clock Cycle Time tCK 5000 8000 3750 8000 ps DQ and DM input setup time tDS 150 - 100 - ps 1 DQ and DM input hold time tDH 275 - 225 - ps 1 Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK tDIPW 0.35 - 0.35 - tCK tHZ - tAC max - tAC max ps tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps tQHS - 450 - 400 ps tQH tHP - tQHS - tHP - tQHS - ps Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK tMRD 2 - 2 - tCK tWPRE 0.35 - 0.35 - tCK DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ hold skew factor DQ/DQS output hold time from DQS Mode register set command cycle time Write preamble Rev. 0.6 / Jul. 2008 20 1240pin DDR2 SDRAM Unbuffered DIMMs - continued - DDR2-400 Parameter Address and control input setup time Address and control input hold time DDR2-533 Symbol Unit Note Min Max Min Max tIS 350 - 250 - ps tIH 475 - 375 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 127.5 - 127.5 - ns Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns Four Activate Window for 2KB page size tFAW 50 - 50 - ns CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 - 15 - ns Auto Precharge Write Recovery + Precharge Time tDAL tWR+tRP - tWR+tRP - tCK Write to Read Command Delay tWTR 10 - 7.5 - ns Internal read to precharge command delay tRTP 7.5 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK Exit active power down to read command tXARD 2 2 tCK Exit active power down to read command (Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK tCKE 3 3 tCK tAOND 2 tAON Exit precharge power down to any non-read command CKE minimum pulse width (high and low pulse width) ODT turn-on delay 2 2 tAC(min) tAC(max)+1 tAONPD tAC(min)+2 2tCK+tAC(m ax)+1 tAOFD 2.5 2.5 tAOF tAC(min) tAC(max)+ 0.6 tAOFPD tAC(min)+2 2.5tCK+tA C(max)+1 ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK OCD drive mode output delay tOIT 0 tDelay tIS+tCK+tIH tREFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3 ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval 12 2 tCK tAC(min) tAC(max)+1 ns tAC(min)+2 2tCK+tAC(m ax)+1 ns 2.5 2.5 tCK tAC(min) tAC(max)+ 0.6 ns tAC(min)+2 2.5tCK+tA C(max)+1 ns 0 12 tIS+tCK+tIH ns ns Note : 1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[8, 16]31CFP). 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 0.6 / Jul. 2008 21 1240pin DDR2 SDRAM Unbuffered DIMMs Parameter Symbol DDR2-667 DDR2-800 min max min max Unit Note DQ output access time from CK/CK tAC -450 +450 -400 +400 ps DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) - min(tCL, tCH) - ps Clock cycle time, CL=x tCK 3000 8000 2500 tDS 100 - 50 - ps 1 tDH 175 - 125 - ps 1 Control & Address input pulse width for each input tIPW 0.6 - 0.6 - tCK DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 - tCK Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 - 200 ps DQ hold skew factor tQHS - 340 - 300 ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps First DQS latching transition to associated clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write preamble tWPRE 0.35 - 0.35 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Address and control input setup time tIS 200 - 175 - ps Address and control input hold time tIH 275 - 250 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 127.5 - 127.5 - ns Active to active command period for 1KB page size products tRRD 7.5 - 7.5 - ns Active to active command period for 2KB page size products tRRD 10 - 10 - ns Four Active Window for 1KB page size products tFAW 37.5 - 35 - ns Four Active Window for 2KB page size products tFAW 50 - 45 - ns DQ and DM input setup time (differential strobe) DQ and DM input hold time (differential strobe) Rev. 0.6 / Jul. 2008 ps 22 1240pin DDR2 SDRAM Unbuffered DIMMs - continued Parameter Symbol DDR2-667 min DDR2-800 max min max CAS to CAS command delay tCCD 2 Write recovery time tWR 15 - 15 - ns Auto precharge write recovery + precharge time tDAL 2 Unit Note tCK WR+tRP - WR+tRP - tCK Internal write to read command delay tWTR 7.5 - 7.5 - ns Internal read to precharge command delay tRTP 7.5 7.5 ns tRFC + 10 ns Exit self refresh to a non-read command tXSNR tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK Exit precharge power down to any non-read command tXP 2 - 2 - tCK Exit active power down to read command tXARD 2 2 tCK tXARDS 7 - AL 8 - AL tCK tCKE 3 3 tCK tAOND 2 2 2 2 tCK tAC(min) tAC(max) +0.7 tAC(min) tAC(max) +0.7 ns tAC(min)+2 2tCK+ tAC(max)+1 tAC(min) +2 2tCK+ tAC(max)+1 ns 2.5 2.5 2.5 2.5 tCK tAC(min) tAC(max) +0.6 ns tAC(min) +2 2.5tCK+ tAC(max)+1 ns Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on tAON ODT turn-on(Power-Down mode) tAONPD ODT turn-off delay tAOFD ODT turn-off tAOF tAC(min) tAC(max)+ 0.6 ODT turn-off (Power-Down mode) tAOFPD tAC(min) +2 2.5tCK+ tAC(max)+1 ODT to power down entry latency tANPD 3 ODT power down exit latency tAXPD 8 OCD drive mode output delay tOIT 0 Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval tDelay 3 tCK 8 12 0 tCK 12 tIS+tCK +tIH tIS+tCK+tIH ns ns tREFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3 Note : 1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[8,16]31CFP). 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 0.6 / Jul. 2008 23 1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 64Mx 64 - HYMP164U64CP(R)6 Front 133.35 Side 128.95 2.7 max (Front) 4.0±0.1 30.0 Detail-B Detail-A 5.175 5.175 63.0 5.0 (2) 2.5 1. 27 ±0.10 55.0 10.0 17.80 Back 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 0.20 2.50 ±0.20 Detail of Contacts A 0.8 ±0.05 1.50 ±0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.6 / Jul. 2008 24 1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 128Mx 64 - HYMP112U64CP(R)8 Front Side 133.35 128.95 2. 7 max (Front) 4.0±0.1 30.0 Detail-B 5.175 5.175 63.0 (2) 2.5 Detail-A 5.0 1. 27 ±0.10 55.0 10.0 17.80 Back 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 0.20 2.50 ±0.20 Detail of Contacts A 0.8 ±0.05 1.50±0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.6 / Jul. 2008 25 1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 128Mx 72 - HYMP112U72CP8 Front Side 133.35 128.95 2. 7 max (Front) 4.0±0.1 30.0 5.175 5.175 (2) 2.5 63.0 Detail-A 5.0 1. 27 ±0.10 55.0 Detail-B 10.0 17.80 Back 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 0.20 2.50 ±0.20 Detail of Contacts A 0.8 ±0.05 1.50 ±0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.6 / Jul. 2008 26 1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 256Mx 64 - HYMP125U64CP(R)8 Front Side 133.35 128.95 4.00 max. 4.0±0.1 30.0 Detail-B 5.175 5.175 (2) 2.5 63.0 Detail-A 5.0 1.27 ± 0.10 55.0 10.0 17.80 Back 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 0.20 2.50 ±0.20 Detail of Contacts A 0.8 ±0.05 1.50 ±0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.6 / Jul. 2008 27 1240pin DDR2 SDRAM Unbuffered DIMMs PACKAGE OUTLINE 256Mx 72 - HYMP125U72CP8 Front Side 133.35 128.95 4.00 max. 4.0±0.1 30.0 Detail-B 5.175 5.175 (2) 2.5 63.0 Detail-A 5.0 1.27 ± 0.10 55.0 10.0 17.80 Back 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 0.20 2.50 ±0.20 Detail of Contacts A 0.8±0.05 1.50±0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.6 / Jul. 2008 28 1240pin DDR2 SDRAM Unbuffered DIMMs REVISION HISTORY Revision History Date 0.1 Initial data sheet released Jan. 2007 0.2 Updated SPEED GRADE & KEY PARAMETERS Feb. 2007 0.3 Updated IDD spec and corrected typos May 2007 0.4 Updated IDD spec Jun. 2007 0.5 S6 items added Sep. 2007 0.6 Updated IDD and Halogen-Free added Jul. 2008 Rev. 0.6 / Jul. 2008 29