ETC AN17831A

Prepared
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AN17831A
Approved
C-1
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9
Page No.
3
Description of Test Circuits and Test Methods
[Test Circuit 1]
AN17831A
1
Vcc
2
3
+
2200µ
4
5
+
10µ
6
Vout1
51kΩ
RL 4Ω
20kΩ
7
8
33µ
9
10
+
8.2kΩ
11
12
Vout2
RL 4Ω
20kΩ
STB
ON
MUTE
OFF
OFF
Vin1
5V
ON
Vin2
3V
Note : * STB 'OFF' means 5V.
MUTE 'OFF' means 0V.
Eff. Date
Eff. Date
Eff. Date
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev.1
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
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Page No.
4
Circuit Function Block Diagram
-
-
REF
-
+
+
+
+
Protection Circuit
Thermal Shutdown
Load Short
Vcc Short
Ground Short
ASO Protect
+
+
-
Standby
Circuit
1
2
3
4
MUTE
5
6
7
8
9
10
11
12
Pin Descriptions
Pin No.
1
2
3
4
5
6
Eff. Date
Pin Descriptions
Vcc
Ch1 +ve Phase Output
Ch1 Output GND
Ch1 -ve Phase Output
Standby
Ch1 Input
Eff. Date
Eff. Date
Pin No.
7
8
9
10
11
12
Pin Descriptions
Pre GND
Ch2 Input
Mute
Ch2 -ve Phase Output
Ch2 Output GND
Ch2 +ve Phase Output
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev.1
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
Prepared
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AN17831A
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Package Name
Ref No.
E
Total Page
9
Page No.
5
FP-12S
Unit : mm
6.4 ± 0.3
7.7 ± 0.3
7.8 ± 0.3
29.6 ± 0.3
3.5 ± 0.3
1.2 ± 0.1
+0.1
0.25 -0.05
1
2.54
0.6
R1.8
0.6 ± 0.1
20.0±0.1
28.0 ± 0.3
29.96 ± 0.3
12
∅ 3.6
Name
of item
Date
Code
Company
insignia
Eff. Date
Eff. Date
Eff. Date
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev.1
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
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F-1
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Page No.
6
(Structure Description)
Chip surface passivation
SiN,
PSG,
Others (
)
1
Lead frame material
Fe group,
Cu group,
Others (
)
2 , 6
Inner lead surface process
Ag plating,
Au plating,
Others (
)
2
Outer lead surface process
Solder plating, Solder dip,
Others (
)
6
Chip mounting method
Ag paste,
Au-Si alloy, Solder, Others (
)
3
Wire bonding method
Thermalsonic bonding,
Others (
)
4
Mold material
Epoxy,
Others (
)
4
Molding method
Transfer mold, Multiplunger mold,
Others (
)
5
Fin material
Cu Group
Others (
)
5
Package FP-12S
1
4
5
6
3
2
Eff. Date
Eff. Date
Eff. Date
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev.1
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
Prepared
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Product Specifications
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Page No.
7
Application Circuit
VCC
12V
Input
GND
7
2200µ
VCC
1
OUT1
40dB
2
Output1
GND
6
IN 1
3
40dB
51k
4
OUT1
5
STB
10µ
RL
4Ω
STB
Vref
MUTE
8.2k
9
MUTE
33µ
40dB
OUT2
10
Output2
GND
11
8
IN 2
40dB
RL
4Ω
12
OUT2
STB 'OFF'
STB 'ON'
Mute 'OFF'
Mute 'ON'
Eff. Date
Eff. Date
5V
0V
0V
3V
Eff. Date
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev.1
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
Prepared
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Checked
AN17831A
Approved
Ref No.
G-2
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9
Page No.
8
PD - Ta Curves
(1) Tc = Ta, 62.5W ( θj-c = 2 °C/W )
(2) 20.83W ( θf = 4.0 °C/W )
With a 100cm 2X 3mm Al heat sink (black colour coated)
or a 200cm 2X 2mm Al heat sink (not lacquered)
(3) 15.63W ( θf = 6.0 °C/W )
2
With a 100cm X 2mm Al heat sink (not lacquered)
(4) 3.0W at Ta = 25°C ( θj-a = 42°C/W )
Without heat sink
80
70
62.5W
Power Dissipation PD ( W )
60
(1)
50
40
30
20.8W
20
(2)
15.6W
(3)
10
3.0W
(4)
0
0
25
50
75
100
125
150
Ambient Temperature Ta ( °C )
Eff. Date
Eff. Date
Eff. Date
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev. 1
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
Prepared
Product Specifications
Checked
AN17831A
Approved
Ref No.
H-1
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Page No.
9
(Precautions for use)
1) Be sure to attach a heat sink to the IC before use. Make sure that the heat sink is secured to
the chassis.
2) Ground the radiation fin so that there will be no difference in electric potential between the
radiation fin and ground.
3) The thermal protection circuit operates at a Tj of approximately 150°C. The thermal
protection circuit is reset automatically when the temperature drops.
4) The overvoltage protection circuit operates at a Vcc of approximately 28V.
5) Use a stabilised power supply with a 3V or higher standby voltage.
Eff. Date
Eff. Date
Eff. Date
Eff. Date
18-FEB-2002
FMSC-PSDA-002-01 Rev1.
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.