AV3168/69 VIDEO PERFORMANCE Item 1 2 3 4 Specification Attenuation of Luminance Signal 0 - 5 Mhz +/- 0.1 dB 6 Mhz > 3dB 9 Mhz > 35 dB 0.4 MHz < 1dB 1 MHz 5 dB 2 MHz > 25 dB Attenuation of PAL Color Difference Signal 1.3 MHz < 2dB 3.6 MHz > 20dB Attenuation of Component Color Difference Signal 2 MHz < 3 dB 5 MHz > 38 dB Attenuation of NTSC Color Difference Signal 5 Luma SNR 6 Chroma SNR > 82 dB AM > 64 dB PM > 60 dB 7 Differential Gain < 0.5% 8 Differential Phase < 1 degree 9 Y/C Delay +/- 2 nsec. 10 Y/C Gain inequality +/- 2% 11 Y/C Intermodulation < 0.7 IRE 12 SCH < 4 degree 3-24 January 4, 2001 AV3168 Detailed Block Diagram VSYN 70 EAV MSTR HSYN 69 68 PDEN CPNT 43 42 AV3168 FMT Video Timing Generation CONT MONO CMOD[1:0] BRTN MUX 2 PD<7:0> DEMUX Y Pedestal Contrast 5 MHz Y 10 CVBS Cb 4 Cr Modulation & Gain LPF SCL Color Space Conv. GEN. CCC GCK XOUT XIN 69 GOUT0 68 GOUT1 R, Cb G,Y B, Cr CLOCK 69 Y, R, Y D/A 36 C, G, Cb Anti-Tapping CK27 70 36 PALMN Gen MacroVision K[1:0] ACK D/A CVBS, B, Cr 10 f sc I 2C Serial I/F 39 C FSEL[1:0] SDA D/A RST Figure 1 Close Caption 10 AV3168/69 VDDA 29 VSS 30 Y 31 VDDA 32 C 33 VSS 34 CVBS 35 VDDA BIAS 37 36 COMP 38 39 IREF PIN DESCRIPTIONS 23 SDA XIN 2 22 VDD MSTR 3 21 HSYN VSS 4 20 VSYN VDD 5 19 PD7 RST 6 18 PD6 17 1 VSS XOUT 16 SCL PD5 24 15 44 PD4 GOUT1 14 ACK PD3 25 13 43 PD2 GOUT0 12 VSS PD1 26 11 42 PD0 VSS 10 CPNT VDD 27 9 41 CK27 VSS 8 PDEN VSS 28 7 40 GCK VREF 5-24 January 4, 2001 AV3168/69 PIN DESCRIPTIONS Pin Name Pin # Type Description DIGITAL VIDEO INPUT PD<7 -0> 11-16 18-19 I Multiplexed Cb, Y, and Cr digital video input bus. HSYN 21 I/O In Slave Mode (MSTR pin is low) Horizontal Synch input. In Master Mode (MSTR pin is high) Horizontal Synch output. VSYN 20 I/O In slave mode (MSTR pin is low) Vertical Sync input. In master mode Vertical Sync output. VIDEO CONTROL SIGNALS MSTR 3 I Master Mode; If this pin is high, the chip outputs horizontal and vertical sync signals. Otherwise it receives both horizontal and vertical sync signals. CPNT 27 I Select either component or composite video output. 0: Simultaneous Composite and S-Video output. 1: Component video output either RGB or YCbCr determined by the register CR0[5:4]. PDEN 28 1 Pedestal enable pins. When this pin is high 7.5 IRE is added for the NTSC composite analog output. VIDEO ANALOG OUTPUT, REFERENCE AND COMPENSATION CVBS 35 O Analog video output Determined by the state of CPNT pin and CR0[5:4] CPNT CR0[5] CR0 [4] --- 0 ---- X------ X: ---Composite video output --- 1----- X------ 0: --- Cr output in YCbCr component mode --- 1 ---0 0------X: --- 1111111111- :: --- 1------1------ 1: ----Blue color output in RGB mode Y 31 O Analog video output Determined by the state of CPNT pin and CR0[5:4] CPNT CR0[5] CR0 [4] --- 0 ----- X----- X: ---S-Video Y output. --i 1------ X---- - 0: ---Y output in YCbCr component mode --- 1 ---0 0------X: -- 1111111111- :: - i 1 ----- 1--- -- 1: - -R color output in RGB mode 6-24 January 4, 2001 AV3168/69 PIN DESCRIPTIONS (Continued) Pin Name Pin # Type Description C 33 O Analog video output Determined by the state of CPNT pin and CR0[5:4] CPNT CR0[5] CR0 [4] --- 0 ------ X------X: --S-Video C output. ---- 1 ------ X-----0:---Cb output in YCbCr component mode --1 1 ------ 0 ---- X:1111111- :: --1 1 ------ 1------1:--Green color output in RGB mode VREF 40 I/O Voltage reference. It has an internal voltage reference circuit, but may be overridden by an external voltage reference input. A 0.1 uF ceramic capacitor is required between this pin and GND. IREF 39 I A resistor should be connected between this pin and GND to control the DAC output current. The recommended value is 198 (382) ohm 1% metal film resistor for double (single) end 75 ohm termination. COMP 38 I Compensation capacitor for the DAC internal reference amplifier. A 0.1 uF ceramic capacitor is required between this pin and VDDA. BIAS 37 I/O DAC bias voltage. A 0.1 uf ceramic capacitor must be used to decouple this pin to VDDA. SERIALCONTRL BUS SCL 24 I Serial bus clock SDA 23 I/0 Serial bus address and data input and output pin. Open drain output. O General Purpose Clock. Clock frequency is determined by the state of GOUT[1:0] when RST pin is low. CLOCK SIGNALS GCK 7 00 : 40.5 MHz clock output. 0 1: 54.0 MHz clock output. 1 0: 67.5 Mhz clock output. 1 1: 81.0 MHz CK27 9 O 27 MHz clock output pin. ACK 25 I/O 384*fs Audio clock output pin. Controlled by CR2[1:0] 0 0: 384 * 48.0 KHz (18.432MHz) clock output. 0 1: 384 * 44.1 KHz (16.934MHz) clock output. 1 0. 384 * 96.0 KHz (36.864MHz) clock output. 1 1: 384 * 88.2 KHz (33.868MHz) clock output. 7-24 January 4, 2001 AV3168/69 PIN DESCRIPTIONS (Continued) Pin Name Pin # Type Description XIN 2 I 27 Mhz oscillator input XOUT 1 O 27 Mhz oscillator output MISCELLANEOUS SIGNALS RST 6 I GOUT1 44 I/O Dual function pin. GCK frequency select pin when RST is low. General purpose output pin when RST is high GOUT0 43 I/O Dual function pin. GCK frequency select pin when RST is low. General purpose output pin when RST is high Active low chip reset input. Chip is in the power down mode when the RST is low. POWER AND GROUND VDD 10, 22, 5 +5V Digital power supply. VSS 8, 17, 26, 30, 34, 41, 42, 4 GND Digital ground VDDA 29, 32, 36. +5V Analog video power supply. 8-24 January 4, 2001 AV3168/69 VIDEO TIMING GENERATION The video encoder can operate as a master or a slave in the timing generation. In the master mode, the video encoder outputs SYNC signals. In the slave mode, the internal timing is lock to the external SYNC signals. MASTER MODE If the MSTR pin is high, the video encoder operates in the master mode. It uses the internal counters to generate the video timing and outputs HSYN and VSYN. The HSYNs are asserted for 64 pixel times. The negative transition of the HSYNs occur in the Cb slot. The VSYNs are asserted for 3 line times for NTSC and 2.5 for PAL. The co-incident negative transitions of HSYN and VSYN indicate the beginning of an odd field. The negative transition of the VSYN while the HSYN is high indicates the beginning of an even field. SLAVE MODE In the slave mode operation, the decoder automatically detects the input format and locks the internal timing counters to the external synchronization signals. It support 2 types of synch inputs: (a) HSYN / VSYNC, or (b) CCIR656 EAV data. If EAV is present, the video encoder synchronized to the EAV packets according to CCIR656 specifications to generate the video timing. HSYN and VSYN signals are ignored. If EAV is not present, the Video Encoder uses the signals presented on HSYN and VSYN for line and field counter increment. If register CR0[3] is low the encoder assumes the negative transition of the HSYN should be co-incited with the Cb0 datum. If CR0[3] is high it assume the transition co-incited with Y0 datum. NTSC VERTICAL INTERVAL TIMING Blanked 524 525 1 2 3 4 5 6 7 8 9 10 - 20 VSYN Field One Blanked 262 263 264 265 266 267 268 269 270 271 272 273 - 280 VSYN Field Two 9-24 January 4, 2001 AV3168/69 PAL VERTICAL INTERVAL TIMING Blanked Field 1 & 5 621 622 623 624 625 1 2 3 4 5 6 7 - 20 VSYN Blanked Field 2 &6 309 310 311 312 313 314 315 316 317 318 319 320 - 333 VSYN Blanked Field 3 & 7 621 622 623 624 625 1 2 3 4 5 6 7 - 20 VSYN Blanked Field 4 & 8 309 310 311 312 313 314 315 316 317 318 319 320 - 333 VSYN 10-24 January 4, 2001 AV3168/69 LUMINANCE PROCESSING The luminance, Y, are interpolated to 27 Mhz sampling rate through a multi-tap linear poly-phase filter. The filter frequency response is flat from 0 to 5 MHz. Contrast and Brightness control are provided for minor adjustment only. Contrast Control Item CREG1<1:0> Contrast 1 00 Normal 2 01 Less Contrast 3 10 Least Contrast 4 11 High Contrast . Brightness Control Item CREG1<3:2> Contrast 1 00 Normal 2 01 Modest Brightness 3 10 High Brightness 4 11 Less Brightness LUMINANCE FILTER luminance Filter Frequency Response 0 Attenuation (dB) -10 -20 -30 -40 -50 0 2 4 6 8 Frequency (Mhz) 11-24 10 12 January 4, 2001 AV3168/69 CHROMINANCE PROCESSING The Cb and Cr signals are filtered and interpolated to 27 Mhz. The filter has 3 bandwidth: 0.675, 1.3 or 2 MHz. The filter bandwidth can be either auto select or user select via control register CREG<7:6>. Chroma Filter Bandwidth Control Item CREG2<7:6> Chroma Bandwidth 1 00 auto-select 2 01 0.675 Mhz 3 10 1.375 MHz. 4 11 2.0 MHz CHROMINANCE FILTER Chrominance Filter Frequency Response 0 Attenuation (dB) Component -10 NTSC PAL -20 -30 -40 -50 0 1 2 3 4 Frequency (MHz) 12-24 5 6 January 4, 2001 AV3168/69 CLOCK FREQUENCY CONTROL The system clock, GCK, output frequency is determined by the state of two general purpose output pins (GOUT0 and GOUT1) while the RST pin is low. The output frequencies are. System Clock Item Frequency (MHz) GOUT<1:0> 1 00 40.5 2 01 54.0 3 10 67.5 4 11 81.0 The ACK outputs 384 times 40.5, 48 or 96 KHz audio clock. The clock frequency is selected via Control Register. CR2 <1:0> . Audio Clock Item CR2<1:0> Audio Sampling Frequency (KHz) Clock Frequency (MHz) 1 00 48.0 18.432 2 01 44.1 16.934 3 10 96.0 36.864 4 11 88.2 33.869 13-24 January 4, 2001 AV3168/69 CONTROL and CLOSED CAPTION REGISTER DESCRIPTION The AV3168 contains three 8-bit registers for timing generation, luma and chroma processing control, clock generation and power management. Additionally it contains 4 Closed Caption Data Registers. These registers are programmed via the 7-bit address I2C bus. I2C Address = 0X65. (I2C bus Address = 0x64 for AV3169). The protocol is 7- bit chip address followed by 8- bit register address and 8-bit register data. Control Register 0, CR0 (Address: 0x0, Default Value: 0x00) Item 1 Register Bits CR0[7:6] Mnemonic FSEL[1:0] #bits 2 Description Chroma Filter Selection 00: Automatic bandwidth assignment based on the output format selection (default) 01: 0.675 MHz bandwidth 10: 1.36 MHz bandwidth 11: 2 MHz bandwidth 2 CR0[5:4] CMOD[1:0] 2 Component Output Selection. Valid only If pin 27 CPNT pin is ‘1’. 00: Sony Betacam (Default) 01: Mashushita M-II 10: SMPTE 11: RGB 3 CR0[3] SDLY 1 Input Hsyn negative transition position 0: The Negative HSYNC transition coincided with Cb0 datum (Default) 1: The Negative HSYNC transition co-incited with Y0 datum. 4 CR0[2] SCH 1 Subcarrier horizontal sync phase control (SCH) 0: Subcarrier reset every 4 fields for NTSC and every 8 field for PAL (Default), SCH =0 according CCIR 624 Spec. 1: Subcarrier free running. 5 CR0[1] PALMN 1 Enable South American PALM and PALN 0: Non-South American Mode, PAL(BDGHI), or NTSC (Default). 1: South American Mode (Pal-M, Pal-N) 6 CR0[0] FMT0 1 Used in master mode only to select either 525 or 625 line system timing. 0: 525-line M system (Default) 1: 626-line system. 14-24 January 4, 2001 AV3168/69 Control Register 1, CR1 (Address: 0x01, Default Value: 0x00) Register Bits Mnemonic 1 CR1[7] 2 Item #bits Description VBIOFF 1 Vertical Blanking Interval disable. 1: Vertical interval (VBI) is not blanked 0: VBI Blanked (Default) For M system line 1-21, 262-284, 525 are blanked. For 625 line system line 1-22, 311-335, 624 - 625 are blanked. CR1[6:5] CCC 2 Close Caption enable 00: Disable Closed Caption Data (Default) 10: Enable Closed Caption Data on odd field only. 01: Enable Closed Caption Data on even field only. 11: Enable Closed Caption Data on all fields 3 CR1[4] YDLY 1 Luma Delay Control 0: Luma output not delayed (Default) 1: Luma output delayed by 74ns 4 CR1[3:2] BGT 2 Brightness Control 00: Brightness Control Off (Default) 01: Moderate Brightness Gain 10: Most Brightness Gain 11: Least Brightness Gain 5 CR1[1:0] CON 2 Contrast Control 00: Contrast Control Off (Default) 01: 15/16 * Luma Gain 10: 14/16 * Luma Gain 11: 17/16 * Luma Gain Control Register 2, CR2 (Address: 0x02, Default Value: 0x00) Item Register Bits Mnemonic #bits Description 1 CR2[7] BW 1 Monochrome Display 0: Color Display (Default) 1: Monochrome Display 2 CR2[6] PWDCV 1 Composite DAC Power Down control. 0: Enable CVBS DAC (Default) 1: Power Down CVBS DAC 3 CR2[5] PWDYC 1 S-video DACs Power Down control. 0: S-video DAC On (Default) 1: S-video DAC Power Down 15-24 January 4, 2001 AV3168/69 Control Register 2, CR2 (Address: 0x02, Default Value: 0x00) Item Register Bits Mnemonic #bits Description 4 CR2[4] GOUTEN 1 General purpose register GOUT<1:0> Output Enable. 0: Pin 44 and 43 in high impedance state. 1: Gout<1:0> are output to pin 44 and 43. 5 CR2[3:2] GOUT[1:0] 2 General purpose output registers. These registers connected to pin 44 and 43 respectively. 6 CR2[1:0] K[1:0] 2 Audio clock, ACK, output frequency select 00: 48 * 384 KHz 01: 44.1 * 384 KHz 10: 96.0 * 384 KHz 11: 88.2 * 384 KHz Extended Closed Caption Register 0 (Address: 0x03, Default Value: 0x00) Register ECC[15:8] Mnemonic ECC[15:8] #bits 8 Description Extended Closed Caption Data (Upper byte) Extended Closed Caption Register 1 (Address: 0x04, Default Value: 0x00) Register ECC[7:0] Mnemonic ECC[7:0] #bits 8 Description Extended Closed Caption Data (Lower byte) Closed Caption Register 0 (Address: 0x05, Default Value: 0x00) Register CC[15:8] Mnemonic CC[15:8] #bits 8 Description Closed Caption Data (Upper byte) Closed Caption Register 1 (Address: 0x06, Default Value: 0x00) Register CC[7:0] Mnemonic CC[7:0] #bits 8 16-24 Description Closed Caption Data (Lower byte) January 4, 2001 I2C Bus Control Register write example: I2C Bus Control Register write example: Start SDA CA6 1 CA0 R/W ACK A7 1 1 Start SDA SCL CA6 1 CA0 R/W ACK A7 1 1 1 1 SCL Chip adrress: CA<6:0> = 65H Register address: A<7:0> = 00H DATA: D<7:0> = 30H Chip adrress: CA<6:0> = 65H Register address: A<7:0> = 00H DATA: D<7:0> = 30H A0 A0 ACK D7 ACK D7 D0 ACK D0 ACK Stop Stop AV3168/69 APPLICATION CIRCUIT De-coupling and Analog Connections +5V Connector FERRITE-BEAD C10 47 uF 47uF C1 5 BIAS C7 VDDA 10 VDD C8 C3 AV3168 C4 C5 COMP C2 22 CSVB C9 Y 27.0000 MHz 29,32,36 12~22pF C 35 31 VLPF Video 33 XIN 75 ohm IREF XOUT +5 V 196 ohm 12~22pF VREF 1.5 K C6 SDL 2 I C SDA 100 ohm GOUT1 GOUT0 GCK Selection C1 -C10 are 0.1 uF Capacitors +5 V Reconstruction Filter (VLPF) for The Double End 75 Ohm Termination 22 pF 1.8 uH Video Output 75 ohm 180 pF 18-24 TV 180 pF 75 ohm January 4, 2001 AV3168/69 DIGITAL VIDEO INPUT PORT TIMING DIAGRAM . tck27L tck27H CK27 tpdhd tpdsu PD<7:0> Figure 1: Pixel Bus . CK27 tsyhd tsysu HSYN VSYN Figure 2: Horizontal Sync and Vertical Sync Signals tSU;STA tBUF SDA tSU;DAT tHD;STA tSU;STO tHIGH SCL P S Sr P tLOW tR tF tHD;DAT Figure 3: I 2C Serial Port Timing 19-24 January 4, 2001 AV3168/69 ABSOLUTE MAXIMUM RATINGS Symbol Characteristics VDD Power Supply Voltage (Measured to GND) Vi Digital Input Applied Voltage2 Min -0.5 Max Units +7.0 V GND-0.5 3,4 Ai Digital Input Forced Current Vo Digital Output Applied Voltage2 3,4 V -100 100 mA GND-0.5 VDD+0.5 V -100 100 mA Ao Digital Output Forced Current TDsc Digital Short Circuit Duration (single output high state to Vss) 1 Sec TASC Analog Short Circuit Duration (single output to VSS1) infinite Sec Ta Ambient Operating Temperature Range -25 +125 o C Tstg Storage Temperature Range -65 +150 o C Tj Junction Temperature (Plastic Package) -65 +150 o C Tsol Lead Soldering Temperature (10 sec., 1/4” from pin) 300 o Tvsol Vapor Phase Soldering (1 minute) 220 Tstor Storage Temperature -65 +150 C oC oC Notes: 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. 20-24 January 4, 2001 AV3168/69 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics VDD Power supply voltage Vref Reference voltage Iref Min Typical 4.35 5 Max Units 5.25 V 1.235 V Reference current 3.15 mA RL Analog output load 37.5 Ta Ambient operating temperature range 0 Ω 70 70 o C ELECTRICAL CHRACTERISTICS Symbol Characteristics Min Typ Max Units Supply IDD Total Power Supply Current, Analog + Digital 130 TBD mA IDDQ Total Power Supply Current, DAC Power Down 37 TBD mA Digital Characteristics VIH Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. 2.0 VDD V VIL Digital Input Voltage, Logic LOW, TTL Compatible Inputs VSS 0.8 V IIH Digital Input Current, Logic HIGH, (VIN=4.0V) 10 µA IIL Digital Input Current, Logic LOW, (VIN=0.4V) -10 µA CIN Digital Input Capacitance (f=1Mhz, VIN=2.4V) 7 pF VOH Digital Output Voltage, Logic HIGH, CMOS Compatible Outputs (IOH= -1mA) 3.7 VDD V VOL Digital Output Voltage, Logic LOW, CMOS Compatible Outputs (IOL=4.0 mA) VSS 0.4 V IOZH Hi-Z Leakage Current, HIGH, VDD=Max, VIN=VDD) 10 µA IOZL Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) -10 µA CI Digital Input Capacitance (TA=25oC, f=1Mhz) 8 pF CO Digital Output Capacitance (TA=25oC, f=1Mhz) 10 pF +30 ppm Mhz Video Clock and Oscillator Signal FX Crystal Oscillator Input Frequency F27 27 Mhz Clock,CK27, Frequency tck27H CK27 Pulse Width, HIGH -30 ppm 10 21-24 27.0000 27.0000 Mhz 18.5 ns January 4, 2001 AV3168/69 Symbol tck27L Characteristics CK27 Pulse Width, LOW Min 14.5 Typ Max Units 18.5 ns Video Bus Master Mode Timing tpdsu tpdhd tsysu tsyhd Digital Pixel Data P<7:0> Input Setup Time 8 ns Digital Pixel Data P<7:0> Input Hold Time 3 ns HSYN and VSYN Output Setup Time 10 ns HSYN and VSYN Output Setup Time 6 ns Digital Pixel Data P<7:0> Input Setup Time 8 ns Digital Pixel Data P<7:0> Input Hold Time 3 ns HSYN and VSYN Input Setup Time 8 ns HSYN and VSYN Input Setup Time 3 ns Video Bus Slave Mode Timing tpdsu tpdhd tsysu tsyhd Miscellaneous Digital Signals tpwd RST, active low reset time µs 1 Serial Port Timing fsc tsu;sta thd;sta tsu;sto tLOW tHIGH tr tf tsu;DAT thd;DAT tvd;DAT tBUF SCL Clock Frequency 100 kHz Start condition set up time 4.7 us Start condition hold time 4.0 us Stop condition set up time 4.0 us SCL Low time 4.7 us SCL High time 4.0 us SCL & SDA rise time 1.0 us SCL & SDA fall time 0.3 us Data set-up time Data hold time 250 ns 0 ns SCL LOW to data out valid 3.4 Bus Free time us 4.7 us Analog Video (DAC) Outputs RES DAC Resolution 10 PSRR Power Supply Rejection Ratio (Full Scale Output) COMP=0.1 µ F, f=DC to 1 Mhz, VRIP= 100 mV p-p.) TBD VRO Voltage Reference (VREF) Output 1.112 ZR Voltage Reference Output Impedance KDAC DAC Gain Factor dB 1.235 1.359 V KΩ 10 10.31 22-24 bits 10.85 11.39 January 4, 2001 AV3168/69 Symbol Characteristics Min Typ -1 Max Units KIMBAC KDAC Imbalance Between DACs IREF DAC Reference Current (IREF=Nominal) 3.15 mA RREF Reference Resistor (VRO=Nominal) 196 Ω VBLANK Blanking Level Output Voltage (NTSC and PAL Modes) 0.300 V VOC Video Output Compliance Voltage COUT Video Output Capacitance (Iout=0 mA, f=1Mhz) RL Total Output Load Resistance TDOV Analog Output Delay 23-24 +1 -0.3 1.6 % V 20 pF 37.5 Ω 20 ns January 4, 2001 AV3168/69 PACKAGING INFORMATION 44-Pin Plastic Leaded Chip Carrier (PLCC) B A 39 29 28 7 18 17 40 44 1 45 6 D C a b f g h d e Dimensions max A norm min 2.15 B 1.27 1.07 unit max norm mm. d 0.53 0.406 mm. e 16.00 15.748 mm. f min 0.33 unit mm. mm. C 1.22 D 0.81 0.736 mm. g 3.04 2.565 mm. a 17.65 17.526 mm. h 4.57 4.368 mm. b 16.66 16.612 mm. 24-24 0.51 mm. January 4, 2001