ETC BT827BKRF

Advance Information
This document contains information on a product under development. The parametric information contains target
parameters that are subject to change.
Bt829B/827B
VideoStreamII Decoders
Distinguishing Features
Bt829B– Video Capture Processor and Scaler for
TV/VCR Analog Input
•
Bt827B– Composite Video and S-Video Decoder
•
•
The Bt829B and Bt827B VideoStream™ Decoders are a family of single-chip, pinand register-compatible, composite NTSC/PAL/SECAM video and S-Video decoders. They are also pin and register backward compatible with the Bt829A/827A
family of products. Low operating power consumption and power-down capability make them ideal low-cost solutions for PC video capture applications on both
desktop and portable system platforms with a 3.3 V digital I/O interface. They
support square pixel and CCIR601 resolutions for NTSC, PAL, and SECAM video.
They have a flexible pixel port which supports a variety of system interface configurations, and they are offered in a 100-pin Plastic Quad Flat Pack (PQFP).
•
•
•
•
Functional Block Diagram
XT0
•
XT1
•
Ultralock
and
Clock
Generation
AGC
YREF+
YIN
YREF–
40 MHz
ADC
CREF+
CIN
CREF–
40 MHz
ADC
Luma-Chroma
Separation
and
Chroma
Demodulation
I2C
•
JTAG
Video
Timing
Unit
Spatial and
Temporal
Scaling
Video
Timing
Output Formatting
Analog
MUX
Decimation LPF
MUX0
MUX1
MUX2
MUX3
MUXOUT
SYNCDET
REFOUT
•
•
Output
Control
16
Output
Data
•
•
•
•
•
•
•
•
•
•
Single-chip composite/S-Video NTSC/PAL/
SECAM to YCrCb digitizer
On-chip Ultralock
Square Pixel and CCIR601 Resolution for:
– NTSC (M)
– NTSC (M) without 7.5IRE pedestal
– PAL (B, D, G, H, I, M, N, N
combination)
– SECAM
Chroma comb filter
Arbitrary horizontal and 5-tap vertical
filtered scaling
Hardware closed-caption decoder
Vertical Blanking Interval (VBI) data
pass-through
Arbitrary temporal decimation for a
reduced frame-rate video sequence
Programmable hue, brightness, saturation,
and contrast
User-programmable cropping of the video
window
2x oversampling to simplify external
analog filtering
Two-wire Inter-Integrated Circuit (I2C) bus
interface
8- or 16-bit pixel interface
YCrCb (4:2:2) output format
Software selectable four-input analog MUX
4 fully programmable GPIO bits
Auto NTSC/PAL format detect
Automatic Gain Control (AGC)
3.3 V I/O
Typical power consumption 0.85 W
IEEE 1149.1 Joint Test Action Group
(JTAG) interface
100-pin PQFP
Related Products
•
Bt829A, Bt856/857, Bt864A/865A, Bt864/
865, Bt852
Applications
•
•
•
•
•
•
Multimedia
Image processing
Desktop video
Video phone
Teleconferencing
Interactive video
Ordering Information
Model Number
Package
Ambient Temperature Range
Bt829BKRF
100-Pin Plastic Quad Flat Pack (PQFP)
0˚C to +70˚C
Bt827BKRF
100-Pin Plastic Quad Flat Pack (PQFP)
0˚C to +70˚C
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: March 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance,
reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is
assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems
where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or
death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use
in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages
resulting from such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC® is a registered trademark of AT&T Technologies, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Bt829B Video Capture Processor for TV/VCR Analog Input . . . . . . . . . . . . . . . . . . .
1.1.2 Bt827B Composite/S-Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 Bt829B Architecture and Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 UltraLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.5 Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.6 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.7 Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.8 VBI Data Pass-Through. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.9 Closed Caption Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.10 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
4
5
5
5
6
6
6
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Differences Between Bt829A/827A and Bt829B/827B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 UltraLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.1 The Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.2 Operation Principles of UltraLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Composite Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Y/C Separation and Chroma Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7 Video Scaling, Cropping, and Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.7.1 Horizontal and Vertical Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.2 Luminance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.3 Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.4 Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.5 Scaling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.6 Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.7 Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.8 Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D829BDSA
20
20
23
25
25
28
30
32
iii
Bt829B/827B
Table of Contents
VideoStream II Decoders
1.8 Video Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.8.1 The Hue Adjust Register (HUE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8.2 The Contrast Adjust Register (CONTRAST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8.3 The Saturation Adjust Registers (SAT_U, SAT_V). . . . . . . . . . . . . . . . . . . . . . . . . .
1.8.4 The Brightness Register (BRIGHT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
33
1.9 Bt829B VBI Data Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.4 VBI Line Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.5 VBI Frame Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
34
36
36
40
1.10 Closed Captioning and Extended Data Services Decoding . . . . . . . . . . . . . . . . . . . . . . . . 41
1.10.1 Automatic Chrominance Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.10.2 Low Color Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.10.3 Coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.0 Electrical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1 Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.1 Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Multiplexer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Autodetection of NTSC or PAL/SECAM Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Flash A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 A/D Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 Power-Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7 Automatic Gain Controls (AGC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.8 Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.9 2X Oversampling and Input Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
46
46
46
47
50
54
2.2 Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.1 Output Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 YCrCb Pixel Stream Format, SPI Mode, 8- and 16-Bit Formats. . . . . . . . . . . . . . . .
2.2.3 Synchronous Pixel Interface (SPI Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Synchronous Pixel Interface (SPI Mode 2, ByteStream) . . . . . . . . . . . . . . . . . . . . .
2.2.5 CCIR601 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
56
57
58
61
2.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.1 Starting and Stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Addressing the Bt829B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Reading and Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
63
63
66
2.4 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.1 Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5 Example BSDL Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
D829BDSA
67
67
68
68
69
Bt829B/827B
Table of Contents
VideoStream II Decoders
3.0 PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1 Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5 Latch-up Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
75
77
77
77
4.0 Control Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
0x00—Device Status Register (STATUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
0x01—Input Format Register (IFORM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
0x02—Temporal Decimation Register (TDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
0x03—MSB Cropping Register (CROP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
0x04—Vertical Delay Register, Lower Byte (VDELAY_LO) . . . . . . . . . . . . . . . . . . . . . . . . 84
0x05—Vertical Active Register, Lower Byte (VACTIVE_LO) . . . . . . . . . . . . . . . . . . . . . . . 84
0x06—Horizontal Delay Register, Lower Byte (HDELAY_LO) . . . . . . . . . . . . . . . . . . . . . 84
0x07—Horizontal Active Register, Lower Byte (HACTIVE_LO) . . . . . . . . . . . . . . . . . . . . 85
0x08—Horizontal Scaling Register, Upper Byte (HSCALE_HI). . . . . . . . . . . . . . . . . . . . . 85
0x09—Horizontal Scaling Register, Lower Byte (HSCALE_LO) . . . . . . . . . . . . . . . . . . . . 85
0x0A—Brightness Control Register (BRIGHT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
0x0B—Miscellaneous Control Register (CONTROL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
0x0C—Luma Gain Register, Lower Byte (CONTRAST_LO) . . . . . . . . . . . . . . . . . . . . . . . 88
0x0D—Chroma (U) Gain Register, Lower Byte (SAT_U_LO) . . . . . . . . . . . . . . . . . . . . . . 89
0x0E—Chroma (V) Gain Register, Lower Byte (SAT_V_LO) . . . . . . . . . . . . . . . . . . . . . . 90
0x0F—Hue Control Register (HUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
0x10—SC Loop Control (SCLOOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
0x11—White Crush Up Count Register (WC_UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
0x12—Output Format Register (OFORM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
0x13—Vertical Scaling Register, Upper Byte (VSCALE_HI) . . . . . . . . . . . . . . . . . . . . . . . 95
0x14—Vertical Scaling Register, Lower Byte (VSCALE_LO) . . . . . . . . . . . . . . . . . . . . . . 96
0x15—Test Control Register (TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
0x16—Video Timing Polarity Register (VPOLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
0x17—ID Code Register (IDCODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
0x18—AGC Delay Register (ADELAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
0x19—Burst Delay Register (BDELAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
0x1A—ADC Interface Register (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
0x1B—Video Timing Control (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
0x1C—Extended Data Service/Closed Caption Status Register (CC_STATUS). . . . . . . . 103
0x1D—Extended Data Service/Closed Caption Data Register (CC_DATA) . . . . . . . . . . . 104
0x1E—White Crush Down Count Register (WC_DN). . . . . . . . . . . . . . . . . . . . . . . . . . . 104
0x1F—Software Reset Register (SRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
0x3F—Programmable I/O Register (P_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
D829BDSA
v
Bt829B/827B
Table of Contents
VideoStream II Decoders
5.0 Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3 Package Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
vi
D829BDSA
Bt829B/827B
List of Figures
VideoStream II Decoders
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Figure 1-8.
Figure 1-9.
Figure 1-10.
Figure 1-11.
Figure 1-12.
Figure 1-13.
Figure 1-14.
Figure 1-15.
Figure 1-16.
Figure 1-17.
Figure 1-18.
Figure 1-19.
Figure 1-20.
Figure 1-21.
Figure 1-22.
Figure 1-23.
Figure 1-24.
Figure 1-25.
Figure 1-26.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Bt829B/827B Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Bt829B/827B Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UltraLock Behavior for NTSC Square Pixel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Y/C Separation and Chroma Demodulation for Composite Video . . . . . . . . . . . . . . . . . . . 18
Y/C Separation Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Filtering and Scaling Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Optional Horizontal Luma Low-Pass Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Combined Luma Notch,
2x Oversampling and Optional Low-Pass Filter Response (NTSC) . . . . . . . . . . . . . . . . . .21
Combined Luma Notch,
2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM) . . . . . . . . . . . . .21
Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . . . . 22
Combined Luma Notch and 2x Oversampling Filter Response . . . . . . . . . . . . . . . . . . . . . 22
Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Luma Peaking Filters with 2x Oversampling Filter and Luma Notch . . . . . . . . . . . . . . . . . 24
Effect of the Cropping and Active Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Regions of the Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Regions of the Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bt829B YCrCb 4:2:2 Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bt829B VBI Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VBI Line Output Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VBI Sample Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Location of VBI Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VBI Sample Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CC/EDS Data Processing Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CC/EDS Incoming Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Closed Captioning/Extended Data Services FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Coring Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bt829B Typical External Circuitry
with Third Overtone Crystal Oscillators (5 V VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Bt829B Typical External Circuitry
with Third Overtone Crystal Oscillators (3.3V VDDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Clock Options (3.3 V VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock Options (5 V VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Luma and Chroma 2x Oversampling Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Output Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
D829BDSA
vii
Bt829B/827B
List of Figures
VideoStream II Decoders
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
viii
YCrCb 4:2:2 Pixel Stream Format (SPI Mode, 8- and 16-Bits) . . . . . . . . . . . . . . . . . . . . . 56
Bt829B/827B Synchronous Pixel Interface, Mode 1 (SPI-1) . . . . . . . . . . . . . . . . . . . . . . 57
Basic Timing Relationships for SPI Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Output in SPI Mode 2 (ByteStream). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Video Timing in SPI Modes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Horizontal Timing Signals in the SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
The Relationship between SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I2C Slave Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I2C Protocol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Example of Ground Plane Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Optional Regulator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical Power and Ground
Connection Diagram and Parts List for 5 V I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Typical Power and Ground
Connection Diagram and Parts List for 3.3 V I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Output Enable Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
100-Pin PQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
D829BDSA
Bt829B/827B
List of Tables
VideoStream II Decoders
List of Tables
Table 1-1.
Table 1-2.
Table 1-3.
Table 1-4.
Table 1-5.
Table 1-6.
Table 1-7.
Table 1-8.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 4-1.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
VideoStream II Features Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions Grouped By Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Function Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 V Pin Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 V Pin Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Video Input Formats Supported by the Bt829B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Values for Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Scaling Ratios for Popular Formats Using Frequency Values . . . . . . . . . . . . . . . . . . . . . . 26
Pixel/Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Description of the Control Codes in the Pixel Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Bt829B Address Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example I2C Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Device Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DC Characteristics (3.3 V digital I/O operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DC Characteristics (5 V only operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Power Supply Current Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Output Enable Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Decoder Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Bt829B Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
D829BDSA
ix
Bt829B/827B
List of Tables
VideoStream II Decoders
x
D829BDSA
1.0 Functional Description
1.1 Functional Overview
Rockwell’s VideoStream II products are a family of single-chip, pin-and registercompatible solutions for processing analog NTSC/PAL/SECAM video into digital 4:2:2 YCrCb video. They provide a comprehensive choice of capabilities to
enable the feature set and cost to be tailored to different system hardware configurations. All solutions are housed in a 100-pin PQFP package. A detailed block
diagram is shown in Figure 1-1.
D829BDSA
1
Bt829B/827B
1.0 Functional Description
1.1 Functional Overview
VideoStream II Decoders
CREF–
CIN
CREF+
CLEVEL
YREF–
YIN
YREF+
SYNCDET
AGCCAP
REFOUT
Figure 1-1. Bt829B/827B Detailed Block Diagram
MUXOUT
C
A/D
Y
A/D
AGC and
Sync Detect
MUX0
Input Interface
MUX1
MUX2
MUX3
Oversampling
Low-Pass Filter
Y/C Separation and
Chroma Demodulation
SDA
I2C
Y/C
Separation
I2C Interface
RST
I2CCS
SCL
XT1O
Hue, Saturation,
and Brightness
Adjust
Clocking
XT1I
Clock Interface
Video
Adjustments
Chroma
Demod
XT0O
XT0I
CLKx1
CLKx2
OE
VD[15:8]
TDO
D829BDSA
Output Interface
Output Formatting
TDI
TMS
TCK
TRST
JTAG
VD[7:0]
JTAG Interface
2
QCLK
Horizontal and
Vertical Filtering
and Scaling
Video Timing Control
Video Scaling
and Cropping
CCVALID
HRESET
VRESET
ACTIVE
VACTIVE
FIELD
CBFLAG
DVALID
Bt829B/827B
1.0 Functional Description
1.1 Functional Overview
VideoStream II Decoders
1.1.1 Bt829B Video Capture Processor for TV/VCR Analog Input
The Bt829B Video Capture Processor is a fully integrated single-chip decoding
and scaling solution for analog NTSC/PAL/SECAM input signals from TV tuners, VCRs, cameras, and other sources of composite or Y/C video. It is the second
generation front-end input solution for low-cost PC video/graphics systems that
deliver complete integration and high-performance video synchronization, Y/C
separation, and filtered scaling. The Bt829B has all the mixed signal and DSP circuitry required to convert an analog composite waveform into a scaled digital
video stream, supporting a variety of video formats, resolutions, and frame rates.
1.1.2 Bt827B Composite/S-Video Decoder
The Bt827B provides full composite and S-Video capability along with horizontal
scaling. Vertical scaling can only be implemented by line-dropping.
The Synchronous Pixel Interface (SPI) is common to both pin-compatible
devices, which enables implementation of a single system hardware design.
Similarly, a common I2C register set allows a single piece of driver code to be
written for software control of both options. Table 1-1 compares Bt829B and
Bt827B features.
Table 1-1. VideoStream II Features Options
Feature Options
Bt829B
Bt827B
Composite Video Decoding
X
X
S-Video Decoding
X
X
SECAM Video
X
X
Hardware Closed Caption Decode
X
X
3.3 V Digital I/O
X
X
Filtered Vertical Scaling
X
D829BDSA
3
Bt829B/827B
1.0 Functional Description
1.1 Functional Overview
VideoStream II Decoders
1.1.3 Bt829B Architecture and Partitioning
The Bt829B has been developed to provide the most cost-effective, high-quality
video input solution. It is used for low-cost multimedia subsystems that integrate
both graphics display and video capabilities. The feature set of the Bt829B supports a video/graphics system partitioning which optimizes the total cost of a system configured both with and without video capture capabilities. This enables
system vendors to easily offer products with various levels of video support using
a single base-system design.
As graphics chip vendors move from graphics-only to video/graphics coprocessors, and eventually to single-chip video/graphics processor implementations,
the ability to efficiently use silicon and package pins to support both graphics
acceleration, video playback acceleration, and video capture becomes critical.
This problem becomes more acute as the race towards higher performance graphics requires more and more package pins to be consumed for wide 64-bit memory
interfaces and glueless local bus interfaces.
The Bt829B minimizes the cost of video capture function integration in two
ways. First, recognizing that YCrCb to RGB color space conversion is a required
feature of multimedia controllers for acceleration of digital video playback, the
Bt829B avoids redundant functionality and allows the downstream controller to
perform this task. Second, the Bt829B can minimize the number of interface pins
required by a downstream multimedia controller in order to keep package costs to a
minimum. The Bt829B can also output all timing and data signals at 3.3 V levels.
Controller systems designed to take advantage of these features allow video
capture capability to be added to the base system in a modular fashion using only
a single Integrated Circuit (IC).
The Bt827B is targeted at system configurations using video processors which
typically integrate the scaling function.
1.1.4 UltraLock
The Bt829B and Bt827B employ a proprietary technique known as UltraLock to
lock to the incoming analog video signal. It will always generate the required
number of pixels per line from an analog source in which the line length can vary
by as much as a few microseconds. UltraLock’s digital locking circuitry enables
the VideoStream decoders to quickly and accurately lock on to video signals,
regardless of their source. Since the technique is completely digital, UltraLock
can recognize unstable signals caused by VCR headswitches or any other deviation and adapt the locking mechanism to accommodate the source. UltraLock
uses nonlinear techniques which are difficult, if not impossible, to implement in
genlock systems. And unlike linear techniques, it adapts the locking mechanism
automatically.
4
D829BDSA
Bt829B/827B
1.0 Functional Description
1.1 Functional Overview
VideoStream II Decoders
1.1.5 Scaling and Cropping
The Bt829B can reduce the video image size in both horizontal and vertical directions independently using arbitrarily selected scaling ratios. The X and Y dimensions can be scaled down to one-sixteenth of the full resolution. Horizontal
scaling is implemented with a 6-tap interpolation filter, while up to 5-tap interpolation is used for vertical scaling with a line store. The Bt827B supports vertical
scaling by line-dropping.
The video image can be arbitrarily cropped by programming the ACTIVE flag
to reduce the number of active scan lines and active horizontal pixels per line.
The Bt829B and Bt827B also support a temporal decimation feature that
reduces video bandwidth by allowing frames or fields to be dropped from a video
sequence at regular but arbitrarily selected intervals.
1.1.6 Input Interface
Analog video signals are input to the Bt829B/827B via a four-input multiplexer
that can select between four composite source inputs or between three composite
and a single S-Video input source. When an S-Video source is input to the
Bt829B, the luma component is fed through the input analog multiplexer, and the
chroma component is fed directly into the C-input pin. An AGC circuit enables
the Bt829B/827B to compensate for reduced amplitude in the analog signal input.
The clock signal interface consists of two pairs of pins for crystal connection
and two clock output pins. One pair of crystal pins is for connection to a
28.64 MHz (8*NTSC Fsc) crystal which is selected for NTSC operation. The
other is for PAL operation with a 35.47 MHz (8*PAL Fsc) crystal. Either of the
two crystal frequencies can be selected to generate CLKx1 and CLKx2 output
signals. CLKx2 operates at the full crystal frequency (8*Fsc), whereas CLKx1
operates at half the crystal frequency (4*Fsc). Either fundamental or third harmonic crystals may be used. Alternatively, CMOS oscillators may be used.
1.1.7 Output Interface
The Bt829B and Bt827B support a Synchronous Pixel Interface (SPI) mode.
The SPI supports a YCrCb 4:2:2 data stream over an 8- or 16-bit-wide path.
When the pixel output port is configured to operate 8-bits wide, 8 bits of chrominance data are output on the first clock cycle followed by 8 bits of luminance data
on the next clock cycle for each pixel. Two clocks are required to output one pixel
in this mode, thus a 2x clock is used to output the data.
The Bt829B/827B outputs all horizontal and vertical blanking pixels in addition to the active pixels synchronous with CLKX1 (16-bit mode) or CLKX2 (8bit mode). It is also possible to insert control codes into the pixel stream using
chrominance and luminance values that are outside the allowable chroma and
luma ranges. These control codes can be used to flag video events such as
ACTIVE, HRESET, and VRESET. Decoding these video events downstream
enables the video controller to eliminate pins required for the corresponding
video control signals. Both Bt829B and Bt827B can output (or receive) all digital
timing, clock, and data signals at either 5 V or 3.3 V levels for connection to 5 V
or 3.3 V graphics/video controllers.
D829BDSA
5
Bt829B/827B
1.0 Functional Description
1.1 Functional Overview
VideoStream II Decoders
1.1.8 VBI Data Pass-Through
The Bt829B/827B provides VBI data passthrough capability. The VBI region
ancillary data is captured by the video decoder and made available to the system
for subsequent software processing. The Bt829B/827B may operate in a VBI Line
Output mode, in which the VBI data is only made available during select lines.
This mode of operation is intended to enable capture of VBI lines containing
ancillary data as well as processing normal YCrCb video image data. In addition,
the Bt829B/827B supports a VBI Frame Output mode, in which every line in the
video signal is treated as if it was a vertical interval line and no image data is output. This mode of operation is designed for use in still-frame capture/processing
applications.
1.1.9 Closed Caption Decoding
The Bt829B and Bt827B provide a Closed Captioning (CC) and Extended Data
Services (EDS) decoder. Data presented to the video decoder on the CC and EDS
lines is decoded and made available to the system through the CC_DATA and
CCSTATUS registers.
1.1.10 I2C Interface
The Bt829B/827B registers are accessed via a two-wire I2C interface. The
Bt829B/827B operates as a slave device. Serial clock and data lines, SCL and
SDA, transfer data from the bus master at a rate of 100 Kbits/s. Chip select and
reset signals are also available to select one of two possible Bt829B/827B devices
in the same system and to set the registers to their default values.
6
D829BDSA
Bt829B/827B
1.0 Functional Description
1.2 Pin Descriptions
VideoStream II Decoders
1.2 Pin Descriptions
Figure 1-2 details the Bt829B and Bt827B pinout. Table 1-2 provides pin numbers, names, input and output
functions, and descriptions.
GND
CLKx2
OE
CLKx1
VDD
GND
QCLK
GND
VDDO
PWRDN
GND
CBFLAG
VDD
CCVALID
VACTIVE
OEPOLE
DVALID
ACTIVE
HRESET
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Figure 1-2. Bt829B/827B Pinout Diagram
VDDO
1
80
NUMXTAL
VD[15]
2
79
VRESET
VD[14]
3
78
FIELD
VD[13]
4
77
GND
VD[12]
5
76
VDD
VD[11]
6
75
AGND
VD[10]
7
74
CLEVEL
VD[9]
8
73
CREF–
VD[8]
9
72
VAA
VDD
10
71
AGND
GND
11
70
N/C
XT0I
12
69
N/C
XT0O
13
68
N/C
I2CCS
14
67
CIN
RST
15
66
AGND
XT1I
16
65
VAA
XT1O
17
64
CREF+
SDA
18
63
N/C
SCL
19
62
YREF–
VDDO
20
61
AGND
GND
21
60
VAA
VD[7]
22
59
SYNCDET
VD[6]
23
58
AGND
VD[5]
24
57
MUX[1]
VD[4]
25
56
AGND
VD[3]
26
55
MUX[0]
VD[2]
27
54
AGND
VD[1]
28
53
MUXOUT
VD[0]
29
52
YIN
VDDO
30
51
N/C
45
46
47
48
49
50
N/C
AGND
VAA
YREF+
MUX[3]
40
VPOS
MUX[2]
39
GND
44
38
VDD
VAA
37
TDI
43
36
TMS
REFOUT
35
TRST
42
34
TCK
VNEG
33
GND
41
32
TDO
AGCCAP
31
GND
Bt829B/827B
D829BDSA
7
Bt829B/827B
1.0 Functional Description
1.2 Pin Descriptions
VideoStream II Decoders
Table 1-2. Pin Descriptions Grouped By Pin Function (1 of 4)
Pin #
I/O
Pin Name
Description
Input Stage Pins
45, 50, 55,
57
I
MUX[3:0]
Analog composite video inputs to the on-chip input multiplexer. They are used to
select between four composite sources or three composite and one S-Video source.
Unused pins should be connected to GND.
53
O
MUXOUT
The analog video output of the 4-to-1 multiplexer. Connected to the YIN pin.
52
I
YIN
The analog composite or luma input to the Y-ADC.
67
I
CIN
The analog chroma input to the C-ADC.
59
I
SYNCDET
The sync stripper input generates timing information for the AGC circuit. Can be
optionally connected through a 0.1 µF capacitor to the same source as the Y-ADC, to
maintain compatibility with Bt829 board layouts. A 1 MΩ bleeder resistor can be
connected to ground, to maintain compatibility with Bt829 board layouts. For new
Bt829B designs, this pin may be connected to VAA.
41
A
AGCCAP
The AGC time constant control capacitor node. Must be connected to a 0.1 µF capacitor to ground.
43
O
REFOUT
Output of the AGC which drives the YREF+ and CREF+ pins.
49
A
YREF+
The top of the reference ladder of the Y-ADC. This should be connected to REFOUT.
62
A
YREF–
The bottom of the reference ladder of the Y-ADC. This should be connected to analog
ground (AGND).
64
A
CREF+
The top of the reference ladder of the C-ADC. This should be connected to REFOUT.
73
A
CREF–
The bottom of the reference ladder of the C-ADC. This should be connected to analog
ground (AGND).
74
A
CLEVEL
An input to provide the DC level reference for the C-ADC. For compatibility with
Bt829 board layouts, the 30 kΩ divider resistors may be maintained.
Note: This pin should be left to float for new Bt829B designs.
51
A
N/C
No connect.
46
A
N/C
No connect.
63, 68
A
N/C
No connect.
70
A
N/C
No connect.
69
A
N/C
No connect.
I2C Interface Pins
8
19
I
SCL
The I2C Serial Clock Line.
18
I/O
SDA
The I2C Serial Data Line.
14
I
I2CCS
The I2C Chip Select Input (TTL compatible). This pin selects one of two Bt829B
devices in the same system. This pin is internally pulled to ground with an effective
18 KΩ resistance.
15
I
RST
Reset Control Input (TTL compatible). A logical 0 for a minimum of four consecutive
clock cycles resets the device to its default state. A logical 0 for less than eight XTAL
cycles will leave the device in an undetermined state.
D829BDSA
Bt829B/827B
1.0 Functional Description
1.2 Pin Descriptions
VideoStream II Decoders
Table 1-2. Pin Descriptions Grouped By Pin Function (2 of 4)
Pin #
I/O
Pin Name
Description
Video Timing Unit Pins
82
O
HRESET
Horizontal Reset Output (TTL compatible). This signal indicates the beginning of a
new line of video. This signal is 64 CLKx1 clock cycles wide. The falling edge of this
output indicates the beginning of a new scan line of video. This pin may be defined in
pixels as opposed to CLKx1 cycles. Refer to the HSFMT bit in the VTC register.
Note: The polarity of this pin is programmable through the VPOLE register.
79
O
VRESET
Vertical Reset Output (TTL compatible). This signal indicates the beginning of a new
field of video. This signal is output coincident with the rising edge of CLKx1, and is
normally 6 lines wide. The falling edge of VRESET indicates the beginning of a new
field of video.
Note: The polarity of this pin is programmable through the VPOLE register.
83
O
ACTIVE
Active Video Output (TTL compatible). This pin can be programmed to output the
composite active or horizontal active signal via the VTC register. It is a logical high
during the active/viewable periods of the video stream. The active region of the video
stream is programmable.
Note: The polarity of this pin is programmable through the VPOLE register.
94
O
QCLK
Qualified Clock Output. This pin provides a rising edge only during valid, active pixel
data. This output is generated from CLKx1 (or CLKx2 in 8-bit mode), DVALID and, if
programmed, ACTIVE. The phase of QCLK is inverted from the CLKx1 (or CLKx2) to
ensure adequate setup and hold time with respect to the data outputs. QCLK is not
output during control codes when using SPI mode 2.
98
I
OE
Output Enable Control (TTL compatible). All video timing unit output pins and all
clock interface output pins contain valid data following the rising edge of CLKx2,
after OE has been asserted low. This function is asynchronous. The three-stated pins
include: VD[15:0], HRESET, VRESET, ACTIVE, DVALID, CBFLAG, FIELD, QCLK,
CLKx1, and CLKx2. See the OES bits in the OFORM register to disable subgroups of
output pins.
78
O
FIELD
Odd/Even Field Output (TTL compatible). A high state on the FIELD pin indicates that
an odd field is being digitized.
Note: The polarity of this pin is programmable through the VPOLE register.
89
O
CBFLAG
Cb Data Identifier (TTL compatible). A high state on this pin indicates that the current
chroma byte contains Cb chroma information.
Note: The polarity of this pin is programmable through the VPOLE register.
2–9
O
VD[15:8]
22–29
I/O
VD[7:0]
Digitized Video Data Outputs (TTL compatible). VD[0] is the least significant bit of
the bus in 16-bit mode. VD[8] is the least significant bit of the bus in 8-bit mode. The
information is output with respect to CLKx1 in 16-bit mode, and CLKx2 in 8-bit
mode. In mode 2, this port is configured to output control codes as well as data.
When data is output in 8-bit mode using VD[15:8], VD[7:0] can be used as general
purpose I/O pins. See the P_IO register.
84
O
DVALID
Data Valid Output (TTL compatible). This pin indicates when a valid pixel is being
output onto the data bus. The Bt829B digitizes video at eight times the subcarrier
rate, and outputs scaled video. Therefore, there are more clocks than valid data.
DVALID indicates when valid pixel data is being output.
Note: The polarity of this pin is programmable through the VPOLE register.
87
O
CCVALID
A logical low on this pin indicates that the CC FIFO is half full (8 characters). This pin
may be disabled. This open drain output requires a pullup resistor for proper operation. However, if closed captioning is not implemented, this pin may be left unconnected.
D829BDSA
9
Bt829B/827B
1.0 Functional Description
1.2 Pin Descriptions
VideoStream II Decoders
Table 1-2. Pin Descriptions Grouped By Pin Function (3 of 4)
Pin #
I/O
Pin Name
Description
91
I
PWRDN
A logical high on this pin puts the device into power-down mode. This is equivalent
to programming CLK_SLEEP high in the ADC register.
86
O
VACTIVE
Vertical Blanking Output (TTL compatible). The falling edge of VACTIVE indicates the
beginning of the active video lines in a field. This occurs VDELAY/2 lines after the rising edge of VRESET. The rising edge of VACTIVE indicates the end of active video
lines and occurs ACTIVE_LINES/2 lines after the falling edge of VACTIVE. VACTIVE is
output following the rising edge of CLKx1.
Note: The polarity of the pin is programmable through the VPOLE register.
85
I
OEPOLE
A logical low on this pin allows the Bt829B/827B to power up in the same manner as
the Bt829/827. A logical high on this pin, followed by a device reset will TRISTATE
the video outputs, sync outputs, and clock outputs.
Clock Interface Pins
12
A
XT0I
Clock Zero pins. A 28.64 MHz (8*Fsc) fundamental (or third harmonic) crystal can be
tied directly to these pins, or a single-ended oscillator can be connected to XT0I.
CMOS level inputs must be used. This clock source is selected for NTSC input
sources. When the chip is configured to decode PAL but not NTSC (and therefore
only one clock source is needed), the 35.47 MHz source is connected to this port
(XT0).
13
A
XT0O
16
A
XT1I
17
A
XT1O
97
O
CLKx1
1x clock output (TTL compatible). The frequency of this clock is 4*Fsc (14.31818
MHz for NTSC or 17.73447 MHz for PAL).
99
O
CLKx2
2x clock output (TTL compatible). The frequency of this clock is 8*Fsc (28.63636
MHz for NTSC, or 35.46895 MHz for PAL).
80
I
NUMXTAL
Clock One pins. A 35.47 MHz (8*Fsc) fundamental (or third harmonic) crystal can be
tied directly to these pins, or a single-ended oscillator can be connected to XT1I.
CMOS level inputs must be used. This clock source is selected for PAL input sources.
If only NTSC or PAL is being decoded, and therefore only XT0I and XT0O are connected to a crystal, XT1I should be tied either high or low, and XT1O must be left
floating.
Crystal Format Pin. This pin is set to indicate whether one or two crystals are present
so that the Bt829B can select XT1 or XT0 as the default in auto format mode. A logical 0 on this pin indicates one crystal is present. A logical 1 indicates two crystals are
present. This pin is internally pulled down to ground with an effective 18 KΩ resistance.
JTAG Pins
34
I
TCK
Test Clock (TTL compatible). Used to synchronize all JTAG test structures. When
JTAG operations are not being performed, this pin must be driven to a logical low.
36
I
TMS
Test Mode Select (TTL compatible). JTAG input pin whose transitions drive the JTAG
state machine through its sequences. When JTAG operations are not being performed, this pin must be left floating or tied high.
37
I
TDI
Test Data Input (TTL compatible). JTAG pin used for loading instruction into the TAP
controller or for loading test vector data for boundary-scan operation. When JTAG
operations are not being performed, this pin must be left floating or tied high.
32
O
TDO
Test Data Output (TTL compatible). JTAG pin used for verifying test results of all
JTAG sampling operations. This output pin is active for certain JTAG operations and
will be three-stated at all other times.
10
D829BDSA
Bt829B/827B
1.0 Functional Description
1.2 Pin Descriptions
VideoStream II Decoders
Table 1-2. Pin Descriptions Grouped By Pin Function (4 of 4)
Pin #
35
I/O
Pin Name
Description
I
TRST
Test Reset (TTL compatible). JTAG pin used to initialize the JTAG controller. This pin
is tied low for normal device operation. When pulled high, the JTAG controller is
ready for device testing.
Power And Ground Pins
10, 38, 76,
88, 96
P
VDD +5 V
Power supply for digital circuitry. All VDD pins must be connected together as close
to the device as possible. A 0.1 µF ceramic capacitor should be connected between
each group of VDD pins and the ground plane as close to the device as possible.
1, 20, 30, 92
P
VDDO + 3.3 V
Power supply for 3.3 V digital circuitry. All VDDO pins must be connected together as
close to the device as possible. A 0.1 µF ceramic capacitor should be connected
between each group of VDDO pins and the ground plane, as close to the device as
possible.
40, 44, 48,
60, 65, 72
P
VAA +5 V,
VPOS +5 V
11, 21, 31,
33, 39, 77,
81, 90, 93,
95, 100
G
GND
Ground for digital circuitry. All GND pins must be connected together as close to the
device as possible.
42, 47, 54,
56, 58, 61,
66, 71, 75
G
AGND, VNEG
Ground for analog circuitry. All AGND pins and VNEG must be connected together as
close to the device as possible.
Power supply for analog circuitry. All VAA pins and VPOS must be connected
together as close to the device as possible. A 0.1 µF ceramic capacitor should be
connected between each group of VAA pins and the ground plane as close to the
device as possible.
I/O Column Legend:
I = Digital Input
O = Digital Output
I/O = Digital Bidirectional
A = Analog
G = Ground
P = Power
D829BDSA
11
Bt829B/827B
1.0 Functional Description
1.3 Differences Between Bt829A/827A and Bt829B/827B
VideoStream II Decoders
1.3 Differences Between Bt829A/827A
and Bt829B/827B
While both Bt829A/827A and Bt829B/827B video decoders are pin and software
compatible, please note the differences, as described in Table 1-3.
A 3.3 V mode has been added which allows the Bt829B to interface to 3.3 V
graphic/video controllers without the use of 5 V to 3.3 V level translators.
Table 1-3. Pin Function Differences
Pins
Bt829A/
827A
Bt829B/
827B
1, 20, 30, 92
VDD
VDDO
Comments
For 3.3 V I/O, connect the pins to the 3.3 V
supply. For 5 V I/O, connect these pins to the 5
V supply.
See Figure 3-4 for typical power and ground connections when in 3.3 V I/O
mode. The pins listed in Table 1-4 can output 3.3 V signal levels when pins 1, 20,
30, and 92 (VDDO) are connected to a 3.3 V power supply.
Table 1-4. 3.3 V Pin Output
12
Pin Number
Pin Name
82
HRESET
79
VRESET
83
ACTIVE
94
QCLK
78
FIELD
89
CBFLAG
2–9
VD[15:8]
22–29
VD[7:0]
84
DVALID
87
CCVALID
86
VACTIVE
97
CLKX1
99
CLKX2
32
TDO
D829BDSA
Bt829B/827B
1.0 Functional Description
1.3 Differences Between Bt829A/827A and Bt829B/827B
VideoStream II Decoders
The pins shown in Table 1-5 can receive 3.3 V signal levels when pins 1, 20, 30,
and 92 (VDDO) are connected to a 3.3 V power supply:
Table 1-5. 3.3 V Pin Input
Pin Number
Pin Name
19
SCL
18
SDA
14
I2CCS
15
RST
98
OE
91
PWRDN
85
OEPOLE
80
NUMXTAL
34
TCK
36
TMS
37
TDI
35
TRST
When using the Bt829B/827B in the 3.3 V I/O mode with the third overtone
crystal oscillators, the tank circuit required is different to the tank circuit when in
5 V I/O mode. See Figures 2-1, 2-2, 2-3, and 2-4.
D829BDSA
13
Bt829B/827B
1.0 Functional Description
1.4 UltraLock
VideoStream II Decoders
1.4 UltraLock
1.4.1 The Challenge
The line length (the interval between the midpoints of the falling edges of succeeding horizontal sync pulses) of analog video sources is not constant. For a stable source such as a studio grade video source or test signal generators, this
variation is very small: ±2 ns. However, for an unstable source such as a VCR,
laser disk player, or TV tuner, line length variation is as much as a few microseconds.
Digital display systems require a fixed number of pixels per line, despite these
variations. The Bt829B employs a technique known as UltraLock to implement
locking to the horizontal sync and the subcarrier of the incoming analog video
signal and generating the required number of pixels per line.
1.4.2 Operation Principles of UltraLock
UltraLock is based on sampling, using a fixed-frequency stable clock. Because
the video line length will vary, the number of samples generated using a fixed-frequency sample clock will also vary from line-to-line. If the number of generated
samples-per-line is always greater than the number of samples-per-line required
by the particular video format, the number of acquired samples can be reduced to
fit the required number of pixels per line.
The Bt829B requires an 8*Fsc (28.64 MHz for NTSC and 35.47 MHz for
PAL) crystal or oscillator input signal source. The 8*Fsc clock signal, or CLKx2,
is divided down to CLKx1 internally (14.32 MHz for NTSC and 17.73 MHz for
PAL). Both CLKx2 and CLKx1 are made available to the system. UltraLock
operates at CLKx1 although the input waveform is sampled at CLKx2 then lowpass filtered and decimated to CLKx1 sample rate.
At a 4*Fsc (CLKx1) sample rate there are 910 pixels for NTSC and 1,135 pixels for PAL/SECAM within a nominal line time interval (63.5 µs for NTSC and
64 µs for PAL/SECAM). For square pixel NTSC and PAL/SECAM formats there
should only be 780 and 944 pixels-per-video line, respectively. This is because
the square pixel clock rates are slower than a 4*Fsc clock rate: for example,
12.27 MHz for NTSC and 14.75 MHz for PAL.
UltraLock accommodates line length variations from nominal in the incoming
video by always acquiring more samples (at an effective 4*Fsc rate) than are
required by the particular video format. It then outputs the correct number of pixels per line. UltraLock then interpolates the required number of pixels so that it
maintains the stability of the original image, despite variation in the line length of
the incoming analog waveform.
Figure 1-3 illustrates three successive lines of video being decoded for square
pixel NTSC output. The first line is shorter than the nominal NTSC line time
interval of 63.5 µs. On this first line, a line time of 63.2 µs sampled at 4*Fsc
(14.32 MHz) generates only 905 pixels. The second line matches the nominal line
time of 63.5 µs and provides the expected 910 pixels. Finally, the third line is too
long at 63.8 µs within which 913 pixels are generated. In all three cases,
UltraLock outputs only 780 pixels.
14
D829BDSA
Bt829B/827B
1.0 Functional Description
1.4 UltraLock
VideoStream II Decoders
Figure 1-3. UltraLock Behavior for NTSC Square Pixel Output
Analog
Waveform
Line
Length
Pixels
Per Line
Pixels
Sent to
the FIFO
by
Ultralock
63.2 µs
63.5 µs
63.8 µs
905 pixels
910 pixels
913 pixels
780 pixels
780 pixels
780 pixels
UltraLock can be used to extract any programmable number of pixels from the
original video stream as long as the sum of the nominal pixel line length (910 for
NTSC and 1,135 for PAL/SECAM) and the worst case line length variation from
nominal in the active region is greater than or equal to the required number of
output pixels per line, for example:
P Nom + P Var ≥ P Desired
where:
NOTE:
PNom
= Nominal number of pixels per line at 4*Fsc sample rate
(910 for NTSC, 1,135 for PAL/SECAM)
PVar
= Variation of pixel count from nominal at 4*Fsc (can be a
positive or negative number)
PDesired = Desired number of output pixels per line
For stable inputs, UltraLock guarantees the time between the falling edges
of HRESET only to within one pixel. UltraLock does, however, guarantee
the number of active pixels in a line as long as the stated relationship
holds.
D829BDSA
15
Bt829B/827B
1.0 Functional Description
1.5 Composite Video Input Formats
VideoStream II Decoders
1.5 Composite Video Input Formats
The Bt829B supports several composite video input formats. Table 1-6 specifies
the different video formats and some of the countries in which each format is
used.
Table 1-6. Video Input Formats Supported by the Bt829B
Format
Lines
Fields
FSC
NTSC-M
525
60
3.58 MHz
U.S., many others
NTSC-Japan(1)
525
60
3.58 MHz
Japan
PAL-B
625
50
4.43 MHz
Many
PAL-D
625
50
4.43 MHz
China
PAL-G
625
50
4.43 MHz
Many
PAL-H
625
50
4.43 MHz
Belgium
PAL-I
625
50
4.43 MHz
Great Britain, others
PAL-M
525
60
4.43 MHz
Brazil
PAL-N
625
50
4.43 MHz
Paraguay, Uruguay
PAL-N combination
625
50
3.58 MHz
Argentina
SECAM
625
50
4.406 MHz
4.250 MHz
Eastern Europe, France,
Middle East
Notes: (1). NTSC-Japan has 0 IRE setup.
16
D829BDSA
Country
Bt829B/827B
1.0 Functional Description
1.5 Composite Video Input Formats
VideoStream II Decoders
The video decoder must be programmed appropriately for each of the
composite video input formats. Table 1-7 lists the register values that need to be
programmed for each input format.
Table 1-7. Register Values for Video Input Formats
Register
IFORM
(0x01)
Cropping:
HDELAY,
VDELAY,
VACTIVE,
CROP
Bit
NTSC-M
NTSC-Japan
PAL-B, D,
G, H, I
PAL-M
PAL-N
PAL-N
Combination
SECAM
XTSEL
4:3
01
01
10
01
10
01
10
FORMAT
2:0
001
010
011
100
101
111
110
7:0 in all 5
registers
Set to
Set to NTSCdesired crop- M square pixel
ping values
values
in registers
Set to desired
cropping values in registers
Set to NTSCSet to PAL-B,
M square pixel D, G, H, I
values
square pixel
values
Set to PAL-B, D, G, Set to PAL-B,
H, I CCIR values
D, G, H, I
square pixel
values
HSCALE
(0x08,
0x09)
15:0
0x02AA
0x02AA
0x033C
0x02AC
0x033C
0x00F8
0x033C
ADELAY
(0x18)
7:0
0x68
0x68
0x7F
0x68
0x7F
0x7F
0x7F
BDELAY
(0x19)
7:0
0x5D
0x5D
0x72
0x5D
0x72
0x72
0xA0
D829BDSA
17
Bt829B/827B
1.0 Functional Description
1.6 Y/C Separation and Chroma Demodulation
VideoStream II Decoders
1.6 Y/C Separation and Chroma Demodulation
Y/C separation and chroma decoding is illustrated in Figure 1-4. Bandpass and
notch filters are implemented to separate the composite video stream. Figure 1-5
displays the filter responses. The optional chroma comb filter is implemented in
the vertical scaling block. See the Video Scaling, Cropping, and Temporal Decimation section in this chapter.
Figure 1-4. Y/C Separation and Chroma Demodulation for Composite Video
Y
Composite
Notch Filter
U
Low-Pass Filter
sin
V
Low-Pass Filter
Band-Pass Filter
cos
Figure 1-5. Y/C Separation Filter Responses
Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM
Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM
NTSC
NTSC
18
PAL/SECAM
D829BDSA
PAL/SECAM
Bt829B/827B
1.0 Functional Description
1.6 Y/C Separation and Chroma Demodulation
VideoStream II Decoders
Figure 1-6 schematically describes the filtering and scaling operations.
In addition to the Y/C separation and chroma demodulation illustrated in
Figure 1-4, the Bt829B also supports chrominance comb filtering as an optional
filtering stage after chroma demodulation. The chroma demodulation generates
baseband I and Q (NTSC) or U and V (PAL/SECAM) color difference signals.
For S-Video operation, the digitized luma data bypasses the Y/C separation
block completely, and the digitized chrominance is passed directly to the chroma
demodulator.
For monochrome operation, the Y/C separation block is also bypassed, and the
saturation registers (SAT_U and SAT_V) are set to zero.
Figure 1-6. Filtering and Scaling Operations
Horizontal Scaler
Luminance
= A + BZ
–1
+ CZ
Chrominance
–2
+ DZ
Vertical Scaler
–3
= G + HZ
+ EZ
–4
+ FZ
–5
Luminance
–1
= C + DZ
Chrominance
–1
1 1 –1
= --- + --- Z (Chroma Comb)
2 2
Vertical Filter Options
1
–1
Luminance = --- ( 1 + z )
2
1
–1
–2
= --- ( 1 + 2 Z + 1 Z )
4
1
–1
–2
–3
= --- ( 1 + 3 Z + 3 Z + 1 Z )
8
1
–1
–2
–3
–4
= ------ ( 1 + 4 Z + 6 Z + 4 Z + Z )
16
Y
C
Note:
Optional
3 MHz
Horizontal
Low-Pass
Filter
6-Tap, 32-Phase
Interpolation
and
Horizontal
Scaling
On-chip Memory
2-Tap, 32-Phase
Interpolation
and
Horizontal
Scaling
On-chip Memory
Luma Comb
Vertical Scaling
Vertical Filtering
Y
Chroma Comb
and
Vertical Scaling
C
Z–1 refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. The coefficients are determined by UltraLock and the scaling algorithm.
D829BDSA
19
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
1.7 Video Scaling, Cropping, and Temporal
Decimation
The Bt829B provides three mechanisms to reduce the amount of video pixel data
in its output stream: down-scaling, cropping, and temporal decimation. All three
can be controlled independently.
1.7.1 Horizontal and Vertical Scaling
The Bt829B provides independent and arbitrary horizontal and vertical downscaling. The maximum scaling ratio is 16:1 in both X and Y dimensions. The
maximum vertical scaling ratio is reduced from 16:1 when using frames, and to
8:1 when using fields. The different methods utilized for scaling luminance and
chrominance are described in the following sections.
1.7.2 Luminance Scaling
The first stage in horizontal luminance scaling is an optional pre-filter which provides the capability to reduce antialiasing artifacts. It is generally desirable to
limit the bandwidth of the luminance spectrum prior to performing horizontal
scaling because the scaling of high-frequency components may create image artifacts in the resized image.
The optional low-pass filters shown in Figure 1-7 reduce the horizontal highfrequency spectrum in the luminance signal. Figure 1-8 and Figure 1-9 illustrates
the combined results of the optional low-pass filters, and the luma notch and 2x
oversampling filter.
Figure 1-7. Optional Horizontal Luma Low-Pass Filter Responses
NTSC
PAL/SECAM
QCIF
QCIF
CIF
ICON
ICON
20
D829BDSA
CIF
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
Figure 1-8. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC)
Pass Band
Full Spectrum
QCIF
CIF
ICON
CIF
ICON
QCIF
Figure 1-9. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM)
CIF
Full Spectrum
Pass Band
QCIF
CIF
ICON
QCIF
ICON
The Bt829B implements horizontal scaling through poly-phase interpolation.
The Bt829B uses 32 different phases to accurately interpolate the value of a pixel.
This provides an effective pixel jitter of less than 6 ns.
In simple pixel- and line-dropping algorithms, non-integer scaling ratios introduce a step function in the video signal that effectively introduces high-frequency
spectral components. Poly-phase interpolation accurately interpolates to the correct pixel and line position providing more accurate information. This results in
more aesthetically pleasing video as well as higher compression ratios in bandwidth limited applications.
For vertical scaling, the Bt829B uses a line store to implement four different
filtering options. The filter characteristics are shown in Figure 1-10. The Bt829B
provides up to 5-tap filtering to ensure removal of aliasing artifacts. Figure 1-11
displays the combined responses of the luma notch and 2x oversampling filters.
D829BDSA
21
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
Figure 1-10. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters
2-tap
3-tap
4-tap
5-tap
Figure 1-11. Combined Luma Notch and 2x Oversampling Filter Response
PAL/SECAM
NTSC
22
D829BDSA
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
1.7.3 Peaking
The Bt829B enables four different peaking levels by programming the PEAK bit
and HFILT bits in the SCLOOP register. The filters are shown in Figures 1-12
and 1-13.
Figure 1-12. Peaking Filters
HFILT = 00
HFILT = 01
HFILT = 10
HFILT = 11
Enhanced Resolution of Passband
HFILT = 00
HFILT = 01
HFILT = 10
HFILT = 11
D829BDSA
23
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
Figure 1-13. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch
HFILT = 00
HFILT = 10
HFILT = 11
HFILT = 01
Enhanced Resolution of Passband
HFILT = 00
HFILT = 01
HFILT = 10
HFILT = 11
The number of taps in the vertical filter is set by the VTC register. The user
may select two, three, four, or five taps. The number of taps must be chosen in
conjunction with the horizontal scale factor to ensure that the needed data can fit
in the internal FIFO (see the VFILT bits in the VTC register for limitations). As
the scaling ratio is increased, the number of taps available for vertical scaling is
increased. In addition to low-pass filtering, vertical interpolation is also employed
to minimize artifacts when scaling to non-integer scaling ratios. The Bt827B
employs line dropping for vertical scaling.
24
D829BDSA
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
1.7.4 Chrominance Scaling
A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chrominance. Vertical scaling of chrominance is implemented through chrominance
comb filtering using a line store, followed by simple decimation or line dropping.
1.7.5 Scaling Registers
Horizontal Scaling Ratio Register (HSCALE) HSCALE is programmed with the
horizontal scaling ratio. When outputting unscaled video (in NTSC), the Bt829B
will produce 910 pixels per line. This corresponds to the pixel rate at fCLKx1
(4*Fsc). This register is the control for scaling the video to the desired size. For
example, square pixel NTSC requires 780 samples-per-line, while CCIR601
requires 858 samples-per-line. HSCALE_HI and HSCALE_LO are two 8-bit registers that, when concatenated, form the 16-bit HSCALE register.
The method below uses pixel ratios to determine the scaling ratio. The following formula should be used to determine the scaling ratio to be entered into the
16-bit register:
NTSC:
HSCALE = [ ( 910/Pdesired ) – 1] * 4096
PAL/SECAM: HSCALE = [ ( 1135/Pdesired ) – 1] * 4096
where:
Pdesired
= Desired number of pixels per line of video, including active, sync and blanking.
For example, to scale PAL/SECAM input to square pixel QCIF, the total number
of horizontal pixels is 236:
HSCALE = [ ( 1135/236 ) – 1 ] * 4096
= 15602
= 0x3CF2
An alternative method for determining the HSCALE value uses the ratio of the
scaled active region to the unscaled active region as shown below:
NTSC:
PAL/SECAM:
where:
HSCALE = [ (754 / HACTIVE) – 1] * 4096
HSCALE = [ (922 / HACTIVE) – 1] * 4096
HACTIVE = Desired number of pixels per line of video, not
including sync or blanking.
D829BDSA
25
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
In this equation, the HACTIVE value cannot be cropped; it represents the total
active region of the video line. This equation produces roughly the same result as
using the full line length ratio shown in the first example. However, due to truncation, the HSCALE values determined using the active pixel ratio will be slightly
different than those obtained using the total line length pixel ratio. The values in
Table 1-8 were calculated using the full line length ratio.
Table 1-8. Scaling Ratios for Popular Formats Using Frequency Values
Scaling Ratio
Format
Total
Resolution
(including
sync and
blanking
interval)
VSCALE Register Values
Full Resolution
1:1
NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel
780 x 525
858 x 525
864 x 625
944 x 625
640 x 480
720 x 480
720 x 576
768 x 576
CIF
2:1
NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel
390 x 262
429 x 262
432 x 312
472 x 312
QCIF
4:1
NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel
ICON
8:1
NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel
Output
Resolution
(Active Pixels)
HSCALE
Register
Values
Use Both
Fields
Single
Field
0x02AC
0x00F8
0x0504
0x033C
0x0000
0x0000
0x0000
0x0000
N/A
N/A
N/A
N/A
320 x 240
360 x 240
360 x 288
384 x 288
0x1555
0x11F0
0x1A09
0x1679
0x1E00
0x1E00
0x1E00
0x1E00
0x0000
0x0000
0x0000
0x0000
195 x 131
214 x 131
216 x 156
236 x 156
160 x 120
180 x 120
180 x 144
192 x 144
0x3AAA
0x3409
0x4412
0x3CF2
0x1A00
0x1A00
0x1A00
0x1A00
0x1E00
0x1E00
0x1E00
0x1E00
97 x 65
107 x 65
108 x 78
118 x 78
80 x 60
90 x 60
90 x 72
96 x 72
0x861A
0x7813
0x9825
0x89E5
0x1200
0x1200
0x1200
0x1200
0x1A00
0x1A00
0x1A00
0x1A00
Notes: 1. PAL-M–HSCALE and VSCALE register values should be the same for NTSC.
2. PAL-N combination–HSCALE register values should be the same as for CCIR resolution NTSC. VSCALE register
values should be the same as for CCIR resolution PAL.
3. SECAM–HSCALE and VSCALE register values should be the same as for PAL.
26
D829BDSA
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
Vertical Scaling Ratio Register (VSCALE) VSCALE is programmed with the
vertical scaling ratio. It defines the number of vertical lines output by the Bt829B.
The following formula should be used to determine the value to be entered into
this 13-bit register. The loaded value is a two’s-complement, negative value.
VSCALE = ( 0x10000 – { [ ( scaling_ratio ) – 1] * 512 } ) & 0x1FFF
For example, to scale PAL/SECAM input to square pixel QCIF, the total number
of vertical lines for PAL square pixel is 156 (see Table 1-8).
VSCALE = ( 0x10000 – { [ ( 4/1 ) –1 ] * 512 } ) & 0x1FFF
= 0x1A00
NOTE:
Only the 13 least significant bits (LSBs) of the VSCALE value are used.
The five LSBs of VSCALE_HI and the 8-bit VSCALE_LO register form
the 13-bit VSCALE register. The three MSBs of VSCALE_HI are used to
control other functions. The user must take care not to alter the values of
the three most significant bits when writing a vertical scaling value. The
following C-code fragment illustrates changing the vertical scaling value:
#define BYTE unsigned char
#define WORD unsigned int
#define VSCALE_HI 0x13
#define VSCALE_LO 0x14
BYTE ReadFromBt829B( BYTE regAddress );
void WriteToBt829B( BYTE regAddress, BYTE regValue );
void SetBt829BVScaling( WORD VSCALE )
{
BYTE oldVscaleMSByte, newVscaleMSByte;
/* get existing VscaleMSByte value from */
/* Bt829B VSCALE_HI register */
oldVscaleMSByte = ReadFromBt829B( VSCALE_HI );
/* create a new VscaleMSByte, preserving top 3 bits */
newVscaleMSByte = (oldVscaleMSByte & 0xE0) | (VSCALE >> 8);
/* send the new VscaleMSByte to the VSCALE_HI reg */
WriteToBt829B( VSCALE_HI, newVscaleMSByte );
/* send the new VscaleLSByte to the VSCALE_LO reg */
WriteToBt829B( VSCALE_LO, (BYTE) VSCALE );
}
D829BDSA
27
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
where: &
= bitwise AND
= bitwise OR
>> = bit shift, MSB to LSB
|
If your target machine has sufficient memory to statically store the scaling
values locally, the READ operation can be eliminated.
On vertical scaling (when scaling below CIF resolution) it may be useful to
use a single field as opposed to using both fields. Using a single field will ensure
there are no inter-field motion artifacts on the scaled output. When performing
single field scaling, the vertical scaling ratio will be twice as large as when scaling with both fields. For example, CIF scaling from one field does not require any
vertical scaling, but when scaling from both fields, the scaling ratio is 50%. Also,
the non-interlaced bit should be reset when scaling from a single field (INT = 0 in
the VSCALE_HI register). Table 1-8 lists scaling ratios for various video formats,
and the register values required.
1.7.6 Image Cropping
Cropping enables the user to output any subsection of the video image. The
ACTIVE flag can be programmed to start and stop at any position on the video
frame as shown in Figure 1-14. The start of the active area in the vertical direction
is referenced to VRESET (beginning of a new field). In the horizontal direction it
is referenced to HRESET (beginning of a new line). The dimensions of the active
video region are defined by HDELAY, HACTIVE, VDELAY, and VACTIVE. All
four registers are 10-bit values. The two MSBs of each register are contained in
the CROP register, while the lower 8 bits are in the respective HDELAY_LO,
HACTIVE_LO, VDELAY_LO, and VACTIVE_LO registers. The vertical and
horizontal delay values determine the position of the cropped image within a
frame while the horizontal and vertical active values set the pixel dimensions of
the cropped image as illustrated in Figure 1-14.
28
D829BDSA
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
VDELAY
Video Frame
VACTIVE
Cropped image
VDELAY
HDELAY
HACTIVE
Video Frame
VACTIVE
Rising edge of VRESET
Figure 1-14. Effect of the Cropping and Active Registers
Cropped Image
Scaled to
1/2 Size
HDELAY
HACTIVE
Falling Edge of HRESET
D829BDSA
29
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
1.7.7 Cropping Registers
Horizontal Delay Register (HDELAY) HDELAY is programmed with the delay
between the falling edge of HRESET and the rising edge of ACTIVE. The count
is programmed with respect to the scaled frequency clock.
NOTE:
HDELAY should always be an even number.
Horizontal Active Register (HACTIVE) HACTIVE is programmed with the actual
number of active pixels per line of video. This is equivalent to the number of
scaled pixels that the Bt829B should output on a line. For example, if this register
contained 90, and HSCALE was programmed to down-scale by 4:1, then 90
active pixels would be output. The 90 pixels would be a 4:1 scaled image of the
360 pixels (at CLKx1) starting at count HDELAY. HACTIVE is restricted in the
following manner:
HACTIVE + HDELAY ≤ Total Number of Scaled Pixels.
For example, in the NTSC square pixel format, there is a total of 780 pixels,
including blanking, sync and active regions. Therefore:
HACTIVE + HDELAY ≤ 780.
When scaled by 2:1 for CIF, the total number of active pixels is 390. Therefore:
HACTIVE +HDELAY ≤ 390.
The HDELAY register is programmed with the number of scaled pixels
between HRESET and the first active pixel. Because the front porch is defined as
the distance between the last active pixel and the next horizontal sync, the video
line can be considered in three components: HDELAY, HACTIVE, and the front
porch. Figure 1-15 illustrates the video signal regions.
Figure 1-15. Regions of the Video Signal
HDELAY
30
Front
Porch
D829BDSA
HACTIVE
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
When cropping is not implemented, the number of clocks at the 4x sample
rate (the CLKx1 rate) in each of these regions is as follows:
CLKx1
Front Porch
CLKx1
HDELAY
CLKx1
HACTIVE
CLKx1
Total
NTSC
21
135
754
910
PAL/SECAM
27
186
922
1135
The value for HDELAY is calculated using the following formula:
HDELAY = [(CLKx1_HDELAY / CLKx1_HACTIVE) * HACTIVE] & 0x3FE
CLKx1_HDELAY and CLKx1_HACTIVE are constant values, so the equation becomes:
NTSC: HDELAY = [(135 / 754) * HACTIVE] & 0x3FE
PAL/SECAM: HDELAY = [(186 / 922) * HACTIVE] & 0x3FE
In this equation, the HACTIVE value cannot be cropped.
Vertical Delay Register (VDELAY) VDELAY is programmed with the delay
between the rising edge of VRESET and the start of active video lines. It determines how many lines to skip before initiating the ACTIVE signal. It is programmed with the number of lines to skip at the beginning of a frame.
Vertical Active Register (VACTIVE) VACTIVE is programmed with the number
of lines used in the vertical scaling process. The actual number of vertical lines
output from the Bt829B is equal to this register times the vertical scaling ratio. If
VSCALE is set to 0x1A00 (4:1), then the actual number of lines output is
VACTIVE/4. If VSCALE is set to 0x0000 (1:1), then VACTIVE contains the
actual number of vertical lines output.
NOTE:
It is important to note the difference between the implementation of the
horizontal registers (HSCALE, HDELAY, and HACTIVE) and the vertical
registers (VSCALE, VDELAY, and VACTIVE). Horizontally, HDELAY
and HACTIVE are programmed with respect to the scaled pixels defined
by HSCALE. Vertically, VDELAY and VACTIVE are programmed with
respect to the number of lines before scaling (before VSCALE is applied).
D829BDSA
31
Bt829B/827B
1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
VideoStream II Decoders
1.7.8 Temporal Decimation
Temporal decimation provides a solution for video synchronization during periods when full frame rate cannot be supported due to bandwidth and system
restrictions.
For example, when capturing live video for storage, system limitations such as
hard disk transfer rates or system bus bandwidth may limit the frame capture rate.
If these restrictions limit the frame rate to 15 frames per second, the Bt829B’s
time scaling operation will enable the system to capture every other frame instead
of allowing the hard disk timing restrictions to dictate which frame to capture.
This maintains an even distribution of captured frames and alleviates the “jerky”
effects caused by systems that simply burst in data when the bandwidth becomes
available.
The Bt829B provides temporal decimation on either a field or frame basis.
The Temporal Decimation TDEC register is loaded with a value from 1 to 60
(NTSC) or 1 to 50 (PAL/SECAM). This value is the number of fields or frames
skipped by the chip during a sequence of 60 for NTSC or 50 for PAL/SECAM.
Skipped fields and frames are considered inactive, which is indicated by the
ACTIVE pin remaining low. Consequently if QCLK is programmed to depend on
ACTIVE, QCLK would become inactive as well.
Examples:
TDEC = 0x02
TDEC = 0x9E
TDEC = 0x01
TDEC = 0x00
Decimation is performed by frames. Two frames are
skipped per 60 frames of video, assuming NTSC
decoding.
Frames 1–29 are output normally, then ACTIVE remains low for one frame. Frames 30–59 are then output
followed by another frame of inactive video.
Decimation is performed by fields. Thirty fields are
output per 60 fields of video, assuming NTSC
decoding.
This value outputs every other field (every odd field)
of video starting with Field 1 in Frame 1.
Decimation is performed by frames. One frame is
skipped per 50 frames of video, assuming
PAL/SECAM decoding.
Decimation is not performed. Full frame rate video is
output by the Bt829B.
When changing the programming in the temporal decimation register, 0x00
should be loaded first, and then the decimation value. This will ensure that the
decimation counter is reset to zero. If zero is not first loaded, the decimation may
start on any field or frame in the sequence of 60 (or 50 for PAL/SECAM). On
power-up, this preload is not necessary because the counter is reset internally.
When decimating fields, the FLDALIGN bit in the TDEC register can be programmed to choose whether the decimation starts with an odd field or an even
field. If the FLDALIGN bit is set to logical 0, the first field that is dropped during
the decimation process will be an odd field. Conversely, setting the FLDALIGN
bit to logical 1 causes the even field to be dropped first in the decimation process.
32
D829BDSA
Bt829B/827B
1.0 Functional Description
1.8 Video Adjustments
VideoStream II Decoders
1.8 Video Adjustments
The Bt829B provides programmable hue, contrast, saturation, and brightness.
1.8.1 The Hue Adjust Register (HUE)
The Hue Adjust Register is used to offset the hue of the decoded signal. In NTSC,
the hue of the video signal is defined as the phase of the subcarrier with reference
to the burst. The value programmed in this register is added or subtracted from the
phase of the subcarrier, which effectively changes the hue of the video. The hue
can be shifted by ±90 degrees. Because of the nature of PAL/SECAM encoding,
hue adjustments cannot be made when decoding PAL/SECAM.
1.8.2 The Contrast Adjust Register (CONTRAST)
The Contrast Adjust Register (also called the luma gain) provides the ability to
change the contrast from approximately 0 percent to 200 percent of the original
value. The decoded luma value is multiplied by the 9-bit coefficient loaded into
this register.
1.8.3 The Saturation Adjust Registers (SAT_U, SAT_V)
The Saturation Adjust Registers are additional color adjustment registers. It is a
multiplicative gain of the U and V signals. The value programmed in these registers are the coefficients for the multiplication. The saturation range is from
approximately 0 percent to 200 percent of the original value.
1.8.4 The Brightness Register (BRIGHT)
The Brightness Register is simply an offset for the decoded luma value. The programmed value is added or subtracted from the original luma value which
changes the brightness of the video output. The luma output is in the range of 0 to
255. Brightness adjustment can be made over a range of –128 to +127.
D829BDSA
33
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
1.9 Bt829B VBI Data Output Interface
1.9.1 Introduction
A frame of video is composed of 525 lines for NSTC and 625 for PAL/SECAM.
Figure 1-16 illustrates an NTSC video frame in which there are a number of distinct regions. The video image or picture data is contained in the ODD and EVEN
fields within lines 21–262 and lines 283–525, respectively. Each field of video
also contains a region for vertical synchronization (lines 1–9 and 263–272) as
well as a region which can contain non-video ancillary data (lines 10–20 and
273–282). We will refer to these regions which are between the vertical synchronization region and the video picture region as the Vertical Blanking Interval
(VBI) portion of the video signal.
Vertical Blanking Interval
Lines 21–262
Video Image Region
Lines 263–272
Lines 273–282
Vertical Blanking Interval
Lines 283–525
Video Image Region
Even Field
Lines 1–9
Lines 10–20
Odd Field
Figure 1-16. Regions of the Video Frame
Vertical
Synchronization
Region
Vertical
Synchronization
Region
1.9.2 Overview
In the default configuration of the Bt829B, the VBI region of the video signal is
treated the same way as the video image region of the signal. The Bt829B will
decode this signal as if it was video. For example, it will digitize at 8xFsc, decimate/filter to a 4xFsc sample stream, color separate to derive luma and chroma
component information, and interpolate for video synchronization and horizontal
scaling. This process is shown in Figure 1-17.
Figure 1-17. Bt829B YCrCb 4:2:2 Data Path
Composite
Analog
ADC
Decimation
Filter
8xFsc
34
D829BDSA
Y/C
Separation
Filter
4xFsc
Interpolation
Filter
YCrCb
4:2:2
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
The Bt829B can be configured in a mode known as VBI data pass through to
enable capture of the VBI region ancillary data for later processing by software.
In this mode the VBI region of the video signal is processed as follows:
•
•
•
The analog composite video signal is digitized at 8*Fsc (28.63636 MHz
for NTSC and 35.46895 MHz for PAL/SECAM). This 8-bit value represents a number range from the bottom of sync tip to the peak of the composite video signal.
The 8-bit data stream bypasses the decimation filter, Y/C separation filters,
and the interpolation filter (see Figure 1-18).
The Bt829B provides the option to pack the 8*Fsc data stream into a 2byte-wide stream at 4*Fsc before outputting it to the VD[15:0] data pins,
or it can simply be output as an 8-bit 8*Fsc data stream on pins VD[15:8].
In the packed format, the first byte of each pair on a 4*Fsc clock cycle is
mapped to VD[15:8] and the second byte to VD[7:0] with VD[7] and
VD[15] being the MSBs. The Bt829B uses the same 16-pin data port for
VBI data and YCrCb 4:2:2 image data. The byte pair ordering is
programmable.
Figure 1-18. Bt829B VBI Data Path
Composite
Analog
ADC
Decimation
Filter
8
Y/C
Separation
Filter
Pack
8xFsc
Composite
Analog
ADC
Decimation
Filter
Interpolation
Filter
VBI
Data
16
4xFsc
Y/C
Separation
Filter
Interpolation
Filter
VBI
Data
8
8xFsc
•
•
•
•
The VBI datastream is not pipeline-delayed to match the YCrCb 4:2:2
image output data with respect to horizontal timing (i.e., valid VBI data
will be output earlier than YCrCb 4:2:2 relative to the Bt829B HRESET
signal).
A larger number of pixels per line are generated in VBI output mode than
in YCrCb 4:2:2 output mode. The downstream video processor must be
capable of dealing with a varying number of pixels per line in order to capture VBI data, as well as YCrCb 4:2:2 data from the same frame.
The following pins may be used to implement this solution: VD[15:0],
VACTIVE, HACTIVE, DVALID, VRESET, HRESET, CLKx1, CLKx2,
and QCLK. This should allow the downstream video processor to load the
VBI data and the YCrCb 4:2:2 data correctly.
Because the 8*Fsc data stream does not pass through the interpolation filter, the sample stream is not locked/synchronized to the horizontal sync
timing. The only implication of this is that the sample locations on each
line are not correlated vertically.
D829BDSA
35
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
1.9.3 Functional Description
There are three modes of operation for the Bt829B VBI data pass-through feature:
VBI Data Pass through Disabled. This is the default mode of operation for
the Bt829B during which the device decodes composite video and generates a YCrCb 4:2:2 data stream.
2 VBI Line Output Mode. The device outputs unfiltered 8*Fsc data only during the vertical interval which is defined by the VACTIVE output signal
provided by the Bt829B. Data is output between the trailing edge of the
VRESET signal and the leading edge of VACTIVE. When VACTIVE is
high, the Bt829B is outputting standard YCrCb 4:2:2 data. This mode of
operation is intended to be used to enable capture of VBI lines containing
ancillary data in addition to processing normal YCrCb 4:2:2 video image
data.
3 VBI Frame Output Mode. In this mode the Bt829B treats every line in the
video signal as if it were a vertical interval line and outputs only the unfiltered 8*Fsc data on every line (i.e., it does not output any image data). This
mode of operation is designed for use in still-frame capture/processing
applications.
1
1.9.4 VBI Line Output Mode
The VBI line output mode is enabled via the VBIEN bit in the VTC Register
(0x1B). When enabled, the VBI data is output during the VBI active period. The
VBI horizontal active period is defined as the interval between consecutive
Bt829B HRESET signals. Specifically, it starts at a point one CLKx1 interval
after the trailing edge of the first HRESET and ends with the leading edge of the
following HRESET. This interval is coincident with the HACTIVE signal as
indicated in Figure 1-19.
Figure 1-19. VBI Line Output Mode Timing
HRESET
HACTIVE
VD[15:0]
VBI Data
DVALID is always at a logical 1 during VBI. Also, QCLK is operating continuously at CLKx1 or CLKx2 rate during VBI. Valid VBI data is available one
CLKx1 (or QCLK) interval after the trailing edge of HRESET. When the Bt829B
is configured in VBI line output mode, it is generating invalid data outside of the
VBI horizontal active period. In standard YCrCb output mode, the horizontal
active period starts at a time point delayed from the leading edge of HRESET as
defined by the value programmed in the HDELAY register.
36
D829BDSA
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
The VBI data sample stream which is output during the VBI horizontal active
period represents an 8*Fsc sampled version of the analog video signal starting in
the vicinity of the subcarrier burst and ending after the leading edge of the horizontal synchronization pulse as illustrated in Figure 1-20.
Figure 1-20. VBI Sample Region
Extent of Analog Signal Captured in VBI Samples
The number of VBI data samples generated on each line may vary depending
on the stability of the analog composite video signal input to the Bt829B. The
Bt829B will generate 845 16-bit VBI data words for NTSC and 1,070 16-bit VBI
data words for PAL/SECAM on each VBI line at a CLKx1 rate, assuming a nominal or ideal video input signal (i.e., the analog video signal has a stable horizontal
time base). This is also equivalent to 1,690 8-bit VBI data samples for NTSC and
2,140 8-bit VBI data samples for PAL/SECAM. These values can deviate from
the nominal depending on the actual line length of the analog video signal.
The VBI vertical active period is defined as the period between the trailing
edge of the Bt829B VRESET signal and the leading edge of VACTIVE.
NOTE:
The extent of the VBI vertical active region can be controlled by setting
different values in the VDELAY register. This provides the flexibility to
configure the VBI vertical active region as any group of consecutive lines
starting with line 10 and extending to the line number set by the equivalent
line count value in the VDELAY register (i.e., the VBI vertical active
region can be extended into the video image region of the video signal).
The VBI horizontal active period starts with the trailing edge of an HRESET;
therefore, if a rising edge of VRESET occurs after the horizontal active period has
already started, the VBI active period starts on the following line. The HACTIVE
pin is held at a logical 1 during the VBI horizontal active period. DVALID is held
high during both the VBI horizontal active and horizontal inactive periods (i.e., it
is held high during the whole VBI scan line.) These relationships are illustrated in
Figure 1-21.
D829BDSA
37
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
Figure 1-21. Location of VBI Data
Odd Field
VRESET
HRESET
HACTIVE
VACTIVE
DVALID
VD[15:0]
VBI Data
VBI Data
VBI Data
Invalid Data
YCrCb Data
VBI Active Region
Even Field
VRESET
HRESET
HACTIVE
VACTIVE
DVALID
VD[15:0]
VBI Data
VBI Data
Invalid Data
YCrCb Data
VBI Active Region
38
D829BDSA
VBI Data
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
The Bt829B can provide VBI data in all the pixel port output configurations
(i.e., 16-bit SPI, 8-bit SPI, and ByteStream modes). The range of the VBI data can
be controlled with the RANGE bit in the OFORM Register (0x12). It is necessary
to limit the range of VBI data for ByteStream output mode.
There must be a video signal present on the Bt829B analog input as defined by
the status of the VPRES bit in the STATUS register in order for the Bt829B to
generate VBI data. If the status of the VPRES bit reflects no analog input, then the
Bt829B generates YCrCb data to create a flat blue field image.
The order in which the VBI data is presented on the output pins is programmable. Setting the VBIFMT bit in the VTC register to a logical 0 places the nth data
sample on VD[15:8] and the nth+1 sample on VD[7:0]. Setting VBIFMT to a logical 1, logical 0 reverses the above. Similarly, in ByteStream and 8-bit output
modes, setting VBIFMT = 0 generates a VBI sample stream with an ordering
sequence of n+1, n, n+3, n+2, n+5, n+4, etc. Setting VBIFMT = 1 for
ByteStream/8-bit output generates an n, n+1, n+2, n+3, etc. sequence as shown in
Figure 1-22.
Figure 1-22. VBI Sample Ordering
16-bit SPI Mode (VBIFMT = 0)
VD[15:8]
n
n+2
VD[7:0]
n+1
n+3
CLKx1
8-bit SPI Mode (VBIFMT = 1)
VD[15:8]
n
n+1
n+2
n+3
CLKx2
A video processor/controller must be able to do the following to capture VBI
data output by the Bt829B:
•
•
•
Keep track of the line count in order to select a limited number of specific
lines for processing of VBI data.
Handle data type transitioning on the fly from the vertical interval to the
active video image region. For example, during the vertical interval with
VBI data pass through enabled, it must grab every byte pair while HACTIVE is high using the 4*Fsc clock or QCLK. However, when the data
stream transitions into YCrCb 4:2:2 data mode with VACTIVE going high,
the video processor must interpret the DVALID signal (or use QCLK for
the data load clock) from the Bt829B for pixel qualification and use only
valid pixel cycles to load image data (default Bt829B operation).
Handle a large and varying number of horizontal pixels per line in the VBI
region as compared to the active image region.
D829BDSA
39
Bt829B/827B
1.0 Functional Description
1.9 Bt829B VBI Data Output Interface
VideoStream II Decoders
1.9.5 VBI Frame Output Mode
In VBI frame output mode, the Bt829B is generating VBI data all the time (i.e.,
there is no VBI active interval). In essence, the Bt829B is acting as an ADC
continuously sampling the entire video signal at 8*Fsc. The Bt829B generates
HRESET,VRESET and FIELD timing signals in addition to the VBI data, but the
DVALID, HACTIVE, and VACTIVE signals are all held high during VBI frame
output operation. The behavior of the HRESET,VRESET, and FIELD timing
signals is the same as normal YCrCb 4:2:2 output operation. The
HRESET,VRESET, and FIELD timing signals can be used by the video processor
to detect the beginning of a video frame/field, at which point it can start to capture
a full frame/field of VBI data.
The number of VBI data samples generated on each line may vary depending
on the stability of the analog composite video signal input to the Bt829B. The
Bt829B will generate 910 16-bit VBI data words for NTSC and 1,135 16-bit VBI
data words for PAL/SECAM for each line of analog video input at a CLKx1 rate,
assuming a nominal or ideal video input signal (i.e., analog video signal has a stable horizontal time base). This is also equivalent to 1,820 8-bit VBI data samples
for NTSC and, 270 8-bit VBI data samples for PAL/SECAM for each line of analog video input. These values can deviate from the nominal depending on the
actual line length of the analog video signal.
VBI frame output mode is enabled via the VBIFRM bit in the OFORM register. The output byte ordering may be controlled by the VBIFMT bit as described
for VBI line output mode. If both VBI line output and VBI frame output modes
are enabled at the same time, the VBI frame output mode takes precedence. The
VBI data range in VBI frame output mode can be controlled using the RANGE
bit in the OFORM register, and a video signal must be present on the Bt829B analog input for this mode to operate as defined by the status of the VPRES bit in the
STATUS register (0x00).
40
D829BDSA
Bt829B/827B
1.0 Functional Description
1.10 Closed Captioning and Extended Data Services Decoding
VideoStream II Decoders
1.10 Closed Captioning and Extended Data
Services Decoding
In a system capable of capturing Closed Captioning and Extended Data Services
adhering to the EIA-608 standard, 2 bytes of information are presented to the
video decoder on line 21 (odd field) for CC and an additional two bytes are presented on line 284 (even field) for EDS.
The data presented to the video decoder is an analog signal on the composite
video input. The signal contains information identifying it as the CC/EDS data
and is followed by a control code and 2 bytes of digital information transmitted
by the analog signal. For the purposes of CC/EDS, only the luma component of
the video signal is relevant. Therefore, the composite signal goes through the decimation and Y/C separation blocks of the Bt829B before any CC/EDS decoding
takes place. See Figure 1-23 for a representation of this procedure.
Figure 1-23. CC/EDS Data Processing Path
Composite
Analog
ADC
Decimation
Filter
Y/C
Separation
Filter
Interpolation
Filter
Luma
CC/EDS
Decoder
YCrCb
4:2:2
CC_Status
Register
I2C
CC_Data
Register
I2C
CC/EDS
FIFO
The Bt829B can be programmed to decode CC/EDS data via the corresponding bits in the Extended Data Services/Closed Caption Status Register
(CC_STATUS;0X1C). The CC and EDS are independent and the video decoder
may capture one or both in a given frame. The CC/EDS signal is displayed in
Figure 1-24. In CC/EDS decode mode, once Bt829B has detected that line 21 of
the field is being displayed, the decoder looks for the Clock Run-In signal. If the
Clock Run-In signal is present and the correct start code (001) is recognized by
Bt829B, then the CC/EDS data capture commences. Each of the 2 bytes of data
transmitted to the video decoder per field contains a 7-bit ASCII code and a parity
bit. The convention for CC/EDS data is odd parity.
Figure 1-24. CC/EDS Incoming Signal
HSync Color
Burst
Clock Run-in
Start Bits
Character One
Character Two
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50
IRE
25
0
–40
D829BDSA
41
Bt829B/827B
1.0 Functional Description
1.10 Closed Captioning and Extended Data Services Decoding
VideoStream II Decoders
The Bt829B provides a 16 x 10 location FIFO for storing CC/EDS data. Once the
video decoder detects the start signal in the CC/EDS signal, it captures the low
byte of CC/EDS data first and checks to see if the FIFO is full. If the FIFO is not
full, then the data is stored in the FIFO, and is available to the user through the
CC_DATA register (0x1D). The high byte of CC/EDS data is captured next and
placed in the FIFO. Upon being placed in the 10-bit FIFO, two additional bits are
attached to the CC/EDS data byte by Bt829B’s CC/EDS decoder. These two bits
indicate whether the given byte stored in the FIFO corresponds to CC or EDS
data and whether it is the high or low byte of CC/EDS. These two bits are available to the user through the CC_STATUS register bits CC_EDS and LO_HI,
respectively.
The parity bit is stored in the FIFO as shown in Figure 1-25. Additionally, the
Bt829B stores the results of the parity check in the PARITY_ERR bit in the
CC_STATUS register.
Figure 1-25. Closed Captioning/Extended Data Services FIFO
9 8 7 6
...
0
...
Location 0
Location 1
MSB
LSB Location 15
7-bit ASCII code available through CC_DATA Register
Parity Bit Available Through CC_DATA Register
LO_HI Available Through CC_STATUS Register
CC_EDS Available Through CC_STATUS Register
The 16-location FIFO can hold eight lines worth of CC/EDS data, at two bytes
per line. Initially when the FIFO is empty, the DA bit in the CC_STATUS register
(0x1C) is set low and indicates that no data is available in the FIFO. Subsequently, when data has been stored in the FIFO, the DA bit is set to logical high.
Once the FIFO is half full, the CC_VALID interrupts pin signals to the system
that the FIFO contents should be read in the near future. The CC_VALID pin is
enabled via a bit in the CC_STATUS register (0x1C). The system controller can
then poll the CC_VALID bit in the STATUS register (0x00) to ensure that it was
the Bt829B that initiated the CC_VALID interrupt. This bit can also be used in
applications where the CC_VALID pin is disabled by the user.
42
D829BDSA
Bt829B/827B
1.0 Functional Description
1.10 Closed Captioning and Extended Data Services Decoding
VideoStream II Decoders
When the first byte of CC/EDS data is decoded and stored in the FIFO, the
data is immediately placed in the CC_DATA and CC_STATUS registers and is
available to be read. Once the data is read from the CC_DATA register, the information in the next location of the FIFO is placed in the CC_DATA and
CC_STATUS registers.
If the controller in the system ignores the Bt829B CC_VALID interrupts pin
for a sufficiently long period of time, then the CC/EDS FIFO will become full and
the Bt829B will not be able to write additional data to the FIFO. Any incoming
bytes of data will be lost and an overflow condition will occur; bit OR in the
CC_STATUS register will be set to a logical 1. The system may clear the overflow
condition by reading the CC/EDS data and creating space in the FIFO for new
information. As a result, the overflow bit is reset to a logical 0.
There will routinely be asynchronous reads and writes to the CC/EDS FIFO.
The writes will be from the CC/EDS circuitry and the reads will occur as the system controller reads the CC/EDS data from Bt829B. These reads and writes will
sometimes occur simultaneously, and the Bt829B is designed to give priority to
the read operations. In the case where the CC_DATA register data is specifically
being read to clear an overflow condition, the simultaneous occurrence of a read
and a write will not cause the overflow bit to be reset, even though the read has
priority. An additional read must be made to the CC_DATA register in order to
clear the overflow condition. As always, the write data will be lost while the FIFO
is in overflow condition.
The FIFO is reset when both CC and EDS bits are disabled in the
CC_STATUS register; any data in the FIFO is lost.
1.10.1 Automatic Chrominance Gain Control
The Automatic Chrominance Gain Control (ACGC) compensates for reduced
chrominance and color-burst amplitude. This can be caused by high-frequency
loss in cabling. Here, the color-burst amplitude is calculated and compared to
nominal. The color-difference signals are then increased or decreased in amplitude according to the color-burst amplitude difference from nominal. The maximum amount of chrominance gain is 0.5–2 times the original amplitude. This
compensation coefficient is then multiplied by the value in the Saturation Adjust
Register for a total chrominance gain range of 0–2 times the original signal. Automatic chrominance gain control may be disabled by setting the ACGC bit in the
SCLOOP register to a logical 0.
1.10.2 Low Color Detection and Removal
If a color burst of 25 percent (NTSC) or 35 percent (PAL/SECAM) or less of the
nominal amplitude is detected for 127 consecutive scan lines, the color-difference
signals U and V are set to zero. When the low color detection is active, the
reduced chrominance signal is still separated from the composite signal to generate the luminance portion of the signal. The resulting Cr and Cb values are 128.
Output of the chrominance signal is re-enabled when a color burst of 43 percent
(NTSC) or 60 percent (PAL/SECAM) or greater of nominal amplitude is detected
for 127 consecutive scan lines.
Low color detection and removal may be disabled by setting the CKILL bit in
the SCLOOP register (0x10) to a logical 0.
D829BDSA
43
Bt829B/827B
1.0 Functional Description
1.10 Closed Captioning and Extended Data Services Decoding
VideoStream II Decoders
1.10.3 Coring
The Bt829B video decoder can perform a coring function, in which it forces all
values below a programmed level to be zero. This is useful because the human
eye is more sensitive to variations in black images. By taking near-black images
and turning them into black, the image appears clearer to the eye.
Four coring values can be selected by the Output Format Register (OFORM;
0x12): 0, 8, 16, or 32 above black. If the total luminance level is below the
selected limit, the luminance signal is truncated to the black value. If the luma
range is limited (i.e., black is 16), then the coring circuitry automatically takes
this into account and references the appropriate value for black. This is illustrated
in Figure 1-26.
Output
Luma Value
Figure 1-26. Coring Map
32
16
8
0
0
44
D829BDSA
8 16 32
Calculated
Luma Value
2.0 Electrical Interfaces
2.1 Input Interface
2.1.1 Analog Signal Selection
The Bt829B/827B contains an on-chip 4:1 MUX. For the Bt829B and Bt827B,
this multiplexer can be used to switch between four composite sources or three
composite sources and one S-Video source. In the first configuration, connect the
inputs of the multiplexer (MUX[0], MUX[1], MUX[2], and MUX[3]) to the four
composite sources. In the second configuration, connect three inputs to the composite sources and the other input to the luma component of the S-Video connector. In both configurations the output of the multiplexer (MUXOUT) should be
connected to the input to the luma A/D (YIN) and the input to the sync detection
circuitry (SYNCDET) through a optional 0.1 µF capacitor (to maintain compatibility with the Bt829/827). When implementing S-Video, the input to the chroma
A/D (CIN) should be connected to the chroma signal of the S-Video connector.
Use of the multiplexer is not a requirement for operation. If digitization of
only one video source is required, the source may be connected directly to YIN.
2.1.2 Multiplexer Considerations
The multiplexer is not a break-before-make design. Therefore, during the multiplexer switching time it is possible for the input video signals to be momentarily
connected together through the equivalent of 200 Ω.
The multiplexers cannot be switched on a real-time pixel-by-pixel basis.
D829BDSA
45
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
2.1.3 Autodetection of NTSC or PAL/SECAM Video
If the Bt829B is configured to decode both NTSC and PAL/SECAM, the Bt829B
can be programmed to automatically detect which format is being input to the
chip. Autodetection will select the proper clock source for the detected format. If
NTSC/PAL–M is detected, XTAL0 is selected. If PAL/SECAM is detected,
XTAL1 is selected. For PAL-N combination the user must manually select the
XTAL0 crystal. Full control of the decoding configuration can be programmed by
writing to the Input Format Register (0x01).
The Bt829B determines the video source input to the chip by counting the
number of lines in a frame. Bit NUML indicates the result in the STATUS register. Based on this bit, the format of the video is determined, and XT0 or XT1 is
selected for the clock source. Automatic format detection will select the clock
source, but it will not program the required registers. The scaling and cropping
registers (VSCALE, HSCALE, VDELAY, HDELAY, VACTIVE, and HACTIVE),
as well as the burst delay and AGC delay registers (BDELAY and ADELAY)
must be programmed accordingly.
2.1.4 Flash A/D Converters
The Bt829B and Bt827B use two on-chip flash A/D converters to digitize the
video signals. YREF+, CREF+, YREF–, and CREF– are the respective top and
bottom of the internal resistor ladder.
The input video is always AC-coupled to the decoder. CREF– and YREF– are
connected to analog ground. The voltage levels for YREF+ and CREF+ are
controlled by the gain control circuitry. If the input video momentarily exceeds
the corresponding REF+ voltage, it is indicated by LOF and COF in the STATUS
register.
2.1.5 A/D Clamping
An internally generated clamp control signal is used to clamp the inputs of the
A/D converter for DC restoration of the video signals. Clamping for both the YIN
and CIN analog inputs occurs within the horizontal sync tip. The YIN input is
always restored to ground while the CIN input is always restored to CLEVEL.
CLEVEL can be set with an optional external resistor network so that it is biased
to the midpoint between CREF– and CREF+. This ensures backward compatibility with the Bt819A/7A/5A, but is not required for the Bt829B/827B. External
clamping is not required because internal clamping is automatically performed.
2.1.6 Power-Up Operation
Upon power-up, the status of the Bt829B’s registers is indeterminate. The RST
signal must be asserted to set the register bits to their default values. The Bt829B
device defaults to NTSC-M format upon reset. If pin 85 (OEPOLE) is tied to a
logical high on power-up and the RST signal is asserted, then the video pixel bus,
sync signals, and output clocks will be three-stated.
46
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
2.1.7 Automatic Gain Controls (AGC)
The REFOUT, CREF+, and YREF+ pins should be connected together as shown
in Figure 2-1. In this configuration, the Bt829B controls the voltage for the top of
the reference ladder for each A/D. The automatic gain control adjusts the YREF+
and CREF+ voltage levels until the back porch of the Y-video input generates a
digital code 0x38 from the A/D. If the video being digitized has a non-standard
sync height to video height ratio, the digital code used for AGC may be changed
by programming the ADC Interface Register (0x1A). Figure 2-2 illustrates
Bt829B external circuitry with reduced passive components.
D829BDSA
47
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
Figure 2-1. Bt829B Typical External Circuitry with Third Overtone Crystal Oscillators (5 V VDD)
Optional
Antialiasing Filter
VAA
REFOUT
YREF+
1.0 µF
3.3 µH
VPOS
MUX(0–2)
AGCCAP
330 pF 330 pF
CREF+
75 Ω
0.1 µF
0.1 µF
VNEG
CLEVEL
JTAG
0.1 µF
I2C
YREF–
Video Timing
CREF–
VDD
100 KΩ
1.0 µF
MUX0
CCVALID
0.1 µF
75 Ω
2.2 µH
XT1O
35.46895
MHz
1.0 µF
1 MΩ
33 pF
XT1I
22 pF
MUX1
75 Ω
0.1 µF
1.0 µF
MUX2
2.7 µH
XT0O
28.63636
MHz
75 Ω
1 MΩ
33 pF
XT0I
22 pF
1.0 µF
MUX3
VAA
75 Ω
MUXOUT
75 Ω Termination
YIN
Digital Ground
0.1 µF
CIN
SYNCDET
Analog Ground
75 Ω
AC-Coupling
Capacitor
48
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
Figure 2-2. Bt829B Typical External Circuitry with Third Overtone Crystal Oscillators (3.3V VDDO)
Optional
Antialiasing Filter
VAA
REFOUT
YREF+
1.0 µF
3.3 µH
VPOS
MUX(0–2)
AGCCAP
330 pF 330 pF
CREF+
75 Ω
0.1 µF
0.1 µF
VNEG
CLEVEL
JTAG
0.1 µF
I2C
YREF–
Video Timing
CREF–
VDD
100 KΩ
1.0 µF
MUX0
CCVALID
75 Ω
22 pF
XT1O
35.46895
MHz
1.0 µF
1 MΩ
XT1I
22 pF
MUX1
75 Ω
2.7 µH
68 pF
0.1 µF
1.0 µF
MUX2
XT0O
28.63636
MHz
75 Ω
1 MΩ
XT0I
22 pF
1.0 µF
2.7 µH
100 pF
MUX3
VAA
75 Ω
MUXOUT
75 Ω Termination
YIN
Digital Ground
0.1 µF
CIN
SYNCDET
Analog Ground
75 Ω
AC-Coupling
Capacitor
D829BDSA
49
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
2.1.8 Crystal Inputs and Clock Generation
The Bt829B has two pairs of pins: XT0I/XT0O and XT1I/XT1O. They are used
to input a clock source. If both NTSC and PAL video are being digitized, both
clock inputs must be implemented. The XT0 port is used to decode NTSC video
and must be configured with a 28.63636 MHz source. The XT1 port is used to
decode PAL video and must be configured with a 35.46895 MHz source.
If the Bt829B is configured to decode either NTSC or PAL, but not both, then
only one clock source must be provided to the chip and it must be connected to
the XT0I/XT0O port. If a crystal input is not used, the crystal amplifiers are
internally shut down to save power.
Crystals are specified as follows:
•
•
•
•
•
•
28.636363 MHz or 35.468950 MHz
Third overtone
Parallel resonant
30 pF load capacitance
50 ppm
Series resistance 40 Ω or less
The following crystals are recommended for use with the Bt829B:
1
2
3
4
5
6
Standard Crystal
(818) 443-2121
2BAK28M636363GLE30A
2BAK35M468950GLE30A
GED
(619) 591-4170
PKHC49-28.63636-.030-005-40R, 3rd overtone crystal
PKHC49-35.46895-.030-005-40R, 3rd overtone crystal
M-Tron
(800) 762-8800
MP-1 28.63636, 3rd overtone crystal
MP-1 35.46895, 3rd overtone crystal
Monitor
(619) 433-4510
MM49X3C3A-28.63636, 3rd overtone crystal
MM49X3C3A-35.46895, 3rd overtone crystal
CTS
(815) 786-8411
R3B55A30-28.63636, 3rd overtone crystal
R3B55A30-35.46895, 3rd overtone crystal
Fox
(813) 693-0099
HC49U-28.63636, 3rd overtone crystal
HC49U-35.46895, 3rd overtone crystal
The two clock sources may be configured using single-ended oscillators, fundamental cut crystals, or third overtone mode crystals, with parallel resonant. If
single-ended oscillators are used, they must be connected to XT0I and XT1I.
Figure 2-3 shows the clock source options and circuit requirements.
50
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
The clock source tolerance should be 50 ppm or less, but 100 ppm is acceptable. Devices that output CMOS voltage levels are required. The load capacitance
in the crystal configurations may vary, depending on the magnitude of board parasitic capacitance. The Bt829B is dynamic; to ensure proper operation, the clocks
must always be running with a minimum frequency of 28.64 MHz.
The CLKx1 and CLKx2 outputs from the Bt829B are generated from XT0
and XT1 clock sources. CLKx2 operates at the crystal frequency (8xFsc), while
CLKx1 operates at half the crystal frequency (4xFsc).
When the Bt829B is run in the 3.3 V digital I/O mode using third overtone
crystals, the circuit shown in Figure 2-3 must be used. When the Bt829B is run in
normal 5 V mode using third overtone crystals, the circuit shown in Figure 2-4
must be used.
D829BDSA
51
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
28.63636 MHz
35.46895 MHz
1 MΩ
1 MΩ
22 pF
2.7 µH
100 pF
68 pF
XT0I
XT1I
Osc
28.63636 MHz
XT1I
XT0I
35.46895 MHz
PAL/SECAM Single-Ended Oscillator
XT0O
NTSC Single-Ended Oscillator
28.63636 MHz
35.46895 MHz
1 MΩ
1 MΩ
47 pF
NTSC Fundamental Crystal Oscillator
52
XT1O
PAL/SECAM Third Overtone Mode Crystal Oscillator
XT0O
NTSC Third Overtone Mode Crystal Oscillator
47 pF
22 pF
22 pF
XT1O
22 pF
2.7 µH
Osc
XT1O
XT1I
XT0I
XT0O
Figure 2-3. Clock Options (3.3 V VDD)
47 pF
47 pF
PAL/SECAM Fundamental Crystal Oscillator
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
28.63636 MHz
35.46895 MHz
1 MΩ
1 MΩ
0.1 µF
XT1O
XT1I
XT0I
35.46895 MHz
PAL/SECAM Single-Ended Oscillator
XT0O
XT0I
47 pF
Osc
28.63636 MHz
NTSC Single-Ended Oscillator
33 pF
PAL/SECAM Third Overtone Mode Crystal Oscillator
XT0O
NTSC Third Overtone Mode Crystal Oscillator
Osc
2.2 µH
33 pF
XT1O
2.7 µH
0.1 µF
22 pF
XT1I
22 pF
XT1O
XT1I
XT0I
XT0O
Figure 2-4. Clock Options (5 V VDD)
28.63636 MHz
35.46895 MHz
1 MΩ
1 MΩ
47 pF
NTSC Fundamental Crystal Oscillator
47 pF
47 pF
PAL/SECAM Fundamental Crystal Oscillator
D829BDSA
53
Bt829B/827B
2.0 Electrical Interfaces
2.1 Input Interface
VideoStream II Decoders
2.1.9 2X Oversampling and Input Filtering
To avoid aliasing artifacts, digitized video needs to be band-limited. Because the
Bt829B samples at CLKx2 (8xFsc—more than twice the normal rate), no filtering
is required at the input to the A/Ds. The analog video needs to be band-limited to
14.32 MHz in NTSC and 17.73 MHz in PAL/SECAM mode. Normal video
signals do not require additional external filtering. However, if noise or other
signal content is expected above these frequencies, the optional antialiasing filter
shown in Figure 2-1 may be included in the input signal path. After digitization,
the samples are digitally low-pass filtered and then decimated to CLKx1. The
response of the digital low-pass filter is shown in Figure 2-5. The digital low-pass
filter provides the digital bandwidth reduction to limit the video to 6 MHz.
Figure 2-5. Luma and Chroma 2x Oversampling Filter
PAL/SECAM
NTSC
NTSC
54
PAL/SECAM
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
2.2 Output Interface
2.2.1 Output Interfaces
The Bt829B supports a Synchronous Pixel Interface (SPI). SPI can support 8-bit
or 16-bit YCrCb 4:2:2 data streams.
Bt829B outputs all pixel and control data synchronous with CLKx1 (16-bit
mode), or CLKx2 (8-bit mode). Events such as HRESET and VRESET may also
be encoded as control codes in the data stream to enable a reduced pin interface
(ByteStream).
Mode selections are controlled by the state of the OFORM register (0x12).
Figure 2-6 shows a diagram summarizing the different operating modes. On
power-up, the Bt829B automatically initializes to SPI Mode 1, 16 bits wide.
Figure 2-6. Output Mode Summary
Parallel Control
(SPI Mode 1)
8-bit
Coded Control
(SPI Mode 2)
8-bit
16-bit
SPI
D829BDSA
(ByteStream)
16-bit
55
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
2.2.2 YCrCb Pixel Stream Format, SPI Mode, 8- and 16-Bit Formats
When the output is configured for an 8-bit pixel interface, the data is output on
pins VD[15:8]. Eight bits of chrominance data precede 8 bits of luminance data
for each pixel. New pixel data is output on the pixel port after each rising edge of
CLKx2. When the output is configured for the 16-bit pixel interface, the
luminance data is output on VD[15:8], and the chrominance data is output on
VD[7:0]. In 16-bit mode, the data is output with respect to CLKx1. See Table 2-1
for a summary of output interface configurations. The YCrCb 4:2:2 pixel stream
follows the CCIR recommendation, as illustrated in Figure 2-7.
Table 2-1. Pixel/Pin Map
16-Bit Pixel Interface
Pin
Name
Data Bit
VD15
VD14
VD13
VD12
VD11
VD10
VD9
VD8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
CrCb7 CrCb6 CrCb5 CrCb4 CrCb3 CrCb2 CrCb1 CrCb0
8-Bit Pixel Interface
Pin
Name
VD15
VD14
VD13
VD12
VD11
VD10
VD9
VD8
Y-Data
Bit
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
C-Data
Bit
VD7
VD6
VD5
VD4
VD3
CrCb7 CrCb6 CrCb5 CrCb4 CrCb3 CrCb2 CrCb1 CrCb0
Figure 2-7. YCrCb 4:2:2 Pixel Stream Format (SPI Mode, 8- and 16-Bits)
CLKx2
CLKx1
8-Bit Pixel Interface
VD[15:8]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
16-Bit Pixel Interface
56
VD[15:8]
Y0
Y1
Y2
Y3
VD[7:0]
Cb0
Cr0
Cb2
Cr2
D829BDSA
VD2
VD1
VD0
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
2.2.3 Synchronous Pixel Interface (SPI Mode 1)
Upon reset, the Bt829B initializes to the SPI output, Mode 1 (SPI-1). In this
mode, Bt829B outputs all horizontal and vertical blanking interval pixels, in addition to the active pixels synchronous with CLKx1 (16-bit mode), or CLKx2 (8-bit
mode). Figure 2-8 illustrates SPI-1 for the Bt829B. The basic timing relationships
remain the same for 16-bit or 8-bit modes. The 16-bit mode uses CLKx1 as the
reference. The 8-bit mode uses CLKx2. Figure 2-9 shows the video timing for
SPI Mode 1.
Figure 2-8. Bt829B/827B Synchronous Pixel Interface, Mode 1 (SPI-1)
HRESET
VRESET
ACTIVE
DVALID
CBFLAG
FIELD
QCLK
Bt829B
16
VD[15:0]
OE
CLKx1 (4*Fsc)
CLKx2 (8*Fsc)
Figure 2-9. Basic Timing Relationships for SPI Mode 1
VD[15:0]
DVALID
ACTIVE
CLKx1
or
CLKx2
QCLK
CbFLAG
D829BDSA
57
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
2.2.4 Synchronous Pixel Interface (SPI Mode 2, ByteStream)
In SPI Mode 2, the Bt829B encodes all video timing control signals onto the pixel
data bus. ByteStream is the 8-bit version of this configuration. Because all timing
data is included on the data bus, a complete interface to a video controller can be
implemented in only nine pins: one for CLK x 2, and eight for data.
When using coded control, the RANGE bit and the CODE bit must be programmed high. When the RANGE bit is high, the chrominance pixels (both Cr
and Cb) are saturated to the range 2 to 253, and the luminance range is limited to
the range 16 to 253. In SPI Mode 2, the following values are inserted as control
codes to indicate video events (see Table 2-2): the chroma values of 255 and 254,
and the luminance values of 0 to 15. A chroma value of 255 indicates that the
associated luma pixel is a control code; a pixel value of 255 indicates that the
CbFlag is high (i.e., the current pixel is a Cb pixel). Similarly, a pixel value of 254
indicates that the luma value is a control code, and that the CbFlag is low (Cr
pixel).
The first pixel of a line is guaranteed to be a Cb flag. However, due to code
precedence relationships, the HRESET code may be delayed by one pixel, so
HRESET can occur on a Cr or a Cb pixel. Also, at the beginning of a new field,
the relationship between VRESET and HRESET may be lost, typically with video
from a VCR. As a result, VRESET can occur during either a Cb or a Cr pixel.
Figure 2-10 demonstrates coded control for SPI Mode 2 (ByteStream).
Table 2-2 shows pixel data output ranges. Independent of RANGE, decimal
128 indicates zero color information for Cr and Cb. Black is decimal 16 when
RANGE = 0 and code 0 when RANGE = 1.
Figures 2-11 and 2-12 illustrate videotiming for SPI Modes 1 and 2.
Table 2-2. Description of the Control Codes in the Pixel Stream
58
Luma
Value
Chroma
Value
0x00
0xFF
0xFE
This is an invalid pixel; last valid pixel was a Cb pixel.
This is an invalid pixel; last valid pixel was a Cr pixel.
0x01
0xFF
0xFE
Cb pixel; last pixel was the last active pixel of the line.
Cr pixel; last pixel was the last active pixel of the line.
0x02
0xFF
0xFE
Cb pixel; next pixel is the first active pixel of the line.
Cr pixel; next pixel is the first active pixel of the line.
Video Event Description
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
Table 2-2. Description of the Control Codes in the Pixel Stream
Luma
Value
Chroma
Value
0x03
0xFF
0xFE
Cb pixel; HRESET of a vertical active line.
Cr pixel; HRESET of a vertical active line.
0x04
0xFF
0xFE
Cb pixel; HRESET of a vertical blank line.
Cr pixel; HRESET of a vertical blank line.
0x05
0xFF
0xFE
Cb pixel; VRESET followed by an even field.
Cr pixel; VRESET followed by an even field.
0x06
0xFF
0xFE
Cb pixel; VRESET followed by an odd field.
Cr pixel; VRESET followed by an odd field.
Video Event Description
Figure 2-10. Data Output in SPI Mode 2 (ByteStream)
CLKx2
HRESET: beginning of horizontal line during vertical blanking
HRESET, beginning of horizontal line during active video
VD(15:8)
0xFF
0x04
0xFF
•••
Cb pixel
•••
0xFF
Cb
•••
Cb pixel
0x02
Next pixel is first
active pixel of the line
•••
0x03
Y
Cb
Y
Cr
Y
•••
Cr
Y
•••
XX
XX
•••
XX
XX
•••
First active pixel of the line
0xFF
0x00
Invalid pixel during active video
Last valid pixel was a Cb pixel
•••
Cb
Y
Last pixel of the line
(Cb pixel)
0xFE
0x01
Last pixel code
(Cr pixel)
VRESET: an odd field follows
•••
XX
XX
0xFE
0x06
Cr pixel
D829BDSA
59
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
Figure 2-11. Video Timing in SPI Modes 1 and 2
Beginning of Fields 1, 3, 5, 7
HRESET
(1)
VRESET
FIELD
ACTIVE
2–6 scan lines
VDELAY/2 scan lines
Beginning of Fields 2, 4, 6, 8
HRESET
VRESET
FIELD
ACTIVE
2–6 scan lines
VDELAY/2 scan lines
Notes: (1). HRESET precedes VRESET by two clock cycles at the beginning of fields 1, 3, 5, and 7 to facilitate external field
generation.
2. ACTIVE pin may be programmed to be composite ACTIVE or horizontal ACTIVE.
3. ACTIVE, HRESET, VRESET and FIELD are shown with their default polarity. The polarity is programmable via the
VPOLE register.
4. FIELD transitions with the end of horizontal active video, defined by HDELAY and HACTIVE.
60
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.2 Output Interface
VideoStream II Decoders
Figure 2-12. Horizontal Timing Signals in the SPI Modes
64 Clock Cycles at FCLKx1
HRESET
HDELAY Clock Cycles at FDesired
ACTIVE
HACTIVE Clock Cycles
at FDesired
Table 2-3. Data Output Ranges
RANGE = 0
RANGE = 1
Y
16 —> 235
0 —> 255
Cr
2 —> 253
2 —> 253
Cb
2 —> 253
2 —> 253
2.2.5 CCIR601 Compliance
When the RANGE bit is set to zero, the output levels are fully compliant with the
CCIR601 recommendation. CCIR601 specifies that nominal video will have Y
values ranging from 16 to 235, and that Cr and Cb values will range from 16 to
240. Excursions outside this range are allowed to handle non standard video. The
only mandatory requirement is that 0 and 255 be reserved for timing information.
D829BDSA
61
Bt829B/827B
2.0 Electrical Interfaces
2.3 I2C Interface
VideoStream II Decoders
2.3 I2C Interface
The Inter-Integrated Circuit bus is a two-wire serial interface. Serial Clock (SCL)
and Data Lines (SDA) are used to transfer data between the bus master and the
slave device. The Bt829B can transfer data at a maximum rate of 100 kbps. The
Bt829B operates as a slave device.
2.3.1 Starting and Stopping
The relationship between SCL and SDA is decoded to provide both a start and
stop condition on the bus. To initiate a transfer on the I2C bus, the master must
transmit a start pulse to the slave device. This is accomplished by taking the SDA
line low while the SCL line is held high. The master should only generate a start
pulse at the beginning of the cycle, or after the transfer of a data byte to or from
the slave. To terminate a transfer, the master must take the SDA line high while
the SCL line is held high. The master may issue a stop pulse at any time during an
I2C cycle. Since the I2C bus will interpret any transition on the SDA line during
the high phase of the SCL line as a start or stop pulse, care must be taken to
ensure that data is stable during the high phase of the clock. Figure 2-13 illustrates the relationship between SCL and SDA.
Figure 2-13. The Relationship between SCL and SDA
SCL
SDA
Start
62
D829BDSA
Stop
Bt829B/827B
2.0 Electrical Interfaces
2.3 I2C Interface
VideoStream II Decoders
2.3.2 Addressing the Bt829B
An I2C slave address consists of two parts: a 7-bit base address and a single bit
R/W command. The R/W bit is appended to the base address to form the transmitted I2C address, as shown in Figure 2-14 and Table 2-4.
Figure 2-14. I2C Slave Address Configuration
A6
A5
A4
A3
A2
A1
A0 R/W
Base Address
R/W Bit
Table 2-4. Bt829B Address Matrix
I2CCS Pin
Bt829B Base
R/W Bit
Action
0
1000100
0
Write
1000100
1
Read
1000101
0
Write
1000101
1
Read
1
2.3.3 Reading and Writing
After transmitting a start pulse to initiate a cycle, the master must address the
Bt829B. To do this, the master must transmit one of the four valid Bt829B
addresses, with the Most Significant Bit (MSB) transmitted first. After transmitting the address, the master must release the SDA line during the low phase of the
SCL and wait for an acknowledgment. If the transmitted address matches the
selected Bt829B address, the Bt829B will respond by driving the SDA line low,
generating an acknowledge to the master. The master samples the SDA line at the
rising edge of the SCL line, and proceeds with the cycle. If no device responds,
including the Bt829B, the master transmits a stop pulse and ends the cycle.
If the slave address R/W bit was low (indicating a write) the master will transmit an 8-bit byte to the Bt829B, with the MSB transmitted first. The Bt829B
acknowledges the transfer and loads the data into its internal address register. The
master then issues a stop command, a start command, or transfers another 8-bit
byte, MSB first. The internal address register points to the 8-bit byte, which is
then loaded into the register. The Bt829B acknowledges the transfer and increments the address register in preparation for the next transfer. As before, the master may issue a stop command, a start command, or transfer another 8 bits which
is loaded into the next register location.
If the slave address R/W bit was high (indicating a read), the Bt829B transfers
the contents of the register. Its internal address register points to the contents,
MSB first. The master acknowledges receipt of the data and pulls the SDA line
low. As with the write cycle, the address register is auto-incremented in preparation for the next read.
D829BDSA
63
Bt829B/827B
2.0 Electrical Interfaces
2.3 I2C Interface
VideoStream II Decoders
To stop a read transfer, the host must not acknowledge the last read cycle. The
Bt829B then releases the data bus in preparation for a stop command. If an
acknowledgment is received, the Bt829B proceeds to transfer the next register.
When the master generates a read from the Bt829B, the Bt829B starts its
transfer from whatever location is currently loaded into the address register. Since
the address register might not contain the address of the desired register, the master generally executes a write cycle, setting the address register to the desired
location. After receiving an acknowledgment for the transfer of the data into the
address register, the master initiates a read of the Bt829B by starting a new I2C
cycle with an appropriate read address. The Bt829B then transfers the contents of
the desired register.
For example, to read register 0x0A, Brightness Control, the master starts a
write cycle with an I2C address of 0x88 or 0x8A. After receiving an acknowledgment from the Bt829B, the master transmits the desired address, 0x0A. After
receiving an acknowledgment, the master then starts a read cycle with an I2C
slave address of 0x89 or 0x8B. The Bt829B acknowledges and transfers the contents of register 0x0A. There is no need to issue a stop command after the write
cycle. The Bt829B detects the repeated start command and starts a new I2C cycle.
This process is illustrated in Table 2-5 and Figure 2-15.
For detailed information on the I2C bus, refer to “The I2C-Bus Reference
Guide,” reprinted by Rockwell.
Table 2-5. Example I2C Data Transactions
Master
Data
Flow
Bt829B
Comment
Write to Bt829B
I2C Start
——
>
Master sends Bt829B chip address, i.e., 0x88 or 0x8A.
ACK
Subaddress
——
>
Master sends subaddress to Bt829B.
ACK
Data(0)
——
>
——
>
——
>
——
>
Data(n)
——
>
64
Bt829B generates ACK on successful receipt of first data byte.
.
.
.
Master sends nth data byte to Bt829B.
ACK(n)
I2C Stop
Bt829B generates ACK on successful receipt of subaddress.
Master sends first data byte to Bt829B.
ACK(0)
.
.
.
Bt829B generates ACK on successful receipt of chip address.
Bt829B generates ACK on successful receipt of nth data byte.
Master generates STOP to end transfer.
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.3 I2C Interface
VideoStream II Decoders
Table 2-5. Example I2C Data Transactions
Master
Data
Flow
Bt829B
Comment
Read from Bt829B
I2C Start
——
>
Master sends Bt829B chip address, i.e., 0x89 or 0x8B.
ACK
<—
—
Data(0)
ACK(0)
.
.
.
Bt829B generates ACK on successful receipt of chip address.
Bt829B sends first data byte to Master.
Master generates ACK on successful receipt of first data byte.
<—
—
<—
—
<—
—
.
.
.
<—
—
Data(n-1)
ACK(n-1)
Bt829B sends (n-1)th data byte to Master.
Master generates ACK on successful receipt of (n-1)th data byte.
<—
—
Data(n)
Bt829B sends nth data byte to Master.
NO ACK
Master does not acknowledge nth data byte.
I2C Stop
Master generates STOP to end transfer.
= I2C start condition and Bt829B chip address (including the
R/W bit).
Subaddress = The 8-bit subaddress of the Bt829B register, MSB first.
Data(n)
= The data to be transferred to/from the addressed register.
I2C Stop
= I2C stop condition.
where: I2C Start
D829BDSA
65
Bt829B/827B
2.0 Electrical Interfaces
2.3 I2C Interface
VideoStream II Decoders
Figure 2-15. I2C Protocol Diagram
S
SR
P
A
NA
Data Write
S
CHIP ADDR
0x88 or 0x8A
A
SUB-ADDR
8 Bits
A
DATA
A
DATA
A
DATA
DATA
A
DATA
A
A
P
= START
= REPEATED START
= STOP
= ACKNOWLEDGE
= NON ACKNOWLEDGE
Data Read
S
CHIP ADDR
0x89 or 0x8B
A
A
DATA
NA P
From Master to Bt829B
From Bt829B to Master
Write Followed by Read
S
CHIP ADDR
0x88 or 0x8A
A
SUB-ADDR
A sr CHIP ADDR
Repeated
Start
A
DATA A
Register
Pointed to
by Subaddress
data
A
A
DATA
NA P
2.3.4 Software Reset
The contents of the control registers may be reset to their default values by issuing a software reset. A software reset can be accomplished by writing any value to
subaddress 0x1F. A read of this location returns an undefined value.
66
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.4 JTAG Interface
VideoStream II Decoders
2.4 JTAG Interface
2.4.1 Need for Functional Verification
As the complexity of imaging chips increases, the need to easily access individual
chips for functional verification is vital. The Bt829B incorporates special circuitry
which makes it accessible in full compliance with Joint Test Action Group
(JTAG) standards. Conforming to IEEE P1149.1 “Standard Test Access Port and
Boundary Scan Architecture,” the Bt829B contains dedicated pins used only for
testability purposes.
2.4.2 JTAG Approach to Testability
JTAG’s approach to testability uses boundary scan cells that are placed at each
digital pin and digital interface. (A digital interface is defined as the boundary
between an analog block and a digital block within the Bt829B). All cells are
interconnected into a boundary scan register that applies or captures test data to
verify functionality of the integrated circuit. JTAG is particularly useful for board
testers using functional testing methods.
JTAG consists of five dedicated pins comprising the Test Access Port (TAP).
These pins are Test Mode Select (TMS), Test Clock (TCK), Test Data Input
(TDI), Test Data Out (TDO), and Test Reset (TRST). The TRST pin resets the
JTAG controller when pulled low at any time. Verification of the integrated circuit
and its connection to other modules on the printed circuit board is achieved
through these five TAP pins. With boundary scan cells at each digital interface
and pin, the Bt829B is capable of applying and capturing the respective logic levels. Because all of the digital pins are interconnected as a long shift register, the
TAP logic has access to the necessary pins. This ensures verification of pin functionality. The TAP controller can shift in any number of test vectors through the
TDI input and can apply them to the internal circuitry. The output result is
scanned on the TDO pin and is externally checked. While isolating the Bt829B
from other components on the board, the user has easy access to all Bt829B digital pins and digital interfaces through the TAP. The user can then perform complete functionality tests without using expensive bed-of-nails testers.
D829BDSA
67
Bt829B/827B
2.0 Electrical Interfaces
2.4 JTAG Interface
VideoStream II Decoders
2.4.3 Optional Device ID Register
The Bt829B has the optional device identification register defined by the JTAG
specification. This register contains information concerning the revision, actual
part number, and manufacturer’s identification code that is specific to Rockwell.
The TAP controller can access the register via an optional JTAG instruction, as
shown in Table 2-6.
Table 2-6. Device Identification Register
Version
Part Number
Manufacturer ID
X X X X 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1
0
0829, 0x033D
0x0D6
4 Bits
16 Bits
11 Bits
Note:
The part number remains the same for both parts: Bt829B and Bt827B.
2.4.4 Verification with the Tap Controller
The TAP controller enables you to perform a variety of verification procedures.
Using a set of four instructions, the Bt829B can verify board connectivity at all
digital interfaces and pins. The instructions can be accessed using a state machine
that is standard to all JTAG controllers. They are Sample/Preload, Extest, ID
Code, and Bypass (see Figure 2-16). Refer to the IEEE P1149.1 specification for
details concerning the instruction register and JTAG state machine.
Rockwell has created a BSDL with the AT&T BSD Editor. If you plan to
implement JTAG testing, you may obtain a disk with an ASCII version of the
complete BSDL file by contacting your local Rockwell sales office.
Figure 2-16. Instruction Register
TDI
68
TDO
D829BDSA
EXTEST
0
0
Sample/Preload
0
0
ID Code
0
1
Bypass
1
1
Bt829B/827B
2.0 Electrical Interfaces
2.4 JTAG Interface
VideoStream II Decoders
2.4.5 Example BSDL Listing
attribute BOUNDARY_REGISTER of Bt829B : entity is
“
0 (BC_1, *, control, 1),” &
“
1 (BC_1, *, internal, 1),” &
“
2 (BC_1, *, control, 1),” &
“
3 (BC_1, *, internal, X),” &
“
4 (BC_1, *, internal, X),” &
“
5 (BC_1, *, internal, X),” &
“
6 (BC_1, *, internal, X),” &
“
7 (BC_1, *, internal, X),” &
“
8 (BC_1, *, internal, X),” &
“
9 (BC_1, *, internal, X),” &
“
10 (BC_1, *, internal, X),” &
“
11 (BC_1, *, internal, X),” &
“
12 (BC_1, *, internal, X),” &
“
13 (BC_1, *, internal, 0),” &
“
14 (BC_1, *, internal, 0),” &
“
15 (BC_1, *, internal, 0),” &
“
16 (BC_1, *, internal, 0),” &
“
17 (BC_1, *, internal, 0),” &
“
18 (BC_1, *, internal, 0),” &
“
19 (BC_1, *, internal, 0),” &
“
20 (BC_1, *, internal, 0),” &
“
21 (BC_1, *, internal, 0),” &
“
22 (BC_1, *, internal, 0),” &
“
23 (BC_1, *, internal, 0),” &
“
24 (BC_1, *, internal, 0),” &
“
25 (BC_1, *, internal, 0),” &
“
26 (BC_1, *, internal, 0),” &
“
27 (BC_1, *, internal, 0),” &
“
28 (BC_1, *, control, 0),” &
“
29 (BC_1, FIELD, output3, X, 28, 0, Z),” &
“
30 (BC_1, NVRESET, output3, X, 28, 0, Z),” &
“
31 (BC_1, XTFMT, input, X),” &
“
32 (BC_1, NHRESET, output3, X, 28, 0, Z),” &
“
33 (BC_1, ACTIVE, output3, X, 28, 0, Z),” &
“
34 (BC_1, DVALID, output3, X, 28, 0, Z),” &
“
35 (BC_1, VACTIVE, output3, X, 28, 0, Z),” &
“
36 (BC_1, TST, output2, 0, 36, 0, Weak1),” &
“
37 (BC_1, *, internal, X),” &
D829BDSA
69
Bt829B/827B
2.0 Electrical Interfaces
2.4 JTAG Interface
70
VideoStream II Decoders
“
38 (BC_1, CBFLAG, output3, X, 28, 0, Z),” &
“
39 (BC_3, NVSEN, input, X),” &
“
40 (BC_1, PWRDN, input, X),” &
“
41 (BC_1, QCLK, output3, X, 28, 0, Z),” &
“
42 (BC_1, CLKX1, output3, X, 28, 0, Z),” &
“
43 (BC_1, NOE, input, 1),” &
“
44 (BC_1, CLKX2, output3, X, 28, 0, Z),” &
“
45 (BC_1, VDB(13), output3, X, 28, 0, Z),” &
“
46 (BC_1, VDB(14), output3, X, 28, 0, Z),” &
“
47 (BC_1, VDB(15), output3, X, 28, 0, Z),” &
“
48 (BC_1, VDB(8), output3, X, 28, 0, Z),” &
“
49 (BC_1, VDB(9), output3, X, 28, 0, Z),” &
“
50 (BC_1, VDB(10), output3, X, 28, 0, Z),” &
“
51 (BC_1, VDB(11), output3, X, 28, 0, Z),” &
“
52 (BC_1, VDB(12), output3, X, 28, 0, Z),” &
“
53 (BC_1, *, internal, X),” &
“
54 (BC_1, XT0I, input, X),” &
“
55 (BC_1, I2CCS, input, X),” &
“
56 (BC_1, NRST, input, X),” &
“
57 (BC_1, *, internal, X),” &
“
58 (BC_1, XT1I, input, X),” &
“
59 (BC_1, SDA, output2, 0, 59, 1, Pull1),” &
“
60 (BC_1, SDA, input, X),” &
“
61 (BC_1, SCL, input, X),” &
“
62 (BC_1, VDA(3), output3, X, 0, 1, Z),” &
“
63 (BC_1, VDA(3), input, X),” &
“
64 (BC_1, VDA(4), output3, X, 2, 1, Z),” &
“
65 (BC_1, VDA(4), input, X),” &
“
66 (BC_1, VDA(5), output3, X, 2, 1, Z),” &
“
67 (BC_1, VDA(5), input, X),” &
“
68 (BC_1, VDA(6), output3, X, 2, 1, Z),” &
“
69 (BC_1, VDA(6), input, X),” &
“
70 (BC_1, VDA(7), output3, X, 2, 1, Z),” &
“
71 (BC_1, VDA(7), input, X),” &
“
72 (BC_1, VDA(0), output3, X, 0, 1, Z),” &
“
73 (BC_1, VDA(0), input, X),” &
“
74 (BC_1, VDA(1), output3, X, 0, 1, Z),” &
“
75 (BC_1, VDA(1), input, X),” &
“
76 (BC_1, VDA(2), output3, X, 0, 1, Z),” &
“
77 (BC_1, VDA(2), input, X),” &
D829BDSA
Bt829B/827B
2.0 Electrical Interfaces
2.4 JTAG Interface
VideoStream II Decoders
“
78 (BC_1, TWREN, input, X),” &
“
79 (BC_0, *, internal, 0),” &
“
80 (BC_0, *, internal, 0)”;
end Bt829B;
D829BDSA
71
Bt829B/827B
2.0 Electrical Interfaces
2.4 JTAG Interface
72
VideoStream II Decoders
D829BDSA
3.0 PC Board Layout Considerations
The layout should be optimized for lowest noise on the Bt829B power and ground
lines. Optimization is achieved by shielding the digital inputs and outputs and by
providing good decoupling. The lead length between groups of power and ground
pins should be minimized to reduce inductive ringing.
3.1 Ground Planes
The ground plane area should encompass all Bt829B ground pins, voltage reference circuitry, power supply bypass circuitry for the Bt829B, analog input traces,
any input amplifiers, and all the digital signal traces leading to the Bt829B.
The Bt829B has digital grounds (GND) and analog grounds (AGND and
VNEG). The layout for the ground plane should be set up so the two planes are at
the same electrical potential, but they should be isolated from each other in the
areas surrounding the chip. The return path for the current should be through the
digital plane. See Figure 3-1 for an example of ground plane layout.
Figure 3-1. Example of Ground Plane Layout
Ground Return
(i.e., PCI Bus Connection)
Circuit Board Edge
1
Bt829B
50
Digital
Ground
D829BDSA
Analog
Ground
73
Bt829B/827B
3.0 PC Board Layout Considerations
3.1 Ground Planes
VideoStream II Decoders
3.1.1 Power Planes
The power plane area should encompass all Bt829B power pins, voltage reference
circuitry, power supply bypass circuitry for the Bt829B, analog input traces, any
input amplifiers, and all the digital signal traces leading to the Bt829B.
The Bt829B has digital power (VDD) and analog power (VAA and VPOS).
The layout for the power plane should be set up so the two planes are at the same
electrical potential, but they should be isolated from each other in the areas surrounding the chip. The return path for the current should be through the digital
plane. This is the same layout as the ground plane (Figure 3-1). When using a regulator, circuitry must be included to ensure proper power sequencing. Figure 3-2
illustrates this circuitry layout.
Figure 3-2. Optional Regulator Circuitry
System Power
(+5 V)
VAA, VDD
(+5 V)
System Power
(+12 V)
Out
In
GND
Ground
Suggested Part Numbers:
Regulator
Texas Instruments
74
D829BDSA
Diodes must handle
the current requirements
of the Bt829B and the
peripheral circuitry.
µA78 MO5M
Bt829B/827B
3.0 PC Board Layout Considerations
3.1 Ground Planes
VideoStream II Decoders
3.1.2 Supply Decoupling
The bypass capacitors should be installed with the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. These capacitors
should be placed as close as possible to the device.
Each group of VAA and VDD pins should have a 0.1 µF ceramic bypass
capacitor to ground, located as close as possible to the device.
Additionally, 10 µF capacitors should be connected between the analog power
and ground planes, as well as between the digital power and ground planes. These
capacitors are at the same electrical potential, but provide additional decoupling
by being physically close to the Bt829B power and ground planes. For additional
information about power supply decoupling, see Figures 3-3 and 3-4.
Figure 3-3. Typical Power and Ground Connection Diagram and Parts List for 5 V I/O Mode
+5 V (VCC)
VDD, VDDO
+
C4
VAA, VPOS
+
C2
C3
ANALOG
AREA
+
AGND, VNEG
+
C1
Bt829B
Ground
GND
Location
Description
Vendor Part Number
C1, C2(1)
0.1 µF ceramic capacitor
Erie RPE112Z5U104M50V
C3, C4(2)
10 µF tantalum capacitor
Mallory CSR13G106KM
Notes: (1). A 0.1 µF capacitor should be connected between each group of power pins and ground. They should be connected
as close to the device as possible (ceramic chip capacitors are preferred).
(2). The 10 µF capacitors should be connected between the analog supply and the analog ground, as well as the digital
supply and the digital ground. These should be connected as close to the Bt829B as possible.
3. Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect the
performance of the Bt829B.
D829BDSA
75
Bt829B/827B
3.0 PC Board Layout Considerations
3.1 Ground Planes
VideoStream II Decoders
Figure 3-4. Typical Power and Ground Connection Diagram and Parts List for 3.3 V I/O Mode
+3.3 V
VDDO
+5 V (VCC)
VDD
+
C4
VAA, VPOS
+ C3
C2
ANALOG
AREA
+
+
AGND, VNEG
C1
Bt829B
C5
Ground
GND
Location
Description
Vendor Part Number
C1, C2(1), C5
0.1 µF ceramic capacitor
Erie RPE112Z5U104M50V
C3, C4(2)
10 µF tantalum capacitor
Mallory CSR13G106KM
Notes: (1). A 0.1 µF capacitor should be connected between each group of power pins and ground. They should be connected
as close to the device as possible (ceramic chip capacitors are preferred).
(2). The 10 µF capacitors should be connected between the analog supply and the analog ground, as well as the digital
supply and the digital ground. These should be connected as close to the Bt829B as possible.
3. Vendor numbers are listed only as a guide. Substitution of devices with similar characteristics will not affect the
performance of the Bt829B.
76
D829BDSA
Bt829B/827B
3.0 PC Board Layout Considerations
3.1 Ground Planes
VideoStream II Decoders
3.1.3 Digital Signal Interconnect
The digital signals of the Bt829B should be isolated as much as possible from the
analog signals and other analog circuitry. Also, the digital signals should not overlay the analog power plane.
Any termination resistors for the digital signals should be connected to the
regular PCB power and ground planes.
3.1.4 Analog Signal Interconnect
To minimize crosstalk, long lengths of closely spaced parallel video signals
should be avoided. Ideally, a ground line should exist between the video signal
traces driving the YIN and CIN inputs.
To minimize noise coupling, high-speed TTL signals should not be routed
close to the analog signals.
3.1.5 Latch-up Avoidance
Latch-up is a failure mechanism inherent to any CMOS device. It is triggered by
static or impulse voltages on any signal input pin when the voltage on the power
pins exceeds 0.5 V, or when it falls below the GND pins by more than 0.5 V.
Latch-up can also occur if the voltage on any power pin exceeds the voltage on
any other power pin by more than 0.5 V.
In some cases, devices with mixed signal interfaces, such as the Bt829B, can
appear more sensitive to latch-up. Mixed signal devices tend to interact with
peripheral devices, such as video monitors or cameras that are referenced to different ground potentials. Voltages applied to the device prior to the time that its
power system is stable can create conditions that are amenable to the onset of
latch-up.
To maintain a robust design with the Bt829B, you should take the following
precautions:
•
•
•
•
Apply power to the device before or at the same time that power is applied
to the interface circuitry.
Do not apply voltages below GND–0.5 V or higher than VAA+0.5 V to any
pin on the device. Do not use negative supply op-amps or any other negative voltage interface circuitry. All logic inputs should be held low until
power to the device has settled to the specified tolerance.
Connect all VDD, VAA, and VPOS pins together through a low impedance
plane.
Connect all GND, AGND, and VNEG pins together through a low
impedance plane.
D829BDSA
77
Bt829B/827B
3.0 PC Board Layout Considerations
3.1 Ground Planes
78
VideoStream II Decoders
D829BDSA
4.0 Control Register Definitions
This section describes the function of the various control registers in detail. Table 4-1 summarizes the register
functions.
Mnemonic
Register Address
640 x 480
Square Pixel NTSC
(Default)
768 x 576
Square Pixel PAL/SECAM
720 x 480
CCIR NTSC
720 x 576
CCIR PAL/SECAM
320 x 240 2:1 NTSC
(Square Pixel, CIF)
320 x 288 2:1 PAL/SECAM
(Square Pixel, CIF)
Table 4-1. Register Map (1 of 2)
Device Status
STATUS
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Input Format
IFORM
0x01
0x58
0x78
0x58
0x78
0x58
0x78
Temporal Decimation
TDEC
0x02
0x00
0x00
0x00
0x00
0x00
0x00
MSB Cropping
CROP
0x03
0x12
0x23
0x12
0x23
0x11
0x21
Vertical Delay, Lower Byte
VDELAY_LO
0x04
0x16
0x16
0x16
0x16
0x16
0x16
Vertical Active, Lower Byte
VACTIVE_LO
0x05
0xE0
0x40
0xE0
0x40
0xE0
0x40
Horizontal Delay,
Lower Byte
HDELAY_LO
0x06
0x78
0x9A
0x80
0x90
0x40
0x48
Horizontal Active,
Lower Byte
HACTIVE_LO
0x07
0x80
0x00
0xD0
0xD0
0x40
0x80
Horizontal Scaling,
Upper Byte
HSCALE_HI
0x08
0x02
0x03
0x00
0x05
0x11
0x1A
Horizontal Scaling,
Lower Byte
HSCALE_LO
0x09
0xAC
0x3C
0xF8
0x04
0xF0
0x09
Brightness Control
BRIGHT
0x0A
0x00
0x00
0x00
0x00
0x00
0x00
Miscellaneous Control
CONTROL
0x0B
0x20
0x20(1)
0x20
0x20(1)
0x20
0x20
Luma Gain,
Lower Byte (Contrast)
CONTRAST_LO
0x0C
0xD8
0xD8
0xD8
0xD8
0xD8
0xD8
Chroma (U) Gain,
Lower Byte (Saturation)
SAT_U_LO
0x0D
0xFE
0xFE
0xFE
0xFE
0xFE
0xFE
Chroma (V) Gain,
Upper Byte (Saturation)
SAT_V_LO
0x0E
0xB4
0xB4
0xB4
0xB4
0xB4
0xB4
Register Name
D829BDSA
79
Bt829B
4.0 Control Register Definitions
VideoStream II Decoders
Mnemonic
Register Address
640 x 480
Square Pixel NTSC
(Default)
768 x 576
Square Pixel PAL/SECAM
720 x 480
CCIR NTSC
720 x 576
CCIR PAL/SECAM
320 x 240 2:1 NTSC
(Square Pixel, CIF)
320 x 288 2:1 PAL/SECAM
(Square Pixel, CIF)
Table 4-1. Register Map (2 of 2)
HUE
0x0F
0x00
0x00
0x00
0x00
0x00
0x00
SC Loop Control
SCLOOP
0x10
0x00
0x00(1)
0x00
0x00(1)
0x00
0x00
White Crush Up Count
WC_UP
0x11
0xCF
0xCF
0xCF
0xCF
0xCF
0xCF
Output Format
OFORM
0x12
0x06
0x06
0x06
0x06
0x06
0x06
Vertical Scaling,
Upper Byte
VSCALE_HI
0x13
0x60
0x60
0x60
0x60
0x40(1)
0x40(1)
Vertical Scaling,
Lower Byte
VSCALE_LO
0x14
0x00
0x00
0x00
0x00
0x00
0x00
TEST
0x15
0x01
0x01
0x01
0x01
0x01
0x01
Video Timing Polarity
Register
VPOLE
0x16
0x00
0x00
0x00
0x00
0x00
0x00
ID Code
IDCODE
0x17
0x70
0x70
0x70
0x70
0x70
0x70
AGC Delay
ADELAY
0x18
0x68
0x7F
0x68
0x7F
0x68
0x7F
Burst Gate Delay
BDELAY
0x19
0x5D
0x72(1)
0x5D
0x72(1)
0x5D
0x72
ADC Interface
ADC
0x1A
0x82
0x82
0x82
0x82
0x82
0x82
Video Timing Control
VTC
0x1B
0x00
0x00
0x00
0x00
0x00
0x00
Extended Data Services/Closed Caption
Status
CC_STATUS
0x1C
0x00
0x00
0x00
0x00
0x00
0x00
Extended Data Services/Closed Caption Data
CC_DATA
0x1D
0x00
0x00
0x00
0x00
0x00
0x00
White Crush Down Count
WC_DN
0x1E
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
Software Reset
SRESET
0x1F
—
—
—
—
—
—
P_IO
0x3F
—
—
—
—
—
—
Register Name
Hue Control
Test Control
Programmable I/O
SECAM Video Register Differences
Miscellaneous Control
CONTROL
—
—
0x00
—
0x00
—
—
SC Loop Control
SCLOOP
—
—
0x10
—
0x10
—
—
Burst Gate Delay
BDELAY
—
—
0xA0
—
0xA0
—
—
Notes: (1). SECAM Video Register differences to PAL video.
(2). When using one field, no additional vertical scaling is necessary for CIF resolutions. The INT bit in register
0xB(VSCALE_HI) should be set to a logical 0 when scaling from only one field.
80
D829BDSA
Bt829B
4.0 Control Register Definitions
0x00—Device Status Register (STATUS)
VideoStream II Decoders
0x00—Device Status Register (STATUS)
\The MPU can read or write to this register at any time. Upon reset, it is initialized to 0x00. COF is the LSB. By
writing to the register, the COF and LOF status bits hold their values until reset to their default values. The other
six bits do not hold their values, but continually output the status. An asterisk indicates the default option.
7
6
5
4
3
2
1
0
PRES
HLOC
FIELD
NUML
CSEL
CCVALID
LOF
COF
0
0
0
0
0
0
0
0
PRES
Video Present Status—Video is determined to be not present when an input sync is not
detected in 31 consecutive line periods.
0*
1
HLOC
=
=
Odd field
Even field
=
=
525-line format (NTSC/PAL-M)
625-line format (PAL/SECAM)
Crystal Select—This bit identifies which crystal port is selected. When automatic format
detection is enabled, this bit will be the same as NUML.
0*
1
CCVALID
Device not in H-lock
Device in H-lock
Number of Lines—This bit identifies the number of lines found in the video stream. This bit is
used to determine the type of video input to the Bt829A. Thirty two consecutive fields with the
same number of lines is required before this status bit will change.
0*
1
CSEL
=
=
Field Status—This bit reflects whether an odd or even field is being decoded. The FIELD bit is
determined by the relationship between HRESET and VRESET.
0*
1
NUML
Video not present
Video present
Device in H-lock—If HSYNC is found within ±1 clock cycle of the expected position of
HSYNC for 32 consecutive lines, this bit is set to a logical 1. Once set, if HSYNC is not found
within ±1 clock cycle of the expected position of HSYNC for 32 consecutive lines, this bit is
set to a logical 0. MPU writes to this bit are ignored. This bit indicates the stability of the
incoming video. Although it is an indicator of horizontal locking, some video sources characteristically vary from line-to-line by more than one clock cycle. This causes the bit to never be
set. Consumer VCRs are examples of sources that tend to never set this bit.
0*
1
FIELD
=
=
=
=
XTAL0 input selected
XTAL1 input selected
Valid Closed Caption Data—This bit indicates that valid closed caption or Extended Data Services (EDS) sample pairs have been stored in the closed caption data registers. This bit indicates that the closed caption data FIFO is half full. It is reset after being written to or when a
chip reset occurs.
D829BDSA
81
Bt829B
4.0 Control Register Definitions
0x01—Input Format Register (IFORM)
VideoStream II Decoders
LOF
Luma ADC Overflow—On power-up, this bit is set to 0. If an ADC overflow occurs, the bit is
set to a logical 1. It is reset after being written to, or when a chip reset occurs. When the ADC
is in power-down mode (Y_SLEEP = 1) the state of this bit is not valid and should be ignored.
When the luma A/D is in sleep mode, LOF is set to 1.
COF
Chroma ADC Overflow—On power-up, this bit is set to 0. If an ADC overflow occurs, the bit
is set to a logical 1. It is reset after being written to, or when a chip reset occurs. When the
ADC is in power-down mode (C_SLEEP = 1), the state of this bit is not valid and should be
ignored. When the chroma A/D is in sleep mode, COF is set to 1.
0x01—Input Format Register (IFORM)
The MPU may read or write to this control register at any time. Upon reset, it is initialized to 0x58.
FORMAT(0) is the LSB. An asterisk indicates the default option.
7
6
HACTIVE
0
HACTIVE
5
4
MUXSEL
1
0
1
FORMAT
1
0
0
0
=
=
Reset HACTIVE with HRESET
Extend HACTIVE beyond HRESET
=
=
=
=
Select MUX3 input to MUXOUT
Select MUX2 input to MUXOUT
Select MUX0 input to MUXOUT
Select MUX1 input to MUXOUT
If automatic format detection is required, logical 11 must be loaded. Logical 01 and 10 are
used if software format selection is desired.
=
=
=
=
Reserved
Select XT0 input (only XT0 present)
Select XT1 input (both XTs present)
Auto XT select enabled (both XTs present)
Automatic format detection may be enabled or disabled. The NUML bit is used to determine
the input format when automatic format detection is enabled.
000*
001
010
011
100
101
110
111
82
0
This bit is used for software control of video input selection. The Bt829A can select between
four composite video sources, or three composite and one S-Video source.
00
01
10
11*
FORMAT
1
When using the Bt829A with a packed memory architecture, for example, with field memories, this bit should be programmed with a logical 1. When implementing a VRAM based
architecture, this bit should be programmed with a logical 0.
00
01
10*
11
XTSEL
2
XTSEL
0*
1
MUXSEL
3
=
=
=
=
=
=
=
=
Auto format detect enabled
NTSC (M) input format
NTSC with no pedestal format
PAL (B, D, G, H, I) input format
PAL (M) input format
PAL (N) input format
SECAM input format
PAL (N combination) input format
D829BDSA
Bt829B
4.0 Control Register Definitions
0x02—Temporal Decimation Register (TDEC)
VideoStream II Decoders
0x02—Temporal Decimation Register (TDEC)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x00.
DEC_RAT(0) is the LSB. This register enables temporal decimation by discarding a finite number of fields or
frames from the incoming video. An asterisk indicates the default option.
7
6
DEC_FIELD
FLDALIGN
0
0
DEC_FIELD
5
4
3
2
1
0
0
0
0
DEC_RAT
0
0
0
This bit defines whether decimation occurs according to fields or frames.
0*
1
=
=
Decimate frames
Decimate fields
This bit aligns the start of decimation with an even or odd field.
FLDALIGN
0*
=
1
=
Start decimation on the odd field (an odd field is the first field
dropped).
Start decimation on the even field (an even field is the first field
dropped).
DEC_RAT is the number of fields or frames dropped out of 60 NTSC or 50 PAL/SECAM
fields or frames. 0x00 value disables decimation (all video frames and fields are output).
DEC_RAT
NOTE:
Use caution when changing the programming in the TDEC register. 0x00 must be
loaded before the decimation value. This ensures that decimation does not start on the
wrong field or frame. The register should not be loaded with DEC_RAT greater than
60 (0x3C) for NTSC, or greater than 50 (0x34) for PAL/SECAM.
xx00 0000–xx11 1111 = Number of fields/frames dropped.
0x03—MSB Cropping Register (CROP)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x12.
HACTIVE_MSB(0) is the LSB. See the VACTIVE, VDELAY, HACTIVE, and HDELAY registers for descriptions on the operation of this register.
7
6
5
VDELAY_MSB
0
4
3
VACTIVE_MSB
0
0
2
1
HDELAY_MSB
1
0
0
HACTIVE_MSB
0
1
VDELAY_MSB
00xx xxxx–11xx xxxx = The most significant two bits of vertical delay register.
VACTIVE_MSB
xx00 xxxx–xx11 xxxx = The most significant two bits of vertical active register.
HDELAY_MSB
xxxx 00xx–xxxx 11xx = The most significant two bits of horizontal delay register.
HACTIVE_MSB
xxxx xx00–xxxx xx11 = The most significant two bits of horizontal active register.
D829BDSA
0
83
Bt829B
4.0 Control Register Definitions
0x04—Vertical Delay Register, Lower Byte (VDELAY_LO)
VideoStream II Decoders
0x04—Vertical Delay Register, Lower Byte (VDELAY_LO)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x16. The LSB
(LSB) is VDELAY_LO(0). This 8-bit register is the lower byte of the 10-bit VDELAY register. The CROP register contains the two MSBs of VDELAY. VDELAY defines the number of half lines between the trailing edge
of VRESET and the start of active video.
7
6
5
4
3
2
1
0
0
1
1
0
VDELAY_LO
0
VDELAY_LO
0
0
1
0x01–0xFF = The LSByte of the vertical delay register.
0x05—Vertical Active Register, Lower Byte (VACTIVE_LO)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0xE0. The LSB is
VACTIVE_LO(0). This 8-bit register is the lower byte of the 10-bit VACTIVE register. The CROP register contains the two MSBs of VACTIVE. VACTIVE defines the number of lines used in the vertical scaling process.
The actual number of lines output by the Bt829A is SCALING_RATIO * VACTIVE.
7
6
5
4
3
2
1
0
0
0
0
0
VACTIVE_LO
1
VACTIVE_LO
1
1
0
0x00–0xFF = The LSByte of the vertical active register.
0x06—Horizontal Delay Register, Lower Byte (HDELAY_LO)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x78.
HDELAY_LO(0) is the LSB. This 8-bit register is the lower byte of the 10-bit HDELAY register. The two
MSBs of HDELAY are contained in the CROP register. HDELAY defines the number of scaled pixels between
the falling edge of HRESET and the start of active video.
7
6
5
4
3
2
1
0
1
0
0
0
HDELAY_LO
0
HDELAY_LO
1
1
1
0x01–0xFF = the LSByte of the horizontal delay register. HACTIVE pixels are output by the
chip starting at the fall of HRESET.
Caution: HDELAY must be programmed with an even number.
84
D829BDSA
Bt829B
4.0 Control Register Definitions
0x07—Horizontal Active Register, Lower Byte (HACTIVE_LO)
VideoStream II Decoders
0x07—Horizontal Active Register, Lower Byte (HACTIVE_LO)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x80.
HACTIVE_LO(0) is the LSB. HACTIVE defines the number of horizontal active pixels-per-line output by the
Bt829A.
7
6
5
4
3
2
1
0
0
0
0
0
HACTIVE_LO
1
HACTIVE_LO
0
0
0
0x00–0xFF = The LSByte of the horizontal active register. This 8-bit register is the lower byte
of the 10-bit HACTIVE register. The CROP registers contains the two MSBs of HACTIVE.
0x08—Horizontal Scaling Register, Upper Byte (HSCALE_HI)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x02. This
8-bit register is the upper byte of the 16-bit HSCALE register.
7
6
5
4
3
2
1
0
0
0
1
0
HSCALE_HI
0
HSCALE_HI
0
0
0
0x00–0xFF = The most significant byte of the horizontal scaling ratio.
0x09—Horizontal Scaling Register, Lower Byte (HSCALE_LO)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0xAC.
This 8-bit register is the lower byte of the 16-bit HSCALE register.
7
6
5
4
3
2
1
0
1
1
0
0
HSCALE_LO
1
HSCALE_LO
0
1
0
0x00–0xFF = The LSByte of the horizontal scaling ratio.
D829BDSA
85
Bt829B
4.0 Control Register Definitions
0x0A—Brightness Control Register (BRIGHT)
VideoStream II Decoders
0x0A—Brightness Control Register (BRIGHT)
The brightness control involves the addition of a two’s complement number to the luma channel. Brightness can
be adjusted in 255 steps, from –128 to +127. The resolution of brightness change is one LSB 0.39% with respect
to the full luma range. An asterisk indicates the default option.
7
6
5
4
3
2
1
0
0
0
0
0
BRIGHT
0
0
0
0
BRIGHT
Brightness Changed By
Hex Value
86
Binary Value
Number of LSBs
Percent of Full Scale
0x80
1000 0000
–128
–100%
0x81
1000 0001
–127
–99.22%
.
.
.
.
.
.
0xFF
1111 1111
–01
–0.78%
0x00*
0000 0000*
00
0%
0x01
0000 0001
+01
+0.78%
.
.
.
.
.
.
0x7E
0111 1110
+126
+99.2%
0x7F
0111 1111
+127
+100%
D829BDSA
Bt829B
4.0 Control Register Definitions
0x0B—Miscellaneous Control Register (CONTROL)
VideoStream II Decoders
0x0B—Miscellaneous Control Register (CONTROL)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x20.
SAT_V_MSB is the LSB. An asterisk indicates the default option.
7
6
5
4
3
2
1
0
LNOTCH
COMP
LDEC
CBSENSE
Reserved
CON_MSB
SAT_U_MSB
SAT_V_MSB
0
0
1
0
0
0
0
0
LNOTCH
This bit is used to include the luma notch filter. For monochrome video, the notch should not
be used. This will output full bandwidth luminance.
0*
1
COMP
=
=
Composite Video
Y/C Component Video
The luma decimation filter is used to reduce the high-frequency component of the luma signal.
This is useful when scaling to CIF resolutions or lower.
0
1*
CBSENSE
Enable the luma notch filter
Disable the luma notch filter
When COMP is set to logical 1, the luma notch is disabled. When COMP is set to logical 0, the
C ADC is disabled.
0*
1
LDEC
=
=
=
=
Enable luma decimation using selectable H filter
Disable luma decimation
This bit controls whether the first pixel of a line is a Cb pixel or a Cr pixel. For example, if
CBSENSE is low and HDELAY is an even number, the first active pixel output is a Cb pixel. If
HDELAY is odd, CBSENSE may be programmed high to produce a Cb pixel as the first active
pixel output.
0*
1
=
=
Normal Cb, Cr order
Invert Cb, Cr order
Reserved
This bit should only be written with a logical 0.
CON_MSB
The most significant bit of the luma gain (contrast) value.
SAT_U_MSB
The most significant bit of the chroma (u) gain value.
SAT_V_MSB
The most significant bit of the chroma (v) gain value.
D829BDSA
87
Bt829B
4.0 Control Register Definitions
0x0C—Luma Gain Register, Lower Byte (CONTRAST_LO)
VideoStream II Decoders
0x0C—Luma Gain Register, Lower Byte (CONTRAST_LO)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0xD8.
CONTRAST_LO(0) is the LSB. The CON_L_MSB bit and the CONTRAST_LO register concatenate to form
the 9-bit CONTRAST register. The value in this register is multiplied by the luminance value to provide contrast
adjustment.
7
6
5
4
3
2
1
0
1
0
0
0
CONTRAST_LO
1
CONTRAST_LO
88
1
0
1
The least significant byte (LSByte) of the luma gain (contrast) value.
Decimal Value
Hex Value
% of Original Signal
511
0x1FF
236.57%
510
0x1FE
236.13%
.
.
.
.
.
.
217
0x0D9
100.46%
216
0x0D8
100.00%
.
.
.
.
.
.
128
0x080
59.26%
.
.
.
.
.
.
1
0x001
0.46%
0
0x000
0.00%
D829BDSA
Bt829B
4.0 Control Register Definitions
0x0D—Chroma (U) Gain Register, Lower Byte (SAT_U_LO)
VideoStream II Decoders
0x0D—Chroma (U) Gain Register, Lower Byte (SAT_U_LO)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0xFE.
SAT_U_LO(0) is the LSB. SAT_U_MSB in the CONTROL register and SAT_U_LO concatenate to give a 9-bit
register (SAT_U). This register is used to add a gain adjustment to the U component of the video signal. By
adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted. For
normal saturation adjustment, the gain in both the color difference paths must be the same (i.e., the ratio
between the value in the U gain register and the value in the V gain register should be kept constant at the
default power-up ratio). When changing the saturation, if the SAT_U_MSB bit is altered, care must be taken to
ensure that the other bits in the CONTROL register are not affected.
7
6
5
4
3
2
1
0
1
1
1
0
SAT_U_LO
1
1
1
1
SAT_U_LO
Decimal Value
Hex Value
% of Original Signal
511
0x1FF
201.18%
510
0x1FE
200.79%
.
.
.
.
.
.
255
0x0FF
100.39%
254
0x0FE
100.00%
.
.
.
.
.
.
128
0x080
50.39%
.
.
.
.
.
.
1
0x001
0.39%
0
0x000
0.00%
D829BDSA
89
Bt829B
4.0 Control Register Definitions
0x0E—Chroma (V) Gain Register, Lower Byte (SAT_V_LO)
VideoStream II Decoders
0x0E—Chroma (V) Gain Register, Lower Byte (SAT_V_LO)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0xB4.
SAT_V_LO(0) is the LSB. SAT_V_MSB in the CONTROL register and SAT_V_LO concatenate to give a 9-bit
register (SAT_V). This register is used to add a gain adjustment to the V-component of the video signal. By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted. For normal saturation adjustment, the gain in both the color difference paths must be the same (i.e., the ratio between the
value in the U gain register and the value in the V gain register should be kept constant at the default power-up
ratio). When changing the saturation, if the SAT_V_MSB bit is altered, care must be taken to ensure that the other
bits in the CONTROL register are not affected.
7
6
5
4
3
2
1
0
0
1
0
0
SAT_V_LO
1
0
1
1
SAT_V_LO
90
Decimal Value
Hex Value
% of Original Signal
511
0x1FF
283.89%
510
0x1FE
283.33%
.
.
.
.
.
.
181
0x0B5
100.56%
180
0x0B4
100.00%
.
.
.
.
.
.
128
0x080
71.11%
.
.
.
.
.
.
1
0x001
0.56%
0
0x000
0.00%
D829BDSA
Bt829B
4.0 Control Register Definitions
0x0F—Hue Control Register (HUE)
VideoStream II Decoders
0x0F—Hue Control Register (HUE)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00.
HUE(0) is the LSB. Hue adjustment involves the addition of a two’s complement number to the demodulating
subcarrier phase. Hue can be adjusted in 256 steps in the range –90˚ to +89.3˚, in increments of 0.7˚. An asterisk
indicates the default option.
7
6
5
4
3
2
1
0
0
0
0
0
HUE
0
0
0
0
HUE
Hex Value
Binary Value
Subcarrier Reference
Changed By
Resulting Hue
Changed By
0x80
1000 0000
–90˚
+90˚
0x81
1000 0001
–89.3˚
+89.3˚
.
.
.
.
.
.
.
.
0xFF
1111 1111
–0.7˚
+0.7˚
0x00*
0000 0000
00˚
00˚
0x01
0000 0001
+0.7˚
–0.7˚
.
.
.
.
.
.
.
.
0x7E
0111 1110
+88.6˚
–88.6˚
0x7F
0111 1111
+89.3˚
–89.3˚
D829BDSA
91
Bt829B
4.0 Control Register Definitions
0x10—SC Loop Control (SCLOOP)
VideoStream II Decoders
0x10—SC Loop Control (SCLOOP)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00.
ACCEL is the LSB. An asterisk indicates the default option.
7
6
5
PEAK
CAGC
CKILL
0
0
0
PEAK
4
2
HFILT
0
1
0
Reserved
0
0
0
0
This bit determines whether the normal luma low pass filters are implemented via the HFILT
bits, or whether the peaking filters are implemented. The LDEC bit in the control register must
be programmed to zero to use these filters.
0*
1
CAGC
3
=
=
Normal luma low pass filtering
Use luma peaking filters
This bit controls the Chroma AGC function. When enabled, Chroma AGC will compensate for
non-standard chroma levels. The compensation is achieved by multiplying the incoming
chroma signal by a value in the range of 0.5 to 2.0.
0*
1
=
=
Chroma AGC Disabled
Chroma AGC Enabled
CKILL
This bit determines whether the low color detector and removal circuitry is enabled.
0* = Low Color Detection and Removal Disabled
1
= Low Color Detection and Removal Enabled
HFILT
These bits control the configuration of the optional 6-tap Horizontal Low-Pass Filter. The Auto
Format Mode determines the appropriate low-pass filter based on the selected horizontal scaling ratio. To use these filters, the LDEC bit in the CONTROL register must be programmed to
zero.
00* =
01
10
=
=
11
=
Auto Format—If Auto Format is selected when horizontally
scaling between full resolution and half resolution, no filtering is
selected. When scaling between one-half and one-third
resolution, the CIF filter is used. When scaling between onethird and one-seventh resolution, the QCIF filter is used; at less
than one-seventh resolution, the ICON filter is used.
CIF
QCIF (When decoding SECAM video, this filter must be
enabled.)
ICON
If the PEAK bit is set to logical 1, the HFILT bits determine which peaking filter is selected.
00
01
10
11
Reserved
92
=
=
=
=
Maximum peaking response
Medium peaking response
Low peaking response
Minimum peaking response
These bits must be set to zero.
D829BDSA
Bt829B
4.0 Control Register Definitions
0x11—White Crush Up Count Register (WC_UP)
VideoStream II Decoders
0x11—White Crush Up Count Register (WC_UP)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0xCF.
UPCNT(0) is the LSB.
7
6
5
4
3
MAJS
1
MAJS
1
0
1
1
1
UPCNT
1
0
0
1
These bits determine the majority comparison point for the White Crush Up function.
00
01
10
11*
UPCNT
2
=
=
=
=
3/4 of maximum luma value
1/2 of maximum luma value
1/4 of maximum luma value
Automatic
The value programmed in these bits accumulates once per field or frame when the majority of
the pixels in the active region of the image are below a selected value. The accumulated value
determines the extent to which the AGC value needs to be raised. This keeps the SYNC level
proportionate with the white level. The UPCNT value is assumed positive:
3F
3E
:
.
00
=
=
:
.
=
63
62
:
.
0
D829BDSA
93
Bt829B
4.0 Control Register Definitions
0x12—Output Format Register (OFORM)
VideoStream II Decoders
0x12—Output Format Register (OFORM)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x06.
OES(0) is the LSB. An asterisk indicates the default option.
7
6
RANGE
0
RANGE
CORE
5
CORE
0
0*
=
1
=
CODE
LEN
0
0
1
0
OES
1
0
Normal operation (Luma range 16–253, chroma range 2–253)
Y=16 is black (pedestal)
Cr, Cb=128 is zero color information
Full-range Output (Luma range 0–255, chroma range 2–253)
Y=0 is black (pedestal)
Cr, Cb=128 is zero color information
=
=
=
=
0x00 no coring
8
16
32
This bit enables the VBI Frame Output Mode. In the VBI Frame Output Mode, every line consists of unfiltered 8*Fsc non-image data. This bit supersedes bit VBIEN in the VTC register.
VBIFMT (also in VTC) works in both VBI frame and line output modes.
=
=
VBI Frame Output Mode disabled
VBI Frame Output Mode enabled
Code Control Disable—This bit determines whether control codes are output with the video
data. SPI Mode 2 requires this bit to be programmed with a logical 1. When control codes are
inserted into the data stream, the external control signals are still available.
=
=
Disable control code insertion
Enable control code insertion
8- or 16-Bit Format—This bit determines the output data format. In 8-bit mode, the data is output on VD[15:8].
0
1*
VD
16-bit
8-bit
94
VBI_FRAME
1
Luma Coring—These bits control the coring value used by the Bt829A. When coring is active
and the total luminance level is below the limit programmed into these bits, the luminance signal is truncated to zero.
0*
1
LEN
2
Luma Output Range—This bit determines the range for the luminance output on the Bt829A.
The range must be limited when using the control codes as video timing.
0*
1
CODE
3
0
00*
01
10
11
VBI_FRAME
4
=
=
8-bit YCrCb 4:2:2 output stream
16-Bit YCrCb 4:2:2 output stream
VD[15]
VD[8] VD[7]
Y[0] Cr/Cb[7]
Y[7]
Y/Cr/Cb[7]
D829BDSA
Y/Cr/Cb[0]
VD[0]
Cr/Cb[0]
Bt829B
4.0 Control Register Definitions
0x13—Vertical Scaling Register, Upper Byte (VSCALE_HI)
VideoStream II Decoders
OES[1] and OES[0] control the output three-states when the OE pin or the OUTEN bit
(VPOLE bit 7) is asserted. The pins are divided into three groups: timing (HRESET, VRESET,
ACTIVE, VACTIVE, CBFLAG, DVALID, and FIELD), clocks (CLKx1, CLKx2 and QCLK),
and data (VD[15:0]). CCVALID cannot output three-states.
OES
00
01
10
11
=
=
=
=
Three-state timing and data only
Three-state data only
Three-state timing, data and clocks
Three-state clocks and data only
0x13—Vertical Scaling Register, Upper Byte (VSCALE_HI)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x60. An
asterisk indicates the default option.
7
6
5
YCOMB
COMB
INT
0
1
1
YCOMB
4
0
0
0
0
0
0
=
=
Vertical low-pass filtering and vertical interpolation
Vertical low-pass filtering only
Chroma Comb Enable—This bit determines whether the chroma comb is included in the data
path. If enabled, a full line store is used to average adjacent lines of color information. This
reduces cross-color artifacts.
=
=
Chroma comb disabled
Chroma comb enabled
Interlace—This bit is programmed to indicate whether the incoming video is interlaced or noninterlaced. For example, when using the full frame as input for vertical scaling, this bit should
be programmed high. If using a single field for vertical scaling, this bit should be programmed
low. Single field scaling is normally used when scaling below CIF resolution and when outputting to a non-interlaced monitor. Using a single field reduces motion artifacts.
0
1*
VSCALE_HI
1
Luma Comb Enable—When enabled, the luma comb filter performs a weighted average on
two, three, four, or five lines of luminance data. The coefficients used for the average are fixed
and no interpolation is performed. The number of lines used for the luma comb filter is determined by the VFILT bits in the VTC register. When disabled by a logical 0, filtering and full
vertical interpolation is performed based upon the value programmed into the VSCALE register. The LUMA comb filter cannot be enabled on the Bt827A.
0
1*
INT
2
VSCALE_HI
0*
1
COMB
3
=
=
Non-interlace VS
Interlace VS
Vertical Scaling Ratio—These five bits represent the most significant portion of the 13-bit vertical scaling ratio register. Care must be taken to avoid altering the contents of the LINE,
COMB, and INT bits when adjusting the scaling ratio.
D829BDSA
95
Bt829B
4.0 Control Register Definitions
0x14—Vertical Scaling Register, Lower Byte (VSCALE_LO)
VideoStream II Decoders
0x14—Vertical Scaling Register, Lower Byte (VSCALE_LO)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00.
7
6
5
4
3
2
1
0
0
0
0
0
VSCALE_LO
0
VSCALE_LO
0
0
0
Vertical Scaling Ratio—These eight bits represent the LSbyte of the 13-bit vertical scaling
ratio register. They are concatenated with 5 bits in VSCALE_HI. The following equation is
used to determine the value for this register:
VSCALE = ( 0x10000 – { [ ( scaling_ratio ) – 1] * 512 } ) & 0x1FFF
For example, to scale PAL/SECAM input to square pixel QCIF, the total number of vertical
lines is 156:
VSCALE = ( 0x10000 – { [ ( 4/1 ) –1 ] * 512 } ) & 0x1FFF
= 0x1A00
0x15—Test Control Register (TEST)
This control register is reserved for putting the part into test mode. Write operation to this register may cause
undetermined behavior and should not be attempted. A read cycle from this register returns 0x01, and only a
write of 0x01 is permitted.
96
D829BDSA
Bt829B
4.0 Control Register Definitions
0x16—Video Timing Polarity Register (VPOLE)
VideoStream II Decoders
0x16—Video Timing Polarity Register (VPOLE)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. An
asterisk indicates the default option.
7
6
5
4
3
2
1
0
OUT_EN
DVALID
VACTIVE
CBFLAG
FIELD
ACTIVE
HRESET
VRESET
0
0
0
0
0
0
0
0
OUTEN
Three-states the pins defined by OES in the OFORM register. The affected pins are: VD[15:0],
HRESET, VRESET, ACTIVE, VACTIVE, DVALID, CBFLAG, FIELD, QCLK, CLKx1, and
CLKx2.
When Pin 85 is a logical 0
0*
1
=
=
Enable outputs
Three-state outputs
When Pin 85 is a logical 1
0*
1
=
=
Three-state outputs
Enable outputs
0*
1
=
=
DVALID Pin: Active high
DVALID Pin: Active low
0*
1
=
=
VACTIVE Pin: Active high
VACTIVE Pin: Active low
0*
1
=
=
CBFLAG Pin: Active high
CBFLAG Pin: Active low
0*
1
=
=
FIELD Pin: High indicates odd field
FIELD Pin: High indicates even field
0*
1
=
=
ACTIVE Pin: Active high
ACTIVE Pin: Active low
0*
1
=
=
HRESET Pin: Active low
HRESET Pin: Active high
0*
1
=
=
VRESET Pin: Active low
VRESET Pin: Active high
DVALID
VACTIVE
CBFLAG
FIELD
ACTIVE
HRESET
VRESET
D829BDSA
97
Bt829B
4.0 Control Register Definitions
0x17—ID Code Register (IDCODE)
VideoStream II Decoders
0x17—ID Code Register (IDCODE)
This control register may be read by the MPU at any time. PART_REV(0) is the LSB.
7
6
5
4
3
2
PART_ID
1
1
1
0
0
0
PART_REV
1
0
0
0
PART_ID
1110 =
1100 =
Bt829A Part ID Code
Bt827A Part ID Code
PART_REV
0x0 – 0xF = Current Revision ID Code
0x18—AGC Delay Register (ADELAY)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x68.
7
6
5
4
3
2
1
0
1
0
0
0
ADELAY
0
ADELAY
1
1
0
This register indicates the AGC gate delay for back-porch sampling. The following equation
should be used to determine the value for this register:
ADELAY = ( 6.8 µS * fCLKx1 ) + 7
For example, for an NTSC input signal:
ADELAY = ( 6.8 µS * 14.32 MHz ) + 7
= 104 (0x68)
98
D829BDSA
Bt829B
4.0 Control Register Definitions
0x19—Burst Delay Register (BDELAY)
VideoStream II Decoders
0x19—Burst Delay Register (BDELAY)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x5D.
BDELAY(0) is the LSB.
7
6
5
4
3
2
1
0
1
1
0
1
BDELAY
0
BDELAY
1
0
1
This register indicates the burst gate delay for sub-carrier sampling. The following equation
should be used to determine the value for this register:
BDELAY = ( 6.5 µS * fCLKx1 )
For example, for an NTSC input signal:
BDELAY = ( 6.5 µS * 14.32 MHz )
= 93 (0x5D)
D829BDSA
99
4.0 Control Register Definitions
Bt829B
0x1A—ADC Interface Register (ADC)
VideoStream II Decoders
0x1A—ADC Interface Register (ADC)
This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x82.
Reserved is the LSB. An asterisk indicates the default option.
7
6
Reserved
1
0
5
4
3
2
1
0
SYNC_T
AGC_EN
CLK_SLEEP
Y_SLEEP
C_SLEEP
CRUSH
0
0
0
0
1
0
Reserved
These bits should only be written with bit 7 set at a logical 1 and bit 6 set at a logical 0.
SYNC_T
This bit defines the voltage level for which the SYNC signal can be detected.
0*
1
=
=
Analog SYNCDET threshold high (~125 mV)
Analog SYNCDET threshold low (~75 mV)
AGC_EN
This bit controls the AGC function. When disabled, REFOUT is not driven, and an external
reference voltage must be provided. When enabled, REFOUT is driven to control the A/D
reference voltage.
0* = AGC Enabled
1
= AGC Disabled
CLK_SLEEP
When this bit is set at a logical 1, the system clock is powered down, but the output clocks
(CLKx1 and CLKx2) are still running, and the I2C registers are still accessible. Recovery time
is approximately one second.
0* = Normal clock operation
1
= Shut down the system clock (power down)
Y_SLEEP
This bit enables the luma ADC to operate in sleep mode.
0*
1
=
=
Normal Y ADC operation
Sleep Y ADC operation
C_SLEEP
This bit enables the chroma ADC to operate in sleep mode.
0
= Normal C ADC operation
1* = Sleep C ADC operation
CRUSH
This bit enables white CRUSH mode, and must be written with a logical 0.
0*
1
100
=
=
Normal SYNC level to white level
Enable white CRUSH mode to compensate for nonstandard
SYNC to white video relationship
D829BDSA
Bt829B
4.0 Control Register Definitions
0x1B—Video Timing Control (VTC)
VideoStream II Decoders
0x1B—Video Timing Control (VTC)
This register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. VFILT(0) is
the LSB. An asterisk indicates the default option.
7
6
5
4
3
2
HSFMT
ACTFMT
CLKGATE
VBIEN
VBIFMT
VALIDFMT
0
0
0
0
0
0
HSFMT
VBIEN
0
0
=
=
HRESET is 64 CLKx1 cycles wide
HRESET is 1 pixel wide
=
=
ACTIVE is composite active
ACTIVE is horizontal active
This bit selects the signals that are gated with CLK to create QCLK. If logical 0 is selected, the
ACTIVE pin (composite ACTIVE or HACTIVE) is used in gating CLK.
0*
=
1
=
CLKx1 and CLKx2 are gated with DVALID and ACTIVE to
create QCLK
CLKx1 and CLKx2 are gated with DVALID to create QCLK
This bit enables VBI data to be captured.
0*
1
VBIFMT
VFILT
This bit selects whether composite ACTIVE (HACTIVE and VACTIVE) or whether
HACTIVE only is output on the ACTIVE pin.
0*
1
CLKGATE
0
This bit selects between a single-pixel-wide HRESET and the standard 64-clock-wide
HRESET.
0*
1
ACTFMT
1
=
=
Do not capture VBI
Capture VBI
This bit determines the byte ordering for VBI data.
0*
=
1
=
0*
1
=
=
Pixel N on the VD[15:8] data bus, pixel N+1 on the VD[7:0]
data bus
Pixel N+1 on the VD[15:8] data bus, Pixel N on the VD[7:0]
data bus (Pixel N refers to the first, third, fifth, and so on, while
pixel N+1 refers to the second, fourth, and sixth in a horizontal
line of video)
VALIDFMT
Normal DVALID timing
DVALID is the logical AND of VALID and ACTIVE, where
ACTIVE is controlled by the ACTFMT bit. Also, the QCLK
signal will free turn and is an inverted version of CLKx1 or
CLKx2, depending upon whether 8- or 16-bit pixel output
format is selected.
D829BDSA
101
Bt829B
4.0 Control Register Definitions
0x1B—Video Timing Control (VTC)
VFILT
VideoStream II Decoders
These bits control the number of taps in the Vertical Scaling Filter. The number of taps must be
chosen in conjunction with the horizontal scale factor to ensure that the needed data does not
overflow the internal FIFO.
If the YCOMB bit in the VSCALE_HI register is set at a logical 1, the following settings
and equations apply:
00* =
2-tap 1--- ( 1 + Z –1 ) Available at all resolutions.
01
=
3-tap 1--- ( 1 + 2Z –1 + Z –2 ) Only available when scaling to less than
4
385 horizontal active pixels for PAL, or 361 for NTSC (CIF or
smaller).
10
=
4-tap 1--- ( 1 + 3Z –1 + 3Z –2 + Z –3 ) Only available when scaling to
8
less than 193 horizontal active pixels for PAL, or 181 for NTSC
(QCIF or smaller).
11
=
1
–1
–2
–3
–4
- ( 1 + 4Z + 6Z + 4Z + Z ) Only available when
5-tap ----16
scaling to less than 193 horizontal active pixels for PAL, or 181
for NTSC (QCIF or smaller).
2
If the YCOMB bit in the VSCALE_HI register is set at a logical 0, the following settings and equations apply:
NOTE:
102
00* =
2-tap interpolation only. Available at all resolutions.
01
=
2-tap 1--- ( 1 + Z –1 ) and 2-tap interpolation. Only available when
2
scaling to less than 385 horizontal active pixels for PAL, or 361
for NTSC (CIF or smaller).
10
=
3-tap 1--- ( 1 + 2Z –1 + Z –2 ) and 2-tap interpolation. Only available
4
when scaling to less than 193 horizontal active pixels for PAL,
or 181 for NTSC (QCIF or smaller).
11
=
4-tap 1--- ( 1 + 3Z –1 + 3Z –2 + Z –3 ) and 2-tap interpolation. Only
8
available when scaling to less than 193 horizontal active pixels
for PAL, or 181 for NTSC (QCIF or smaller).
The Bt827A can only be used with a VFILT value of 00, because it does not have a
vertical scaling filter.
D829BDSA
Bt829B
4.0 Control Register Definitions
0x1C—Extended Data Service/Closed Caption Status Register
VideoStream II Decoders
0x1C—Extended Data Service/Closed Caption Status Register (CC_STATUS)
This register may be written or read by the MPU at any time. Upon reset, the value of register bits 7, 1, and 0 are
indeterminate because their status depends on the incoming CC/EDS data. Having register bits 6, 5, and 4 at
their reset value causes the CC/EDS circuitry to be powered down. LO_HI is the LSB. An asterisk indicates the
default option.
7
6
5
4
3
2
1
0
PARITY_ERR
CCVALID_EN
EDS
CC
OR
DA
CC_EDS
LO_HI
X
1
0
0
0
0
X
X
PARITY_ERR
This bit corresponds to the current word in CC_DATA.
0
1
NOTE:
CCVALID_EN
Closed caption data is transmitted using odd parity.
This bit serves as a mask for the CCVALID interrupts pin.
0
1
EDS
CC data is not written into the CC_DATA FIFO
CC data is written into the CC_DATA FIFO
=
=
An overflow has not occurred since this bit was last reset
An overflow has occurred
=
=
FIFO is empty
One or more bytes available
This bit indicates whether a CC byte or an EDS byte is in the CC_DATA register. After the
CC_DATA register is read, this bit is automatically updated. This bit is read only. On reset, this
bit is not valid.
0
1
LO_HI
=
=
CC/EDS data available. This bit indicates whether valid data exists in the CC_DATA FIFO.
This bit is read only. On reset, this bit is set to zero.
0
1
CC_EDS
EDS data is not written into the CC_DATA FIFO
EDS data is written into the CC_DATA FIFO
This bit indicates the CC_DATA FIFO is full and that EDS or CC data has been lost. This bit is
read only. On reset or read of CC_DATA, this bit is set to zero.
0
1
DA
=
=
This bit determines whether CC data is written into the CC_DATA FIFO.
0*
1
OR
= Disabled CCVALID interrupts pin
= Enabled CCVALID interrupts pin
This bit determines whether EDS data is written into the CC_DATA FIFO.
0*
1
CC
= No error
= Odd parity error
=
=
Closed caption byte in CC_DATA
Extended data service byte in CC_DATA
CC/EDS data are output in 16-bit words. This bit indicates whether the low or high byte is
located in the CC_DATA register. This bit is read only. On reset, this bit is not valid.
0
1
=
=
Low byte is in the CC_DATA register
High byte is in the CC_DATA register
D829BDSA
103
Bt829B
4.0 Control Register Definitions
0x1D—Extended Data Service/Closed Caption Data Register
VideoStream II Decoders
0x1D—Extended Data Service/Closed Caption Data Register (CC_DATA)
The CC-DATA register is read only and can be read by the MPU at any time. Any writes to this register are
ignored. Upon reset, the value of the bits in this register are indeterminate because their status depends on the
incoming CC/EDS data. CC_DATA(0) is the LSB.
7
6
5
4
3
2
1
0
X
X
X
X
CC_DATA
X
CC_DATA
X
X
X
The low or high data byte transmitted in a closed caption or extended data service line.
0x1E—White Crush Down Count Register (WC_DN)
This control register may be written to or read by the MPU at any time. Upon reset, the value of the register bits
is initialized to 0x7F. DNCNT(0) is the LSB. This register is programmed with a two’s complement number.
7
6
VERTEN
WCFRAME
0
1
5
4
3
2
1
0
1
1
1
DNCNT
1
1
1
VERTEN
0*
1
WCFRAME
Normal operation
Adds vertical detection algorithm to reject noise causing false
vertical syncs.
This bit programs the rate at which the DNCNT and UPCNT values are accumulated.
0
1
DNCNT
=
=
=
=
Once-per-field
Once-per-frame
The value programmed in these bits accumulates at a rate of once-per-field or frame. The accumulated value determines the extent to which the AGC value needs to be lowered to keep the
SYNC level proportionate to the white level.
The DNCNT value is assumed negative:
3F
3E
:
.
00
=
=
:
.
=
–1
–2
:
.
–64
0x1F—Software Reset Register (SRESET)
This command register can be written at any time. Read cycles to this register return an undefined value. A data
write cycle to this register resets the device to the default state (indicated in the command register definitions by
an asterisk). Writing any data value into this address resets the device.
104
D829BDSA
Bt829B
4.0 Control Register Definitions
0x3F—Programmable I/O Register (P_IO)
VideoStream II Decoders
0x3F—Programmable I/O Register (P_IO)
This control register may be written to or read by the MPU at any time. Upon reset, the value of the register bits
is initialized to 0x00. OUT_0 is the LSB. While in 8-bit output mode (SPI-8), the VD[7:0] pins are completely
asynchronous. IN[3:0] represent the digital levels input on VD[7:4], while the values programmed into
OUT[3:0] represent the output on VD[3:0]
7
6
5
4
3
2
1
0
IN_3
IN_2
IN_1
IN_0
OUT_3
OUT_2
OUT_1
OUT_0
0
0
0
0
0
0
0
0
IN[3:0]
These input bits can be used to monitor external signals from VD[7:4]. The programmable I/O
register is only accessible in the 8-Bit 4:2:2 YCrCb Output Mode (LEN = 0). When not in 8Bit Output Mode, the values returned by the IN[3:0] bits are not valid.
OUT[3:0]
These output bits can be programmed to output miscellaneous additional signals from the
video decoder on VD[3:0]. The Programmable I/O register is only accessible in the 8-bit 4:2:2
YCrCb Output Mode. When not in the 8-Bit output mode, the OUT[3:0] bits are set to
logical 1.
D829BDSA
105
Bt829B
4.0 Control Register Definitions
0x3F—Programmable I/O Register (P_IO)
106
VideoStream II Decoders
D829BDSA
5.0 Parametric Information
5.1 DC Electrical Parameters
Table 5-1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Power Supply — Analog
VAA
4.75
5.00
5.25
V
Power Supply — 5.0 V Digital
VDD
4.75
5.00
5.25
V
Power Supply — 3.3 V Digital
VDDO
3.00
3.3
3.6
V
0.5
V
Maximum ∆ |VDD – VAA|
MUX0, MUX1 and MUX2 Input Range
(AC coupling required)
0.5
1.00
2.00
V
VIN Amplitude Range (AC coupling required)
0.5
1.00
2.00
V
+70
˚C
Ambient Operating Temperature
TA
0
D829BDSA
107
Bt829B/827B
5.0 Parametric Information
5.1 DC Electrical Parameters
VideoStream II Decoders
Table 5-2. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Units
VAA (measured to AGND)
7.00
V
VDD (measured to DGND)
7.00
V
Voltage on any signal pin (See the note below)
DGND – 0.5
VDD + 0.5
V
Analog Input Voltage
AGND – 0.5
VAA + 0.5
V
–65
+150
˚C
Storage Temperature
TS
Junction Temperature
TJ
+125
˚C
Vapor Phase Soldering
(15 Seconds)
TVSOL
+220
˚C
Note:
Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional
operation at these or any other conditions above those listed in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD-sensitive device.
Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V, or drops below ground by more than
0.5 V, can induce destructive latch-up.
Table 5-3. DC Characteristics (3.3 V digital I/O operation)
Parameter
Symbol
Min
Input High Voltage (TTL)
VIH
2.0
Input Low Voltage (TTL)
VIL
Input High Voltage (XT0I, XT1I,)
VIH
Input Low Voltage (XT0I, XT1I,)
VIL
Input High Current (VIN=VDD)
Typ
Max
Units
VDDO + 0.5
V
0.8
V
2.3
VDDO + 0.5
V
GND – 0.5
1.0
V
IIH
10
µA
Input Low Current (VIN=GND)
IIL
–10
µA
Input Capacitance (f=1 MHz, VIN=2.4 V)
CIN
Input High Voltage (NUMXTAL, I2CCS)
VIH
2.5
Output High Voltage (IOH = –400 µA)
VOH
2.4
Output Low Voltage (IOL= 3.2 mA)
Digital Inputs
pF
V
Digital Outputs
VDDO
V
VOL
0.4
V
Three-State Current
IOZ
10
µA
Output Capacitance
CO
5
pF
CA
5
pF
Analog Pin Input Capacitance
108
D829BDSA
Bt829B/827B
5.0 Parametric Information
5.1 DC Electrical Parameters
VideoStream II Decoders
Table 5-4. DC Characteristics (5 V only operation)
Parameter
Symbol
Min
Input High Voltage (TTL)
VIH
2.0
Input Low Voltage (TTL)
VIL
Input High Voltage (XT0I, XT1I,)
VIH
Input Low Voltage (XT0I, XT1I,)
VIL
Input High Current (VIN=VDD)
Typ
Max
Units
VDD + 0.5
V
0.8
V
3.5
VDD + 0.5
V
GND – 0.5
1.5
V
IIH
10
µA
Input Low Current (VIN=GND)
IIL
–10
µA
Input Capacitance (f=1 MHz, VIN=2.4 V)
CIN
Digital Inputs
5
pF
Digital Outputs
Output High Voltage (IOH = –400 µA)
VOH
Output Low Voltage (IOL= 3.2 mA)
VDD
V
VOL
0.4
V
Three-State Current
IOZ
10
µA
Output Capacitance
CO
5
pF
CA
5
pF
Analog Pin Input Capacitance
2.4
D829BDSA
109
Bt829B/827B
5.0 Parametric Information
5.2 AC Electrical Parameters
VideoStream II Decoders
5.2 AC Electrical Parameters
Table 5-5. Clock Timing Parameters (1 of 2)
Parameter
Symbol
NTSC:
CLKx1 Rate
CLKx2 Rate (50 PPM source required)
FS1
PAL/SECAM:
CLKx1 Rate
CLKx2 Rate (50 PPM source required)
FS1
XT0 and XT1 Inputs
Cycle Time
High Time
Low Time
110
Min
FS2
FS2
1
2
3
28.2
12
12
D829BDSA
Typ
Max
Units
14.318180
28.636360
MHz
MHz
17.734475
35.468950
MHz
MHz
ns
ns
ns
Bt829B/827B
5.0 Parametric Information
5.2 AC Electrical Parameters
VideoStream II Decoders
Table 5-5. Clock Timing Parameters (2 of 2)
Parameter
CLKx1 Duty Cycle
CLKx2 Duty Cycle
CLKx2 to CLKx1 Delay
CLKx1 to Data Delay
CLKx2 to Data Delay
CLKx1 (Falling Edge) to QCLK (Rising Edge)
CLKx2 (Falling Edge) to QCLK (Rising Edge)
8-Bit Mode(1)
Data to QCLK (Rising Edge) Delay
QCLK (Rising Edge) to Data Delay
16-Bit Mode(1)
Data to QCLK (Rising Edge) Delay
QCLK (Rising Edge) to Data Delay
Symbol
Min
Typ
Max
Units
4
5
6
41
42
45
40
0
3
3
0
0
55
60
2
11 (25)(2)
11 (25)(2)
8
8
%
%
ns
ns
ns
ns
ns
7b
8b
5
15
ns
ns
7a
8a
14
25
ns
ns
Notes: (1). Because QCLK is generated with a gated version of CLKx1 or CLKx2, the timing in symbols 7 and 8 are subject to
changes in the duty cycle of CLKx1 and CLKx2. If crystals are used as clock sources for the Bt829A, the duty cycle is
symmetric. This assumption is used to generate the timing numbers shown in 7 and 8. For non-symmetric clock
sources, use the following equations:
Data to QCLK (setup) 16-bit mode
xtal period + CLKx1 to qclk (max) - CLKx1 to data (max)
or
symbol 1 + symbol 41 (max) - symbol 5 (max)
NTSC: 34.9 nS + 8 nS - 11 nS = 31.9 nS
PAL: 28.2 nS + 8 nS -11 nS = 25.2 nS
QCLK to Data (hold) 16-bit mode
xtal period - CLKx1 to qclk (min) + CLKx1 to data (min)
or
symbol 1 - symbol 41 (min) + symbol 5 (min)
NTSC: 34.9 nS - 0 nS + 3 nS = 37.9 nS
PAL: 28.3 nS - 0 nS + 3 nS = 31.3 nS
Data to QCLK (setup) 8-bit mode
(xtal period)/2 + CLKx2 to qclk (max) - CLKx2 to data (max)
or
(symbol 1)/2 + symbol 42 (max) - symbol 6 (max)
NTSC: 17.5 nS + 8nS - 11 nS = 14.5 nS
PAL: 14.1 nS + 8 nS - 11 nS = 11.1 nS
QCLK to data (hold) 8-bit mode
(xtal period)/2 - CLKx2 to qclk (min) + CLKx2 to data (min)
or
(symbol 1)/2 - symbol 42 (min) + symbol 6 (min)
NTSC: 17.5 nS - 0 nS + 3 nS = 20.5 nS
PAL: 14.1 nS - 0 nS + 3 nS = 17.1 nS
(2). Parenthesis indicate max CLKx1/CLKx2 to Data Delay when using VDDO = 3.3 V.
D829BDSA
111
Bt829B/827B
5.0 Parametric Information
5.2 AC Electrical Parameters
VideoStream II Decoders
Figure 5-1. Clock Timing Diagram
3
2
XT0I
or
XT1I
1
CLKx2
4
CLKx1
42
41
5
16-Bit Mode
Pixel and
Control
Data
7a
8a
QCLK
6
8-Bit Mode
Pixel and
Control
Data
7b
8b
QCLK
Table 5-6. Power Supply Current Parameters (3 and 5 V operation)
Parameter
Supply Current
VAA=VDD=5.0V, FCLKx2=28.64 MHz, T=25˚C
VAA=VDD=5.25V, FCLKx2=35.47 MHz, T=70˚C
VAA=VDD=5.25V, FCLKx2=35.47 MHz, T=0˚C
Supply Current, Power Down
Symbol
Min
Typ
Max
Units
250
280
mA
mA
mA
mA
Max
Units
100
100
nS
nS
nS
I
170
65
Table 5-7. Output Enable Timing Parameters
Parameter
OE Asserted to Data Bus Driven
OE Asserted to Data Valid
OE Negated to Data Bus Not Driven
Symbol
Min
9
10
11
0
RST Low Time
112
8
D829BDSA
Typ
XTAL cycles
Bt829B/827B
5.0 Parametric Information
5.2 AC Electrical Parameters
VideoStream II Decoders
Figure 5-2. Output Enable Timing Diagram
OE
11
10
9
Pixel, Clock
and
Control Data
Table 5-8. JTAG Timing Parameters
Parameter
Symbol
Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
10
10
60
5
80
12
13
14
15
16
17
18
TMS, TDI Setup Time
TMS, TDI Hold Time
TCK Asserted to TDO Valid
TCK Asserted to TDO Driven
TCK Negated to TDO Three-stated
TCK Low Time
TCK High TIme
Typ
25
25
Figure 5-3. JTAG Timing Diagram
12
13
TDI, TMS
17
TCK
18
14
15
16
TDO
Table 5-9. Decoder Performance Parameters
Parameter
Symbol
Min
Horizontal Lock Range
Fsc, Lock-in Range
Gain Range
Note:
Typ
Max
Units
±7
% of Line Length
±800
–6
Hz
6
dB
Test conditions (unless otherwise specified): “Recommended Operating Conditions.” TTL input values are 0–3 V, with
input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for digital inputs
and outputs. Pixel and control data loads ≤ 30 pF and ≥10 pF. CLKx1 and CLKx2 loads ≤ 50 pF. Control data includes
CBFLAG, DVALID, ACTIVE, VACTIVE, HRESET, VRESET and FIELD.
D829BDSA
113
Bt829B/827B
5.0 Parametric Information
5.3 Package Mechanical Drawings
VideoStream II Decoders
5.3 Package Mechanical Drawings
Figure 5-4. 100-Pin PQFP Package Mechanical Drawing
114
D829BDSA
Bt829B/827B
5.0 Parametric Information
5.4 Revision History
VideoStream II Decoders
5.4 Revision History
Table 5-10. Bt829B Datasheet Revision History
Revision
Date
Description
A
03/27/98
Engineering Release
D829BDSA
115
Please mail or fax this form to:
Manager, Technical Publications Dept.
Rockwell Semiconductor Systems
9868 Scranton Road
San Diego, CA 92121
Fax: (619) 597–4338
READER RESPONSE PAGE
e welcome your evaluation of this
publication. Your comments and suggestions will help us make improvements to all current and future
documents. Please rate the following characteristics
of the publication you received:
W
1. Overall usefulness of the publication.
Poor
Excellent
❍ ❍ ❍ ❍ ❍ ❍
2. Organization of the publication.
❍ ❍ ❍ ❍ ❍ ❍
3. Completeness and thoroughness of the material.
❍ ❍ ❍ ❍ ❍ ❍
4. Clarity and accuracy of the material.
❍ ❍ ❍ ❍ ❍ ❍
11. In what format(s) would you prefer to receive
future documents? (Check all that apply.)
❏ Printed books
❏ Internet/PDF delivery
❏ CD-ROM
❏ Other: _____________________________
12. How would you rank the importance of the following publication features? (1=Very important)
____ Publication design and layout
____ Accuracy of content
____ Detailed diagrams and illustrations
____ Receiving the publication in a timely manner
13. We would like to hear your thoughts on how we
could improve this publication. Please write
your comments or suggestions below:
_____________________________________
5. Usefulness of the diagrams and illustrations.
❍ ❍ ❍ ❍ ❍ ❍
6. Quantity of diagrams and Illustrations.
❍ ❍ ❍ ❍ ❍ ❍
7. Ease of finding specific information.
❍ ❍ ❍ ❍ ❍ ❍
8. Publication page layout and format.
❍ ❍ ❍ ❍ ❍ ❍
9. I received the publication(s): (Please mark one).
❏ Within one week after ordering it
❏ Within two weeks after ordering it
❏ Within three or more weeks after ordering it
_____________________________________
_____________________________________
Thank you for taking the time to evaluate this publication.
Document title:____________________________
Revision No.: _____________________________
Your Name: ______________________________
Title: ____________________________________
Company: ________________________________
10. The publication delivery time was: (Please mark
one).
❏ Earlier than I needed for my needs
❏ Just in time for my needs
❏ Too late for my needs
E-mail: __________________________________
Phone: __________________________________