RTH010 DATA SHEET REV F Electrical Specification (Continued) PARAMETER SYMBOL CONDITIONS, NOTE TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH1 Aperture Delay ta After V(CLK1) - V(CLK1B) Goes Neg. 4,5 Aperture Jitter Jitter Free 1-GHz 0.5-Vpp CLK1(B) ∆t At Hold Capacitors. ttrack1,min Settling Time to 1 mV ts Observed 6 Differential Pedestal/VIN Diff. Droop Rate/VIN 7 Hold Noise Per Sqrt(Hold Time) Minimum CLK1 Freq. fclk1, min 50% Duty Cycle Clock Maximum CLK1 Freq. fclk1, max 50% Duty Cycle Clock 8 Maximum Hold Time thold1, max HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH1 9 Acquisition Time to 1 mV tacq At Hold Caps, FSR Step At Input 9 Max. Acq. Slew Rate dvdt,max At Hold Caps, FSR Step At Input 9 Rise Time tr 20 – 80% Minimum Track Time ttrack1,min thold1,max Observed Required Accumulated Track Time Recovery Time After thold1,max Violation TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH2 Aperture Delay ta2 After V(CLK2) - V(CLK2B) Goes Neg. 10 Settling Time to 1 mV ts2 At DTH Output. ttrack2,min Observed 11 Differential Pedestal/VIN Diff. Droop Rate/VIN 7 Hold Noise Per Sqrt(Hold Time) Minimum CLK2 Freq. fclk2,min 50% Duty Cycle Clock Maximum CLK2 Freq. fclk2,max 50% Duty Cycle Clock 8 Maximum Hold Time thold2,max HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH2 Minimum Track Time after ttrack2,min thold2,max Observed 12 TH1 in Hold Mode Required Accumulated Track Time Recovery Time After thold2,max Violation POWER SUPPLY REQUIREMENTS Positive Supply Voltage VCC VCC Current ICC Negative Supply Voltage VEE VEE Current IEE Power Dissipation 13 Warm-up Time After Power-up 4 5 6 7 8 9 10 11 12 13 TEST LEVEL MIN TYP MAX UNITS 4 3 70 +60 100 130 ps fs 4 300 ps 4 4 4 2 2 3 -2 -1 50 % %/ns µV/√ns MHz MHz ns 1000 5 4 4 3 2 8 250 15 50 0.4 3 4 4 4 4 4 2 2 3 1000 10 15 ns 100 1250 20 ps ps % %/ns µV/√ns MHz MHz ns 0.5 3 4.75 -5.45 2.2 5.0 130 -5.2 325 2.35 ps V/ns ps ns 4 +60 300 ±0.25 -0.12 25 2 1 1 1 1 1 2 200 1250 12 ns 4 ns 5.25 180 -4.95 400 2.5 10 V mA V mA W s The clock source jitter and the aperture jitter combine in an rms manner to yield the total sampling jitter. See Definition of Terms. Device aperture jitter increases as the V(CLK1) – V(CLK1B) slew rate at the zero crossing decreases. See Theory of Operation. The differential pedestal error is proportional to the input signal. For TH1 it corresponds to a track-to-hold gain ~ -0.17 dB. This gain loss may be observed at the DTH output if TH2 is in track mode during the TH1 track-to-hold transition. The variance of the hold noise is proportional to the hold time, thold. For example, for TH1, a 4-ns hold time, thold1, gives about 100 µV accumulated hold noise. TH1 and TH2 hold noise, up to the output sampling instant, should be rms added to the hold mode integrated noise of the DTH. Maximum hold time is determined by droop of single-ended hold capacitor voltages. The resulting shift of internal operating voltages is not directly observable at the DTH outputs but eventually causes device performance degradation. TH1 tacq, dvdt,max, and tr also apply to the reconstructed DTH output if sub-sampling a fast-edge repetitive wave form. Output is settled ta2 + ts2 after CLK2(B) downward transition. The differential pedestal error is proportional to the input signal. For TH2 it corresponds to a track-to-hold gain ~ ±0.02 dB. ttrack2,min > ts, since the buffered TH1 output onto the TH2 hold capacitors lags behind the TH1 hold capacitor signal. The part functions immediately and reaches specification after warm-up time. The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 3 RTH010 DATA SHEET REV F Test Levels TEST LEVEL 1 2 3 4 1 TEST PROCEDURE 1 100% production tested at Ta = 25 C 1 Sample tested at Ta = 25 C unless other temperature is specified Quaranteed by design and/or characterization testing Typical value only All tests are continuous, not pulsed. Therefore, Tj (junction temperature) > Tc (case temperature) > Ta (ambient temperature). This is the normal operating condition and is more stressful than a pulsed test condition. Pin Description and Pin Out P/I/O P I I O I I P P I O I I NAME GND TMS INP OUTP CLK1 CLK2 VEE VCC INN OUTN CLK1B CLK1B FUNCTION Power Supply Ground Track Mode Select Analog Input Analog Output Clock Input 1, High = Track Mode Clock Input 2, High = Track Mode Negative Power Supply, -5.2V ± 5% Positive Power Supply, 5.0V ± 5% Complementary Analog Input Complementary Analog Output Complementary Clock Input 1 Complementary Clock Input 2 Figure 2. Pin configuration (top view, not to scale)24-lead glass-wall metallized ceramic quad flat pack Definitions of Terms Acquisition Time (tacq). The delay between the time that a track-and-hold circuit (TH) enters track mode and the time that the TH hold capacitor nodes track the input within some specified precision. The acquisition time sets a lower limit on the required track time during clocked operation. Aperture Delay (ta). The average (or mean value) of the delay between the hold command (input clock switched from track to hold state) and the instant at which the analog input is sampled. The time is positive if the clock path delay is longer than the signal path delay. It is negative if the signal path delay is longer than the clock path delay. Aperture Jitter (∆t). The standard deviation of the delay between the hold command (input clock switched from hold to track state) and the instant at which the analog input is sampled, excluding clock source jitter. It is the total jitter if the clock source is jitter free (ideal). Jitter diverges slowly as measurement time increases because of “1/f” noise, important at low frequencies (< 10 kHz). The specified jitter takes into account the white noise sources only (thermal and shot noise). For high-speed samplers this is reasonable, since even long data records span a time shorter than the time scale important for 1/f noise. For white-noise caused jitter, the clock and aperture jitter can be added in an rms manner to obtain the total sampling jitter. The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 4 RTH010 DATA SHEET REV F If the underlying voltage noise mechanism of the sampling jitter has a white spectrum, the sampled signal will display a white noise floor as well. In this case, the required aperture jitter, ∆t, to achieve a certain SNR, for a full-scale sinewave at frequency, f, is given by (B. Razavi, Principles of Data Conversion, IEEE Press, 1995, Appendix 2.1): SNR (dB) = −20 log(2πf∆t ) If this TH is used in front of an n-bit ADC, then the ideal ADC SNDR is given by: SNDR (dB) = 10 log(3 / 2) + 20 log(2)n = 1.76 + 6.02n In order that the TH jitter performance not limit the ADC performance, the jitter must fulfill: ∆t ≤ 1 . 6π 2 n f Note that this is independent of the sampling rate, so undersampling does not improve jitter tolerance. The averaging that is often combined with undersampling in test equipment, does improve jitter tolerance (and tolerance to other white noise effects). The criterion above is sharper than the standard (incorrect) time-domain slope estimate by a factor √6. The reason is that n-bit quantization requires an rms error of (quantization step)/√12, which is considerably smaller than the quantization step error implicitly allowed in the usual time-domain estimates (another √2 comes from the energy of a sinewave relative to its amplitude squared). The time-domain maximum slope argument can be appropriate for non-sinusoidal inputs, such as those encountered in instrumentation. If the rms error, ∆V, in the maximum slope region, slope FSR/(rise time), is used to define an effective number of bits, n, then the jitter simply needs to fulfill: ∆t ≤ rise time 2n Clock Jitter. The standard deviation of the instants of the mid-point of the relevant (rising or falling) edge of the clock source relative to the ideal instants (best fit). This jitter can be derived from the phase noise of the clock source, where the lower frequency bound of integration should correspond to the duration of a measurement record that the source will be used for. Full Scale Range (FSR). The maximum difference between the highest and lowest input levels for which various device performance specifications hold, unless otherwise noted. Gain. Ratio of output signal magnitude to input signal magnitude. For sinewave inputs, it is the ratio of the amplitude of the first (main) harmonic output (HD1) to the amplitude of the input. Input Bandwidth (BW, bw). The input frequency at which the gain for sinewave inputs is reduced by 3 dB (factor 1/√2) relative to its average value at low frequencies. The low frequency range is defined as the range including DC over which the gain stays essentially constant. The high frequency range is characterized by an increase in gain variation versus frequency, at least including the eventual monotonic decrease of the gain (“roll-off”). The input bandwidth tends to be input amplitude dependent. It is normally largest for very small inputs (small signal bandwidth, bw) and smallest for FSR inputs (large signal bandwidth, BW). Settling Time (ts). The delay between the time that a track-and-hold circuit (TH) enters hold mode and the time that the TH hold capacitor nodes settle to within some specified precision. The settling time sets a lower limit on the required hold time during clocked operation. Spectrum. The finite Fourier transform (FFT) of the discrete-time-sampled TH output. Ideally, this is obtained with a very high-resolution ADC quantizing the TH output with a clock rate locked to the TH clock (the ADC may be clocked at a slower rate than the TH). In the case of a dual TH (DTH), we can also use the beat frequency test, where the input frequency is close to an integer multiple of the clock frequency, and the DTH output is fed directly into a spectrum analyzer. The DTH output then contains little high frequency energy and the low frequency part of the spectrum analyzer sweep accurately The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 5 RTH010 DATA SHEET REV F represents the TH spectrum that would have been obtained with the ADC method. 20 log(SFDR as amplitude ratio), and is generally positive. Spurious Free Dynamic Range (SFDR). The ratio of the magnitude of the first (main) harmonic, HD1, and the highest other harmonic (or nonharmonic other tone, if present), as observed in the TH spectrum. The input is FSR, unless otherwise noted. SFDR in dB is given by Total Harmonic Distortion (THD). The ratio of the square root of the sum of the harmonics 2 to 5 to the amplitude of the first (main) harmonic in the TH spectrum. THD in dB is given by 20 log(THD as amplitude ratio), and is generally negative. Figure 3. Timing diagram for out-of-phase clocking of TH1 and TH2 The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 6 RTH010 DATA SHEET REV F Theory of Operation The DTH chip contains two TH’s, TH1 and TH2, in series, together with clock shaping circuitry, BUFFER1 and BUFFER2, and a 50-ohm output driver, OUTBUF (Figure 1). To maximize dynamic range and insensitivity to noise, all nonDC internal circuits and all non-DC inputs and outputs are differential. TH1 determines the dynamic sampled-mode performance of the DTH. Its sampling bridges exploit the ultra-high speed of the Schottky diodes available in the GaAs HBT process. TH1 clock inputs, CLK1 and CLK1B, should be driven by a low-jitter clock source. TH2 is similar to TH1, except that its bandwidth requirement is lower and its gain is closer to unity. The DTH receives a differential analog input signal at inputs INP and INN, which is sampled on the TH1 hold capacitors upon a falling transition of its differential clock voltage V(CLK1) – V(CLK1B), after an aperture delay, ta, see Figure 2. TH1’s aperture delay is positive, nominally 60 ps. The sampling instant is affected by clock source jitter (off-chip) and aperture jitter (caused by onchip noise). From the Definition of Terms, the required total sampling jitter for sampling a 1GHz 1-Vpp sine wave with 10-bit accuracy is 127 fs. The aperture jitter of the RTH010 is less than 100 fs for a 1-GHz 0.5-Vpp TH1 clock, CLK1(B). Using rms addition of jitter, the clock source jitter must be less than 80 fs (over the measurement record time) for direct 10-bit sampling of GHz range signals. Given a noise variance, ∆V, of the on-chip clock buffer, its aperture jitter, ∆t, is inversely proportional to the clock buffer gain and the slew rate of the incoming clock at the zero-crossing point: ∆t = ∆V gain × slew rate For low slew rates or frequencies, the clock buffer gain is constant and its aperture jitter is inversely proportional to the input clock slew rate, improving with increasing slew rate. For high slew rates or high frequencies, the jitter increases again, because the buffer gain drops steeply. For the RTH010, the clock buffer gain is still roughly constant up to 1 GHz, so that the aperture jitter is inversely proportional with the slew rate of the incoming clock. In the above equation, we have ∆V/gain ≈ 0.15 mV. The RTH010 aperture jitter at various slew rates can then be estimated. For example, a 1-GHz 0.5Vpp sinusoidal CLK1(B) signal corresponds to a slew rate ~ 1.6 V/ns, correctly yielding an aperture jitter < 100 fs. The held and buffered output of TH1, VTH1, is sampled on the TH2 hold capacitors upon a falling transition of its differential clock voltage V(CLK2) – V(CLK2B), after an aperture delay closely equal to that of TH1. This allows simple out-of-phase clocking of TH1 and TH2 by having opposite phases for CLK1(B) and CLK2(B). Aperture jitter of TH2 is irrelevant, since the slew rate of the TH2 input is equal to the TH1 differential droop rate, about 1000x lower than the input slew rate for TH1 for a 1-GHz 1-Vpp sine wave. TH2 can be in track mode before TH1 switches to hold, but a minimum track time of TH2 after TH1 enters hold mode must be observed to ensure that TH2 has fully acquired the TH1 output (ttrack2,min). Hold mode feedthrough, or in-to-out hold-mode gain in dB, again is important for TH1 and not for TH2, since any distortion on the held TH1 signal by a rapidly varying TH1 input will be sampled by TH2, and can not be removed. RTH010’s TH1 hold mode feedthrough performance is more than sufficient for 10-bit sampling of GHz range signals. After a TH1 postamplifier, TH2 produces an output VTH2. For out-of-phase clocking, the delay from the hold instant of TH1 to the ideal sampling time of circuitry after TH2 is close to one full clock cycle, for example 1 ns at a 1-GHz sampling rate. The TH2 output is flat for more than half a clock cycle, which eases the bandwidth requirement of subsequent circuitry. This is true, even though a small glitch will be present at the transition from track to hold of The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 7 RTH010 DATA SHEET REV F TH2 and the output is only 10-bit accurate during the latter part of half a clock cycle. Lower limits for the sampling rates of TH1 and TH2 are set by single-ended hold-mode droop rates, and lead to the specification of maximum hold times (thold1,max and thold2,max). For longer hold times, the DTH must be allowed sufficient recovery time during track phase (or a sequence of track phases), so it can return to normal operation mode. The bandwidth of subsequent circuitry can be minimal if TH2 is clocked at its lowest recommended frequency, 100 MHz. Since TH1 should be clocked at least at 200 MHz, and possibly faster to meet jitter requirements, CLK1(B) and CLK2(B) can be chosen different, as long as they are locked to each other with a proper phase relationship. Minimum required single-pole bandwidth at the output for 10-bit precision is (10ln2/2π) x fCLK2, or approximately 1.1fCLK2. In practice, <200 MHz bandwidth of subsequent circuitry would be sufficient, if fCLK2 is 100 MHz. One digital input, Track Mode Select (TMS), is provided to put both TH’s in track mode, independent of the clock signals. The bandwidth of the DTH is substantially lower in this mode than in the sampled mode. The TMS is useful for low sample-rate operation, including DC testing Signal Descriptions The RTH010 inputs are terminated on-chip with 50 Ω to GND. This automatically protects against off-chip high-impedance high-voltage disturbances. The absolute maximum rated voltage at input termination resistors is ±1 V, at 20 mA current. The RTH010 is designed for 1Vpp differential input signals, and can accept common-mode offsets up to ±100 mV. If operated in single-ended mode, terminate the complementary input off-chip with 50 Ω to the same common mode as the driven input. The single-ended FSR is half that of the differential FSR. Distortion in the single-ended mode can be up to 6 dB higher than in differential mode, and differential input should be used for optimal performance. The INP and INN inputs are equivalent, except for the polarity of their effect on OUTP and OUTN. All four clock input signals are terminated onchip with 50 Ω to GND. For lowest clock source jitter, use a sinusoidal clock source. Use differential clock signals for optimal performance. Large CLK1(B) amplitude benefits aperture jitter performance, small CLK1(B) and CLK2(B) amplitudes minimizes distortion due to clock feed-through in the higher clock frequency range (500 to 1000 MHz). Independent of the clock waveform, clock slew rates < 2 V/ns are recommended to minimize clock feed-through related distortion. In case of single-ended clocking the complementary input(s) can be terminated directly to GND (lowest noise, clock waveform distortion is not critical). Distortion for single-ended clocks can be several dB higher than for differential clocks, and differential clocks should be used for optimal performance. The track-mode select, TMS, can simply be left open for the (default) sampled-mode operation of the RTH010. Grounding the TMS puts both track-and-holds, TH1 and TH2, in track-mode. In this state, the TMS draws up to 0.75 mA of current. Due to its highly differential design, the RTH010 requires relatively modest power supply decoupling. The 0.01 µF capacitors VEE-toGND and VEE-to-VCC (Figure 4) should be placed as close to the package as possible. Larger low frequency power supply decoupling capacitors, VEE-to-GND and VCC-to-GND, should be placed within 1 inch of the RTH010. Depending on the expected noise on the supplies more capacitors in parallel may need to be used. With low-impedance supplies that are very quiet (no digital circuitry), the RTH010 can also perform well with no external decoupling at all. The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 8 RTH010 DATA SHEET REV F Typical Operating Circuit Figure 4. Typical interface circuit (sampled mode, connect TMS to GND for track mode). All differential inputs are terminated on-chip with 50 Ω to GND Die Plot and Pad Arrangement The inputs and output of the RTH010 are arranged in signal-ground-signal (SGS) configurations on opposite sides of the die (Figure 5). The clock signals come in under an orthogonal direction, which reduces inductive coupling to the signal path, both for bond wires and for package leads. The part does not require other components inside the package, since sufficient bypass capacitance is supplied on-chip. Figure 5. RTH010 die photo and pad arrangement Die size: 104 x 60 x 7 mils (2.650 x 1.525 x 0.178 mm) Pad pitch: 5.91 mil (0.150 mm) The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 9 RTH010 DATA SHEET REV F Typical Performance Characteristics (b) 1.9 -20 -40 -60 SA_TH400_W 7_B6b_TH_clk500M_in1V_1020M_2ndv6.QPC RSCTH01 1000 MHz CLK1,2 0 dB m 1020 MHz IN 1 Vpp at DUT RE S B W 3 kHz VBW 10 kHz SFDR (HD 3) 60.5 dB THD -58.8 dB -66.1 -58.6 TH Output (dBm ) TH O utput (dBm) SA_TH400_W 7_B6b_TH_clk1G_in1V_1020M_2ndv6.QPC 0 -63.8 -80 0 20 40 60 Frequency (MHz) 80 RSCTH01 500 MHz CLK1,2 0 dB m 1020 MHz IN 1 Vpp at DUT RE S B W 3 kHz VBW 10 kHz SFDR (HD 3) 57.9 dB THD -58.9 dB -57.9 -60 -69.7 -64.0 -80 20 40 60 Frequency (MHz) 80 100 Figure 7. Beat frequency spectrum for 1 GS/s and 1020-MHz 1-Vpp input sine wave (floor set by source and spectrum analyzer) TH400_W7_B6b_TH_THDall.QPC 0 Data 10 6:06:12 PM 11/27/2000 -2 60 1.0 V 0.5 V 40 0.1 1 Input Frequency (GHz) Figure 8. THD vs. input frequency for full and half scale input power (500 MS/s) Gain (dB) 70 -THD (dB) 2.2 -40 0 80 TH400_W9_A2b_TH_THDallV2.QPC 30 (a) -20 100 Figure 6. Beat frequency spectrum for 500 MS/s and 1020-MHz 1-Vpp input sine wave (floor set by source and spectrum analyzer) 50 0 -4 -6 1.000 V -8 0.500 V -10 0.250 V -12 0.015 V -14 1 10 Input Frequency (GHz) Figure 9. Gain vs. input frequency for various input power levels (500 MS/s) The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 10 RTH010 DATA SHEET REV F Package Information The package is a 24-lead metallized ceramicbase glass-sidewall Quad Flat-Pack. The leads are trimmed to 0.150 inch (3.81 mm) length. The thermal impedance (junction to base) is approximately 15 °C/W. The lid is sealed with epoxy. 0.275 SQ Pin #1 0.012 0.150 0.030 0.381 Figure 10. RTH010 package outline. Dimensions shown in inches, tolerance ±0.002 inch Ordering Information PART NUMBER RTH010QFP RTH010DIE 14 PACKAGE TYPE 24-Lead Ceramic Quad FP Die14 TEMPERATURE RANGE -30 to +70 °C 0 to +100 °C Die performance is as good as or better than that of the packaged part. On-wafer measurements show large/small-signal bandwidths, BW/bw, and THD at 5-GHz 0.5-Vpp equal to 6/9.3 GHz and –42 dB vs. 6/9 GHz and –32 dB for the packaged part. The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 11