ETC TBS6416B4E-7G

M.tec
TBS6416B4E
1M x 16Bit x 4 Banks synchronous DRAM
GENERAL DESCRIPTION
The TBS6416B4E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,
fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four-banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
ORDERING INFORMATION
Part No.
Max Freq.
Interface
Package
TBS6416B4E-7G
143MHz
LVTTL
54
TSOP(II)
Revision_1.1
1
TwinMOS Technologies Inc.
Sep. 2000
M.tec
TBS6416B4E
PIN CONFIGURATION (Top View)
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
Revision_1.1
2
TwinMOS Technologies Inc.
Sep. 2000
M.tec
TBS6416B4E
PIN FUNCTION DESCRIPTION
Pin Name
Function
Description
A0~ A11
Address
Multiplexed pins for row and column address Row address: A0~ A11.
Column address: A0 ~ A7.
BS0, BS1
Bank
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
DQ0 ~DQ15
Data Input / Output
Multiplexed pins for data output and input.
/CS
Chip Select
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
/RAS
Row Address Strobe
Command input. When sampled at the rising edge of the clock, /RAS,
/CAS and /WE define the operation to be executed.
/CAS
Column Address Strobe
Referred to /RAS
/WE
Write Enable
Referred to /RAS
UDQM/LDQM
Input /output mask
CLK
Clock Input
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE
Clock Enable
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Vcc
Power (+3.3 V)
Power for input buffers and logic circuit inside DRAM.
Vss
Ground
Ground for input buffers and logic circuit inside DRAM.
Vcc
Q Power (+ 3.3 V) for I/O Separated power from VCC , used for output buffers to improve noise.
buffer
Vss
Q Ground for I/O buffer
Separated ground from VSS , used for output buffers to improve noise.
NC
No Connection
No connection
Revision_1.1
3
TwinMOS Technologies Inc.
Sep. 2000
M.tec
TBS6416B4E
FUNCTIONAL BLOCK DIAGRAM
Buffer
Data Input
Row Decoder
&
1Mx16
1Mx16
Refresh Counter
1Mx16
Sense AMP
Address
ADD
Bank Select
Output Buffer
DQ
1Mx16
Column Decoder
Column Buffer
/CS
/ RAS
/ CAS
/ WE
CLK
CKE
Commend
Decoder
&
Clock
Buffer
Revision_1.1
Latency &
Burst Length
Programming
Register
4
TwinMOS Technologies Inc. Sep. 2000
M.tec
TBS6416B4E
ABSOLUTE MAXIMUM RATING
Parameter
Symbol
Value
Unit
VIN, VOUT
-1.0 ~ 4.6
V
VCC, VCCQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
℃
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage temperature
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to the recommended operating conditions.
Exposure to higher voltage than recommended for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
VCC, VCCQ
3.0
3.3
3.6
V
Input logic high voltage
VIH
2.0
3.0
VCCQ+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL=2mA
Input leakage current (Input)
IIL
-1
-
1
uA
3
Input leakage current (I/O pins)
IIL
-1.5
-
1.5
uA
3,4
Supply voltage
Note
Notes:
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≦ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≦ 3ns.
3. Any input 0V ≦ VIN ≦ VCCQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≦ Vout ≦ VCCQ
Revision_1.1
5
TwinMOS Technologies Inc. Sep. 2000
M.tec
TBS6416B4E
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
ICC1
ICC2P
Test Condition
Burst length = 1
tRC≧tRC(min)
IOL = 0mA
CKE≦VIL(max), tCC = 15 ns
TBS6416B4E-7G
Unit
Note
100
mA
1
2
Pre-charge standby current
in power- down mode
mA
ICC2PS
ICC2N
Pre-charge standby current
in non power-down mode
ICC2NS
ICC3P
CKE&CLK≦VIL(max), tCC = ∞
CKE≧VIH(min), /CS≧VIH(min) ,
tCC = 15ns
Input signals are stable
CKE≧VIH(min), CLK≦VIL(Max) ,
tCC = ∞
Input signals are stable
CKE≦VIL(max), tCC = 15 ns
2
30
mA
10
5
Active standby current in
power-down mode
mA
ICC3PS
Active standby current in
non power-down mode
(One bank active)
ICC3N
ICC3NS
CKE&CLK≦VIL(max), tCC = ∞
CKE≧VIH(min), /CS≧VIH(min) ,
tCC = 15ns
Input signals are stable
CKE≧VIH(min), CLK≦VIL(Max) ,
tCC = ∞
Input signals are stable
IOL=0 mA
Page burst
2Banks activated
tCCD = 2CLKS
Operating current
(Burst mode)
ICC4
Refresh current
ICC5
tRC≧tRC(min)
Self refresh current
ICC6
CKE≦0.2V
5
40
mA
20
CL = 3
150
CL = 2
140
mA
1
160
mA
2
1
mA
Note: 1.Measured with outputs open.
2.Refresh period is 64 ms.
Revision_1.1
6
TwinMOS Technologies Inc. Sep. 2000
M.tec
TBS6416B4E
AC CHARACTERISTICS AND OPERATING CONDITION FOR PC-143
(Vcc=3.3V±0.3V, Ta=0° to 70°C)
Parameter
TBS6416B4E-7G
Symbol
Min
Unit
Max
Row active to row active delay
tRRD
14
ns
/RAS to /RAS delay
tRCD
20
ns
Row pre-charge time
tRP
20
ns
Row active time
tRAS
45
Row cycle time
tRC
63
ns
Col. Address to col. Address delay
tCCD
1
CLK
Write Recovery Time
tWR
14
CLK Cycle Time
tCK
CLK High Level width
tCH
2.5
ns
CLK Low Level width
tCL
2.5
ns
Access Time from CLK
tAC
Output Data Hold Time
tOH
2.5
ns
Data-in Set-up Time
tDS
1.5
ns
Data-in Hold Time
tDH
1
ns
Address Set-up Time
tAS
1.5
ns
Address Hold Time
tAH
1
ns
CKE Set-up Time
tCKS
1.5
ns
CKE Hold Time
tCKH
1
ns
Command Set-up Time
tCMS
1.5
ns
Command Hold Time
tCMH
1
ns
Refresh Time
tREF
Mode register Set Cycle Time
tRSC
Revision_1.1
CL=2
10
CL=3
7
100K
1000
6
CL=3
5.4
64
7
ns
ns
CL=2
15
ns
ns
ms
ns
TwinMOS Technologies Inc. Sep. 2000
M.tec
TBS6416B4E
54PIN PLASTIC TSOP(II) (400mil)
54
28
detail of lead end
F
E
1
2
P
7
A
H
J
I
G
C
D
M
L
N
K
M
B
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
Revision_1.1
8
ITEM
A
MILLIMETERS
22.62 MAX.
INCHES
0.891 MAX.
B
0.91 MAX.
0.036 MAX.
C
0.80 (T.P.)
0.031 (T.P.)
D
0.32 +0.08
–0.07
0.013±0.003
E
0.10±0.05
0.004±0.002
F
1.20 MAX.
0.048 MAX.
G
1.00
0.039
H
11.76±0.20
0.463±0.008
I
10.16±0.10
0.400±0.004
J
0.80±0.20
0.031 +0.009
–0.008
K
0.145 +0.025
–0.015
0.006±0.001
L
0.50±0.10
0.020 +0.004
–0.005
M
0.13
0.005
N
0.10
0.004
P
3° +7°
–3°
3° +7°
–3°
TwinMOS Technologies Inc.
Sep. 2000