HY5V16CF 2 Banks x 512K x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY5V16CF is a 16,777,216-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V16CF is organized as 2banks of 524,288x16. HY5V16CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3±0.3V power supply Note) • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 60Ball FD-BGA with 0.65mm of • Programmable Burst Length and Burst Type pin pitch - 1, 2, 4, 8 or Full page for Sequential Burst • All inputs and outputs referenced to positive edge of - 1, 2, 4 or 8 for Interleave Burst system clock • Data mask function by UDQM or LDQM • Internal four banks operation • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY5V16CF-H 133MHz HY5V16CF-S 100MHz Power Normal Organization 2Banks x 512Kbits x16 Interface LVTTL Package 10.1x 6.4 60Ball 0.65 Pin -pitch FD-BGA This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Jun.01 HY5V16CF PIN CONFIGURATION (16 M S D R A M ) PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA Bank Address A0 ~ A10 Address Row Address Strobe, R A S , C A S, W E Column Address Strobe, Write Enable DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 R A S , C A S and W E define the operation Refer function truth table for details LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin V D D /V S S Power Supply/Ground Power supply for internal circuits and input buffers V D D Q /V S S Q Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.0/Jun.01 2 HY5V16CF FUNCTIONAL BLOCK DIAGRAM 512Kbit x 2banks x 16 I/O Synchronous DRAM Refresh Ref. Addr .[0:11] Auto/Self Refresh Address[0:10] Counter Row Decoder Refresh Interval Timer Row Addr. Latch/ Predecoder Self Refresh Counter 512 Kx16 Bank 0 Sense AMP & I/O gates Column Decoder CLK DQ0 DQ1 Register DQ2 Row Active CS RAS CAS State Machine BA(A11) C o l u m n A d d r. Column Active Latch & Counter Overflow Burst Length Counter WE Data Input/Output Buffers Precharge CKE Address DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 UDQM DQ14 Column Decoder LDQM Row Addr. Latch/ Predecoder Mode Register Rev. 0.0/Jun.01 DQ15 Sense AMP & I/O gates 512Kx16 Bank 1 Test Mode I/O Control 3 HY5V16CF ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TS T G -55 ~ 125 °C Voltage on Any Pin relative to V S S V IN, V O U T -1.0 ~ 4.6 V Voltage on V D D relative to V S S VDD, VD D Q -1.0 ~ 4.6 V Short Circuit Output Current IO S 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ T i m e TSOLDER 260 ⋅ 10 °C ⋅ S e c Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION Parameter ( T A = 0 t o 7 0 °C ) Symbol Min Typ. Max Unit Note Power Supply Voltage VD D , VDDQ 3.0 3.3 3.6 V 1 Input High Voltage V IH 2.0 3.0 V DDQ + 2.0 V 1,2 Input Low Voltage V IL V S S Q - 2.0 0 0.8 V 1,3 Note : 1.All voltages are referenced to VSS = 0 V 2.V IH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration 3.V IL (min) is acceptable -2.0V AC pulse width with ≤ 3ns of duration AC OPERATING CONDITION ( T A = 0 t o 7 0 ° C , V D D = 3 . 3 ± 0 . 3 VN o t e 2 , V S S = 0 V ) Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Output Load Capacitance for Access Time Measurement Symbol Value Unit V I H / V IL 2.4/0.4 V Vtrip 1.4 V tR / tF 1 ns Voutref 1.4 V CL 50 pF Note 1 Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit Rev. 0.0/Jun.01 4 HY5V16CF CAPACITANCE ( T A = 2 5° C , f = 1 M H z ) Parameter Pin Input capacitance Symbol Min Max Unit CLK C I1 2 4 pF A0 ~ A11, BA0, BA1, CKE, C S, RAS, CI 2 2.5 5 pF C I/O 2 6.5 pF CAS, W E, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF 50 pF DC Output Load Circuit DC CHARACTERISTICS I Parameter AC Output Load Circuit ( T A = 0 t o 7 0 ° C , V DD =3.3 ± 0 . 3 V Note3) Symbol Min. Max Unit Note Input Leakage Current IL I -1 1 uA 1 Output Leakage Current IL O -1 1 uA 2 Output High Voltage VOH 2.4 - V IO H = - 4 m A Output Low Voltage VOL - 0.4 V IO L = + 4 m A Note : 1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V 2.DO U T is disabled, V O U T =0 to 3.6 Rev. 0.0/Jun.01 5 HY5V16CF DC CHARACTERISTICS II ( T A = 0 t o 7 0 °C , V D D = 3 . 3 ± 0 . 3 V Note5 , VSS =0V) Speed Parameter Operating Current Precharge Standby Current in Power Down Mode Symbol ID D 1 Test Condition Burst length=1, One bank active tRC ≥ tR C( m i n ) , I O L = 0 m A ID D 2 P C K E ≤ V IL(max), tC K = min ID D 2 P S C K E ≤ V IL(max), tC K = -H -S 110 90 ∞ Unit Note mA 1 2 mA 1 mA 50 mA 12 mA 7 mA 5 mA 50 mA 20 mA C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K = m i n ID D 2 N Input signals are changed one time during 2clks. All other pins ≥ V D D -0.2V or ≤ 0.2V Precharge Standby Current in Non Power Down Mode ID D 2 N S C K E ≥ V IH ( m i n ) , t C K = ∞ Input signals are stable. Active Standby Current in Power Down Mode ID D 3 P C K E ≤ V IL(max), tC K = min ID D 3 P S C K E ≤ V IL(max), tC K = ∞ C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K = m i n ID D 3 N Input signals are changed one time during 2clks. All other pins ≥ V D D -0.2V or ≤ 0.2V Active Standby Current in Non Power Down Mode ID D 3 N S Burst Mode Operating Current ID D 4 C K E ≥ V IH ( m i n ) , t C K = ∞ Input signals are stable. tC K ≥ tC K ( m i n ) , I O L = 0 m A All banks active Auto Refresh Current ID D 5 tR R C ≥ tR R C ( m i n ) , A l l b a n k s a c t i v e Self Refresh Current ID D 6 CKE ≤ 0.2V CL=3 CL=2 150 100 mA 100 mA 100 mA 1 mA 1 2 Note : 1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II Rev. 0.0/Jun.01 6 HY5V16CF AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -H Parameter Unit Min System clock cycle time C A S Latency = 3 -S Symbol tCK3 Max 7.5 Min 10 1000 ns 1000 tCK2 10 Clock high pulse width tCHW 3 - 3 - ns 1 Clock low pulse width tCLW 3 - 3 - ns 1 6 ns Access time from clock C A S Latency = 2 Note Max 10 ns C A S Latency = 3 tAC3 6 C A S Latency = 2 tAC2 8 - 8 ns 2 Data-out hold time tOH 2.5 - 2.5 - ns Data-Input setup time tDS 2 - 2 - ns 1 Data-Input hold time tDH 1 - 1 - ns 1 Address setup time tAS 2 - 2 - ns 1 Address hold time tAH 1 - 1 - ns 1 CKE setup time tCKS 2 - 2 - ns 1 CKE hold time tCKH 1 - 1 - ns 1 Command setup time tCS 2 - 2 - ns 1 Command hold time tCH 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1.5 - 1 - ns CLK to data output in high Z-time C A S Latency = 3 tOHZ3 ns 5.4 C A S Latency = 2 tOHZ2 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate Rev. 0.0/Jun.01 7 HY5V16CF AC CHARACTERISTICS I -H Parameter -S Symbol Unit Min Max Min Max Operation tR C 65 - 70 - ns Auto Refresh tR R C 65 - 70 - ns R A S to C A S Delay tR C D 20 - 20 - ns R A S Active Time tR A S 45 120K 50 120K ns RAS Precharge Time tR P 20 - 20 - ns R A S to R A S Bank Active Delay tR R D 15 - 20 - ns C A S to C A S Delay tC C D 1 - 1 - CLK Write Command to Data-In Delay tW T L 0 - 0 - CLK Data-In to Precharge Command tD P L 1 - 1 - CLK Data-In to Active Command tD A L 4 - 3 - CLK DQM to Data-Out Hi-Z tD Q Z 2 - 2 - CLK DQM to Data-In Mask tD Q M 0 - 0 - CLK MRS to New Command tM R D 1 - 1 - CLK C A S Latency = 3 tP R O Z 3 3 - 3 - CLK C A S Latency = 2 tP R O Z 2 2 - 2 - CLK Power Down Exit Time tP D E 1 - 1 - CLK Self Refresh Exit Time tS R E 1 - 1 - CLK Refresh Time tR E F - 64 - 64 ms Note R A S Cycle Time Precharge to Data Output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.0/Jun.01 8 HY5V16CF DEVICE OPERATING OPTION TABLE HY5V16CF-H C A S Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.5ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns 100MHz(10ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns HY5V16CF-S C A S Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 8CLKs 3CLKs 6ns 2.5ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns Rev. 0.0/Jun.01 9 HY5V16CF COMMAND TRUTH TABLE Command A10/ ADDR CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X AP RA Read Note V L CA Read with Autoprecharge V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Burst Stop H X DQM H Auto Refresh H H L L L Entry H L L L H H H X Exit L H L L V X V X H X X L H X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge X X X Self Refresh1 H L H X Precharge selected Bank Entry V H Precharge All Banks X X power down Exit Clock BA Entry L H H L Suspend Exit L X H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2 . X = D o n′ t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s , Opcode = Operand Code, NOP = No Operation Rev. 0.0/Jun.01 10 HY5V16CF PACKAGE INFORMATION 60 Ball FD-BGA Package Rev. 0.0/Jun.01 11