ETC ADM6926

ADM6926
26 port 10/100 Mbps Ethernet Switch
Controller
Version 1.0
ADMtek.com.tw
Information in this document is provided in connection with ADMtek products. ADMtek may make
changes to specifications and product descriptions at any time, without notice. Designers must not rely on
the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek
reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them
The products may contain design defects or errors know as errata, which may cause the product to deviate
from published specifications. Current characterized errata are available on request. To obtain latest
documentation please contact you local ADMtek sales office or visit ADMtek’s website at
http://www.ADMtek.com.tw
*Third-party brands and names are the property of their respective owners.
ADMtek Inc.
V1.0
About this Manual
General Release
Intended Audience
ADMtek’s Customers
Structure
This Data sheet contains 5 chapters
Chapter 1
Product Overview
Chapter 2
Interface Description
Chapter 3
Function Description
Chapter 4.
Electrical Specification
Chapter 5.
Packaging
Revision History
Date
Version
08 Aug 2003
1.0
Customer Support
ADMtek Incorporated,
2F, No.2, Li-Hsin Rd.,
Science-based Industrial Park,
Hsinchu, 300, Taiwan, R.O.C.
Sales Information
Tel + 886-3-5788879
Fax + 886-3-5788871
Change
1. First release of ADM6926
ADMtek Inc.
V1.0
Table of Contents
Chapter 1 Product Overview ........................................................................................ 1-1
1.1
Overview.......................................................................................................... 1-1
1.2
Features ............................................................................................................ 1-1
1.3
Block Diagram ................................................................................................. 1-2
1.4
Abbreviations................................................................................................... 1-3
1.5
Conventions ..................................................................................................... 1-4
1.5.1
Data Lengths............................................................................................ 1-4
1.5.2
Register Type Descriptions ...................................................................... 1-4
1.5.3
Pin Type Descriptions.............................................................................. 1-4
Chapter 2 Interface Description ................................................................................... 2-1
2.1 Pin Diagram – ADM6926 (SS-SMII Interface)..................................................... 2-1
2.2
Pin Description................................................................................................. 2-2
2.2.1
SS-SMII Networking Interface, 60 pins ................................................... 2-2
2.2.2
MII/RMII Interface, 28pins...................................................................... 2-3
2.2.3
Power/Ground.......................................................................................... 2-5
2.2.4
Miscellaneous pins, 16 pins ..................................................................... 2-5
Chapter 3 Function Description ................................................................................... 3-1
3.1.1
Basic Operation ....................................................................................... 3-1
3.1.2
Address Learning ..................................................................................... 3-1
3.1.3
Address Aging .......................................................................................... 3-2
3.1.4
Address Recognition and Packet Forwarding ......................................... 3-3
3.1.5
Trunking Port Forwarding ...................................................................... 3-4
3.1.6
Illegal Frames.......................................................................................... 3-4
3.1.7
Back off Algorithm ................................................................................... 3-4
3.1.8
Buffers and Queues .................................................................................. 3-4
3.1.9
Half Duplex Flow Control ....................................................................... 3-5
3.1.10
Full Duplex Flow Control........................................................................ 3-5
3.1.11
Inter-Packet Gap (IPG) ........................................................................... 3-5
3.1.13
Priority Control ....................................................................................... 3-6
3.1.14
Alert LED Display.................................................................................... 3-7
3.1.15
Broadcast Storm Filter ............................................................................ 3-7
3.1.16
Collision LED Display............................................................................. 3-7
3.1.17
Bandwidth Control................................................................................... 3-8
3.1.18
Smart Discard .......................................................................................... 3-8
3.1.19
Security Support....................................................................................... 3-8
3.1.20
Smart Counter Support ............................................................................ 3-8
3.1.21
Length 1536 Mode ................................................................................... 3-8
3.1.22
PHY Management (MDC/MDIO Interface)............................................. 3-8
3.1.23
Forward Special Packets to the CPU Port .............................................. 3-9
3.1.24
Special TAG ........................................................................................... 3-10
3.1.25
Port 24 and Port 25 Interface (Only SS-SMII package support)........... 3-12
3.1.26
Hardware, EEPROM and SMI Interface for Configuration.................. 3-13
3.2
EEPROM Register Format ............................................................................ 3-17
3.2.1
Signature (Index: 0h) ............................................................................. 3-20
3.2.2
Global Configuration Register (Index: 1h)............................................ 3-20
ADM6926
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ADMtek Inc.
V1.0
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
3.2.19
3.2.20
3.2.21
3.2.22
3.2.23
3.2.24
3.2.25
3.2.26
3.2.27
3.2.28
3.2.29
3.2.30
3.2.31
3.2.32
3.2.33
3.2.34
3.2.35
3.2.36
3.2.37
3.2.38
3.2.39
3.2.40
3.2.41
3.2.42
3.2.43
3.2.44
3.2.45
3.2.46
3.2.47
3.2.48
ADM6926
Port Configuration Registers (Index: 2h ~ 1bh).................................... 3-21
Miscellaneous Configuration (Index: 1ch) ............................................ 3-23
VLAN(TOS) Priority Map (Index: 1dh) ................................................. 3-23
Forwarding Group Outbound Port Map Low ....................................... 3-24
Forwarding Group Outbound Port Map High ...................................... 3-25
P0 VID and PVID Shift (Index: 5eh) ..................................................... 3-25
P1~P25 VID Configuration ................................................................... 3-26
P0, P1, P2, P3 Bandwidth Control Register (Index: 78h)..................... 3-26
P4, P5, P6, P7 Bandwidth Control Register (Index: 79h)..................... 3-27
P8, P9, P10, P11 Bandwidth Control Register (Index: 7ah)................. 3-27
P12, P13, P14, P15 Bandwidth Control Register (Index: 7bh)............. 3-28
P16, P17, P18, P19 Bandwidth Control Register (Index: 7ch) ............. 3-28
P20, P21, P22, P23 Bandwidth Control Register (Index: 7dh)............. 3-29
P24, P25 Bandwidth Control Register (Index: 7eh).............................. 3-29
Bandwidth Control Enable Register Low (Index: 7fh) .......................... 3-30
Bandwidth Control Enable Register High (Index: 80h) ........................ 3-30
Reserved Registers (Index: 81h~8ah) .................................................... 3-30
Customized PHY Control Group 0 (Index: 8bh).................................... 3-31
Customized PHY Control Group 1 (Index: 8ch).................................... 3-31
Customized PHY Control Group 2 (Index: 8dh).................................... 3-32
Customized PHY Control Group 3 (Index: 8eh).................................... 3-32
Group 0 PHY Customized DATA 0 (Index: 8fh).................................... 3-32
Group 0 PHY Customized DATA 1 (Index: 90h) ................................... 3-32
Group 1 PHY Customized DATA 0 (Index: 91h) ................................... 3-33
Group 1 PHY Customized DATA 1 (Index: 92h) ................................... 3-33
Group 2 PHY Customized DATA 0 (Index: 93h) ................................... 3-33
Group 2 PHY Customized DATA 1 (Index: 94h) ................................... 3-33
Group 3 PHY Customized DATA 0 (Index: 95h) ................................... 3-33
Group 3 PHY Customized DATA 1 (Index: 96h) ................................... 3-33
PHY Customized Enable Register (Index: 97h)..................................... 3-33
PPPOE Control Register0 (Index: 98h) ................................................ 3-34
PPPOE Control Register 1 (Index: 99h) ............................................... 3-34
PHY Control Register 0 (Index: 9ah) .................................................... 3-35
PHY Control Register 1 (Index: 9bh) .................................................... 3-35
Disable MDIO Active Register 0 (Index: 9ch)....................................... 3-36
Disable MDIO Active Register 1 (Index: 9dh) ...................................... 3-36
Port Disable Register 0 (Index: 9eh) ..................................................... 3-37
Port Disable Register 1 (Index: 9fh)...................................................... 3-37
IGMP Snooping Control Register 0 (Index: a0h).................................. 3-37
IGMP Snooping Control Register 1 (Index: a1h).................................. 3-38
CPU Control Register (Index: a2h)....................................................... 3-38
Special MAC Forward Control Register 0 (Index: a3h) ....................... 3-39
Special MAC Forward Control Register 2 (Index: a4h) ....................... 3-40
Special MAC Forward Control Register 2 (Index: a5h) ....................... 3-40
Trunking Enable Register 0 (Index: a6h) .............................................. 3-41
Trunking Enable Register 1 (Index: a7h) .............................................. 3-41
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ADMtek Inc.
V1.0
3.3
Switch Register Map...................................................................................... 3-42
3.3.1
Version ID (Offset: 0h) .......................................................................... 3-42
3.3.2
Link Status (Offset: 1h) .......................................................................... 3-42
3.3.3
Speed Status (Offset: 2h)........................................................................ 3-43
3.3.4
Duplex Status (Offset: 3h)...................................................................... 3-44
3.3.5
Flow Control Status (Offset: 4h)............................................................ 3-44
3.3.6
Address Table Control and Status Register ........................................... 3-45
3.3.7
PHY Control Register (Offset: bh)......................................................... 3-51
3.3.8
Hardware Status (Offset: dh)................................................................. 3-51
3.3.9
Receive Packet Count Overflow (Offset: eh) ......................................... 3-52
3.3.10
Receive Packet Length Count Overflow (Offset: fh).............................. 3-53
3.3.11
Transmit Packet Count Overflow (Offset: 10h) ..................................... 3-53
3.3.12
Transmit Packet Length Count Overflow (Offset: 11h)......................... 3-54
3.3.13
Error Count Overflow (Offset: 12h) ...................................................... 3-54
3.3.14
Collision Count Overflow (Offset: 13h)................................................. 3-55
3.3.15
Renew Counter Register (Offset: 14h)................................................... 3-56
3.3.16
Read Counter Control & Status Register .............................................. 3-57
3.3.17
Reload MDIO Register (Offset: 17h)..................................................... 3-57
3.3.18
Spanning Tree Port State 0 (Offset: 18h) .............................................. 3-58
3.3.19
Spanning Tree Port State 1 (Offset: 19h) .............................................. 3-58
3.3.20
Source Port Register (Offset: 1ah) ........................................................ 3-59
3.3.21
Transmit Port Register (Offset: 1bh) ..................................................... 3-59
3.3.22
Counter Register: Offset Hex. 0100h ~ 019b......................................... 3-59
Chapter 4 Electrical Specification................................................................................ 4-1
4.1
DC Characterization......................................................................................... 4-1
4.1.1
Absolute Maximum Rating....................................................................... 4-1
4.1.2
Recommended Operating Conditions ...................................................... 4-1
4.1.3
DC Electrical Characteristics for 3.3V Operation .................................. 4-1
4.2
AC Characterization......................................................................................... 4-2
4.2.1
XI/OSCI (Crystal/Oscillator) Timing....................................................... 4-2
4.2.1
Power On Reset........................................................................................ 4-2
4.2.2
EEPROM Interface Timing...................................................................... 4-3
4.2.3
10Base-TX MII Output Timing ................................................................ 4-3
4.2.4
10Base-TX MII Input Timing ................................................................... 4-4
4.2.5
100Base-TX MII Output Timing .............................................................. 4-5
4.2.6
100Base-TX MII Input Timing ................................................................. 4-5
4.2.7
Reduced MII Timing ................................................................................ 4-6
4.2.8
SS_SMII Transmit Timing........................................................................ 4-7
4.2.9
SS_SMII Receive Timing.......................................................................... 4-7
4.2.10
Serial Management Interface (MDC/MDIO) Timing .............................. 4-8
Chapter 5 Packaging...................................................................................................... 5-1
ADM6926
iii
ADMtek Inc.
V1.0
List of Figures
Figure 1-1 ADM6926 Block Diagram............................................................................. 1-2
Figure 2-1 ADM6926 Pin Diagram ................................................................................. 2-1
Figure 3-1 The Search Pointer ....................................................................................... 3-48
Figure 3-2 Address Table Mapping to Output Port MAP.............................................. 3-50
Figure 4-1 Crystal/Oscillator Timing............................................................................... 4-2
Figure 4-2 Power on reset timing..................................................................................... 4-2
Figure 4-3 EEPROM Interface Timing............................................................................ 4-3
Figure 4-4 10Base-TX MII Output Timing ..................................................................... 4-3
Figure 4-5 10Base-TX MII Input Timing........................................................................ 4-4
Figure 4-6 100Base-TX MII Output Timing ................................................................... 4-5
Figure 4-7 100Base-TX MII Input Timing...................................................................... 4-5
Figure 4-8 Reduced MII Timing (1 of 2)......................................................................... 4-6
Figure 4-9 Reduced MII Timing (2 of 2)......................................................................... 4-6
Figure 4-10 SS_SMII Transmit Timing........................................................................... 4-7
Figure 4-11 SS_SMII Receive Timing ............................................................................ 4-7
Figure 4-12 Serial Management Interface (MDC/MDIO) Timing .................................. 4-8
List of Table
Table 4-4-1 Electrical Absolute Maximum Rating.......................................................... 4-1
Table 4-4-2 Recommended Operating Conditions .......................................................... 4-1
Table 4-4-3 DC Electrical Characteristics for 3.3V Operation........................................ 4-1
Table 4-4 Crystal/Oscillator Timing................................................................................ 4-2
Table 4-5 Power on reset timing...................................................................................... 4-3
Table 4-6 EEPROM Interface Timing............................................................................. 4-3
Table 4-7 10Base-TX MII Output Timing....................................................................... 4-4
Table 4-8 10Base-TX MII Input Timing ......................................................................... 4-4
Table 4-9 100Base-TX MII Output Timing..................................................................... 4-5
Table 4-10 100Base-TX MII Input Timing ..................................................................... 4-6
Table 4-11 Reduced MII Timing ..................................................................................... 4-6
Table 4-12 SS_SMII Transmit Timing ............................................................................ 4-7
Table 4-13 SS_SMII Receive Timing.............................................................................. 4-8
Table 4-14 Serial Management Interface (MDC/MDIO) Timing ................................... 4-8
ADM6926
iv
ADM6926
Product Review
Chapter 1 Product Overview
1.1
Overview
The ADM6926 is a high performance/low cost, twenty six-port 10/100 Mbps Ethernet
Switch Controller with all ports supporting 10/100 Mbps full duplex switch function.
The ADM6926 is intended for applications to standalone-bridge for the low cost etherswitch market. ADM6926 can be programmed trunking port active. The trunking port
can be connected to server or stacking two switch boxes to enhance the performance.
The ADM6926 also supports back-pressure in half duplex mode and 802.3x flow control
in full duplex mode. When back-pressure is enabled, and there is no receive buffer
available for the incoming packet, the ADM6926 will force a JAM pattern on the
receiving port in half duplex mode and transmit the 802.3x packet back to receiving end
in full duplex mode.
An intelligent address recognition algorithm makes ADM6926 to recognize up to 4096
different MAC addresses and enables filtering and forwarding at full wire speed.
The ADM6926 has embedded SRAM for the proprietary buffer management. The SRAM
is used to store the incoming/outgoing packets. These buffers provide elastic storage for
transferring data between low-speed and high-speed segments and buffers are efficiently
allocated to improve the efficiency.
1.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ADMtek Inc.
Support twenty four 10/100M auto-detect Half/Full duplex switch ports with SS-SMII
interface and two 10/100M Half/Full duplex port with RMII/MII interface
Supports up to 4096 MAC addresses table (4-way hashing)
Support two queue for QOS (1:2 or 1:4 or 1:8 or 1:16)
Support Port-base, 802.1p and IP TOS priority
Supports store & forward architecture and Performs forwarding and filtering at nonblocking full wire speed
Support buffer allocation with 256 bytes each
Supports aging function and 802.3x flow control for full duplex and back-pressure
function for half duplex operation in case buffer is full
Support packet length up to 1536 bytes
Support Congestion Flow Control
Broadcast storm filter and Alert LED
Port-base VLAN and adjustable VLAN to support up to 32 VLAN group
serial CPU interface for counter and port status output
CPU can see-through to access PHY
flexible port trunking on fault tolerance and load balance
per port 32bits smart counter for Rx/Tx byte/packet count, error count and collision
count
1-1
ADM6926
Product Review
•
•
•
•
•
1.3
rate-limit control (64K/128K/256K/512K/1M/4M/10M/20M)
per port auto learning enable/disable and if disable, forward non-learned packet to
CPU
MAC address table accessible (in each entry, reserve one bit for CPU to
enable/disable aging out)
forward special multicast, BPDU, GMRP, GVRP and IGMP packets to CPU port
128 pin QFP package with 3.3V/1.8V power supply
Block Diagram
Embedded Memory
Memory
BIST
Switching Fabric
EEPROM
Control
10/100M
10/100M
MAC
MAC
...
10/100M
10/100M
Clock/
LED
Interface
93C66
Interface
MII/RMII
Interface
10/100M
MAC
MAC
MAC
CLOCK
GENERATOR
Interface Convertor
PHY Control
MDC/
MDIO
BIAS
SS-SMII
Interface
Figure 1-1 ADM6926 Block Diagram
ADMtek Inc.
1-2
ADM6926
1.4
Product Review
Abbreviations
BPDU
CRC
CRSDV
DA
DUPCOL
EDI
EDO
EECS
EESK
ESD
FCS
FET
GARP
GMRP
GVRP
IGMP
IPG
MAC
MDC
MDIO
MII
PHY
PLL
PPPoE
PVID
QFP
QOS
RMII
SA
SS-SMII
TA
TOS
TTL
UNIQUE
VID
VIH
VIL
VLAN
ADMtek Inc.
Bridge Protocol Data Unit
Cyclic Redundancy Check
Carrier Sense and Data Valid
Destination Address
Duplex and Collision
EEPROM Data Input
EEPROM Data Output
EEPROM Chip Select
EEPROM Serial Clock
End of Stream Delimiter
Frame Check Sequence
Field Effect Transistor
Generic Attribute Registration Protocol
GARP Multicast Registration Protocol
GARP VLAN Registration Protocol
Internet Group Management Protocol
Inter-Packet Gap
Media Access Controller
Management Data Clock
Management Data Input/Output
Media Independent Interface
Physical Layer
Phase Lock Loop
Point to Point Protocol over Ethernet
Port VLAN ID
Quad Flat Pack
Quality of Service
Reduced Media Independent Interface
Source Address
Source Synchronous Serial MII
Turn Around
Type of Service
Transistor Transistor Logic
Universal Queue management
VLAN ID
Voltage Input High
Voltage Input Low
Virtual LAN
1-3
ADM6926
Product Review
1.5
Conventions
1.5.1
Data Lengths
qword
dword
word
byte
nibble
1.5.2
1.5.3
64-bits
32-bits
16-bits
8 bits
4 bits
Register Type Descriptions
Register Type
RO
R/W
SC
LL
LH
COR
Description
Read Only
Read and Write capable
Self-clearing
Latching low, unlatch on read
Latching high, unlatch on read
Clear On Read
Pin Type Descriptions
Pin Type
I:
O:
I/O:
OD:
SCHE:
PU:
PD:
Description
Input
Output
Bi-directional
Open drain
Schmitt Trigger
Pull Up
Pull Down
ADMtek Inc.
1-4
ADM6926
Interface Description
Chapter 2 Interface Description
2.1 Pin Diagram – ADM6926 (SS-SMII Interface)
65
66
67
68
69
70
71
SRXD2[7]
VCCIK
GNDIK
M0CRS
M0COL
M0TXD[3]
M0TXD[2]
M0TXD[1]
M0TXD[0]
M0TXEN
ALERT
STXD2[7]
STXD0[0]
SRXD2[6]
STXD2[6]
EECS
SRXD0[0]
SRXD2[5]
STXD2[5]
RESETL
STXD0[1]
SRXD0[1]
STXD0[2]
SRXD2[4]
CLK_RX2
STXD2[4]
VCC3O
GNDO
SRXD0[2]
CLK_TX2
SRXD2[3]
SYNC_RX2
SYNC_TX0
STXD0[3]
SYNC_RX0
GNDO
ADM6926
SRXD0[3]
VCC3O
GNDIK
CLK_TX0
STXD0[4]
VCCIK
STXD2[3]
SYNC_TX2
CLK_RX0
SRXD0[4]
VCCIK
SRXD2[2]
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
STXD1[6]
SRXD1[6]
39
36
37
38
STXD1[5]
VCCIK
GNDIK
SRXD1[5]
32
33
34
35
28
29
30
31
25
26
27
21
22
23
24
20
18
19
15
16
17
13
14
11
12
9
10
6
7
8
2
3
4
5
1
GNDO
STXD1[4]
CLK_RX1
SRXD1[4]
STXD1[7]
SRXD1[3]
CLK_TX1
VCC3O
VCC3O
XI
XO
TEST1
SYNC_RX1
STXD2[0]
SRXD1[7]
STXD1[3]
MDC
MDIO
TEST2
SRXD2[0]
SRXD0[6]
STXD0[7]
CONTROL
VCCPLL
GNDPLL
SYNC_TX1
STXD0[6]
VCCRG
GNDRG
VREF
SRXD2[1]
STXD2[1]
CKO25M
SRXD1[1]
STXD1[2]
SRXD1[2]
STXD2[2]
STXD0[5]
SRXD0[5]
STXD1[0]
SRXD1[0]
CKO50M
STXD1[1]
GNDIK
GNDO
SRXD0[7]
127
128
72
73
74
75
125
126
M0TXCLK
M0RXCLK
M0RXDV
VCC3O
124
76
77
78
122
123
GNDO
M0RXD[0]
M0RXD[1]
M0RXD[2]
121
79
80
81
82
119
120
83
118
M0RXD[3]
M1CRS
M1COL
116
117
84
85
115
M1TXD[3]
M1TXD[2]
M1TXD[1]
M1TXD[0]
113
114
86
87
88
89
112
VCCIK
GNDIK
M1TXEN
M1TXCLK
111
90
91
92
109
110
M1RXCLK
M1RXDV
M1RXD[0]
M1RXD[1]
108
93
94
95
96
106
107
M1RXD[2]
M1RXD[3]
EESK
EDI
EDO
105
97
98
99
100
101
102
103
104
Figure 2-1 ADM6926 Pin Diagram
ADMtek Inc.
2-1
ADM6926
2.2
Interface Description
Pin Description
ADM6926 pins are categorized into one of the following groups:
•
Section 2.2.1 SS-SMII Networking Interface, 60 pins
•
Section 2.2.2 MII/RMII Interface, 28pins
•
•
2.2.1
Section 2.2.3 Power/Ground
Section 2.2.4 Miscellaneous pins, 16 pins
SS-SMII Networking Interface, 60 pins
Name
Type
SRXD0[0:7] I,
TTL
SYNC_RX0 I,
TTL
Pin #
Description
106,108,
112,116,
120,124,
126,2
115
Port 0 to Port 7 SS-SMII Receive Data bit. The receive data
should be synchronous to the rising edge of CLK_RX0.
CLK_RX0 I,
119
TTL
STXD0[0:7] O, TTL 104,107,
8mA
109,114,
118,123,
125,127
SYNC_TX0 O, TTL 113
8mA
CLK_TX0
O, TTL
16mA
SRXD1[0:7] I,
TTL
SYNC_RX1 I,
TTL
CLK_RX1 I,
TTL
STXD1[0:7] O, TTL
8mA
SYNC_TX1 O, TTL
8mA
CLK_TX1
ADMtek Inc.
O, TTL
Port 0 to Port 7 SS-SMII Synchronous signal. This signal is
synchronous to the rising edge of CLK_RX0. Active high
indicates the byte boundary.
Reference Receive Clock for Port 0 to Port 7. This signal is
125MHz input for SS-SMII interface.
Port 0 to Port 7 SS-SMII Transmit Data bit. The transmit
data is synchronous to the rising edge of CLK_TX0.
Port 0 to Port 7 SS-SMII Synchronous signal. This signal is
synchronous to the rising edge of CLK_TX0. Active high
indicates the byte boundary.
117
Reference Transmit Clock for Port 0 to Port 7. This signal
is 125MHz output for SS-SMII interface.
4,8,10,26, Port 8 to Port 15 SS-SMII Receive Data bit. The receive
32,36,38, data should be synchronous to the rising edge of CLK_RX1.
40
25
Port 8 to Port 15 SS-SMII Synchronous signal. This signal
is synchronous to the rising edge of CLK_RX1. Active high
indicates the byte boundary.
31
Reference Receive Clock for Port 8 to Port 15. This signal
is 125MHz input for SS-SMII interface.
3,6,9,18, Port 8 to Port 15 SS-SMII Transmit Data bit. The transmit
30,33,37, data is synchronous to the rising edge of CLK_TX1.
39
17
Port 8 to Port 15 SS-SMII Synchronous signal. This signal
is synchronous to the rising edge of CLK_TX1. Active high
indicates the byte boundary.
27
Reference Transmit Clock for Port 8 to Port 15. This
2-2
ADM6926
Interface Description
Name
Type
Pin #
Description
16mA
SRXD2[0:7] I,
TTL
SYNC_RX2
CLK_RX2
STXD2[0:7]
SYNC_TX2
CLK_TX2
2.2.2
signal is 125MHz output for SS-SMII interface.
42,44,46, Port 16 to Port 23 SS-SMII Receive Data bit. The receive
54,58,61, data should be synchronous to the rising edge of CLK_RX2.
63,65
I,
53
Port 16 to Port 23 SS-SMII Synchronous signal. This
TTL
signal is synchronous to the rising edge of CLK_RX2. Active
high indicates the byte boundary.
I,
57
Reference Receive Clock for Port 16 to Port 23. This signal
TTL
is 125MHz input for SS-SMII interface.
O, TTL 41,43,45, Port 16 to Port 23 SS-SMII Transmit Data bit. The
8mA
48,56,60, transmit data is synchronous to the rising edge of CLK_TX2.
62,64
O, TTL 47
Port 16 to Port 23 SS-SMII Synchronous signal. This
8mA
signal is synchronous to the rising edge of CLK_TX2. Active
high indicates the byte boundary.
O, TTL 55
Reference Transmit Clock for Port 16 to Port 23. This
16mA
signal is 125MHz output for SS-SMII interface.
MII/RMII Interface, 28pins
Name
Type
Pin #
Description
M0CRS
I,
TTL
PD
I,
TTL
PD
I/O,
TTL
8mA
PD
68
MII Port0 Carrier Sense
This pin is internal pull_down.
69
MII Port0 Collision input
This pin is internal pull_down.
M0COL
M0TXD
[0:3]
M0TXEN
I/O,
TTL
8mA
PD
M0TXCLK I,
TTL
PD
M0RXCLK I,
TTL
PD
ADMtek Inc.
73,72,71, MII Port 0 Transmit Data Bit[0:3].
70
Synchronous to the rising edge of M0TXCLK.
RMII Port 0 Transmit Data Bit[0:1].
Synchronous to the rising edge of M0RXCLK.
RMIIMODE[1] : Value on M0TXD[3] will be latched at the
rising edge of RESETL to configure port 25 as RMII mode.
RMIIMODE[0] : Value on M0TXD[2] will be latched at the
rising edge of RESETL to configure port 24 as RMII mode.
74
MII/RMII Port 0 Transmit Enable.
AGDIS. Value on this pin will be latched at the rising edge
of RESETL to set aging disable.
75
MII Port 0 Transmit clock Input.
This pin is 25MHz input for MII interface.
76
MII/RMII Port 0 Receive Clock Input.
This pin is 25MHz input for MII interface and 50MHz
REFCLK input for RMII interface.
2-3
ADM6926
Interface Description
Name
Type
Pin #
M0RXDV
I,
TTL
PD
I,
TTL
PD
77
M0RXD
[0:3]
M1CRS
M1COL
I,
TTL
PD
I,
TTL
PD
I/O,
TTL
8mA
Description
MII Port 0 Receive Data Valid.
RMII Port 0 Carrier Sense/Receive Data Valid.
This pin is internal pull_down.
80,81,82, MII Port 0 Receive Data Bit[0:3].
83
RMII Port 0 Receive Data Bit[0:1].
If in RMII mode, M0RXD[3] used for ext_dup_enable and
M0RXD[2] used for ext_dup_full. Internal pull_down. See
Sec3.1.27 for details.
84
MII Port 1 Carrier Sense
This pin is internal pull_down.
85
MII Port 1 Collision input
This pin is internal pull_down.
89,88,87, MII Port 1Transmit Data Bit[0:3].
86
Synchronous to the rising edge of M1TXCLK.
RMII Port 1Transmit Data Bit[0:1].
Synchronous to the rising edge of M1RXCLK.
BPEN. Value on M1TXD[3] will be latched at the rising
edge of RESETL to set Back_pressure enable. Internal
pull_up.
FCEN. Value on M1TXD[2] will be latched at the rising
edge of RESETL to set flow control enable. Internal pull_up.
TNKEN. Value on M1TXD[1] will be latched at the rising
edge of RESETL to set trunking enable. Internal pull_up.
IPGLVING. Value on M1TXD[0] will be latched at the
rising edge of RESETL to set shorter IPG. Internal
pull_down.
M1TXEN O, TTL 92
MII Port 1 Transmit Enable.
ANEN. Value on this pin will be latched at the rising edge of
8mA
RESETL to set auto_negotiation enable. Internal pull_up.
PU
93
MII Port1 Transmit clock Input. This signal is 25MHz
M1TXCLK I,
input for MII interface.
TTL
PD
94
MII1 Receive Clock Input. This signal is 25MHz input for
M1RXCLK I,
MII interface and 50MHz REFCLK input for RMII interface.
TTL
PD
M1RXDV I,
95
MII/RMII Port 1 Receive Data Valid.
TTL
This pin is internal pull_down.
PD
M1RXD
I,
96,97,98, MII Port 1 Receive Data Bit[0:3].
[0:3]
TTL
99
RMII Port 1 Receive Data Bit[0:1].
If in RMII mode, M1RXD[3] used for ext_dup_enable and
PD
M1RXD[2] used for ext_dup_full. Internal pull_down. See
Sec3.1.27 for details.
M1TXD
[0:3]
ADMtek Inc.
2-4
ADM6926
Interface Description
2.2.3 Power/Ground
Pin Name
Pin Type Pin #
Pin Description
GNDRG
Analog
Ground
Analog
Power
Analog
Ground
Analog
Power
Digital
Ground
Digital
Power
Digital
Ground
Digital
Power
12
Ground for Regulator
11
3.3V Power supply for Regulator
16
Ground for PLL
15
1.8V Power supply PLL
35,50,67,
91,122
34,49,66,
90,121
1,29,52,
79,111
28,51,78,
110,128
Ground for Core Logic
VCCRG
GNDPLL
VCCPLL
GNDIK
VCCIK
GNDO
VCC3O
2.2.4
1.8V Power supply for Core Logic
Ground for I/O PAD
3.3V Power supply for I/O PAD
Miscellaneous pins, 16 pins
Pin Name
Pin Type Pin #
O, TTL 7
16mA
CK50MO/ O, TTL 5
COL_LED_ 16mA
10M
22
XI
I,
Analog
Pin Description
CK25MO
25MHz clock Output. This pin will drive out 25Mhz.
XO
50MHz clock Output. This pin will drive out 50MHz.
COL_LED_10M. This pin shows collision LED for 10M
domain (see EEPROM Register 1ch, Bit[9])
Crystal or OSC 50MHz Input. This is the clock source of
PLL. The PLL will generate 125Mhz for SS-SMII and
50MHz for RMII and 25Mhz for MII.
Crystal 50Mhz Output.
O,
23
Analog
RESETL
I, TTL 59
SCHE
ALERT/
O, TTL 103
COL_LED_ 8mA
100M
TEST[2:1]
MDC
ADMtek Inc.
21,24
I,
TTL
PD
O, TTL 19
16mA
Reset Signal. An active low signal with minimum 100ms
duration is required.
Alert LED Display. This pin will show the status of poweron-diagnostic and broadcast traffic.
COL_LED_100M. This pin shows collision LED for 100M
domain (see EEPROM Register 1ch, Bit[9])
Industrial Test pins.
These pins are internal pull_down.
Management Data Clock.
This pin output 2.2MHz clock to drive PHY and access
corresponding speed and duplex and link status through
2-5
ADM6926
Pin Name
Interface Description
Pin Type Pin #
Pin Description
MDIO.
MDIO
I/O,
TTL
8mA
PU
EESK
I/O,
TTL
4mA
PU
EECS
I/O,
TTL
4mA
PD
EDI
I/O,
TTL
4mA
PU
EDO
I,
TTL
PU
CONTROL O,
Analog
VREF
ADMtek Inc.
20
Management Data.
This pin is in-out to PHY. When RESETL is low, this pin will
be tri-state. This pin is internal pull_up.
100
EEPROM Serial Clock.
This pin is clock source for EEPROM. When RESETL is low,
it will be tri-state. This pin is internal pull-up.
105
EEPROM Chip Select. This pin is chip enable for EEPROM.
When RESETL is low, it will be tri-state. This pin is internal
pull-down.
101
EEPROM Serial Data Input.
This pin is output for serial data transfer. When RESETL is
low, it will be tri-state. This pin is internal pull-up.
102
EEPROM Serial Data Output.
This pin is input for serial data transfer. This pin is internal
pull-up.
FET Control Signal.
The pin is used to control FET for 3.3V to 1.8V regulator.
14
I,
13
Analog
Regulator Control Input Signal.
2-6
ADM6926
Function Description
Chapter 3 Function Description
3.1
Introduction
The ADM6926 uses a “store & forward” switching approach for the following reasons:
1) Store & forward switches allow switching between different speed media (e.g.
10BaseX and 100BaseX). Such switches require the large elastic buffers, especially
bridging between a server on a 100Mbps network and clients on a 10Mbps segment.
2) Store & forward switches improve overall network performance by acting as a
“network cache”
3) Store & forward switches prevent the forwarding of corrupted packets by the frame
check sequence (FCS) before forwarding to the destination port.
3.1.1
Basic Operation
The ADM6926 receives incoming packets from one of its ports, uses the source address
(SA) and VID to update the address table, and then forwards the packet to the output
ports determined by the destination address (DA) and VID.
If the DA and VID are not found in the address table, the ADM6926 treats the packet as a
broadcast packet and forwards the packet to the other ports within the same group.
The ADM6926 automatically learns the port number of attached network devices by
examining the SA and VID of all incoming packets. If the SA and VID are not found in
the address table, the device adds it to the table.
3.1.2
Address Learning
The ADM6926 provides two ways to create the entry in the address table: dynamic
learning and manual learning. A four-way hash algorithm is implemented to allow 4
different addresses to be stored at the same location. Up to 4k entries can be created and
all entries are stored in the internal SSRAM. Two parameters, SA and VID, are combined
to generate the 10-bit hash key to allow that the same addresses with different port
number can exist in the table at the same time.
1. Dynamic Learning
The ADM6926 searches for SA and VID of an incoming packet in the address table and
acts as follows:
If the SA+VID was not found in the address table (a new address), the ADM6926 waits
until the end of the packet (non-error packet) and updates the address table. If the
ADMtek Inc.
3-1
ADM6926
Function Description
SA+VID was found in the address table, then aging value of each corresponding entry
will be reset to 0.
Dynamic learning will be disabled in the following condition:
(1)
Security violation happened.
(2)
The packet is a PAUSE frame.
(3)
The first bit of SA is 1’b1.
(4)
The packet is an error packet (too long, too short or FCS error).
(5)
The CPU port leaning function is disabled or enabled but the CPU port instructs
the switch not to learn the packet.
(6)
The port is in the Disabled or Blocking-not-Listening state in the Spanning Tree
Protocol.
2. Manual Learning
The ADM6926 implements the manual learning through the CPU’s help. The CPU can
create or remove any entry in the address table. Each entry could be static or pointed to
the output port map table. “Static” means the entry will not be aged forever. It is useful in
the security function (forward unknown packets to the CPU port or discard) or monitor
function (forward monitored address to the specific port). Output port map table is also
helpful in the IGMP function (if the number of the output port is more than one) or the
users want to redirect the special packets with reserved DA.
3.1.3 Address Aging
The ADM6926 will periodically (300ms) remove the non-static address in the address
table. This could help to prevent a station leaves the network and occupies a table space
for a long time. Aging function can be disabled from the hardware pin.
ADMtek Inc.
3-2
ADM6926
3.1.4
Function Description
Address Recognition and Packet Forwarding
The ADM6926 forwards the incoming packets between bridge ports according to the DA
and VID as follows:
DA
DA+VID was found in the DA+VID was found in the DA+VID was not found in the
address table (entry not pointed address table (entry pointed to the address table
to the output port map table)
output port map table)
No Security Violation
Unicast Address
Forward packets to the port
Forward packets to the ports
determined by the address table.
Forward packets to the other
determined by the output port
The packet may be dropped
ports within the same forwarding
map table constrained by the
because of forwarding group
group.
forwarding group.
boundary violation.
Security Violation
Drop or forward to CPU
Drop or forward to CPU
Drop or forward to CPU
No Security Violation
Forward packets to the ports
Forwarding packets to the other
Forward packets to the other
determined by the output port
Broadcast Address ports
within
the
same
ports within the same forwarding
map table constrained by the
forwarding
group.
group.
(All 1’b1)
forwarding group.
Security Violation
Drop or forward to CPU
Drop or forward to CPU
Drop or forward to CPU
No Security Violation
Forward packets to the ports
Forwarding packets to the other
Forward packets to the other
determined by the output port
ports
within
the
same
ports within the same forwarding
(01-80-c2-00-00-xx,
map table constrained by the
forwarding
group.
group.
with the option to
forwarding group.
forward normally)
Security Violation
Reserved Address
Same as the above
Same as the above
Same as the above
No Security Violation
Reserved Address
Forward the packet to the CPU Forward the packet to the CPU Forward the packet to the CPU
(01-80-c2-00-00-xx, port.
port.
port.
with the option to
Security Violation
forward to CPU)
Same as the above
Same as the above
Same as the above
No Security Violation
Reserved Address
(01-80-c2-00-00-xx, Discard the packet.
with the option to
discard)
Same as the above
Discard the packet.
Discard the packet.
Security Violation
Same as the above
Same as the above
No Security Violation
IGMP Packet
(Port Enable IGMP)
Forward the packet to the CPU Forward the packet to the CPU Forward the packet to the CPU
port.
port.
port.
Security Violation
Drop or forward to CPU
ADMtek Inc.
Drop or forward to CPU
Drop or forward to CPU
3-3
ADM6926
Function Description
DA
DA+VID was found in the DA+VID was found in the DA+VID was not found in the
address table (entry not pointed address table (entry pointed to the address table
to the output port map table)
output port map table)
No Security Violation
Forward packets to the port
Forward packets to the ports
determined by the address table.
determined by the output port Forward packets according the
The packet may be dropped
IGMP Packet
map table constrained by the Multicast Option.
(Port Disable IGMP) because of forwarding group forwarding group.
boundary violation.
Security Violation
Drop or forward to CPU
Drop or forward to CPU
Drop or forward to CPU
No Security Violation
Others
Forward packets to the port
Forward packets to the ports
determined by the address table.
determined by the output port Forward packets according the
The packet may be dropped
map table constrained by the Multicast Option.
because of forwarding group
forwarding group.
boundary violation.
Security Violation
Drop or forward to CPU
3.1.5
Drop or forward to CPU
Drop or forward to CPU
Trunking Port Forwarding
ADM6926 supports the trunking forwarding and any port could be assigned to the
trunking port. When one or more of the members link fail, the ADM6926 will
automatically change the transmit path from the failed link port to normal link port. Port
based load balancing is implemented to distribute the loading.
3.1.6
Illegal Frames
The ADM6926 will discard all illegal frames such as runt packet (less than 64 bytes),
oversize packet (greater than 1518 or 1522 bytes) or bad CRC.
3.1.7
Back off Algorithm
The ADM6926 implements the truncated exponential back off algorithm compliant to the
802.3 standard. ADM6926 will restart the back off algorithm by choosing 0-9 collision
count. After 16 consecutive retransmit trials, the ADM6926 resets the collision counter.
3.1.8
Buffers and Queues
The ADM6926 incorporates 26 transmit queues and receive buffer area for the 26
Ethernet ports. The receive buffers as well as the transmit queues are located within the
ADM6926 along with the switch fabric. The buffers are divided into 640 blocks of 256
ADMtek Inc.
3-4
ADM6926
Function Description
bytes each. The queues of each port are managed according to each port’s read/write
pointer.
Input buffers and output queues are maintained through proprietary patent pending
UNIQUE (Universal Queue management) scheme.
3.1.9
Half Duplex Flow Control
Back-pressure is supported for half-duplex operation.
When the ADM6926 cannot allocate a receive buffer for an incoming packet (buffer full),
the device will transmit a jam pattern on the port, thus forcing a collision.
3.1.10 Full Duplex Flow Control
When full duplex port runs out of its receive buffer, a PAUSE command will be issued
by ADM6926 to notice the packet sender to pause transmission. This frame based flow
control is totally compliant to IEEE 802.3x. When flow control hardware pin is set to
high during power on reset and per port PAUSE is enabled, ADM6926 will output and
accept 802.3x flow control packet.
3.1.11 Inter-Packet Gap (IPG)
IPG is the idle time between any two successive packets from the same port. The value is
9.6us for 10Mbps ETHERNET and 960ns for 100Mbps fast Ethernet.
3.1.12 Port VLAN or Tag VLAN Support
Two VLAN settings are supported by the ADM6926: the port-based VALN or the tagbased VLAN. For the port-based VLAN the ADM6926 will use the port number as the
index to lookup the forwarding table. For the tag-based VLAN, the ADM6926 will use
the VID to lookup the forwarding table. Each port is assigned a Port VID as the Default
VID if tag-based VLAN is used. The ADM6926 will check TAG, remove TAG, insert
TAG, and re-calculate CRC if packet is changed:
ADMtek Inc.
3-5
ADM6926
Function Description
Packets received are untagged
(1)
Force no
tag
Output port
Bypass
Action
is tagged or
not
Don’t Care
(2)
No
No
Untag as the original.
Yes
No
Untag as the original
No
Yes
Add Tag.
Yes
Yes
Untag as the original
Packets received are tagged
Force no
tag
Output port
Bypass
Action
is tagged or
not
No
No
No
Yes
No
No
No
Yes
No
No
No
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
The Tag is removed.
Tag as the original. The priority in the TAG header is not checked and VID will not
change even if VID is 0 or 1.
Tag as the original. The priority in the TAG header is checked and if the VID is 0 or
1, it may change to PVID (see EEPROM register 1ch, Bit[3])
Tag as the original. The priority in the TAG header is checked and if the VID is 0 or
1, it may change to PVID (see EEPROM register 1ch, Bit[3])
Tag as the original. The priority in the TAG header is checked and if the VID is 0 or
1, it may change to PVID (see EEPROM register 1ch, Bit[3])
Tag as the original. The priority in the TAG header is not checked. The VID will not
change.
The Tag will be added and packet will be double tagged output. The VID will not
change.
Tag as the original. The priority in the TAG header is not checked. The VID will not
change.
3.1.13 Priority Control
The ADM6926 provides two priority queues on each output port. Five ways could be
used to assign a priority to a packet.
(1) The priority assigned to each receiving port.
(2) The priority field in the 802.1Q Tag Header.
(3) The IPv4 TOS field in the IPv4 Header.
(4) Priority assigned by the CPU.
(5) Management packet (high priority assigned).
ADMtek Inc.
3-6
ADM6926
Function Description
3.1.14 Alert LED Display
Two functions are displayed through the Alert LED.
1. Diagnostic mode after power on.
a) After reset or power up, LED keeps on at least 3 second, and processes internal
SSRAM self-test.
b) If test passes, the ADM6926 turns off LED and goes to the broadcast storm mode.
c)
If SSRAM test fails, the ADM6926 turns off LED, then keeps on.
2. Broadcast storm mode after SSRAM self-test. Packets with DA = 48’hffffffffffff
will be counted into the storm counter.
Two thresholds (rising and falling) are used to control the broadcast storm.
a) Time Scale: 50ms is used. The max packet number in 100BaseT is 7490. The max
packet number in 10BaseT is 749.
b) Port Rising Threshold.
Broadcast Storm
Threshold.
All 100TX
Not All 100TX
00
01
10
11
Disable
Disable
10%
1%
20%
2%
40%
4%
00
01
10
11
Disable
Disable
5%
0.5%
10%
1%
20%
2%
c) Port Falling Threshold
Broadcast Storm
Threshold.
All 100TX
Not All 100TX
3.1.15 Broadcast Storm Filter
If broadcast storming filter is enabled, the broadcast packets (DA = 48’hffff-ffff-ffff)
over the rising threshold within 50 ms will be discarded when the alert LED is turned on.
3.1.16 Collision LED Display
Two collision LEDs are supported. (see EEPROM Register 1ch, Bit[9])
1) 100M Collision LED. If collision happens in one of the ports configured 100M,
the 100M Collision LED will flash in rate of 2Hz.
2) 10M Collision LED. If collision happens in one of the ports configured 10M, the
10M Collision LED will flash in rate of 2Hz.
ADMtek Inc.
3-7
ADM6926
Function Description
3.1.17 Bandwidth Control
The ADM6926 allows the user to limit the bandwidth for each input or output port. 64k,
128K, 256k, 512K, 1M, 4M, 10M and 20M are supported.
3.1.18 Smart Discard
The ADM6926 supports a smart mechanism to discard packets early according to their
priority to prevent the resource blocked by the low priority. The discard ratio is as follows:
Discard Mode
Utilization
00
01
11
00
01
10
11
0%
0%
0%
0%
0%
25%
0%
25%
50%
0%
50%
75%
3.1.19 Security Support
4 level security schemes are supported by the ADM6926. All the security violation
address will not be automatically learned.
The violated packet could be forwarded to the CPU port for management or discarded.
When CPU is not present, ADM6926 also provides a simple way to lock the first address
to prevent illegal address access.
3.1.20 Smart Counter Support
Six counters per port are supported by the ADM6926.
1) Receive Packet Count.
2) Receive Packet Length Count.
3) Transmit Packet Count.
4) Transmit Packet Length Count.
5) The Error Count
6) The Collision Count.
3.1.21 Length 1536 Mode
The ADM6926 provides a function to enable the port to receive packets up to 1536 Byte.
3.1.22 PHY Management (MDC/MDIO Interface)
The ADM6926 uses the MDC/MDIO interface to set the PHY status. After the reset or
power up, the MDC/MDIO controller will delay about 130ms to wait for the PHY to
ready. The ADM6926 supports two ways to configure the PHY setting.
1) PHY master. The switch only reads the PHY status (speed, duplex, link, and
pause). This mode is useful when users want to configure PHY through the CPU
help. The ADM6926 supports an indirect way (a PHY Control Register) for CPU
to access PHYs.
2) PHY slave. The switch uses the EEPROM setting to control the PHY attached
(only speed, duplex, link, and pause are supported). After the port setting
changed, the ADM6926 will use the new setting to program the PHY again and
update the status. 8 commands are provided in this mode to allow the customer to
customize the PHY setting.
ADMtek Inc.
3-8
ADM6926
Function Description
Note:
The PHY address attached to port 0 is 5’h8, the PHY address attached to port 1 is 5’h9,..,
the PHY address attached to port 23 is 5’h1f, the PHY address attached to port 24 is 5’h7
and the PHY address attached to port 25 is 5’h8.
3.1.23 Forward Special Packets to the CPU Port
(IGMP and Spanning Tree Support)
ADM6926 will forward the special packets to the CPU port to provide the management
function.
1) DA is 01-80-C2-00-00-00 (BPDU)
2) DA is 01-80-C2-00-00-02 (Slow Protocol)
3) DA is 01-80-C2-00-00-03 (802.1x PAE)
4) DA is 01-80-C2-00-00-04 ~ 01-80-C2-00-00-0f
5) DA is 01-80-C2-00-00-20 (GMRP)
6) DA is 01-80-C2-00-00-21 (GVRP)
7) DA is 01-80-C2-00-00-22 (GVRP)
8) DA is 01-00-5E-xx-xx-xx and protocol field is 2 for IPV4 (IGMP)
ADMtek Inc.
3-9
ADM6926
Function Description
3.1.24 Special TAG
The ADM6926 has an ability to insert 4Byte special TAG when packets transmitted to
the CPU port or to remove 8Byte additional TAG in the packets when packets are
received from the CPU port. The configuration is shown in the CPU Configuration
Register. This special function allows the CPU to know the source port which will be
used in the IGMP Snooping , Spanning Tree or the Security function. The CPU also
could insert additional 8-byte Tag to instruct the switch to handle the packets. The
packets format is as follows:
Transmit End
7 OCTETS
PREAMBLE
1 OCTET
SFD
6 OCTETS
DESTINATION ADDRESS
6 OCTETS
SOURCE ADDRESS
4 OCTETS
Special TAG
2 OCTETS
LENGTH/TYPE
8
7
6
5
4
3
2
1
1st Byte
Label
Reserve = 0
2nd Byte
Source Port[4:0]
TAG[15:8]
3rd Byte
TAG[7:0]
4th Byte
Learn Select
46--1500
OCTETS
MAC CLIENT DATA
Learn Valid
PAD
Queue Select
4 OCTETS
FRAME CHECK SEQUENCE
Queue Valid
Output Port Map Valid
Receive End
8
7 OCTETS
PREAMBLE
1 OCTET
SFD
6 OCTETS
DESTINATION ADDRESS
6 OCTETS
SOURCE ADDRESS
8 OCTETS
Special TAG
2 OCTETS
LENGTH/TYPE
7
6
5
4
3
2
1st Byte
Label
2nd Byte
Output Port Map[26:20]
8
7
6
5Port 4Map[19:12]
3
2
Output
Output Port Map[11:4]
Output Port Map[3:0]
46--1500
OCTETS
4 OCTETS
ADMtek Inc.
1
1
3rd Byte
4th Byte
5th Byte
Reserved
6th Byte
Reserved
7th Byte
Reserved
8th Byte
MAC CLIENT DATA
PAD
FRAME CHECK SEQUENCE
3-10
ADM6926
Function Description
Special TAG Fields
Configurati Description
Default
on
8’b0
Label
The field is used for CPU to decide if the special TAG is valid. If the
switch finds the Label doesn’t equal to the value assigned by the
EEPROM, it must receive as the normal mode. This case exists when user
wants the switch to insert 4 byte special tag even for Pause packets.
1’b0
Output Port 1 = The switch is instructed to override the switch operation. It will
Map Valid forward the packets
following the Output Port Map field.
0 = The switch will treat the packet as the normal mode.
27’h0
Bit[26] = 1, the CPU wants to forward packets to more than 2 ports.
Bit[26] = 0, the CPU wants to forward packets to only one port.
Bit[x], x = 0 ~25, the CPU wants to forward packets to Port x.
Example: 1. The CPU wants to forward packet to P1 and P2 then the
Output Port Output Port Map is as follows:
Map[26:0] Bit
26 25~24 23~16
15~8
7~0
Map
1
00
0000_0000 0000_0000 0000_0110
2. The CPU wants to forward packets to P5 only.
Bit
26 25~24 23~16
15~8
7~0
Map
0
00
0000_0000 0000_0000 0010_0000
This value is the same as the TAG header if the CPU port is configured to a
TAG[25:0]
16’h0
TAG port.
Source
This field indicates the source port the packet comes from.
5’h0
Port[4:0]
1 = The switch is instructed to override the switch operation. It will
forward the packets
Queue
1’b0
using the Queue Select Field.
Valid
0 = The switch will treat the packets as the normal mode.
Queue
1 = Mapped for High Queue
1’b0
Select
0 = Mapped for Low Queue
1 = The switch is instructed to override the switch operation. The CPU port
will use the
Learn Field to decide how to learn the packet.
1’b0
Learn Valid
0 = The switch will treat the packets as the normal mode. That is, the CPU
port will learn or disable learning according the Disable CPU Port Learning
Function configured in the CPU Control Register. .
Learn
1 = Learn the packet.
1’b0
Select
0 = Don’t learn the packet
ADMtek Inc.
3-11
ADM6926
Function Description
3.1.25 Port 24 and Port 25 Interface (Only SS-SMII package support)
Three interfaces in port 24 and port 25 are supported by the ADM6926: (1) MII Interface
(2) RMII Interface (3) Reserved MII Interface.
1. MII Interface Diagram
T X _CL K
M 0T X CL K
P o rt 2 4
(M II)
TX _C LK
M 1T X CL K
M 0TX E N
T X _EN
M 1TX E N
TX _E N
M 0T X D 0
T X D [0 ]
M 1T X D 0
T X D [0 ]
M 0T X D 1
T X D [1 ]
M 1T X D 1
T X D [1 ]
M 0T X D 2
T X D [2 ]
M 1T X D 2
T X D [2 ]
M 0T X D 3
T X D [3 ]
M 1T X D 3
T X D [3 ]
R X _C LK
M 0R X CL K
M 0R X D V
R X _D V
M 0R X D 0
M 0R X D 1
PH Y
P o rt 2 5
(M II)
R X _CL K
M 1R X CL K
M 1RX D V
R X _D V
R X D [0 ]
M 1R X D 0
R X D [0 ]
R X D [1 ]
M 1R X D 1
R X D [1 ]
M 0R X D 2
R X D [2 ]
M 1R X D 2
R X D [2 ]
M 0R X D 3
R X D [3 ]
M 1R X D 3
R X D [3 ]
M 0C RS
CRS
M 1C RS
CRS
M 0CO L
COL
M 1CO L
COL
PH Y
2. RMII Interface
50M H Z
M 0RX CLK
P o rt 2 4
(R M II)
50M H Z
M 1R X C LK
CLKREF
M 0TX EN
T X _E N
M 0TX D 0
T X D [0 ]
M 0TX D 1
T X D [1 ]
PH Y
P o rt 2 5
(R M II)
CLKREF
M 1T X EN
T X _E N
M 1T X D 0
T X D [0 ]
M 1T X D 1
T X D [1 ]
M 0RX D V
C R S_D V
M 1RX D V
C R S_D V
M 0R X D 0
R X D [0 ]
M 1RX D 0
R X D [0 ]
M 0R X D 1
R X D [1 ]
M 1RX D 1
R X D [1 ]
PH Y
3. Reversed MII Interface
M 0TXCLK
M 1TXCLK
RX_CLK
RX_DV
M 1TXEN
RX_DV
M 0TXD0
RXD[0]
M 1TXD0
RXD[0]
M 0TXD1
RXD[1]
M 1TXD1
RXD[1]
M 0TXD2
RXD[2]
M 1TXD2
RXD[2]
M 0TXD3
RXD[3]
M 1TXD3
RXD[3]
Port 24 M 0RXCLK
(Reversed M II)
M 0RXDV
ADMtek Inc.
RX_CLK
M 0TXEN
TX_CLK
TX_EN
CPU
(M II)
Port 25 M 1RXCLK
(Reversed M II)
M 1RXDV
TX_CLK
TX_EN
M 0RXD0
TXD[0]
M 1RXD0
TXD[0]
M 0RXD1
TXD[1]
M 1RXD1
TXD[1]
M 0RXD2
TXD[2]
M 1RXD2
TXD[2]
M 0RXD3
TXD[3]
M 1RXD3
TXD[3]
M 0CRS
CRS
M 1CRS
CRS
M 0COL
COL
M 1COL
COL
CPU
(M II)
3-12
ADM6926
Function Description
3.1.26 Hardware, EEPROM and SMI Interface for Configuration
Three ways are supported to configure the setting in the ADM6926: (1) Hardware Setting
(2) EERPROM Interface (3) SMI Interface. Users could use EEPROM and SMI
interfaces combined with the CPU port to provide proprietary functions. Four pins are
needed when using these two interfaces. See the following figure as a description.
EECS
EESK
AD3110
EDI
EDO
EEPROM(93c66)
CPU
1. Hardware Setting
The ADM6926 provides some hardware pins where values reside on during power on or
reset will be strapped for the default setting.
SS-SMII Pin
Name
M1TXD0
M1TXD1
M1TXD2
M1TXD3
M1TXEN
M0TXEN
M0TXD0
M0TXD2
ADMtek Inc.
RMII Pin Name
Description
IPG Average 92 bit time. Internally Pulled Down.
1 = Enable IPG Average 92.
0 = Disable IPG Average 92.
Trunk En. Internally Pulled Up.
M1TXD1
1 = Trunking Enable. Use EEPROM to configure the trunk member.
0 = Trunking Disable. The ADM6926 has no trunking function even if EEPROM sets.
Pause. Internally Pulled Up.
1 = The switch allows the Pause function. This function can be disabled by the
M1TXD2
EEPROM.
0 = The switch doesn’t allow the Pause function even if EEPROM set. The only way
to start the Pause function is through the CPU help.
Back-Pressure. Internally Pulled Up.
1 = The switch allows the Back-Pressure function. This function can be disabled by
M1TXD3
the EEPROM.
0 = The switch doesn’t allow the Back-Pressure function even if EEPROM set.
M1TXEN
Auto-Neg En. Internally Pulled Up.
1 = The switch allows the Auto-Negotiation function. This function can be disabled
by the EEPROM.
0 = The switch doesn’t allow Auto-Negotiation function even if EEPROM set. The
only way to start the Auto-Negotiation function is through the CPU help.
Aging Dis. Internally Pulled Down.
M0TXEN
0 = The switch will age the entry in the address table..
1 = The switch will not age the entry in the address table.
Port 24 Interface Configuration.
M0TXD0 M0TXD2 Interface
Don’t Support 0
0 Port 24 is configured to MII in SS-SMII package (internal value.
x
1 Port 24 is configured to RMII in SS-SMII package.
1
0 Port 24 is configured to Reversed MII in SS-SMII package.
M1TXD0
Don’t Support
3-13
ADM6926
Function Description
SS-SMII Pin
Name
RMII Pin Name
M0TXD1
Don’t Support
M0TXD3
Don’t Support
Description
Port 25 Interface Configuration.
M0TXD1 M0TXD3 Interface
configured to MII in SS-SMII package (internal value.
x
1 Port 25 is configured to RMII is SS-SMII package.
1
0 Port 25 is configured to Reversed MII in SS-SMII package.
When port 24 or port 25 is configured to RMII mode in SS-SMII package, we can use the
hardware pins to configure duplex status of these two ports.
M0RXD3
0
0
1
1
M0RXD2
0
1
0
1
Port 24 Duplex Configuration
Description
Duplex status is determined as port 0 ~ port 23.
Duplex status is determined as port 0 ~ port 23.
Full Duplex is determined.
Half Duplex is determined.
M1RXD3
0
0
1
1
M1RXD2
0
1
0
1
Port 25 Duplex Configuration
Description
Duplex status is determined as port 0 ~ port 23.
Duplex status is determined as port 0 ~ port 23.
Full Duplex is determined.
Half Duplex is determined.
2. EEPROM Interface
The EEPROM Interface is provided so the users could easily configure the setting
without CPU’s help. Because the EEPROM Interface is the same as the 93c66, it also
allows the CPU to write the EEPROM register and renew the 93c66 at the same time.
After the power up or reset (default value from the hardware pins fetched in this stage),
the ADM6926 will automatically detect the presence of the EEPROM by reading the
address 0 in the 96c66. If the value = 16’h4154, it will read all the data in the 93c66. If
not, the ADM6926 will stop loading the 93c66. The user also could pull down the EDO
to force the ADM6926 not to load the 93c66. The 93c66 loading time is around 30ms.
Then CPU should give the high-z value in the EECS, EESK and EDI pins in this period if
we really want to use CPU to read or write the registers in the ADM6926.
The EEPROM Interface needs only one Write command to complete a writing operation.
If updating the 93c66 at the same time is necessary, three commands Write Enable,
Write, and Write Disable are needed to complete this job (See 93c66 Spec. for a
reference). Users should note that the EERPOM interface only allows the CPU to write
the EEPROM register in the ADM6926 and doesn’t support the READ command. If CPU
gives the Read Command, ADM6926 will not respond and 93c66 will respond with the
value. Users should also note that one additional EESK cycle is needed between any
continuous commands (Read or Write).
ADMtek Inc.
3-14
ADM6926
Function Description
(1) Read 93c66 via the EEPROM Interface (Index = 2, Data = 16’h1111).
EECS(CPU)
EESK(CPU)
EDI (CPU)
One more EESK is needed
1
1
Start
0
A7
A6
Opcode
A5
A4
A3
A2
A1
A0
EEPROM Adress (Index)
EDO (93c46)
0
D15
D14
D13
D12
D11
D10
D9
D8
Dummy
D7
D6
D5
D4
D3
D2
D1
D0
Data
EEPROM Read Operation
(2) Write EEPROM registers in the ADM6926 (Index = 2, Data =16’h2222).
EECS(CPU)
EESK(CPU)
EDI (CPU)
One more EESK is needed
1
Start
0
0
Opcode
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
EEPROM Adress (Index)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data
EEPROM Write Operation
3. SMI Interface
The SMI consists of two pins, management data clock (EESK) and management data
input/output (EDI). The ADM6926 is designed to support an EESK frequency up to 25
MHz. The EDI pin is bi-directional and may be shared with other devices. EECS pin may
be needed (pulled to low) if EEPROM interface is also used.
The EDI pin requires a 1.5 KΩ pull-up which, during idle and turnaround periods, will
pull EDI to a logic one state. ADM6926 requires a single initialization sequence of 32
bits of preamble following power-up/hardware reset. The first 32 bits are preamble
consisting of 32 contiguous logic one bits on EDI and 32 corresponding cycles on EESK.
Following preamble is the start-of-frame field indicated by a <01> pattern. The next field
signals the operation code (OP): <10> indicates read from management register
operation, and <01> indicates write to management register operation. The next field is
management register address. It is 10 bits wide and the most significant bit is transferred
first.
During Read operation, a 2-bit turn around (TA) time spacing between the register
address field and data field is provided for the EDI to avoid contention. Following the
turnaround time, a 32-bit data stream is read from or written into the management
registers of the ADM6926.
(A) Preamble Suppression
The SMI of ADM6926 supports a preamble suppression mode. The ADM6926 requires a
single initialization sequence of 32 bits of preamble following power-up/hardware reset.
This requirement is generally met by pulling-up the resistor of EDI While the ADM6926
will respond to management accesses without preamble, a minimum of one idle bit
between management transactions is required.
ADMtek Inc.
3-15
ADM6926
Function Description
When ADM6926 detects that there is address match, then it will enable Read/Write
capability for external access. When address is mismatched, then ADM6926 will tri-state
the EDI pin.
(B) Read Switch Register via SMI Interface (Offset Hex = 10’h2, Data =
32’h2600_0000)
One more EESK is needed
EESK
EDI(CPU)
~
~
EDI(AD3110)
z
0
Preamble
1
1
0
0
0
0
Opcode
(Read)
Start
0
0
0
0
0
1
0
z
0
0
0
1
0
0
TA
Register Address (10'h2 in this example)
1
1
0
0
0
0
0
0
z
Register Data (32'h26000000 in this Example)
SMI Read Operation
(C) Write Switch Register via SMI Interface (Offset Hex = 10’h180, Data =
32’h1300_0000)
One more EESK is needed
EESK
EDI (CPU)
z
Preamble
0
1
Start
0
1
0
Opcode
(Write)
1
1
0
0
0
0
0
0
0
Register Address (10'h180 in this example)
1
0
TA
0
0
0
1
0
0
1
1
0
0
0
~
~
0
0
0
z
Register Data (32'h13000000 in this Example)
SMI Write Operation
(D) The pin type of EECS, EESK, EDI and EDO during the operation.
Pin Name
EECS
EESK
EDI
EDO
ADMtek Inc.
Reset Operation
Input
Input
Input
Input
Load EEPROM
Output
Output
Output
Input
Write Operation
Input
Input
Input
Input
Read Operation
Input
Input
Input/Output
Input
3-16
ADM6926
3.2
Function Description
EEPROM Register Format
The EEPROM can be auto-detected by ADM6926 through the signature register. The
ADM6926 supports C66 EEPROM. After the EEPROM is loaded, the output pins of
ADM6926 are tri-state and released to CPU. The release time is about 30ms after end of
RESET. Whenever CPU modifies the setting of C66, the new value will be written to
ADM6926 at the same time. If CPU changes the port setting (Duplex/Speed/AEN), the
ADM6926 will restart the auto-negotiation automatically.
EEPROM Format:
Offset Hex
0200h
Low
0201h
High
0202h
Low
0203h
High
0204h
Low
0205h
High
0206h
Low
0207h
High
0208h
Low
0209h
High
020ah
Low
020bh
High
020ch
Low
020dh
High
020eh
Low
020fh
High
0210h
Low
0211h
High
0212h
Low
0213h
High
0214h
Low
0215h
High
0216h
Low
0217h
High
0218h
Low
0219h
High
021ah
Low
021bh
High
021ch
Low
021dh
High
021eh
Low
021fh
High
0220h
Low
0221h
High
0222h
Low
0223h
High
0224h
Low
0225h
High
0226h
Low
0227h
High
0228h
Low
0229h
High
ADMtek Inc.
Index
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
ah
bh
ch
dh
eh
fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1ah
1bh
1ch
1dh
1eh
1fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
Bit 15- 8
Bit 7 – 0
Signature
Global configuration
Port 0 Configuration
Port 1 Configuration
Port 2 Configuration
Port 3 Configuration
Port 4 Configuration
Port 5 Configuration
Port 6 Configuration
Port 7 Configuration
Port 8 Configuration
Port 9 Configuration
Port10 Configuration
Port 11 Configuration
Port 12 Configuration
Port 13 Configuration
Port 14 Configuration
Port 15 Configuration
Port 16 Configuration
Port 17 Configuration
Port 18 Configuration
Port 19 Configuration
Port 20 Configuration
Port 21 Configuration
Port 22 Configuration
Port 23 Configuration
Port 24 Configuration
Port 25 Configuration
Miscellaneous Configuration
TOS Priority Map
VLAN Priority Map
Forwarding Group 0 Outbound Port Map Low
Forwarding Group 0 Outbound Port Map High
Forwarding Group 1 Outbound Port Map Low
Forwarding Group 1 Outbound Port Map High
Forwarding Group 2 Outbound Port Map Low
Forwarding Group 2 Outbound Port Map High
Forwarding Group 3 Outbound Port Map Low
Forwarding Group 3 Outbound Port Map High
Forwarding Group 4 Outbound Port Map Low
Forwarding Group 4 Outbound Port Map High
Forwarding Group 5 Outbound Port Map Low
Forwarding Group 5 Outbound Port Map High
Type
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
4154h
3800h
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
80ffh
820h
0h
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
3-17
ADM6926
Offset Hex
022ah
Low
022bh
High
022ch
Low
022dh
High
022eh
Low
022fh
High
0230h
Low
0231h
High
0232h
Low
0233h
High
0234h
Low
0235h
High
0236h
Low
0237h
High
0238h
Low
0239h
High
023ah
Low
023bh
High
023ch
Low
023dh
High
023eh
Low
023fh
High
0240h
Low
0241h
High
0242h
Low
0243h
High
0244h
Low
0245h
High
0246h
Low
0247h
High
0248h
Low
0249h
High
024ah
Low
024bh
High
024ch
Low
024dh
High
024eh
Low
024fh
High
0250h
Low
0251h
High
0252h
Low
0253h
High
0254h
Low
0255h
High
0256h
Low
0257h
High
0258h
Low
0259h
High
025ah
Low
025bh
High
025ch
Low
025dh
High
025eh
Low
ADMtek Inc.
Function Description
Index
2ah
2bh
2ch
2dh
2eh
2fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3ah
3bh
3ch
3dh
3eh
3fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4ah
4bh
4ch
4dh
4eh
4fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5ah
5bh
5ch
5dh
5eh
Bit 15- 8
Bit 7 – 0
Forwarding Group 6 Outbound Port Map Low
Forwarding Group 6 Outbound Port Map High
Forwarding Group 7 Outbound Port Map Low
Forwarding Group 7 Outbound Port Map High
Forwarding Group 8 Outbound Port Map Low
Forwarding Group 8 Outbound Port Map High
Forwarding Group 9 Outbound Port Map Low
Forwarding Group 9 Outbound Port Map High
Forwarding Group 10 Outbound Port Map Low
Forwarding Group 10 Outbound Port Map High
Forwarding Group 11 Outbound Port Map Low
Forwarding Group 11 Outbound Port Map High
Forwarding Group 12 Outbound Port Map Low
Forwarding Group 12 Outbound Port Map High
Forwarding Group 13 Outbound Port Map Low
Forwarding Group 13 Outbound Port Map High
Forwarding Group 14 Outbound Port Map Low
Forwarding Group 14 Outbound Port Map High
Forwarding Group 15 Outbound Port Map Low
Forwarding Group 15 Outbound Port Map High
Forwarding Group 16 Outbound Port Map Low
Forwarding Group 16 Outbound Port Map High
Forwarding Group 17 Outbound Port Map Low
Forwarding Group 17 Outbound Port Map High
Forwarding Group 18 Outbound Port Map Low
Forwarding Group 18 Outbound Port Map High
Forwarding Group 19 Outbound Port Map Low
Forwarding Group 19 Outbound Port Map High
Forwarding Group 20 Outbound Port Map Low
Forwarding Group 20 Outbound Port Map High
Forwarding Group 21 Outbound Port Map Low
Forwarding Group 21 Outbound Port Map High
Forwarding Group 22 Outbound Port Map Low
Forwarding Group 22 Outbound Port Map High
Forwarding Group 23 Outbound Port Map Low
Forwarding Group 23 Outbound Port Map High
Forwarding Group 24 Outbound Port Map Low
Forwarding Group 24 Outbound Port Map High
Forwarding Group 25 Outbound Port Map Low
Forwarding Group 25 Outbound Port Map High
Forwarding Group 26 Outbound Port Map Low
Forwarding Group 26 Outbound Port Map High
Forwarding Group 27 Outbound Port Map Low
Forwarding Group 27 Outbound Port Map High
Forwarding Group 28 Outbound Port Map Low
Forwarding Group 28 Outbound Port Map High
Forwarding Group 29 Outbound Port Map Low
Forwarding Group 29 Outbound Port Map High
Forwarding Group 30 Outbound Port Map Low
Forwarding Group 30 Outbound Port Map High
Forwarding Group 31 Outbound Port Map Low
Forwarding Group 31 Outbound Port Map High
PVID shift
P0 VID
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
ffffh
3ffh
1h
3-18
ADM6926
Offset Hex
025fh
High
0260h
Low
0261h
High
0262h
Low
0263h
High
0264h
Low
0265h
High
0266h
Low
0267h
High
0268h
Low
0269h
High
026ah
Low
026bh
High
026ch
Low
026dh
High
026eh
Low
026fh
High
0270h
Low
0271h
High
0272h
Low
0273h
High
0274h
Low
0275h
High
0276h
Low
0277h
High
0278h
Low
0279h
High
027ah
Low
027bh
High
027ch
Low
027dh
High
027eh
Low
027fh
High
0280h
Low
0281h
High
0282h
Low
0283h
High
0284h
Low
0285h
High
0286h
Low
0287h
High
0288h
Low
0289h
High
028ah
Low
028bh HIGH
028ch
Low
028dh HIGH
028eh
Low
028fh
HIGH
0290h
Low
0291h HIGH
0292h
Low
0293h HIGH
ADMtek Inc.
Function Description
Index
5fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6ah
6bh
6ch
6dh
6eh
6fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7ah
7bh
7ch
7dh
7eh
7fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8ah
8bh
8ch
8dh
8eh
8fh
90h
91h
92h
93h
Bit 15- 8
Bit 7 – 0
P1 VID
P2 VID
P3 VID
P4 VID
P5 VID
P6 VID
P7 VID
P8 VID
P9 VID
P10 VID
P11 VID
P12 VID
P13 VID
P14 VID
P15 VID
P16 VID
P17 VID
P18 VID
P19 VID
P20 VID
P21 VID
P22 VID
P23 VID
P24 VID
P25 VID
P0, P1, P2, P3 Bandwidth Control Register
P4, P5, P6, P7 Bandwidth Control Register
P8, P9, P10, P11 Bandwidth Control Register
P12, P13, P14, P15 Bandwidth Control Register
P16, P17, P18, P19 Bandwidth Control register
P20, P21, P22, P23 Bandwidth Control Register
P25, P24 Bandwidth Control Register
Bandwidth Control Enable Register Low
Bandwidth Control Enable Register High
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Customized PHY Control Group 0
Customized PHY Control Group 1
Customized PHY Control Group 2
Customized PHY Control Group 3
Group 0 PHY Customized DATA 0
Group 0 PHY Customized DATA 1
Group 1 PHY Customized DATA 0
Group 1 PHY Customized DATA 1
Group 2 PHY Customized DATA 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
1h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
100h
0h
0h
0h
0h
0h
0h
ff00h
0h
0h
0h
0h
0h
0h
0h
0h
0h
3-19
ADM6926
Function Description
Offset Hex
0294h
Low
0295h HIGH
0296h
Low
0297h HIGH
0298h
Low
0299h HIGH
029ah
Low
029bh HIGH
029ch
Low
029dh HIGH
029eh
Low
029fh
HIGH
02a0h
Low
02a1h HIGH
02a2h
Low
02a3h HIGH
02a4h
Low
02a5h HIGH
02a6h
Low
02a7h HIGH
3.2.1
Index
94h
95h
96h
97h
98h
99h
9ah
9bh
9ch
9dh
9eh
9fh
a0h
a1h
a2h
a3h
a4h
a5h
a6h
a7h
Bit 15- 8
Bit 7 – 0
Group 2 PHY Customized DATA 1
Group 3 PHY Customized DATA 0
Group 3 PHY Customized DATA 1
PHY Customized Enable Register
PPPOE Control Register 0
PPPOE Control Register 1
PHY Control Register 0
PHY Control Register 1
Disable MDIO Active Register 0
Disable MDIO Active Register 1
Disable Port Register 0
Disable Port Register 1
IGMP Enable Register 0
IGMP Enable Register 1
CPU Control Register
MAC Forward Mode Register 0
MAC Forward Mode Register 1
MAC Forward Mode Register 2
Trunking Enable Register 0
Trunking Enable Register 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
001fh
4h
3h
0h
0h
0h
Signature (Index: 0h)
Configuration
Bit [15:0]
Description
The value must be at 4154h. ADM6926 uses this value to check if the EEPROM is
attached. If the value in the EEPROM doesn’t equal to 4154h, the ADM6926 will
not load the EEPROM even if the EEPROM is attached.
Default
4154h
3.2.2 Global Configuration Register (Index: 1h)
Configuration
Bit [1:0]
Bit [2]
Bit [4:3]
Bit [8:5]
Bit[9]
ADMtek Inc.
Description
Broadcast Storm Threshold.
Broadcast Storm Filtering Enable Bit.
1 = The ADM6926 enables the broadcast storm filtering function.
0 = The ADM6926 disables the broadcast storm filtering function.
Priority Queue Ratio. The ADM6926 supports two priorities on each output port
using weighted round robin scheme. The ratio between the low and high queue is as
follows:
Bit[4:3] Ratio
00
1:2
01
1:4
10
1:8
11
1:16
Discard Mode. This function enables the switch to discard packets according to their
priorities if the receiving port disables the flow control function. Users could use this
to prevent packets with the low priority to block those with high priority.
Bit[8:7] = High Queue Discard Mode (see Sec. 3.1.18)
Bit[6:5] = Low Queue Discard Mode.
Check VLAN Group.
1 = The ADM6926 will check if the packets and the receiving port are at the same
Forwarding Group. That is, the output port map for the receiving packet must
contain the receiving port. If they belong to different Forwarding Group, the
receiving packets will be discarded.
Example: Port 3 receives a packet and finds Forwarding Group contains P0, P1,
and P2 (doesn’t contain P3). This packet will be dropped.
Default
2’b00
1’b0
2’b00
4’b0000
1’b0
3-20
ADM6926
Function Description
Configuration
Bit[10]
Bit[11]
Bit[12]
Bit [13]
Bit[14]
3.2.3
Description
0 = The ADM6926 will disable the Check VLAN Group function.
VLAN Group Mode.
1 = The switch is configured to Tagged Based VLAN.
0 = The switch is configured to Port Based VLAN.
Bypass Mode.
1 = The switch is configured to Bypass Mode. The packets will not be modified
when they are transmitted.
0 = The switch is not configured to Bypass Mode.
Force No Tag Mode.
1 = The switch is configured to Force No Tag Mode. In this mode, the ADM6926
will not recognize the VLAN TAG even if they contain a Tag Header.
0 = The switch is not configured to Force No Tag Mode.
Length 1536 Enable bit.
1 = The switch can receive packets of less than 1536 bytes.
0 = The switch can receive packets of less then 1518 bytes.
Fast Management Clock Enable Bit.
1 = The switch will use 10 M clock to configure the phys.
0 = The switch will use 2.5M clock to configure the phys.
Default
1’b0
1’b1
1’b1
1’b1
1’b0
Port Configuration Registers (Index: 2h ~ 1bh)
Configuration
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
ADMtek Inc.
Description
10Base-T Half Duplex Ability in Auto-Negotiation Advertisement Register.
1 = 10Base-T Half Duplex is advertised.
0 = 10Base-T Half Duplex is not advertised.
10Base-T Full Duplex Ability in Auto-Negotiation Advertisement Register.
1 = 10Base-T Full Duplex is advertised.
0 = 10Base-T Full Duplex is not advertised.
100Base-TX Half Duplex Ability in Auto-Negotiation Advertisement Register.
1 = 100Base-TX Half Duplex is advertised.
0 = 100Base-TX Half Duplex is not advertised.
100Base-TX Full Duplex Ability in Auto-Negotiation Advertisement Register.
1 = 100Base-TX Full Duplex is advertised.
0 = 100Base-Tx Full Duplex is not advertised.
802.3x Flow Control Ability in Full Duplex.
1=
(1). MAC controller supports Pause Frames when the port is configured to bypass
management function from MDC/MDIO.
(2). If the port is not configured to bypass management function form MDC/MDIO,
then it will be used as the Pause bit in Auto-Negotiation Advertisement Register
and the Pause function will be advertised. If Auto-Negotiation function is disabled,
then this bit is used and Pause is supported.
(3). If the port is not configured to bypass management function from MDC/MDIO
and no PHY is attached to this port, the MAC controller will support Pause Frames
in the full duplex.
0=
(1). Mac controller doesn’t support Pause Frames when the port is configured to
bypass management function from MDC/MDIO.
(2). If the port is not configured to bypass management function form MDC/MDIO,
then it will be used as the Pause bit in Auto-Negotiation Advertisement Register
and the Pause function will not be advertised. If Auto-Negotiation function is
disabled, then this bit is used and Pause is not supported.
(3). If the port is not configured to bypass management function from MDC/MDIO
and no PHY is attached to this port, the MAC controller will not support Pause
Frames in the full duplex.
Default
1’b1
1’b1
1’b1
1’b1
1’b1
3-21
ADM6926
Configuration
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit [10]
Bit [11]
Bit [12]
Bit[14:13]
ADMtek Inc.
Function Description
Description
Auto Negotiation Enable in Basic Mode Control Register.
1 = Auto-Negotiation is Enabled.
0 = Auto-Negotiation is Disabled.
Speed Ability. This bit will be used as Bit 13 (Speed Select) in the Basic Mode
Control Register if bypass management function is not enabled, and be used as Speed
Desired if bypass management function is enabled.
1 = 100Mb/s Enabled.
0 = 10 Mb/s Enabled.
Duplex Ability. This bit will be used as Bit 8 (Duplex Select) in the Basic Mode
Control Register if bypass management function is not enabled, and be used as
Duplex Desired if bypass management function is enabled.
1 = Full Duplex Enabled.
0 = Half Duplex Enabled.
Tagged Port.
1 = The transmitted port is configured to a tagged port. The transmitted packets from
a tagged port will always contain a Tag Header except the transmitted packets
are management packet or the Bypass Mode is enabled.
0 = The transmitted port is configured to an untagged port. The transmitted packets
from an untagged port will not contain a Tag Header except the transmitted
packets are management packet or the Bypass Mode is enabled.
Security Function Enable.
1 = The switch enables the security function. Four security modes could be selected
through Bit[14:13].
0 = The switch disables the security function.
TOS over VLAN priority.
1 = When the receiving packets contain the IPv4 and Tag Priority at the same time,
the switch will use IPv4 priority field for the queue mapping.
0 = When the receiving packets contain the IPv4 and Tag Priority at the same time,
the switch will use Tag priority field for the queue mapping.
Enable port-base priority.
1 = The switch will always use the Port-Priority for the queue mapping even if the
receiving packets contain IPv4 or Tag information.
0 = The switch will use the IPv4 or Tag priority fields for the queue mapping (See
Bit [10]). If the packets contain no priority field, then the switch will use the
Port-Priority for the default priority.
Port-base Priority Mapping.
1 = Mapped for the High Queue.
0 = Mapped for the Low Queue.
Four Security Mode.
00 = The switch will forward packets with “unknown source addresses” to the CPU
port and not learn it if the receiving port is configured to enable security
function. The “unknown source address” means that we can’t find an equal
address existed in the learning table and its corresponding port number equals to
the receiving port. This function needs CPU’s help because we need to create a
“static address” to the learning table from the CPU. “Static” means this address
will always exist in the leaning table and can only be removed through the CPU.
When the address is configured to “Static”, we can prevent this address from
overlapping when it is received from a port without the security function
enabled.
01 = The switch will discard packets with “unknown source addresses” and not learn
it if the receiving port is configured to enable security function. Only packets
with source addresses existed in the learning table will be forwarded.
10 =The first received packets will be locked at the receiving port if the receiving
port is configured to enable security function. Only the packets with the source
address same as the locked one will be forwarded and learned.
Default
1’b1
1’b1
1’b1
1’b0
1’b0
1’b0
1’b0
1’b0
2’b00
3-22
ADM6926
Function Description
Configuration
Bit[15]
3.2.4
Description
11= The first received packets will be locked as above. The difference is that the
receiving port will not receive and learn packets any more after the link goes
down even it links up again (it may happen if the station moves to the other
port).
Back Pressure Enable Bit.
1 = The MAC controller supports back-pressure function in half duplex.
0 = The MAC controller doesn’t support back-pressure function in half duplex.
Default
1’b1
Miscellaneous Configuration (Index: 1ch)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[7:4]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Description
Disable CSMA/CD Back-off Function.
1 = The MAC controller will disable random back off function.
0 = The Mac controller supports random back off function.
Recommend 16th Collision Drop.
1 = The Mac controller will drop packets when the collision count is larger than 16.
0 = The Mac controller will retransmit packets even when the collision count is
larger than 16.
Reserved
Enable Replace VLAN ID
1 = The switch will replace the VID with the PVID associated with the receiving port
when the received packets are priority tagged or its VID in the Tag Header
equals to 1.
0 = The switch will use the original VID received from the Tag Header.
Reserved
Reserved
Collision LED Enable.
1 = The switch will provide two collision LEDs for 10M and 100M domain
individually and flash in rate of 2Hz.
0 = The switch will not provide two collision LEDs for 10M and 100M domain
individually.
Reserved
Reserved
Reserved
Reserved
Default
1’b0
1’b0
1’b0
1’b0
4’b0010
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.5 VLAN(TOS) Priority Map (Index: 1dh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
ADMtek Inc.
Description
Mapped Priority Queue of Tag Value 0
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of Tag Value 1
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped priority Queue of Tag Value 2
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of Tag Value 3
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of Tag Value 4
1 = Mapped for High Queue
0 = Mapped for Low Queue
Mapped Priority Queue of Tag Value 5
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-23
ADM6926
Configuration
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Function Description
Description
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of Tag Value 6
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of Tag Value 7
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 0
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 1
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 2
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 3
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 4
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 5
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 6
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Mapped Priority Queue of TOS 7
1 = Mapped for the High Queue
0 = Mapped for the Low Queue
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.6 Forwarding Group Outbound Port Map Low
(Index: 1eh, 20h, 22h, 24h, 26h, 28h, 2ah, 2ch, 2eh, 30h, 32h, 34h, 36h, 38h, 3ah, 3ch,
3eh, 40h, 42h, 44h, 46h, 48h, 4ah, 4ch, 4eh, 50h, 52h, 54h, 56h, 58h, 5ah, 5ch)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
ADMtek Inc.
Description
1= Port 0 is in the Forwarding Group
0 = Port 0 is not in the Forwarding Group
1= Port 1 is in the Forwarding Group
0 = Port 1 is not in the Forwarding Group
1= Port 2 is in the Forwarding Group
0 = Port 2 is not in the Forwarding Group
1= Port 3 is in the Forwarding Group
0 = Port 3 is not in the Forwarding Group
1= Port 4 is in the Forwarding Group
0 = Port 4 is not in the Forwarding Group
1= Port 5 is in the Forwarding Group
0 = Port 5 is not in the Forwarding Group
1= Port 6 is in the Forwarding Group,
0 = Port 6 is not in the Forwarding Group
1= Port 7 is in the Forwarding Group
0 = Port 7 is not in the Forwarding Group
1= Port 8 is in the Forwarding Group
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
3-24
ADM6926
Function Description
Configuration
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Description
0 = Port 8 is not in the Forwarding Group
1= Port 9 is in the Forwarding Group
0 = Port 9 is not in the Forwarding Group
1= Port 10 is in the Forwarding Group
0 = Port 10 is not in the Forwarding Group
1= Port 11 is in the Forwarding Group
0 = Port 11 is not in the Forwarding Group
1= Port 12 is in the Forwarding Group
0 = Port 12 is not in the Forwarding Group
1= Port 13 is in the Forwarding Group
0 = Port 13 is not in the Forwarding Group
1= Port 14 is in the Forwarding Group
0 = Port 14 is not in the Forwarding Group
1= Port 15 is in the Forwarding Group
0 = Port 15 is not in the Forwarding Group
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
3.2.7 Forwarding Group Outbound Port Map High
(Index: 1fh, 21h, 23h, 25h, 27h, 29h, 2bh, 2dh, 2fh, 31h, 33h, 35h, 37h, 39h, 3bh, 3dh,
3fh, 41h, 43h, 45h, 47h, 49h, 4bh, 4dh, 4fh, 51h, 53h, 55h, 57h, 59h, 5bh, 5dh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
3.2.8
Description
1= Port 16 is in the Forwarding Group
0 = Port 16 is not in the Forwarding Group
1= Port 17 is in the Forwarding Group
0 = Port 17 is not in the Forwarding Group
1= Port 18 is in the Forwarding Group
0 = Port 18 is not in the Forwarding Group
1= Port 19 is in the Forwarding Group
0 = Port 19 is not in the Forwarding Group
1= Port 20 is in the Forwarding Group
0 = Port 20 is not in the Forwarding Group
1= Port 21 is in the Forwarding Group
0 = Port 21 is not in the Forwarding Group
1= Port 22 is in the Forwarding Group
0 = Port 22 is not in the Forwarding Group
1= Port 23 is in the Forwarding Group
0 = Port 23 is not in the Forwarding Group
1= Port 24 is in the Forwarding Group
0 = Port 24 is not in the Forwarding Group
1= Port 25 is in the Forwarding Group
0 = Port 25 is not in the Forwarding Group
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
P0 VID and PVID Shift (Index: 5eh)
Configuration
Bit [11:0]
Bit [15:13]
ADMtek Inc.
Description
Port 0 VID. The port’s Default VID is used if the frame is untagged or if the frame’s
VID is 0x0000 or 0x0001 and Enable Replace VLAN ID function (also see
Miscellaneous Configuration register) is enabled.
VID Shift. This function maps 4096 VLAN into 32 Forwarding Groups.
1. In Tagged Based VLAN, the ADM6926 will use 5 bits from VID as the Index to
map into forwarding groups. 32 forwarding groups are defined in the ADM6926. We
use F0, F1, .F31 to call each forwarding group. This looking scheme is different from
the Port Based VLAN because Port Based VLAN uses port number as the Index to
map into the forwarding groups and then F26 ~ F31 will not be used. The VID is
Default
0001h
3’b000
3-25
ADM6926
Configuration
Function Description
Description
defined as follows:
1.1 The port’s Default VID is used if the frame is not 802.3ac Tagged (No Tag
Header in the frame).
1.2 The port’s Default VID is used if the frame is 802.3ac Tagged (Tag Header in
the frame) and the frame’s VID is 0x0000 or 0x0001 and the Enable Replace
VLAN ID function is enabled.
1.3 The VID in the Tag Header is used if the frame is 802.3 Tagged and the frame’s
VID is not 0x0000 or 0x0001.
1.4 The VID in the Tag Header is used if the frame is 802.3 Tagged and the frame’s
VID is 0x0000 or 0x0001 and Enable Replace VLAN ID function is not enabled.
2. The relation between VID Shift, VID and the forwarding group is as follows:
Bit[15:13] Forwarding Group
000
= VID[4:0]
001
= VID[5:1]
010
= VID[6:2]
011
= VID[7:3]
100
= VID[8:4]
101
= VID[9:5]
110
= VID[10:6]
111
= VID[11:7]
Default
3.2.9 P1~P25 VID Configuration
(Index: 5fh, 60h, 61h, 62h, 63h, 64h, 65h, 66h, 67h, 68h, 69h, 6ah, 6bh, 6ch, 6dh, 6eh,
6fh, 70h, 71h, 72h, 73h, 74h, 75h, 76h, 77h)
Configuration
Bit [11:0]
Description
Default
0001h
The port’s Default VID
3.2.10 P0, P1, P2, P3 Bandwidth Control Register (Index: 78h)
Configuration
Bit [2:0]
Bit [3]
Bit [6:4]
Bit [7]
Bit [10:8]
Bit [11]
Bit [14:12]
Description
Port 0 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 0 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P0 counter.
Port 1 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 1 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P1 counter.
Port 2 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
101
110
111
Port 2 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P2 counter.
Port 3 Meter Threshold Control, default 000
000
ADMtek Inc.
001
010
011
100
3-26
ADM6926
Function Description
Configuration
64K
Bit [15]
128K
256K
Description
512K
1M
4M
10M
20M
Port 3 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P3 counter.
3.2.11 P4, P5, P6, P7 Bandwidth Control Register (Index: 79h)
Configuration
Bit [2:0]
Bit [3]
Bit [6:4]
Bit [7]
Bit [10:8]
Bit [11]
Bit [14:12]
Bit [15]
Description
Port 4 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 4 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P4 counter.
Port 5 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 5 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P5 counter.
Port 6 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 6 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P6 counter.
Port 7 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 7 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P7 counter.
3.2.12 P8, P9, P10, P11 Bandwidth Control Register (Index: 7ah)
Configuration
Bit [2:0]
Bit [3]
Bit [6:4]
Bit [7]
Bit [10:8]
Description
Port 8 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 8 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P8 counter.
Port 9 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
101
110
111
Port 9 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P9 counter.
Port 10 Meter Threshold Control, default 000
000
ADMtek Inc.
001
010
011
100
3-27
ADM6926
Function Description
Configuration
64K
Bit [11]
Bit [14:12]
Bit [15]
128K
256K
Description
512K
1M
4M
10M
20M
Port 10 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P10 counter.
Port 11 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 11 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P11 counter.
3.2.13 P12, P13, P14, P15 Bandwidth Control Register (Index: 7bh)
Configuration
Bit [2:0]
Bit [3]
Bit [6:4]
Bit [7]
Bit [10:8]
Bit [11]
Bit [14:12]
Bit [15]
Description
Port 12 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 12 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P12 counter.
Port 13 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 13 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P13 counter.
Port 14 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 14 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P14 counter.
Port 15 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 15 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P15 counter.
3.2.14 P16, P17, P18, P19 Bandwidth Control Register (Index: 7ch)
Configuration
Bit [2:0]
Bit [3]
Bit [6:4]
Description
Port 16 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
101
110
111
Port 16 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P16 counter.
Port 16 Meter Threshold Control, default 000
000
ADMtek Inc.
001
010
011
100
3-28
ADM6926
Function Description
Configuration
64K
Bit [7]
Bit [10:8]
Bit [11]
Bit [14:12]
Bit [15]
128K
256K
Description
512K
1M
4M
10M
20M
Port 17 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P17 counter.
Port 18 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 18 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P18 counter.
Port 19 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 19 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P19 counter.
3.2.15 P20, P21, P22, P23 Bandwidth Control Register (Index: 7dh)
Configuration
Bit [2:0]
Bit [3]
Bit [6:4]
Bit [7]
Bit [10:8]
Bit [11]
Bit [14:12]
Bit [15]
Description
Port 20 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 20 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P20 counter.
Port 21 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 21 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P21 counter.
Port 22 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 22 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P22 counter.
Port 23 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 23 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P23 counter.
3.2.16 P24, P25 Bandwidth Control Register (Index: 7eh)
Configuration
Bit [2:0]
Description
Port 24 Meter Threshold Control, default 000
000
ADMtek Inc.
001
010
011
100
101
110
111
3-29
ADM6926
Function Description
Configuration
64K
Bit [3]
Bit [6:4]
Bit [7]
128K
256K
Description
512K
1M
4M
10M
20M
Port 24 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P24 counter.
Port 25 Meter Threshold Control, default 000
000
001
010
011
100
101
110
111
64K
128K
256K
512K
1M
4M
10M
20M
Port 25 Receive Packet Length Counted on the Source Port, default 0
0 = The switch will add length to the P25 counter.
3.2.17 Bandwidth Control Enable Register Low (Index: 7fh)
Configuration
Bit [0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Description
Bandwidth Control Enable for Port 0.
1 = Port 0 enables the bandwidth control.
0 = Port 0 disables the bandwidth control.
Bandwidth Control Enable for Port 1.
Bandwidth Control Enable for Port 2.
Bandwidth Control Enable for Port 3.
Bandwidth Control Enable for Port 4
Bandwidth Control Enable for Port 5
Bandwidth Control Enable for Port 6
Bandwidth Control Enable for Port 7
Bandwidth Control Enable for Port 8
Bandwidth Control Enable for Port 9
Bandwidth Control Enable for Port 10
Bandwidth Control Enable for Port 11
Bandwidth Control Enable for Port 12
Bandwidth Control Enable for Port 13
Bandwidth Control Enable for Port 14
Bandwidth Control Enable for Port 15
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.18 Bandwidth Control Enable Register High (Index: 80h)
Configuration
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Description
Bandwidth Control Enable for Port 16.
Bandwidth Control Enable for Port 17
Bandwidth Control Enable for Port 18.
Bandwidth Control Enable for Port 19.
Bandwidth Control Enable for Port 20.
Bandwidth Control Enable for Port 21.
Bandwidth Control Enable for Port 22.
Bandwidth Control Enable for Port 23.
Bandwidth Control Enable for Port 24
Bandwidth Control Enable for Port 25.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.19 Reserved Registers (Index: 81h~8ah)
Configuration
Bit [15:0]
ADMtek Inc.
Description
Reserved for the future use and don’t modify the values.
Default
See Sec.3.2
EEPROM
Register
3-30
ADM6926
Function Description
3.2.20 Customized PHY Control Group 0 (Index: 8bh)
Configuration
Bit [4:0]
Bit [7:5]
Bit [12:8]
Bit [15:13]
Description
Register Address of the Command 0.
PHY Address of the Command 0 if Bit[2:0] in PHY Customized Enable Register =
3’b001 or 3’b011.
000 = The switch will write command 0 into Port 0 (PHY Address = 32’h8).
001 = The switch will write command 0 into Port 1 (PHY Address = 32’h9).
010 = The switch will write command 0 into Port 2 (PHY Address = 32’ha).
011 = The switch will write command 0 into Port 3 (PHY Address = 32’hb).
100 = The switch will write command 0 into Port 4 (PHY Address = 32’hc).
101 = The switch will write command 0 into Port 5 (PHY Address = 32’hd).
110 = The switch will write command 0 into Port 6 (PHY Address = 32’he).
111 = The switch will write command 0 into Port 7 (PHY Address = 32’hf).
Register Address of the Command 1.
PHY Address of the Command 1 if Bit[2:0] in PHY Customized Enable Register =
3’b010 or 3’b011
000 = The switch will write command 1 into Port 0 (PHY Address = 32’h8).
001 = The switch will write command 1 into Port 1 (PHY Address = 32’h9).
010 = The switch will write command 1 into Port 2 (PHY Address = 32’ha).
011 = The switch will write command 1 into Port 3 (PHY Address = 32’hb).
100 = The switch will write command 1 into Port 4 (PHY Address = 32’hc).
101 = The switch will write command 1 into Port 5 (PHY Address = 32’hd).
110 = The switch will write command 1 into Port 6 (PHY Address = 32’he).
111 = The switch will write command 1 into Port 7 (PHY Address = 32’hf).
Default
5’b00000
3’b000
5’b00000
3’b000
Note:
The ADM6926 supports eight additional commands for the customer to configure the PHY
attached. Four groups are defined and each group shares two commands. Group 0 contains P0,
P1, P2, P3, P4, P5, P6 and P7. Group 1 contains P8, P9, P10, P11, P12, P13, P14 and P15. Group
2 contains P16, P17, P18, P19, P20, P21, P22 and P23. Group 3 contains P24 and P25. 3 bits
enable register is associated with each group. Each command is associated with a PHY address, a
register address, and data for writing.
3.2.21 Customized PHY Control Group 1 (Index: 8ch)
Configuration
Bit [4:0]
Bit [7:5]
Bit [12:8]
Bit [15:13]
ADMtek Inc.
Description
Register Address of the Command 2.
PHY Address of the Command 2 (Bit[5:3] in PHY Customized Enable Register =
3’b001 or 3’b011)
000 = The switch will write command 2 into Port 8 (PHY Address = 32’h10).
001 = The switch will write command 2 into Port 9 (PHY Address = 32’h11).
010 = The switch will write command 2 into Port 10 (PHY Address = 32’h12).
011 = The switch will write command 2 into Port 11 (PHY Address = 32’h13).
100 = The switch will write command 2 into Port 12 (PHY Address = 32’h14).
101 = The switch will write command 2 into Port 13 (PHY Address = 32’h15).
110 = The switch will write command 2 into Port 14 (PHY Address = 32’h16).
111 = The switch will write command 2 into Port 15 (PHY Address = 32’h17).
Register Address of the Command 3.
PHY Address of the Command 3 (Bit[5:3] in PHY Customized Enable Register =
3’b010 or 3’b011)
000 = The switch will write command 3 into Port 8 (PHY Address = 32’h10).
001 = The switch will write command 3 into Port 9 (PHY Address = 32’h11).
010 = The switch will write command 3 into Port 10 (PHY Address = 32’h12).
011 = The switch will write command 3 into Port 11 (PHY Address = 32’h13).
100 = The switch will write command 3 into Port 12 (PHY Address = 32’h14).
101 = The switch will write command 3 into Port 13 (PHY Address = 32’h15).
Default
5’b00000
3’b000
5’b00000
3’b000
3-31
ADM6926
Configuration
Function Description
Description
110 = The switch will write command 3 into Port 14 (PHY Address = 32’h16).
111 = The switch will write command 3 into Port 15 (PHY Address = 32’h17).
Default
3.2.22 Customized PHY Control Group 2 (Index: 8dh)
Configuration
Bit [4:0]
Bit [7:5]
Bit [12:8]
Bit [15:13]
Description
Register Address of the Command 4.
PHY Address of the Command 4 (Bit[8:6] in PHY Customized Enable Register =
3’b001 or 3’b011)
000 = The switch will write command 4 into Port 16 (PHY Address = 32’h18).
001 = The switch will write command 4 into Port 17 (PHY Address = 32’h19).
010 = The switch will write command 4 into Port 18 (PHY Address = 32’h1a).
011 = The switch will write command 4 into Port 19 (PHY Address = 32’h1b).
100 = The switch will write command 4 into Port 20 (PHY Address = 32’h1c).
101 = The switch will write command 4 into Port 21 (PHY Address = 32’h1d).
110 = The switch will write command 4 into Port 22 (PHY Address = 32’h1e).
111 = The switch will write command 4 into Port 23 (PHY Address = 32’h1f).
Register Address of the Command 5.
PHY Address of the Command 5 (Bit[8:6] in PHY Customized Enable Register =
3’b010 or 3’b011)
000 = The switch will write command 5 into Port 16 (PHY Address = 32’h18).
001 = The switch will write command 5 into Port 17 (PHY Address = 32’h19).
010 = The switch will write command 5 into Port 18 (PHY Address = 32’h1a).
011 = The switch will write command 5 into Port 19 (PHY Address = 32’h1b).
100 = The switch will write command 5 into Port 20 (PHY Address = 32’h1c).
101 = The switch will write command 5 into Port 21 (PHY Address = 32’h1d).
110 = The switch will write command 5 into Port 22 (PHY Address = 32’h1e).
111 = The switch will write command 5 into Port 23 (PHY Address = 32’h1f).
Default
5’b00000
3’b000
5’b00000
3’b000
3.2.23 Customized PHY Control Group 3 (Index: 8eh)
Configuration
Bit [4:0]
Bit [5]
Bit [12:8]
Bit [13]
Description
Register Address of the Command 6.
PHY Address of the Command 6 (Bit[11:9] in PHY Customized Enable Register =
3’b001 or 3’b011)
0 = The switch will write command 6 into Port 24 (PHY Address = 32’h6).
1 = The switch will write command 6 into Port 25 (PHY Address = 32’h7).
Register Address of the Command 7.
PHY Address of the Command 7 (Bit[11:9] in PHY Customized Enable Register =
3’b010 or 3’b011)
0 = The switch will write command 7 into Port 24 (PHY Address = 32’h6).
1 = The switch will write command 7 into Port 25 (PHY Address = 32’h7).
Default
5’b00000
3’b000
5’b00000
3’b000
3.2.24 Group 0 PHY Customized DATA 0 (Index: 8fh)
Configuration
Bit [15:0]
Description
Data for Command 0
Default
0000h
3.2.25 Group 0 PHY Customized DATA 1 (Index: 90h)
Configuration
Bit [15:0]
ADMtek Inc.
Description
Data for Command 1
Default
0000h
3-32
ADM6926
Function Description
3.2.26 Group 1 PHY Customized DATA 0 (Index: 91h)
Configuration
Bit [15:0]
Description
Default
0000h
Data for Command 2
3.2.27 Group 1 PHY Customized DATA 1 (Index: 92h)
Configuration
Bit [15:0]
Description
Default
0000h
Data for Command 3
3.2.28 Group 2 PHY Customized DATA 0 (Index: 93h)
Configuration
Bit [15:0]
Description
Default
0000h
Data for Command 4
3.2.29 Group 2 PHY Customized DATA 1 (Index: 94h)
Configuration
Bit [15:0]
Description
Default
0000h
Data for Command 5
3.2.30 Group 3 PHY Customized DATA 0 (Index: 95h)
Configuration
Bit [15:0]
Description
Default
0000h
Data for Command 6
3.2.31 Group 3 PHY Customized DATA 1 (Index: 96h)
Configuration
Bit [15:0]
Description
Default
0000h
Data for Command 7
3.2.32 PHY Customized Enable Register (Index: 97h)
Configuration
Bit[2:0]
Bit[5:3]
Bit[8:6]
ADMtek Inc.
Description
PHY Customized Enable For Group 0.
000 = Disable writing additional commands into any PHYs in Group 0.
001 = Write command 0 into related port specified by the Customized
Group 0.
010 = Write command 1 into related port specified by the Customized
Group 0.
100 = Disable writing additional commands into any PHYs in Group 0.
101 = Write command 0 into all PHYs in Group 0.
110 = Write command 1 into all PHYs in Group 0.
111 = Write command 0 and command 1 into all PHYs in Group 0.
PHY Customized Enable For Group 1.
000 = Disable writing additional commands into any PHYs in Group 1.
001 = Write command 2 into related port specified by the Customized
Group 1.
010 = Write command 3 into related port specified by the Customized
Group 1.
100 = Disable writing additional commands into any PHYs in Group 1.
101 = Write command 2 into all PHYs in Group 1.
110 = Write command 3 into all PHYs in Group 1.
111 = Write command 2 and command 3 into all PHYs in Group 1.
PHY Customized Enable For Group 2.
000 = Disable writing additional commands into any PHYs in Group 2.
001 = Write command 4 into related port specified by the Customized
Default
3’b000
PHY Control
PHY Control
3’b000
PHY Control
PHY Control
3’b000
PHY Control
3-33
ADM6926
Configuration
Bit[11:9]
Function Description
Description
Group 2.
010 = Write command 5 into related port specified by the Customized PHY Control
Group 2.
100 = Disable writing additional commands into any PHYs in Group 2.
101 = Write command 4 into all PHYs in Group 2.
110 = Write command 5 into all PHYs in Group 2.
111 = Write command 5 and command 5 into all PHYs in Group 2.
PHY Customized Enable For Group 3.
000 = Disable writing additional commands into any PHYs in Group 3.
001 = Write command 6 into related port specified by the Customized PHY Control
Group 3.
010 = Write command 7 into related port specified by the Customized PHY Control
Group 3.
100 = Disable writing additional commands into any PHYs in Group 3.
101 = Write command 6 into all PHYs in Group 3.
110 = Write command 7 into all PHYs in Group 3.
111 = Write command 6 and command 7 into all PHYs in Group 3.
Default
3’b000
3.2.33 PPPOE Control Register0 (Index: 98h)
Configuration
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit [10]
Bit [11]
Bit [12]
Bit[13]
Bit[14]
Bit[15]
Description
Enable Port 0 to Transmit PPPoE Packet Only. The ADM6926 will recognize packets
with length-type = 16’h8863 or 16’h8864 as the PPPOE packets.
1 = The port 0 is configured to transmit PPPOE packets only.
0 = The port 0 is not configured to transmit PPPOE packets only.
Enable Port 1 to Transmit PPPoE Packet Only.
Enable Port 2 to Transmit PPPoE Packet Only.
Enable Port 3 to Transmit PPPoE Packet Only.
Enable Port 4 to Transmit PPPoE Packet Only.
Enable Port 5 to Transmit PPPoE Packet Only.
Enable Port 6 to Transmit PPPoE Packet Only.
Enable Port 7 to Transmit PPPoE Packet Only.
Enable Port 8 to Transmit PPPoE Packet Only.
Enable Port 9 to Transmit PPPoE Packet Only.
Enable Port 10 to Transmit PPPoE Packet Only.
Enable Port 11 to Transmit PPPoE Packet Only.
Enable Port 12 to Transmit PPPoE Packet Only.
Enable Port 13 to Transmit PPPoE Packet Only.
Enable Port 14 to Transmit PPPoE Packet Only.
Enable Port 15 to Transmit PPPoE Packet Only.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.34 PPPOE Control Register 1 (Index: 99h)
Configuration
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit[10]
ADMtek Inc.
Description
Enable Port 16 to Transmit PPPoE Packet Only.
Enable Port 17 to Transmit PPPoE Packet Only.
Enable Port 18 to Transmit PPPoE Packet Only.
Enable Port 19 to Transmit PPPoE Packet Only.
Enable Port 20 to Transmit PPPoE Packet Only.
Enable Port 21 to Transmit PPPoE Packet Only.
Enable Port 22 to Transmit PPPoE Packet Only.
Enable Port 23 to Transmit PPPoE Packet Only.
Enable Port 24 to Transmit PPPoE Packet Only.
Enable Port 25 to Transmit PPPoE Packet Only.
Enable Management Packet Cross PPPOE PORT Function.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-34
ADM6926
Configuration
Function Description
Description
1 = Management packets could be transmitted by any port even if it is configured to
PPPOE port.
0 = Management packets could not be transmitted by the PPPOE port.
Default
3.2.35 PHY Control Register 0 (Index: 9ah)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Description
1 = PHY attached to port 0 acts as the master. That is the switch will not configure
the PHY attached and it will only poll the PHY to know the state that PHY
operates.
0 = PHY acts as the slave. The switch will use the setting in the eeprom register to
manage PHY attached.
1 = PHY attached to port 1 acts as the master.
0 = PHY acts as the slave
1 = PHY attached to port 2 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 3 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 4 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 5 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 6 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 7 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 8 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 9 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 10 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 11 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 12 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 13 acts as the master
0 = PHY acts as the slave.
1 = PHY attached to port 14 acts as the master.
0 = PHY acts as the slave.
1 = PHY attached to port 15 acts as the master.
0 = PHY acts as the slave.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.36 PHY Control Register 1 (Index: 9bh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
ADMtek Inc.
Description
1 = PHY attached to port 16 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 17 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 18 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 19 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 20 acts as the master.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
3-35
ADM6926
Configuration
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Function Description
Description
0 = PHY actives as the slave.
1 = PHY attached to port 21 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 22 acts as the master
0 = PHY actives as the slave.
1 = PHY attached to port 23 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 24 acts as the master.
0 = PHY actives as the slave.
1 = PHY attached to port 25 acts as the master.
0 = PHY actives as the slave.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.37 Disable MDIO Active Register 0 (Index: 9ch)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Description
Port 0 Bypass MDIO Function Enable.
1 = Bypass MDIO Enable. The effect by the function is as follows:
1.2 Link Status: Port 0 is forced to link up unless the port is disabled or the
spanning tree is in disabled state.
1.3 Speed Status: Port 0 is configured to Bit [6] in the Port Configuration
Register.
1.4 Duplex Status: Port 0 is configured to Bit [7] in the Port Configuration
Register.
1.5 Pause Status: Port 0 is configured to Bit [4] in the Port Configuration
Register.
1.6 Back Pressure Status. Port 0 is configured to Bit[15] in the Port
Configuration Register.
0 = Bypass MDIO Disable. The status is dominated by the MDC/MDIO function
except the linkup status, which may be disabled, by the port disable function or
the spanning protocol.
Port 1 Bypass MDIO Function Enable.
Port 2 Bypass MDIO Function Enable.
Port 3 Bypass MDIO Function Enable.
Port 4 Bypass MDIO Function Enable.
Port 5 Bypass MDIO Function Enable.
Port 6 Bypass MDIO Function Enable.
Port 7 Bypass MDIO Function Enable.
Port 8 Bypass MDIO Function Enable.
Port 9 Bypass MDIO Function Enable.
Port 10 Bypass MDIO Function Enable.
Port 11 Bypass MDIO Function Enable.
Port 12 Bypass MDIO Function Enable.
Port 13 Bypass MDIO Function Enable.
Port 14 Bypass MDIO Function Enable.
Port 15 Bypass MDIO Function Enable.
default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.38 Disable MDIO Active Register 1 (Index: 9dh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
ADMtek Inc.
Description
Port 16 Bypass MDIO Function Enable.
Port 17 Bypass MDIO Function Enable.
Port 18 Bypass MDIO Function Enable.
Port 19 Bypass MDIO Function Enable.
Port 20 Bypass MDIO Function Enable.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
3-36
ADM6926
Configuration
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Function Description
Description
Port 21 Bypass MDIO Function Enable.
Port 22 Bypass MDIO Function Enable.
Port 23 Bypass MDIO Function Enable.
Port 24 Bypass MDIO Function Enable.
Port 25 Bypass MDIO Function Enable.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.39 Port Disable Register 0 (Index: 9eh)
Configuration
Bit [0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Description
Port 0 Disable Receive and Transmit.
1 = The port will not receive or transmit packets. Learning is disabled in the disabled
port.
0 = The port acts as the normal mode.
Port 1 Disable Receive and Transmit.
Port 2 Disable Receive and Transmit.
Port 3 Disable Receive and Transmit.
Port 4 Disable Receive and Transmit.
Port 5 Disable Receive and Transmit.
Port 6 Disable Receive and Transmit.
Port 7 Disable Receive and Transmit.
Port 8 Disable Receive and Transmit.
Port 9 Disable Receive and Transmit.
Port 10 Disable Receive and Transmit.
Port 11 Disable Receive and Transmit.
Port 12 Disable Receive and Transmit.
Port 13 Disable Receive and Transmit.
Port 14 Disable Receive and Transmit.
Port 15 Disable Receive and Transmit.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.40 Port Disable Register 1 (Index: 9fh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Description
Port 16 Disable Receive and Transmit.
Port 17 Disable Receive and Transmit.
Port 18 Disable Receive and Transmit.
Port 19 Disable Receive and Transmit.
Port 20 Disable Receive and Transmit.
Port 21 Disable Receive and Transmit.
Port 22 Disable Receive and Transmit.
Port 23 Disable Receive and Transmit.
Port 24 Disable Receive and Transmit.
Port 25 Disable Receive and Transmit.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.41 IGMP Snooping Control Register 0 (Index: a0h)
Configuration
Bit [0]
Bit[1]
ADMtek Inc.
Description
Port 0 Enable IGMP Snooping Function. The packets with the header (DA =
01005exxxxxx, Length_Type = 0800, IP version = 4, and Protocol type = 2) will be
recognized as the IGMP packets, and the switch will forward it to the CPU port.
1 = The port 0 is configured to enable IGMP Snooping Function.
The port 0 is not configured to enable IGMP Snooping Function. And the IGMP
packets will be handled as the normal multicast packets.
Port 1 Enable IGMP Snooping Function.
Default
1’b0
1’b0
3-37
ADM6926
Configuration
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Function Description
Description
Port 2 Enable IGMP Snooping Function.
Port 3 Enable IGMP Snooping Function.
Port 4 Enable IGMP Snooping Function.
Port 5 Enable IGMP Snooping Function.
Port 6 Enable IGMP Snooping Function.
Port 7 Enable IGMP Snooping Function.
Port 8 Enable IGMP Snooping Function.
Port 9 Enable IGMP Snooping Function.
Port 10 Enable IGMP Snooping Function.
Port 11 Enable IGMP Snooping Function.
Port 12 Enable IGMP Snooping Function.
Port 13 Enable IGMP Snooping Function.
Port 14 Enable IGMP Snooping Function.
Port 15 Enable IGMP Snooping Function.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.42 IGMP Snooping Control Register 1 (Index: a1h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[11:10]
Description
Port 16 Enable IGMP Snooping Function.
Port 17 Enable IGMP Snooping Function.
Port 18 Enable IGMP Snooping Function.
Port 19 Enable IGMP Snooping Function.
Port 20 Enable IGMP Snooping Function.
Port 21 Enable IGMP Snooping Function.
Port 22 Enable IGMP Snooping Function.
Port 23 Enable IGMP Snooping Function.
Port 24 Enable IGMP Snooping Function.
Port 25 Enable IGMP Snooping Function.
Multicast Control Register. Packets with the following conditions will follow the
Multicast Control Register to handle packets.
Conditions:
Destination address is not found in the address table. AND
2. Destination address is a multicast address. AND
Destination address is not all 1’b1. AND
Destination address is not a reserved address(0180c2000~~). OR
IGMP packets received by the port which disables the IGMP function.
Multicast Control Action
00 =
Forward to all ports within the same forwarding group except the self port.
01 =
Send to the CPU port.
10 =
Discard.
11 =
Reserved.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.43 CPU Control Register (Index: a2h)
Configuration
Bit [4:0]
ADMtek Inc.
Description
CPU Port Number. The ADM6926 allows any port to be configured to be the CPU port.
The default CPU port is port 31. That is CPU port is not present.
00000 = CPU port is configured to port 0.
00010 = CPU port is configured to port 2.
00001 = CPU port is configured to port 1.
00011 = CPU port is configured to port 3.
00100 = CPU port is configured to port 4
00110 = CPU port is configured to port 6.
00101 = CPU port is configured to port 5.
00111 = CPU port is configured to port 7.
Default
5’b11111
3-38
ADM6926
Configuration
Function Description
Description
01000 = CPU port is configured to port 8. 01001 = CPU port is configured to port 9.
01010 = CPU port is configured to port 10. 01011 = CPU port is configured to port 11.
01100 = CPU port is configured to port 12
01110 = CPU port is configured to port 14.
10000 = CPU port is configured to port 16.
10010 = CPU port is configured to port 18.
10100 = CPU port is configured to port 20
10110 = CPU port is configured to port 22.
11000 = CPU port is configured to port 24
Bit[5]
Bit[6]
Bit[7]
Bit[10:8]
Bit [12:11]
Bit [13]
Default
01101 = CPU port is configured to port 13.
01111 = CPU port is configured to port 15.
10001 = CPU port is configured to port 17.
10011 = CPU port is configured to port 19.
10101 = CPU port is configured to port 21.
10111 = CPU port is configured to port 23.
11001 = CPU port is configured to port 25.
Enable receive 8-byte special tag from the CPU port to support IGMP snooping,
spanning tree or the security function.
1 = CPU will transmit packets with additional 8-byte special TAG and the ADM6926
will remove this special TAG, use information contained to forward packets and
recalculate CRC value when this packet is re-transmitted.
0 = CPU will transmit packets as the normal state.
Enable transmit 4-byte special tag to the CPU port to support IGMP snooping, spanning
tree or the security function.
1 = ADM6926 will insert addition 4-byte special TAG when it has packets to be
transmitted to the CPU port.
0 = ADM6926 will transmit packets as the normal mode.
Enable insert 4-byte special tag when Pause happens and Bit[6] is enabled.
1 = ADM6926 will add 4-byte special TAG when pause happens.
0 = ADM6926 will add 4-byte special TAG when pause happens.
Reserved.
Learning Group. ADM6926 has an ability to learn packets according their forwarding
groups. The ADM6926 could be divided into 32 learning groups. We use L0, L1, …and
L31 to call each learning group.
0x = Normal mode, learning with SA only
10 = MAC Clone mode, learning with SA and VID[0]. When packets are received and
could be learned, they are learned divided into two Groups. Even forwarding
groups are learned into L0 and odd forwarding groups are learned into L1.
11 = Learning with SA and VID[4:0]. When packets are received and could be learned,
they are learned according to their forwarding group. That is packets belonging to
F0 is learned into L0, packets belonging to F1 is learned into L1,.., and packets
belonging to F31 is leaned into L31.
Disable CPU Port Learning Function.
1 = The packets received from the CPU port will not be learned.
0 = The packets received from the CPU port will be learned.
1’b0
1’b0
1’b0
3’b000
2’b00
1’b0
3.2.44 Special MAC Forward Control Register 0 (Index: a3h)
Configuration
Bit[1:0]
Bit[3:2]
Bit[5:4]
Bit[7:6]
Bit[9:8]
Bit[11:10]
Bit[13:12]
Bit[15:14]
ADMtek Inc.
Description
The forwarding option for destination address = 48’h0180c2000000 (BPDU)
The forwarding option for destination address = 0180c2000001 (Reserved for Pause
address), MAC control field = 8808, OP Code != 0001.
The forwarding option for destination address = 48’h0180c2000002 (Slow Protocol)
The forwarding option for destination address = 0180c2000003 (802.1x PAE address)
The forwarding option for destination address = 0180c2000004 ~0180c200000f
The forwarding option for destination address = 0180c2000010~0180c200001f
The forwarding option for destination address = 0180c2000020~0180c2000022
(GMRP, GVRP, GARP)
The forwarding option for destination address = 0180c2000023~0180c20000ff
Default
2’b00
2’b01
2’b00
2’b00
2’b00
2’b00
2’b00
2’b00
3-39
ADM6926
Function Description
Note:
1. The options are defined here:
00 = The switch will forward the packets as the normal mode. That is for reserved
addresses existed in the learning table (because reserved address is multicast address,
it could only be created through the CPU help if it really exists in the learning table).
We will use “output port field” as the index to lookup the multicast table. At last, the
looked output port map (may be modified by the forwarding process) is used as the
output ports to forward packets. For reserved addresses, which don’t exist in the
learning table, it will be broadcast to the forwarding group except the receiving port.
01 = The switch will discard the packets.
10 = The switch will forward the packets to the CPU port. If the packet is received
from the CPU port, the packet will be forwarded as the normal mode.
11 = The switch will forward the packet to CPU port. If this packet is received from
CPU Port, this packet will be discard.
2. The forwarding options stated above will be of no effect for the CPU port when users
enable the “Special Tag Function” and its output vector field is valid.
3.2.45 Special MAC Forward Control Register 2 (Index: a4h)
Configuration
Bit[1:0]
Bit[3:2]
Bit[5:4]
Bit[7:6]
Bit[9:8]
Bit[11:10]
Bit[13:12]
Bit[15:14]
Description
The forwarding option for destination address = 48’h0180c2000000 (BPDU)
Reserved.
The forwarding option for destination address = 48’h0180c2000002 (Slow Protocol)
The forwarding option for destination address = 0180c2000003 (802.1x PAE address)
The forwarding option for destination address = 0180c2000004 ~0180c200000f
The forwarding option for destination address = 0180c2000010~0180c200001f
The forwarding option for destination address = 0180c2000020~0180c2000022
(GMRP, GVRP, GARP)
The forwarding option for destination address = 0180c2000023~0180c20000ff
Default
2’b11
2’b00
2’b00
2’b00
2’b00
2’b00
2’b00
2’b00
Note:
The ADM6926 will divide packets into management or unmanagement packets.
Management packets will not be dropped even if the buffer is full for no flow control
environment. Only management packets will be forwarded or received in Blocking-NListening or the Learning state.
The options are defined here:
00 = The packets will not be classified as the management packets and it will be treated
as the normal packet.
01 = The packets will be classified as the management packets and it will be transmitted
no modified.
10 = The packets will be classified as the management packets and it will be transmitted
without tag.
11 = The packets will be classified as the management packets and it will be transmitted
with tag or without tag as the system configuration.
3.2.46 Special MAC Forward Control Register 2 (Index: a5h)
Configuration
Bit[0]
Bit[1]
ADMtek Inc.
Description
The forwarding option for destination address = 48’h0180c2000000 (BPDU)
Reserved.
Default
1’b0
1’b0
3-40
ADM6926
Function Description
Configuration
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Description
The forwarding option for destination address = 48’h0180c2000002 (Slow Protocol)
The forwarding option for destination address = 0180c2000003 (802.1x PAE address)
The forwarding option for destination address = 0180c2000004 ~0180c200000f
The forwarding option for destination address = 0180c2000010~0180c200001f
The forwarding option for destination address = 0180c2000020~0180c2000022
(GMRP, GVRP, GARP)
The forwarding option for destination address = 0180c2000023~0180c20000ff
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
Note:
The options are defined here:
1 = The packets will cross forwarding group.
0 = The packets will not cross the forwarding packet.
3.2.47 Trunking Enable Register 0 (Index: a6h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Description
Port 0 Trunking Enable. The ADM6926 supports one trunking port. Any port could
be assigned to the trunking port. The trunking function is of the effect only the
trunking hardware setting = 1.
1 = Port 0 is assigned to a member of the trunking port.
0 = Port 0 is not assigned to a member of the trunking port.
1 Trunking Enable.
2 Trunking Enable.
3 Trunking Enable.
4 Trunking Enable.
5 Trunking Enable.
6 Trunking Enable.
7 Trunking Enable.
8 Trunking Enable.
9 Trunking Enable.
10 Trunking Enable.
11 Trunking Enable.
12 Trunking Enable.
13 Trunking Enable.
14 Trunking Enable.
15 Trunking Enable.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.2.48 Trunking Enable Register 1 (Index: a7h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
ADMtek Inc.
Description
16 Trunking Enable.
17 Trunking Enable.
18 Trunking Enable.
19 Trunking Enable.
20 Trunking Enable.
21 Trunking Enable.
22 Trunking Enable.
23 Trunking Enable.
24 Trunking Enable.
25 Trunking Enable.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-41
ADM6926
3.3
Function Description
Switch Register Map
Offset Hex
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
ah
bh
ch
dh
eh
fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1ah
1bh
1ch
1dh
1eh
1fh
1xxh
2xxh
Bit 31 ~ 0
Version ID
Link Status
Speed Status
Duplex Status
Flow Control Status
Address Table Control Register 0
Address Table Control Register 1
Address Table Control Register 2
Address Table Status Register 0
Address Table Status Register 1
Address Table Status Register 2
PHY Control/Status Register
Reserved
Hardware Status
RxPKT Overflow
RxLEN Oveflow
TxPKT Oveflow
TxLEN Overflow
RxERR Overflow
RxCOL Overflow
Renew Counter Register
Read Counter Control Register
Read Counter Status Register
Reload MDIO Register
P0 ~ P15 Spanning Tree Port State
P16 ~ P25 Spanning Tree Port State
Source Port Register
Transmit Port Register
Buffer Status Register 0
Buffer Status Register 1
Buffer Status Register 2
Buffer Status Register 3
Counter Register
EEPROM Register
Type
RO
RO
RO
RO
RO
RW
RW
RW
RO
RO
RO
RW
RO
RO
ROC
ROC
ROC
ROC
ROC
ROC
RW
RW
RO
RW
RW
RW
RO
RW
ROC
ROC
ROC
ROC
RW
RW
3.3.1 Version ID (Offset: 0h)
Configuration
Bit[19:4]
Bit[3:0]
3.3.2
Description
Project Code
Version Code
Default
16’h3110
4’h0
Link Status (Offset: 1h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
ADMtek Inc.
Description
Port 0 Link Status
1 = Port 0 links up.
0 = Port 0 links down.
Port 1 Link Status
Port 2 Link Status
Port 3 Link Status
Port 4 Link Status
Port 5 Link Status
Port 6 Link Status
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-42
ADM6926
Function Description
Configuration
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
3.3.3
Description
Port 7 Link Status
Port 8 Link Status
Port 9 Link Status
Port 10 Link Status
Port 11 Link Status
Port 12 Link Status
Port 13 Link Status
Port 14 Link Status
Port 15 Link Status
Port 16 Link Status
Port 17 Link Status
Port 18 Link Status
Port 19 Link Status
Port 20 Link Status
Port 21 Link Status
Port 22 Link Status
Port 23 Link Status
Port 24 Link Status
Port 25 Link Status
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
Speed Status (Offset: 2h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
ADMtek Inc.
Description
Port 0 Speed Status
1 = Port 0 operates in 100M.
0 = Port 0 operates in 10M.
Port 1 Speed Status
Port 2 Speed Status
Port 3 Speed Status
Port 4 Speed Status
Port 5 Speed Status
Port 6 Speed Status
Port 7 Speed Status
Port 8 Speed Status
Port 9 Speed Status
Port 10 Speed Status
Port 11 Speed Status
Port 12 Speed Status
Port 13 Speed Status
Port 14 Speed Status
Port 15 Speed Status
Port 16 Speed Status
Port 17 Speed Status
Port 18 Speed Status
Port 19 Speed Status
Port 20 Speed Status
Port 21 Speed Status
Port 22 Speed Status
Port 23 Speed Status
Port 24 Speed Status
Port 25 Speed Status
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
3-43
ADM6926
Function Description
3.3.4 Duplex Status (Offset: 3h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
3.3.5
Description
Port 0 Duplex Status
1 = Port 0 operates in full duplex.
0 = Port 0 operates in half duplex.
Port 1 Duplex Status
Port 2 Duplex Status
Port 3 Duplex Status
Port 4 Duplex Status
Port 5 Duplex Status
Port 6 Duplex Status
Port 7 Duplex Status
Port 8 Duplex Status
Port 9 Duplex Status
Port 10 Duplex Status
Port 11 Duplex Status
Port 12 Duplex Status
Port 13 Duplex Status
Port 14 Duplex Status
Port 15 Duplex Status
Port 16 Duplex Status
Port 17 Duplex Status
Port 18 Duplex Status
Port 19 Duplex Status
Port 20 Duplex Status
Port 21 Duplex Status
Port 22 Duplex Status
Port 23 Duplex Status
Port 24 Duplex Status
Port 25 Duplex Status
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
Flow Control Status (Offset: 4h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
ADMtek Inc.
Description
Port 0 Flow Control Status
rt 0 enables Pause function in full duplex or Back Pressure function in half duplex.
0 = Port 0 disables flow control function.
Port 1 Flow Control Status
Port 2 Flow Control Status
Port 3 Flow Control Status
Port 4 Flow Control Status
Port 5 Flow Control Status
Port 6 Flow Control Status
Port 7 Flow Control Status
Port 8 Flow Control Status
Port 9 Flow Control Status
Port 10 Flow Control Status
Port 11 Flow Control Status
Port 12 Flow Control Status
Port 13 Flow Control Status
Port 14 Flow Control Status
Port 15 Flow Control Status
Port 16 Flow Control Status
Port 17 Flow Control Status
Port 18 Flow Control Status
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
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ADM6926
Function Description
Configuration
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Description
Port 19 Flow Control Status
Port 20 Flow Control Status
Port 21 Flow Control Status
Port 22 Flow Control Status
Port 23 Flow Control Status
Port 24 Flow Control Status
Port 25 Flow Control Status
Default
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
3.3.6 Address Table Control and Status Register
Address Table Control Register 0 (Offset: 5h), Address Table Control Register 1 (Offset: 6h),
Address Table Control Register 2 (Offset: 7h), Address Table Status Register 0 (Offset: 8h),
Address Table Status Register 1 (Offset: 9h), Address Table Status Register 2 (Offset: ah)
The ADM6926 provides custom commands to access the address table as well as the multicast output port
map table. Six registers are used and they mean differently when different tables are accessed.
3.3.6.1 Control and status register for the address table.
1. The Control and Status Register description
Control Register Description
Command Field Entry State
Control_2
[2:0]
ADMtek Inc.
Control_1
[31:30]
Control Field
Control_1
[29:26]
Output Port/
Forwarding Group
MAC Address
Multicast Index
Control_l
Control_1
{Control_1[15:0], Control_0[31:0]}
[25:21]
[20:16]
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ADM6926
Function Description
Field Description in the Control Register
Description
This field is 48-bit layer 2 address. The address could be the unicast address or the multicast
address.
Forwarding Group[4:0] This field describes the Learning Group the address belongs to.
Output Port[4:0]/
This field has two means. One is described as the output port and the other is described as the
Multicast Index[4:0] multicast index.
Entry State[0]
The Static Bit. When this bit is set to a one, then the address entry will not be aged forever. This bit
could be changed only through the CPU’s help.
Entry State[1]
This bit is used to distinguish the output port/ multicast index field.
When a match (the same MAC address and the same forwarding group in the address table) is
found, the value in the output port field is returned as the output port, and may be modified by the
forwarding group before the packet is transferred to the output queue.
When a match (the same MAC address and the same forwarding group in the address table) is
found, the multicast output port map entry addressed by the multicast index is returned as the output
port map, and may be modified by the forwarding group before the packet is transferred to the
output queue.
Field
MAC Address[47:0]
Command Field[2:0]/ The command and control fields are combined to provide different operations. Before the operation
Control Field[3:0] is initiated, users should confirm if the search engine is available. See the busy bit in the status
register.
Command Field
Control Field
000
000
001
0111
1111
1111
010
010
0000
1001
010
1010
010
010
010
010
010
011
011
1100
1110
1101
1011
1111
0100
0000
Operation
Create a new address
Overwrite an existed address
Erase an existed address
Search an empty address
Search by the port in the Output Port field
Search by the forwarding group specified in the Forwarding
Group field
Search by the address specified in the MAC Address field.
Search by the address and forwarding group
Search by the address and output port
Search by the forwarding group and the output port
Search by the address, the forwarding group and the output port
Initial to location by the address field
Initial to the first address
Status Register Description
Busy
Status_2
[3]
ADMtek Inc.
Command
Result
Status_2
[2:0]
Bad State Entry State Occupy
Status_1
[29]
Status_1
[28:27]
Output Port/ Forwarding
MAC Address
Multicast Index
Group
Status_1
Status_1
Status_1
{Status_1[15:0], Status_0[31:0]}
[26]
[25:21]
[20:16]
3-46
ADM6926
Function Description
Field Description in the Status Register
Description
After the search operation is successful, the switch will return the MAC address in this field. If the
search fails, this field doesn’t mean anything.
Forwarding Group[4:0] After the search operation is successful, the switch will return the Forwarding Group in this. If the
search fails, this field doesn’t mean anything.
Output Port[4:0]/
After the search operation is successful, the switch will return output port / multicast index in this
Multicast Index[4:0] field. The users could use the entry_state[1] returned to distinguish if the entry should point to the
multicast output port map table.
Occupy
After the search is successful, the switch will return the value indicating if the entry existed.
1 = The searched entry exists.
0 = The searched entry doesn’t exist.
Entry State[0]
After the search is successful, the switch will return the value in this field indicating if value is
static.
1 = The searched entry is static.
0 = The searched entry is not static and will be aged.
Entry State[1]
After the search is successful, the switch will return the value in this field indicating if the entry
points to the multicast output port map table.
1 = The entry points to the multicast output port map table.
0 = The entry doesn’t point to the multicast output port map table.
Bad State
After the search is successful, the switch will return the value indicating if the entry is bad.
1 = The entry is bad and isn’t used for data storage.
0 = The entry is not bad and will be used for data storage.
Command Result[2:0] This field indicates the access result.
000 = Command OK
001 = All Entry Used. This result happens only for the create operation. ADM6926 uses the 4-way
address lookup engine so it allows 4 different addresses stored at each hash location. If
these 4 entries are all static, then CPU will not successfully create 5th different address
hashed to the same location and 001 will be returned. The only way to create 5th different address is
to remove one of early addresses.
010 = Entry Not Found.
011 = Try Next Entry.
101 = Command Error.
Busy
This bit indicates if the table engine for access is available.
1 = The engine is busy and it will not access the command from the CPU.
0 = The engine is available.
Field
MAC Address[47:0]
2. Rules to access the address table
2.1 Check the Busy Bit in the status register to see if the access engine is available. If the
engine is busy, wait until the
engine is free. If the engine is available, go to the following step.
2.2 Write the MAC address[31:0] into the control register 0.
2.3 Write the MAC address[47:32], Forwarding Group, Output Port/Multicast Index,
Control Field and the Entry State
into the control register 1.
2.4 Write the Command into the control register 2 to define the operation.
2.5 Wait for the engine to complete (Check the Busy Bit).
2.6 Read the desired result returned in the status register.
Note: Before the “Search command”, the CPU should execute the “Initial command” to
initial the search pointer. The search engine could search the aim from the top to the
bottom. The search engine has an ability to automatically move the pointer to the
ADMtek Inc.
3-47
ADM6926
Function Description
associated location (The result will be returned). Because more than one entry may match
the searching condition (by port, by address, etc) at the same time, the CPU should
continue to restart the search engine until the Command Result = Entry Not is found to
confirm that no other matching entries exist.
Initial to first address
(Pointer jum ps to M AC 0)
Address after hashed
0
M AC0
M AC1
M AC2
M AC3
1
M AC4
M AC5
M AC6
M AC7
2
M AC8
M AC9
M AC10
M AC11
Initial to M AC8, M AC9, M AC10, M AC11
(Pointer jum ps to M AC8)
1021
1022
1023
M AC
4084
M AC
4088
M AC
4092
M AC
4085
M AC
4089
M AC
4093
M AC
4086
M AC
4090
M AC
4094
M AC
4087
M AC
4091
M AC
4095
Figure 3-1 The Search Pointer
3. Example
Example
The user needs ADM6926 to
forward the specified unicast packet
(DA = 48’h0012_3456_789a and
Forwarding Group = 2) to port 3
forever.
Step
Step 1: Check the Busy bit. If Busy = 1’b0, go to the step 2. If Busy = 1’b1, wait.
Step 2: Write 32’h3456_789a into control register 0.
Step 3: Write 32’h5c62_0012 into the control register 1.
Step 4: Write 32’h0 into the control register 2 to start the “Create” operation.
Step 5: Read the status register 2 to check the busy bit. If Busy = 1’b0, check the
Command Result to see if the create operation is successful. If Busy = 1’b1, wait for
completion.
The user needs the ADM6926 to
Step 1: Check the Busy bit. If Busy = 1’b0, go to the step 2. If Busy = 1’b1, wait.
forward the specified multicast
Step 2: Write 32’h4567_89ab into control register 0.
packet (DA = 48’h0123_4567_89ab Step 3: Write 32’h1ca3_0123 into the control register 1.
and Forwarding Group = 3) to port 5 Step 4: Write 32’h0 into the control register 2 to start the “Create” operation.
only. This address could be aged.
Step 5: Read the status register 2 to check the busy bit. If Busy = 1’b0, check the
Command Result to see if the create operation is successful. If Busy = 1’b1, wait for
completion.
ADMtek Inc.
3-48
ADM6926
Function Description
Example
The user wants to know how many
stations attached to port 4.
Step
Step 1: Check the Busy bit. If Busy = 1’b0, go to the step 2. If Busy = 1’b1, wait.
Step 2: Write 32’h0000_0000 into control register 1.
Step 3: Write 32’h0000_0003 into control register 2 to start the “Initial to the first
address” operation.
Step 4: Read the status register 2 to check the busy bit. If Busy = 1’b0, check the
Command Result to see if the initial operation is successful. If Busy = 1’b1, wait for
completion.
Step 5: Write 32’h2480_0000 into control register 1.
Step 6: Write 32’h0000_0002 into control register 2 to start the “Search by port”
operation.
Step 7: Read the status register 2 to check the busy bit. If Busy = 1’b0, check the
Command Result to see if the search operation is successful (the Mac address attached
to port 4 could be derived from the MAC address in the status register). If Busy = 1’b1,
wait for completion.
Step 8: If Command Result = “Command OK”, it means some other MAC addresses
attached to port 4 may exist. We should restart the “Search by port” command again to
let the search engine to look another addresses.
Step 9: If the Command Result = “Entry Not Found”, it means no other addresses
attached to port 4 exist.
3.3.6.2 Control and status register for the multicast output port map table.
1. The Control and Status Register description
Control Register Description
Command Field
Multicast Index
Output Port Map
Control_2[2:0]
Control_0[30:26]
Control_0[25:0]
Field
Output Port Map
Multicast Index
Command Field
ADMtek Inc.
Field Description in the Control Register
Description
This field describes the output ports associated with the multicast index.
Bit [0] is for port 0, Bit[1] is for port 1,.., and Bit[25] for port 25.
See Figure 3.3.6.2.
100 = Create an entry in the output port map table (indexed by the Multicast Index).
101= Search an entry in the output port map table (indexed by the Multicast Index).
3-49
ADM6926
Function Description
Multicast Output Port Map Table
Multicast
Index
Address Table
25 24
~~
2 1
0
0
1
Entry State[1] = 0
Output Port
Unicast Addr
Entry State[1] = 0
Output Port
Unicast Addr
Entry State[1] = 1
Multicast Index = 2
Multicast Addr
Entry State[1] = 0
Output Port
Unicast Addr
Entry State[1] = 0
Output Port
Unicast Addr
Entry State[1] = 0
Output Port
Unicast Addr
2
Output Port Map
30
31
Figure 3-2 Address Table Mapping to Output Port MAP
Status Register Description
Busy
Command Result
Output Port Map
Status_2[3]
Status_2[2:0]
Status_0[25:0]
Field
Output Port Map
Command Result
Busy
Field Description in the Status Register
Description
The content associated with the multicast index will be here after searching.
000 = Command OK
This bit indicates if the output port map engine is available.
1 = The engine is busy and it will not access the command from the CPU.
0 = The engine is available.
2. Rules to access the multicast output port map table
2.1 Check the Busy Bit to see if the access engine is available. If the engine is busy, wait
until the engine is free. If the engine is available, go to the following step.
2.2 Write output port map and the multicast index into the control register 0.
2.3 Write the command into the control register 2.
2.4 Read the Busy Bit. If Busy = 1’b1, wait. If Busy = 1’b0, the operation completes.
ADMtek Inc.
3-50
ADM6926
Function Description
3. Example
Example
The user needs the ADM6926 to
forward the specified multicast
packet (DA = 48’h0123_4567_89ab
and Forwarding Group = 3) to port
1, port2 and port 25. This address
could be aged. We assume the CPU
wants to write output port map into
index 1.
3.3.7
Step
Step 1: Check the Busy bit. If Busy = 1’b0, go to the step 2. If Busy = 1’b1, wait.
Step 2: Write 32’h0060_0006 into control register 0.
Step 3: Write 32’h0000_0004 into control register 2 start the “Write” command.
Step 4: Check the Busy bit. If Busy = 1’b1, wait. If Busy = 1’b1, go to the next step.
Step 5: Write 32’h4567_89ab into control register 0.
Step 6: Write 32’h9c23_0123 into the control register 1.
Step 7: Write 32’h0 into the control register 2 to start the “Create” operation.
Step 8: Read the status register 2 to check the busy bit. If Busy = 1’b0, check the
Command Result to see if the create operation is successful. If Busy = 1’b1, wait for
completion.
PHY Control Register (Offset: bh)
Configuration
Bit[15:0]
Bit[20:16]
Bit[25:21]
Bit[26]
Bit[27]
Description
Data Field. This field indicates the data for reading or writing.
Register Address
Port Number
Command Option.
1 = Read
0 = Write
Access (Busy) Bit.
Default
16’h0
5’h0
5’h0
1’b0
1’b0
Note:
1. This register allows the user to control the PHY attached through the CPU’s help.
2. Rule for Read Operation:
Step 1: Poll the Busy bit (Bit[27]) to check if the PHY control module is busy.
Step 2: Write the port number (Bit[25:21]), register address (Bit[20:16]),
command (Bit[26]) and Access bit(Bit[27]) to start the read operation.
Step 3: Poll the Busy bit (Bit[27]). If Busy = 1’b1, wait. If Busy = 1’b0, data is
returned in the data field.
3. Rule for Write Operation:
Step 1: Poll the Busy bit (Bit[27]) to check if the PHY control module is busy.
Step 2: Write the port number (Bit[25:21]), register address (Bit[20:16]),
command (Bit[26]), data field (Bit[15:0]) and Access bit(Bit[27]) to start the write
operation.
Step 3: Poll the Busy bit (Bit[27]). If Busy = 1’b1, wait. If Busy = 1’b0, writing
operation completes.
4. Example: The user wants to read the Basic Control Register in Port 1.
Step 1: Read Bit[27] to check if PHY module is in progress.
Step 2: If Bit[27] = 1’b0, write Bit[27] = 1’b1, Bit[26] = 1’b1, Bit[25:21] = 5’h1
and Bit[20:16] = 5’h0.
Step 3: Poll the Busy bit. If Bit[27] = 1’b0, data is returned in the data field. If
Bit[27] = 1’b1, wait.
3.3.8
Hardware Status (Offset: dh)
Configuration
Bit[0]
Bit[1]
ADMtek Inc.
Description
Aging Disable From Hardware Pin
1 = Aging Disable.
0 = Aging Enable.
Auto-Negotiation Enable From Hardware Pin
1 = Auto-Negotiation Enable.
Default
Hardware Setting
Hardware Setting
3-51
ADM6926
Function Description
Configuration
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[7:6]
Bit[8]
3.3.9
Description
0 = Auto-Negotiation Disable.
Back Pressure Enable From Hardware Pin
1 = Back Pressure Enable.
0 = Back Pressure Disable.
Flow Control Enable For Full Duplex From Hardware Pin
1 = Flow Control Enable.
0 = Flow Control Disable.
IPG 92 Bit Time Enable From Hardware Pin
1 = IPG 92 Enable.
0 = IPG 92 Disable.
Trunking Enable From Hardware
1 = Trunking Enable.
0 = Trunking Disable.
Port 24 or Port 25 operate in RMII or MII Mode
00 = Port 24 and Port 25 are both configured to MII mode.
01 = Port 24 is configured to RMII; Port 25 is configured to MII.
10 = Port 24 is configured to MII; Port 25 is configured to RMII.
11 = Port 24 and Port 25 are both configured to RMII.
Bond RMII (SS-SMII or Pure RMII Mode)
1 = The switch is in RMII package.
0 = The switch is in SS-SMII package.
Default
Hardware Setting
Hardware Setting
Hardware Setting
Hardware Setting
Hardware Setting
Hardware Setting
Receive Packet Count Overflow (Offset: eh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
ADMtek Inc.
Description
Port 0 Receive Packet Count Overflow.
1 = Receive packet count in port 0 overflows and it will be cleared after read from
CPU.
Port 1 Receive Packet Count Overflow.
Port 2 Receive Packet Count Overflow.
Port 3 Receive Packet Count Overflow.
Port 4 Receive Packet Count Overflow.
Port 5 Receive Packet Count Overflow.
Port 6 Receive Packet Count Overflow.
Port 7 Receive Packet Count Overflow.
Port 8 Receive Packet Count Overflow.
Port 9 Receive Packet Count Overflow.
Port 10 Receive Packet Count Overflow.
Port 11 Receive Packet Count Overflow.
Port 12 Receive Packet Count Overflow.
Port 13 Receive Packet Count Overflow.
Port 14 Receive Packet Count Overflow.
Port 15 Receive Packet Count Overflow.
Port 16 Receive Packet Count Overflow.
Port 17 Receive Packet Count Overflow.
Port 18 Receive Packet Count Overflow.
Port 19 Receive Packet Count Overflow.
Port 20 Receive Packet Count Overflow.
Port 21 Receive Packet Count Overflow.
Port 22 Receive Packet Count Overflow.
Port 23 Receive Packet Count Overflow.
Port 24 Receive Packet Count Overflow.
Port 25 Receive Packet Count Overflow.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-52
ADM6926
Function Description
3.3.10 Receive Packet Length Count Overflow (Offset: fh)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Description
Port 0 Receive Packet Length Count Overflow.
1 = Receive packet length count in port 0 overflows and it will be cleared after read
from CPU.
Port 1 Receive Packet Length Count Overflow
Port 2 Receive Packet Length Count Overflow
Port 3 Receive Packet Length Count Overflow
Port 4 Receive Packet Length Count Overflow
Port 5 Receive Packet Length Count Overflow
Port 6 Receive Packet Length Count Overflow
Port 7 Receive Packet Length Count Overflow
Port 8 Receive Packet Length Count Overflow
Port 9 Receive Packet Length Count Overflow
Port 10 Receive Packet Length Count Overflow
Port 11 Receive Packet Length Count Overflow
Port 12 Receive Packet Length Count Overflow
Port 13 Receive Packet Length Count Overflow
Port 14 Receive Packet Length Count Overflow
Port 15 Receive Packet Length Count Overflow
Port 16 Receive Packet Length Count Overflow
Port 17 Receive Packet Length Count Overflow
Port 18 Receive Packet Length Count Overflow
Port 19 Receive Packet Length Count Overflow
Port 20 Receive Packet Length Count Overflow
Port 21 Receive Packet Length Count Overflow
Port 22 Receive Packet Length Count Overflow
Port 23 Receive Packet Length Count Overflow
Port 24 Receive Packet Length Count Overflow
Port 25 Receive Packet Length Count Overflow
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.3.11 Transmit Packet Count Overflow (Offset: 10h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
ADMtek Inc.
Description
Port 0 Transmit Packet Count Overflow
1 = Transmit packet count in port 0 overflows and it will be cleared after read from
CPU
Port 01 Transmit Packet Count Overflow
Port 2 Transmit Packet Count Overflow
Port 3 Transmit Packet Count Overflow
Port 4 Transmit Packet Count Overflow
Port 5 Transmit Packet Count Overflow
Port 6 Transmit Packet Count Overflow
Port 7 Transmit Packet Count Overflow
Port 8 Transmit Packet Count Overflow
Port 9 Transmit Packet Count Overflow
Port 10 Transmit Packet Count Overflow
Port 11 Transmit Packet Count Overflow
Port 12 Transmit Packet Count Overflow
Port 13 Transmit Packet Count Overflow
Port 14 Transmit Packet Count Overflow
Port 15 Transmit Packet Count Overflow
Port 16 Transmit Packet Count Overflow
Port 17 Transmit Packet Count Overflow
Port 18 Transmit Packet Count Overflow
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-53
ADM6926
Configuration
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Function Description
Description
Port 19 Transmit Packet Count Overflow
Port 20 Transmit Packet Count Overflow
Port 21 Transmit Packet Count Overflow
Port 22 Transmit Packet Count Overflow
Port 23 Transmit Packet Count Overflow
Port 24 Transmit Packet Count Overflow
Port 25 Transmit Packet Count Overflow
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.3.12 Transmit Packet Length Count Overflow (Offset: 11h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Description
Port 0 Transmit Packet Length Count Overflow
1 = Transmit packet length count in port 0 overflows and it will be cleared after read
from CPU
Port 1 Transmit Packet Length Count Overflow
Port 2 Transmit Packet Length Count Overflow
Port 3 Transmit Packet Length Count Overflow
Port 4 Transmit Packet Length Count Overflow
Port 5 Transmit Packet Length Count Overflow
Port 6 Transmit Packet Length Count Overflow
Port 7 Transmit Packet Length Count Overflow
Port 8 Transmit Packet Length Count Overflow
Port 9 Transmit Packet Length Count Overflow
Port 10 Transmit Packet Length Count Overflow
Port 11 Transmit Packet Length Count Overflow
Port 12 Transmit Packet Length Count Overflow
Port 13 Transmit Packet Length Count Overflow
Port 14 Transmit Packet Length Count Overflow
Port 15 Transmit Packet Length Count Overflow
Port 16 Transmit Packet Length Count Overflow
Port 17 Transmit Packet Length Count Overflow
Port 18 Transmit Packet Length Count Overflow
Port 19 Transmit Packet Length Count Overflow
Port 20 Transmit Packet Length Count Overflow
Port 21 Transmit Packet Length Count Overflow
Port 22 Transmit Packet Length Count Overflow
Port 23 Transmit Packet Length Count Overflow
Port 24 Transmit Packet Length Count Overflow
Port 25 Transmit Packet Length Count Overflow
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.3.13 Error Count Overflow (Offset: 12h)
Configuration
Bit[0]
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
ADMtek Inc.
Description
Port 0 Error Count Overflow
1 = Error count in port 0 overflows and it will be cleared after read from CPU
Port 0 Error Count Overflow
Port 1 Error Count Overflow
Port 2 Error Count Overflow
Port 3 Error Count Overflow
Port 4 Error Count Overflow
Port 5 Error Count Overflow
Port 6 Error Count Overflow
Port 7 Error Count Overflow
Port 8 Error Count Overflow
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-54
ADM6926
Configuration
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Function Description
Description
Port 9 Error Count Overflow
Port 10 Error Count Overflow
Port 11 Error Count Overflow
Port 12 Error Count Overflow
Port 13 Error Count Overflow
Port 14 Error Count Overflow
Port 15 Error Count Overflow
Port 16 Error Count Overflow
Port 17 Error Count Overflow
Port 18 Error Count Overflow
Port 19 Error Count Overflow
Port 20 Error Count Overflow
Port 21 Error Count Overflow
Port 22 Error Count Overflow
Port 23 Error Count Overflow
Port 24 Error Count Overflow
Port 25 Error Count Overflow
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.3.14 Collision Count Overflow (Offset: 13h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
ADMtek Inc.
Description
Port 0 Collision Count Overflow.
1 = Collision Count in port 0 overflows and it will be cleared after read from CPU.
Port 1 Collision Count Overflow.
Port 2 Collision Count Overflow.
Port 3 Collision Count Overflow.
Port 4 Collision Count Overflow.
Port 5 Collision Count Overflow.
Port 6 Collision Count Overflow.
Port 7 Collision Count Overflow.
Port 8 Collision Count Overflow.
Port 9 Collision Count Overflow.
Port 10 Collision Count Overflow.
Port 11 Collision Count Overflow.
Port 12 Collision Count Overflow.
Port 13 Collision Count Overflow.
Port 14 Collision Count Overflow.
Port 15 Collision Count Overflow.
Port 16 Collision Count Overflow.
Port 17 Collision Count Overflow.
Port 18 Collision Count Overflow.
Port 19 Collision Count Overflow.
Port 20 Collision Count Overflow.
Port 21 Collision Count Overflow.
Port 22 Collision Count Overflow.
Port 23 Collision Count Overflow.
Port 24 Collision Count Overflow.
Port 25 Collision Count Overflow.
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-55
ADM6926
Function Description
3.3.15 Renew Counter Register (Offset: 14h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Bit[26]
Description
1 = Clear Port 0 Corresponding Counters
1 = Clear Port 1 Corresponding Counters
1 = Clear Port 2 Corresponding Counters
1 = Clear Port 3 Corresponding Counters
1 = Clear Port 4 Corresponding Counters
1 = Clear Port 5 Corresponding Counters
1 = Clear Port 6 Corresponding Counters
1 = Clear Port 7 Corresponding Counters
1 = Clear Port 8 Corresponding Counters
1 = Clear Port 9 Corresponding Counters
1 = Clear Port 10 Corresponding Counters
1 = Clear Port 11 Corresponding Counters
1 = Clear Port 12 Corresponding Counters
1 = Clear Port 13 Corresponding Counters
1 = Clear Port 14 Corresponding Counters
1 = Clear Port 15 Corresponding Counters
1 = Clear Port 16 Corresponding Counters
1 = Clear Port 17 Corresponding Counters
1 = Clear Port 18 Corresponding Counters
1 = Clear Port 19 Corresponding Counters
1 = Clear Port 20 Corresponding Counters
1 = Clear Port 21 Corresponding Counters
1 = Clear Port 22 Corresponding Counters
1 = Clear Port 23 Corresponding Counters
1 = Clear Port 24 Corresponding Counters
1 = Clear Port 25 Corresponding Counters
Access (Busy) bit
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
Note:
1.
This register allows the user to reset all counters for the corresponding port. If the
renew counter module is busy
all other modules about counters are not accessible.
2.
Rule:
Step 1: Poll the busy bit to check if the renew counter module is busy.
Step 2: If the renew counter module is available, write the port (Bit[25:0]) the
user wants to reset and the busy bit(Bit[26]) to 1.
Step 3: Poll the busy bit to check if the renew counter module completes the job.
3.
Example:
Users want to reset P0, P1, P2, P3 corresponding counters.
Step 1: Read Bit[26] to check if reset is in progress.
Step 2: If Bit[26] = 0, write Bit[26] = 1’b1, Bit[25:0] =
26’b00_0000_0000_0000_0000_0000_1111 into the register.
Step 3: Poll the busy bit to check if reset completes
ADMtek Inc.
3-56
ADM6926
Function Description
3.3.16 Read Counter Control & Status Register
Read Counter Control Register (Offset: 15h), Read Counter Status Register (Offset: 16h)
1.
Configuration
Bit[8]
Bit[7:0]
2.
Configuration
Bit[31:0]
3.
4.
5.
Read Counter Control Register
Description
Access (busy) bit
Counter Index
Default
1’h0
8’h0
Read Counter Status Register
Description
The corresponding counter index by the Bit[7:0] is returned here.
Default
32’h0
Note: This register provides user to read counter if he wants to use fast
management clock (fast than 5mhz).
Rules:
Step 1: Read the Busy bit to check if the read counter module is busy.
Step 2: If the module is free, write the counter index and access bit into the
control register.
Step 3: Poll the Busy bit. If Busy = 1’b1, wait. If Busy = 1’b0, read the status
register.
Example: Users want to read Port 1 Receive Packet Count
Step 1: Read Bit[8] to check if the read counter module is busy
Step 2: If Bit[8] = 0, then write bit[8] = 1’b1, Bit[7:0] = 8’b1 into the register.
Step 3: Then Port 1 Receive Packet Count will be loaded into the Counter Status
Register (Offset: 16h)
Step 4: Read Counter Status Register (Offset: 16h) and the content read is the Port
1 Receive Packet Count.
3.3.17 Reload MDIO Register (Offset: 17h)
Configuration
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit[16]
Bit[17]
Bit[18]
ADMtek Inc.
Description
Port 0 MDIO Register Reload
1 = Status of Port 0 PHY attached will be reloaded and updated to the switch. After
PHY is reloaded, Bit[0] will be cleared.
Port 1 MDIO Register Reload
Port 2 MDIO Register Reload
Port 3 MDIO Register Reload
Port 4 MDIO Register Reload
Port 5 MDIO Register Reload
Port 6 MDIO Register Reload
Port 7 MDIO Register Reload
Port 8 MDIO Register Reload
Port 9 MDIO Register Reload
Port 10 MDIO Register Reload
Port 11 MDIO Register Reload
Port 12 MDIO Register Reload
Port 13 MDIO Register Reload
Port 14 MDIO Register Reload
Port 15 MDIO Register Reload
Port 16 MDIO Register Reload
Port 17 MDIO Register Reload
Port 18 MDIO Register Reload
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3-57
ADM6926
Function Description
Configuration
Bit[19]
Bit[20]
Bit[21]
Bit[22]
Bit[23]
Bit[24]
Bit[25]
Description
Port 19 MDIO Register Reload
Port 20 MDIO Register Reload
Port 21 MDIO Register Reload
Port 22 MDIO Register Reload
Port 23 MDIO Register Reload
Port 24 MDIO Register Reload
Port 25 MDIO Register Reload
Default
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3.3.18 Spanning Tree Port State 0 (Offset: 18h)
Configuration
Bit[1:0]
Bit[3:2]
Bit[5:4]
Bit[7:6]
Bit[9:8]
Bit[11:10]
Bit[13:12]
Bit[15:14]
Bit[17:16]
Bit[19:18]
Bit[21:20]
Bit[23:22]
Bit[25:24]
Bit[27:26]
Bit[29:28]
Bit[31:30]
Description
Port 0 Spanning Tree Port Status
Port 1 Spanning Tree Port Status
Port 2 Spanning Tree Port Status
Port 3 Spanning Tree Port Status
Port 4 Spanning Tree Port Status
Port 5 Spanning Tree Port Status
Port 6 Spanning Tree Port Status
Port 7 Spanning Tree Port Status
Port 8 Spanning Tree Port Status
Port 9 Spanning Tree Port Status
Port 10 Spanning Tree Port Status
Port 11 Spanning Tree Port Status
Port 12 Spanning Tree Port Status
Port 13 Spanning Tree Port Status
Port 14 Spanning Tree Port Status
Port 15 Spanning Tree Port Status
Default
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
Note:
The ADM6926 supports 4 port status to support Spanning Tree Protocol
00 = Forwarding State. The port acts as the normal mode.
01 = Disabled State. The port entity will not transmit and receive any packets. Learning is
disabled in this state.
10 = Learning State. The port entity will only transmit and receive management packets.
All other packets are discarded.
Learning is enabled for all good frames.
11 = Blocking-not-Listening. Only the management packets defined by the ADM6926
will be received and transmitted.
All other packets are discarded by the port entity. Learning is disabled in this state.
3.3.19 Spanning Tree Port State 1 (Offset: 19h)
Configuration
Bit[1:0]
Bit[3:2]
Bit[5:4]
Bit[7:6]
Bit[9:8]
Bit[11:10]
Bit[13:12]
Bit[15:14]
ADMtek Inc.
Description
Port 16 Spanning Tree Port Status
Port 17 Spanning Tree Port Status
Port 18 Spanning Tree Port Status
Port 19 Spanning Tree Port Status
Port 20 Spanning Tree Port Status
Port 21 Spanning Tree Port Status
Port 22 Spanning Tree Port Status
Port 23 Spanning Tree Port Status
Default
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
2’h0
3-58
ADM6926
Function Description
Configuration
Bit[17:16]
Bit[19:18]
Description
Default
2’h0
2’h0
Port 24 Spanning Tree Port Status
Port 25 Spanning Tree Port Status
3.3.20 Source Port Register (Offset: 1ah)
Configuration
Bit[4:0]
Description
The Source Port. The CPU can read this register to get the source port when he
receives a packet.
Default
2’h0
Note:
The value will be correct after the SA is transmitted.
3.3.21 Transmit Port Register (Offset: 1bh)
Configuration
Bit[25:0]
Bit[26]
Bit[27]
Description
The destination ports the CPU wants to forward.
The destination ports is more than 1.
1 = The command is valid.
0 = The command is not valid.
Default
26’b0
1’b0
Note:
The value should be written before CPU transmits a packet.
3.3.22 Counter Register: Offset Hex. 0100h ~ 019b
Offset Hex
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010ah
010bh
010ch
010dh
010eh
010fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
Index
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
Offset Hex Index
0134
34
ADMtek Inc.
The Receive Count
Description
Offset Hex Index
Port 0 Receive Packet Count
011a
1A
Port 1 Receive Packet Count
011b
1B
Port 2 Receive Packet Count
011c
1C
Port 3 Receive Packet Count
011d
1D
Port 4 Receive Packet Count
011e
1E
Port 5 Receive Packet Count
011f
1F
Port 6 Receive Packet Count
0120
20
Port 7 Receive Packet Count
0121
21
Port 8 Receive Packet Count
0122
22
Port 9 Receive Packet Count
0123
23
Port 10 Receive Packet Count
0124
24
Port 11 Receive Packet Count
0125
25
Port 12 Receive Packet Count
0126
26
Port 13 Receive Packet Count
0127
27
Port 14 Receive Packet Count
0128
28
Port 15 Receive Packet Count
0129
29
Port 16 Receive Packet Count
012a
2A
Port 17 Receive Packet Count
012b
2B
Port 18 Receive Packet Count
012c
2C
Port 19 Receive Packet Count
012d
2D
Port 20 Receive Packet Count
012e
2E
Port 21 Receive Packet Count
012f
2F
Port 22 Receive Packet Count
0130
30
Port 23 Receive Packet Count
0131
31
Port 24 Receive Packet Count
0132
32
Port 25 Receive Packet Count
0133
33
The Transmit Count
Description
Offset Hex Index
Port 0 Transmit Packet Count
014e
4E
Description
Port 0 Receive Packet Length Count
Port 1 Receive Packet Length Count
Port 2 Receive Packet Length Count
Port 3 Receive Packet Length Count
Port 4 Receive Packet Length Count
Port 5 Receive Packet Length Count
Port 6 Receive Packet Length Count
Port 7 Receive Packet Length Count
Port 8 Receive Packet Length Count
Port 9 Receive Packet Length Count
Port 10 Receive Packet Length Count
Port 11 Receive Packet Length Count
Port 12 Receive Packet Length Count
Port 13 Receive Packet Length Count
Port 14 Receive Packet Length Count
Port 15 Receive Packet Length Count
Port 16 Receive Packet Length Count
Port 17 Receive Packet Length Count
Port 18 Receive Packet Length Count
Port 19 Receive Packet Length Count
Port 20 Receive Packet Length Count
Port 21 Receive Packet Length Count
Port 22 Receive Packet Length Count
Port 23 Receive Packet Length Count
Port 24 Receive Packet Length Count
Port 25 Receive Packet Length Count
Description
Port 0 Transmit Packet Length Count
3-59
ADM6926
Function Description
0135
0136
0137
0138
0139
013a
013b
013c
013d
013e
013f
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
014a
014b
014c
014d
Offset Hex
0168
0169
016a
016b
016c
016d
016e
016f
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
017a
017b
017c
017d
017e
017f
0180
0181
ADMtek Inc.
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
Index
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
Port 1 Transmit Packet Count
Port 2 Transmit Packet Count
Port 3 Transmit Packet Count
Port 4 Transmit Packet Count
Port 5 Transmit Packet Count
Port 6 Transmit Packet Count
Port 7 Transmit Packet Count
Port 8 Transmit Packet Count
Port 9 Transmit Packet Count
Port 10 Transmit Packet Count
Port 11 Transmit Packet Count
Port 12 Transmit Packet Count
Port 13 Transmit Packet Count
Port 14 Transmit Packet Count
Port 15 Transmit Packet Count
Port 16 Transmit Packet Count
Port 17 Transmit Packet Count
Port 18 Transmit Packet Count
Port 19 Transmit Packet Count
Port 20 Transmit Packet Count
Port 21 Transmit Packet Count
Port 22 Transmit Packet Count
Port 23 Transmit Packet Count
Port 24 Transmit Packet Count
Port 25 Transmit Packet Count
014f
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
015a
015b
015c
015d
015e
015f
0160
0161
0162
0163
0164
0165
0166
0167
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
Error and Collision Count
Description
Offset Hex Index
Port 0 Receive Error Count
0182
82
Port 1 Receive Error Count
0183
83
Port 2 Receive Error Count
0184
84
Port 3 Receive Error Count
0185
85
Port 4 Receive Error Count
0186
86
Port 5 Receive Error Count
0187
87
Port 6 Receive Error Count
0188
88
Port 7 Receive Error Count
0189
89
Port 8 Receive Error Count
018a
8A
Port 9 Receive Error Count
018b
8B
Port 10 Receive Error Count
018c
8C
Port 11 Receive Error Count
018d
8D
Port 12 Receive Error Count
018e
8E
Port 13 Receive Error Count
018f
8F
Port 14 Receive Error Count
0190
90
Port 15 Receive Error Count
0191
91
Port 16 Receive Error Count
0192
92
Port 17 Receive Error Count
0193
93
Port 18 Receive Error Count
0194
93
Port 19 Receive Error Count
0195
95
Port 20 Receive Error Count
0196
96
Port 21 Receive Error Count
0197
97
Port 22 Receive Error Count
0198
98
Port 23 Receive Error Count
0199
99
Port 24 Receive Error Count
019a
9A
Port 25 Receive Error Count
019b
9B
Port 1 Transmit Packet Length Count
Port 2 Transmit Packet Length Count
Port 3 Transmit Packet Length Count
Port 4 Transmit Packet Length Count
Port 5 Transmit Packet Length Count
Port 6 Transmit Packet Length Count
Port 7 Transmit Packet Length Count
Port 8 Transmit Packet Length Count
Port 9 Transmit Packet Length Count
Port 10 Transmit Packet Length Count
Port 11 Transmit Packet Length Count
Port 12 Transmit Packet Length Count
Port 13 Transmit Packet Length Count
Port 14 Transmit Packet Length Count
Port 15 Transmit Packet Length Count
Port 16 Transmit Packet Length Count
Port 17 Transmit Packet Length Count
Port 18 Transmit Packet Length Count
Port 19 Transmit Packet Length Count
Port 20 Transmit Packet Length Count
Port 21 Transmit Packet Length Count
Port 22 Transmit Packet Length Count
Port 23 Transmit Packet Length Count
Port 24 Transmit Packet Length Count
Port 25 Transmit Packet Length Count
Description
Port 0 Collision Count
Port 1 Collision Count
Port 2 Collision Count
Port 3 Collision Count
Port 4 Collision Count
Port 5 Collision Count
Port 6 Collision Count
Port 7 Collision Count
Port 8 Collision Count
Port 9 Collision Count
Port 10 Collision Count
Port 11 Collision Count
Port 12 Collision Count
Port 13 Collision Count
Port 14 Collision Count
Port 15 Collision Count
Port 16 Collision Count
Port 17 Collision Count
Port 18 Collision Count
Port 19 Collision Count
Port 20 Collision Count
Port 21 Collision Count
Port 22 Collision Count
Port 23 Collision Count
Port 24 Collision Count
Port 25 Collision Count
3-60
ADM6926
Electrical Specification
Chapter 4 Electrical Specification
4.1
DC Characterization
4.1.1 Absolute Maximum Rating
Symbol Parameter
VCCO
VCCIK
VIN
Vout
TSTG
PD
ESD
Rating
3.3V Power Supply
1.8V Power Supply
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
ESD Rating
Units
3.0 to 3.6
1.71 to 1.89
-0.3 to VCC33 + 0.3
-0.3 to Vcc33 + 0.3
-55 to 155
1.0
3000
V
V
V
V
°C
W
V
Table 4-4-1 Electrical Absolute Maximum Rating
4.1.2 Recommended Operating Conditions
Symbol
Parameter
Vcc
Vin
Tj
Power Supply
Input Voltage
Junction Operating Temperature
Min
Typical
Max
Units
3.135
0
0
3.3
25
3.465
Vcc
115
V
V
°C
Table 4-4-2 Recommended Operating Conditions
4.1.3
DC Electrical Characteristics for 3.3V Operation
(Under Vcc=3.0V~3.6V, Tj= 0 °C ~ 115 °C )
Symbol
Parameter
Conditions
Min
VIL
VIH
VOL
VOH
RI
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Pull_up/down Resistance
TTL
TTL
TTL
TTL
VIL= 0V or
VIH = Vcc
Typical
Max
Units
0.8
V
V
V
V
KΩ
2.0
0.4
2.3
50
Table 4-4-3 DC Electrical Characteristics for 3.3V Operation
ADMtek Inc.
4-1
ADM6926
Electrical Specification
4.2
AC Characterization
4.2.1
XI/OSCI (Crystal/Oscillator) Timing
t XI PE
t XI H
V
V
t XI L
IH XI
IL XI
t XI RIS
t XI FAL
Figure 4-1 Crystal/Oscillator Timing
Symbol
Parameter
Conditions
t_XI_PER
XI/OSCI Clock Period
Min
20.0 50ppm
8
8
T_XI_HI
XI/OSCI Clock High
T_XI_LO
XI/OSCI Clock Low
T_XI_RISE XI/OSCI Clock Rise Time , VIL
(max) to VIH (min)
T_XI_FALL XI/OSCI Clock Fall Time , VIH
(min) to VIL (max)
Typical
20.0
Max
Units
20.0 +
50ppm
ns
10.0
10.0
2
ns
ns
ns
2
ns
Table 4-4 Crystal/Oscillator Timing
4.2.1
Power On Reset
0us
50ms
100ms
150ms
tRST
RST*
tCONF
All Configuration Pins
Figure 4-2 Power on reset timing
ADMtek Inc.
4-2
ADM6926
Electrical Specification
Symbol
TRST
TCONF
Parameter
Conditions
RST Low Period
Start of Configuration Pins
Min
Typical
Max
Units
150
100
ms
ns
Table 4-5 Power on reset timing
4.2.2
EEPROM Interface Timing
0us
6.4us
12.8us
19.2us
EECS
tESKL
tESKH
tESK
EESK
tEWDD
EEDO
tERDS
tERDH
EEDI
Figure 4-3 EEPROM Interface Timing
Symbol
TESK
TESKL
TESKH
TERDS
TERDH
TEWDD
Parameter
Conditions
EESK Period
EESK Low Period
EESK High Period
EEDI to EESK Rising Setup Time
EEDI to EESK Rising Hold Time
EESK Falling to EEDO Output
Delay Time
Min
Typical
Max
Units
20
us
us
us
ns
ns
ns
3.2
1.6
1.6
10
10
Table 4-6 EEPROM Interface Timing
4.2.3
10Base-TX MII Output Timing
0ns
500ns
1000ns
1500ns
2000ns
2500ns
tCK
tCKL
tCKH
MII_TXCLK
tTXOD
MII_TXEN
MII_TXD
Figure 4-4 10Base-TX MII Output Timing
ADMtek Inc.
4-3
ADM6926
Electrical Specification
Symbol
tCK
tCKL
tCKH
tTXOD
Parameter
Conditions
MII_TXCLK Period
MII_TXCLK Low Period
MII_TXCLK High Period
MII_TXD, MII_TXEN to
MII_TXCLK Rising Output Delay
Min
Typical
Max
Units
240
240
20
ns
ns
ns
ns
Max
Units
240
240
ns
ns
ns
ns
400
160
160
10
Table 4-7 10Base-TX MII Output Timing
4.2.4 10Base-TX MII Input Timing
0ns
1000ns
2000ns
tCK
tCKL
tCKH
MII_RXCLK
tRXS
MII_RXDV
tRXH
MII_RXD
MII_CRS
Figure 4-5 10Base-TX MII Input Timing
Symbol
tCK
tCKL
tCKH
tRXS
tRXH
Parameter
Conditions
MII_RXCLK Period
MII_RXCLK Low Period
MII_RXCLK High Period
MII_CRS, MII_RXDV and
MII_RXD to MII_RXCLK rising
setup
MII_CRS, MII_RXDV and
MII_RXD to MII_RXCLK rising
hold
Min
Typical
400
160
160
10
10
ns
Table 4-8 10Base-TX MII Input Timing
ADMtek Inc.
4-4
ADM6926
Electrical Specification
4.2.5 100Base-TX MII Output Timing
0ns
50ns
100ns
150ns
200ns
250ns
tCK
tCKL
tCKH
MII_TXCLK
tTXOD
MII_TXEN
MII_TXD
Figure 4-6 100Base-TX MII Output Timing
Symbol
tCK
tCKL
tCKH
tTXOD
Parameter
Conditions
MII_TXCLK Period
MII_TXCLK Low Period
MII_TXCLK High Period
MII_TXD, MII_TXEN to
MII_TXCLK Rising Output Delay
Min
Typical
Max
Units
24
24
20
ns
ns
ns
ns
Max
Units
24
24
ns
ns
ns
ns
40
16
16
10
Table 4-9 100Base-TX MII Output Timing
4.2.6
100Base-TX MII Input Timing
0ns
100ns
200ns
tCK
tCKL
tCKH
MII_RXCLK
tRXS
MII_RXDV
tRXH
MII_RXD
MII_CRS
Figure 4-7 100Base-TX MII Input Timing
Symbol
tCK
tCKL
tCKH
tRXS
tRXH
ADMtek Inc.
Parameter
MII_RXCLK Period
MII_RXCLK Low Period
MII_RXCLK High Period
MII_CRS, MII_RXDV and
MII_RXD to MII_RXCLK rising
setup
MII_CRS, MII_RXDV and
Conditions
Min
Typical
40
16
16
10
10
ns
4-5
ADM6926
Electrical Specification
Symbol
Parameter
Conditions
Min
Typical
Max
Units
Max
Units
MII_RXD to MII_RXCLK rising
hold
Table 4-10 100Base-TX MII Input Timing
4.2.7
Reduced MII Timing
0ns
50ns
100ns
tCKL
tCK
tCKH
REFCLK
RMII_TXEN
tTXH
tTXS
TXD[1:0]
Figure 4-8 Reduced MII Timing (1 of 2)
0ns
50ns
100ns
tCK
tCKL
tCKH
REFCLK
RMII_CRSDV
tRXH
tRXS
RXD[1:0]
Figure 4-9 Reduced MII Timing (2 of 2)
Symbol
tCK
tCKL
tCKH
tTXS
tTXH
tRXS
tRXH
Parameter
Conditions
RMII_REFCLK Period
RMII_REFCLK Low Period
RMII_REFCLK High Period
TXEN, TXD to REFCLK rising
setup time
TXEN, TXD to REFCLK rising
hold time
CSRDV, RXD to REFCLK rising
setup time
CRSDV, RXD to REFCLK rising
hold time
Min
Typical
20
10
10
4
ns
ns
ns
ns
2
ns
4
ns
2
ns
Table 4-11 Reduced MII Timing
ADMtek Inc.
4-6
ADM6926
4.2.8
Electrical Specification
SS_SMII Transmit Timing
0ns
20ns
40ns
tCKL
tCK
tCKH
CLK_TX
SYNC_TX
tTRN
tOD
STXD[7:0]
Figure 4-10 SS_SMII Transmit Timing
Symbol
tCK
tCKL
Parameter
Conditions
SS_SMII Output Clock Period
SS_SMII Output Clock Low
Period
R SS_SMII Output Clock High
Period
Txdata/TxSync output delay to
CLK_TX
Txdata/RxSync Rise/Fall Time
tCKH
tOD
tTRN
Min
Typical
Max
Units
8
4
ns
ns
4
ns
2
5
1
ns
ns
Table 4-12 SS_SMII Transmit Timing
4.2.9 SS_SMII Receive Timing
0ns
20ns
40ns
tCKL
tCK
tCKH
CLK_RX
SYNC_RX
tDH
tDS
SRXD[7:0]
Figure 4-11 SS_SMII Receive Timing
Symbol
tCK
tCKL
tCKH
tDS
ADMtek Inc.
Parameter
SS_SMII CLK_RX Clock Period
SS_SMII CLK_RX Low Period
SS_SMII CLK_RX High Period
Rxdata/RxSync setup to CLK_RX
Conditions
Min
Typical
8
4
4
1.5
Max
Units
ns
ns
ns
ns
4-7
ADM6926
Electrical Specification
Symbol
tDH
Parameter
Conditions
rising edge
Rxdata/RxSync hold from
CLK_RX rising edge
Min
Typical
Max
1
Units
ns
Table 4-13 SS_SMII Receive Timing
4.2.10 Serial Management Interface (MDC/MDIO) Timing
0ns
1ms
2ms
tCKL
tCK
tCKH
MDC
tOD
MDIO (output)
tDS
tDH
MDIO (input)
Figure 4-12 Serial Management Interface (MDC/MDIO) Timing
Symbol
tCK
tCKL
tCKH
tOD
tDS
tDH
Parameter
Conditions
SS_SMII CLK_RX Clock Period
SS_SMII CLK_RX Low Period
SS_SMII CLK_RX High Period
MDC to MDIO Output Delay
MDIO Input to MDC Setup Time
MDIO Input to MDC Hold Time
Min
Typical
Max
400
200
200
20
10
10
Units
ns
ns
ns
ns
ns
ns
Table 4-14 Serial Management Interface (MDC/MDIO) Timing
ADMtek Inc.
4-8
ADM6926
Packaging
Chapter 5 Packaging
17.2 +/- 0.2 mm
14.0 +/- 0.1 mm
18.5 mm
23.2 +/- 0.2 mm
20.0 +/- 0.1 mm
12.5 mm
3.4 mm
MAX
0.5 mm
ADMtek Inc.
5-1