ADMtek Incorporated Partnership Now and Future Olive Family ADM6308 − Eight-port 10/100M Ethernet Switch Controller Overview ADM6308, a single chip, is a 10/100Mbps eight-port stand-alone switching controller with built-in data buffer memory which provides low cost and simple solution though a high integration design. Eight Reduced MII interfaces are designed for 10BASE/100BASE ports. MAC controller, switch engines and data buffer memory are built-in. The chip can fit to desktop or SOHO applications, and each 10/100M port directly connects either 10BASE or 100BASE devices. Additionally, ADM6308 breaks the distance limitation of 10BASE or any class 100BASE repeaters, and increases throughput. Features ê ê ê ê ê ê ê ê ê ê ê ê ê ê ê ê ê ê Non-blocking eight-port 10/100M switching controller with MAC controller and switching engine included low cost and a simple solution for 100BASE-TX, 100BASE-FX, and 10BASE applications. Configurable 10/100BASE Reduced MII interfaces and 1MII+ 7RMII mode provided. The single clock input, 50M, for RMII and system Speed auto negotiation function for all ports Store-and- forward operation support. Full line speed capability of 14880 packet/sec for 10M and 148810 packet/sec for 100M, with no HOL blocking. Broadcast storming prevention Support 4 groups port-based VLAN. Full-duplex (IEEE802.3x) and three-way half-duplex flow control (Back pressure). Data buffer SSRAM embedded, CoS support: Port-based, VLAN tag, TCP/IP TOS/DS. Intelligently back-pressure and flow control turned on/off in the port with priority frames Buffer management included. 93C46 EEPROM interface or Dynamic configured by 8051 Buffer full and faulty LED provided. Bridging functions such as: u Local MAC address filtering. u CRC or direct mapping hashing schemes for better address coverage. u Short routing decision time. u Aging function included with configurable aging time. u Embedded 1K entries of address table. Low power 2.5 V CMOS technology with 3.3V tolerance I/O 100-pins Plastic Quad Flat Package. ADMtek Incorporate 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 2 Block Diagram EEPROM I/F N-WAY Monitor Link Table Data Buffer Configuration Control & Fabric TX DMA RX DMA TX DMA RX DMA TX DMA TMAC RMAC TMAC RMAC RMII RX DMA From port 0 to port 7 TMAC RMAC From port 0 to port 7 RMII RMII From port 0 to port 7 Example of System Diagram ADM6308 8-port switch EEPROM (Option) OSC ADMtek Incorporated 00/04/25 Quad PHYceiver Quad PHYceiver Transformer Transformer 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 3 Pin Diagram RXD2[1] RXD2[0] RXDV2 TXD2[1] TXD2[0] TXE2 VDDo RXD1[1] RXD1[0] Vss RXDV1 VDDi TXD1[1] TXD1[0] TXE1 Vss RXD0[3] RXD0[2] RXD0[1] RXD0[0] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 Vss 1 80 RXDV0 TXE3 2 79 RXC0 TXD3[0] TXD3[1] 3 78 4 77 TXC0 TXD0[3] RXDV3 5 76 TXD0[2] VDDi 6 75 Vss RXD3[0] 7 74 TXD0[1] RXD3[1] 8 73 TXD0[0] Vss 9 72 TXE0 REFCLK 10 71 VDDo VDDo 11 70 COL0 TXE4 12 69 CRS0 TXD4[0] 13 68 VDDi TXD4[1] 14 67 MII# RXDV4 15 66 TEST[1] RXD4[0] 16 65 TEST[0] RXD4[1] 17 64 Vss Vss 18 63 RESET# Vss 19 62 Vss TXE5 20 61 high_port[7] TXD5[0] 21 60 high_port[6] TXD5[1] 22 59 high_port[5] VDDi 23 58 high_port[4] VDDi OLIVE plus ADM6308 RXDV5 24 57 RXD5[0] 25 56 high_port[3] RXD5 [1] 26 55 high_port[2] VDDo 27 54 high_port[1] TXE6 28 53 high_port[0] TXD6[0] 29 52 RECALL TXD6[1] 30 51 EEDO/NA16# 40 41 42 43 44 45 46 47 RXDV7 RXD7[0] RXD7[1] Vss MDC VDDo MDIO QFLED# Vss EEDI/BP0 39 VDDi 50 38 TXD7[1] EECS/BP1 37 TXD7[0] 49 36 TXE7 Version : 1.10 EESK/XFC# 35 Vss 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu 48 34 RXD6[1] RXD6[0] 33 32 RXDV6 00/04/25 31 ADMtek Incorporated Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 4 Pin Descriptions Pin Name Pin # Type Descriptions EEPROM Interface EEDO 51 I EEDO: Data Output of serial EEPROM. Internally pull up (50K Ohm). Inputs configuration information to ADM6308. EEDI 50 BI EEDI: Data Input of serial EEPROM. Internally pull down (50K Ohm). ADM6308 outputs 4ma data to EEPROM EESK 48 BI EESK: Clock input of serial EEPROM. Internally pull up. ADM6308 outputs clock signal to 4ma EEPROM EECS 49 BI Chip Select of serial EEPROM. Internally pull down. 4ma EECK/s:50ns, h:0ns Reduced MII Interface TXE0 TXE1 TXE2 TXE3 TXE4 TXE5 TXE6 TXE7 72, 86 95, 2 12, 20 28, 35 O Transmit Enable. TXE0~7 shows that ADM6308 is presenting the recovered and decoded 8ma data on the TXD0~7[1:0]. TXE0~7 indicates that the MAC is presenting di-bits on TXD0~7[1:0] on the Reduced MII for transmission. TXE0~7 shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented to the Reduced MII. TXE0~7 shall be negative prior to the first REFCLK rising edge following the final di-bit of a frame. TXE0~7 shall transition synchronously with REFCLK. TXD0[1:0] TXD1[1:0] TXD2[1:0] TXD3[1:0] TXD4[1:0] TXD5[1:0] TXD6[1:0] TXD7[1:0] 74, 73 88, 87, 97, 96 4,3 14, 13 22, 21 30, 29 37, 36 O Transmit Data. These bundle signals are output from ADM6308 to Reduced MII connecting 4ma device. These signals are transited synchronously with the rising edge of TXE0~7. When TXE0~7 is being asserted, for each period of TXE0~7, ADM6308 drives the recovered and encoded data into TXD0~7[1:0] for transmission. While TXE0~7 is de-asserted, the TXD0~7[1:0] will have no effect upon the Reduced MII connecting device. TXD0~7[1:0] shall transition synchronously with REFCLK. When TXE0~7 is being asserted, TXD0~7[1:0] is accepted for transmission by the PHY. TXD0~7[1:0] shall be “00” to indicate idle when TXE0~7 is de-asserted. Values of TXD0~7[1:0] other than “00” when TXE0~7 is de-asserted are reserved for out-of-band signaling (to be defined). Values other than “00” on TXD0~7[1:0] while TXE0~7 is de-asserted shall be ignored by the PHY. TXC0 TXD0[3:2] 78 BI Transmit Clock for port0 MII mode. 4ma 77, 76 O Transmit Data for port0 MII mode. 4ma ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 5 RXDV0 RXDV1 RXDV2 RXDV3 RXDV4 RXDV5 RXDV6 RXDV7 80, 90 98, 5 15, 24 31, 39 I Carrier Sense and Receive Data Valid. RXDV2, RXDV3, RXDV5, RDDV6, RXDV7 internally pull down. RXDV0~7 shall be asserted by the PHY when the receiver is not idle. The specific definition of idle for 10BASE-T and 100BASE-X is contained in IEEE 802.3 and IEEE 802.3u. RXDV0~7 also shows that the receiving data is presented on the RXD0~7[1:0] from Reduced MII connecting device. RXDV0~7 is being asserted asynchronous on detection of carrier due to criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected, carrier is said to be detected. Loss of carrier shall result in the de-assertion of RXDV0~7 synchronous to the cycles of REFCLK which presents the first di-bit of a nibble onto RXD0~7[1:0]. If the PHY has additional bits to be presented on RXD0~7[1:0] following the initial de-assertion of RXDV0~7, then the PHY shall assert RXDV0~7 on cycles of REFCLK which present the second di-bit of each nibble, and de-assert RXDV0~7 on cycles of REFCLK which present the first di-bit of a nibble. During a false carrier event, RXDV0~7 shall remain asserted for the duration of carrier activity. The data on RXD0~7[1:0] is considered valid once RXDV0~7 is being asserted. However, since the assertion of RXDV0~7 is asynchronous relative to REFCLK, the data on RXD0~7[1:0] shall be “00” until proper receive signal decoding takes place. RXD0[1:0] RXD1[1:0] RXD2[1:0] RXD3[1:0] RXD4[1:0] RXD5[1:0] RXD6[1:0] RXD7[1:0] 82, 81 93, 92 100, 99 8,7 17, 16 26, 25 33, 32 41, 40 I Receive Data. RXD 2[1:0], RXD 3[1:0], RXD 5[1:0], RXD 6[1:0], RXD 7[1:0] internally pull down. These bundle signals are input from the Reduced MII connecting device. RXD0~7[1:0] shall transition synchronously to REFCLK. For each clock period in which RXDV0~7 is being asserted, RXD0~7[1:0] transfers two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined value for RXD0~7[1:0] is transferred instead of the recovered data. RXD0~7[1:0] shall be “00” to indicate idle when RXDV0~7 is de-asserted. Values of RXD0~7[1:0] other than “00” when RXDV0~7 as recovered from RXDV0~7 is de-asserted are reserved for out-ofband signaling (to be defined). Values other than “00”on RXD0~7[1:0] while RXDV0~7 as recovered from RXDV0~7 is de-asserted shall be ignored by the MAC. Upon assertion of RXDV0~7, the PHY shall ensure that RXD0~7[1:0]=”00”until proper receive decoding takes place. These pins will be in high impedance, and ignore the input when RXDV0~7 is negative. RXC0 79 BI Receive Clock for port0 MII mode. 4ma RXD0[3:2] 84, 83 BI Receive Data. RXD 0[3:2] internally pull down for port0 MII mode.. 4ma CRS0 69 BI Carrier Sense for port0 MII mode. 4ma COL0 70 BI Collision for port0 MII mode. 4ma MII# 67 ADMtek Incorporated 00/04/25 I Internally pull up. Active low. This pin can be tied to low for reversing the Reduced MII to MII (port0 only). There is an internal pull high for default configuration. ADM6308 also provides the 1MII+7RMII mode for customer specific requirement. The default address IDs for PHY are the consecutive numbers as follows: 7(for port 0 MII), 8, 9, 10, 11,12,13,14,(for port 1~7 RMII). P.S.: The ID addresses must be the consecutive numbers, otherwise, ADM6308 won’t recognize the ID address for PHY. 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification MDC 43 6 O Management Data Clock. Provides the reference clock for the MDIO signal 8ma MDIO 45 BI Management Data Input/output. This pin provides the channels for ADM6308 and Transceivers to transfer the control information and status. 8ma 46 tri Buffer Full or Faulty LED Display. This occurs when the packet is lost and flow control is 8ma disabled. Or, if flow control is enabled and jam or PAUSE frames are sent, buffer full LED will flash. If it is found faulty, the LED will always be on. (See LED function description) LED Display QFLED# High Priority Frame high_port[0] high_port[1] high_port[2] high_port[3] high_port[4] high_port[5] high_port[6] high_port[7] 53 54 55 56 58 59 60 61 BI Priority setting for port0~port7. Internally pull down. High = high priority BP0 BP1 50 49 I Back Pressure Mode. Internally pull down. The BP0~1 modes define 4 different backpressure methods. Each BPA1~3 has different algorithm described in EEPROM section. The following shows ADM6308 configuration of back-pressure. BP1 BP0 0 0 Back Pressure Disable 0 1 BPA1 (Back Pressure Algorithm 1) Enable 1 0 BPA2 (Back Pressure Algorithm 2) Enable 1 1 BPA3 (Back Pressure Algorithm 3) Enable NA16# 51 I Not aborted after continuous 16- times of collision if pull down. Internally pull up. XFC# 48 I Full Duplex Flow Control. Internally pull up. When 802.3 x flow control is disable, no PAUSE frame will be sent. (default) REFCLK 10 I Clock reference input of 50MHz Reduced MII. Synchronous clock reference for receiving, transmitting, and control interface. RESET# 63 I RESET#. Active low. For power on reset to initiate ADM6308 and let all the state machines and statuses enter the initial and default state. Besides, all the LED will be turned on when power is on or RAM testing failed. RECALL 52 I Whenever the level is changed, ADM6308 recalls EEPROM or 8051-like controller to get configuration data. Internally pull down. TEST[0] 65 I Test mode. Internally pull down TEST[1] 66 I Test mode. Internally pull down Configuration Miscellaneous Power Vddi 6, 23, 38, 57, 68, 89 2.5V Vddo 11, 27, 44, 71, 94 3.3V ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification Vss 9, 19, 42, 64, 75, 91 1, 18, 34, 47, 62, 85 ADMtek Incorporated 00/04/25 7 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 8 EEPROM Content The EEPROM setting must be in 16-bit mode. Offset Content 00H Check Pattern 01H System Configuration Description Must be set to 017C Bit 3~0 – Inter Frame Gap in half-duplex mode only. Default is zero (96 bittime). Bit 3 is a sign bit. When bit 3 is zero, it means negative. Bit 0 ~ 2 present decimal value of bit time (times four). For example, 1010, the IFG is equal to 96 + 2 X 4 = 104. Bit 7~4 – Configurable aging time. Default is 300 sec. When bit 7 is one, fast aging time (15 sec) is set. If all zero, aging timer is disabled. For the other value, list below. bit 7 bit 6 bit 5 bit 4 0 0 0 1 Aging time is 300 sec (Default) 0 0 1 0 Aging time is 600 sec 0 0 1 1 Aging time is 1200 sec 0 1 0 0 Aging time is 2400 sec 0 1 0 1 Aging time is 4800 sec 0 1 1 0 Aging time is 9600 sec 0 1 1 1 Aging time is 38400 sec Bit 9~ 8 – Broadcast storming mode. This mode is only for broadcast destination address, FF FF FF FF FF FF. bit 9 bit 8 0 0 Disable (Default) 0 1 256 blocks 1 0 192 blocks 1 1 128 blocks Bit 11 ~ 10 – Maximum Length of the data field of frame format. Bit 11 bit 10 0 0 Maximum length is 1536 bytes (Default) 0 1 Maximum length is 1518 bytes 1 0 Maximum length is 1522 bytes 1 1 Reserved Bit 12 – Continuous 16-time collision abort per packet is enabled if set to zero. Default is zero. EEPROM setting has higher priority than pin’s. Bit 13 – Hashing algorithm selection. If zero, direct mapping algorithm is selected. Otherwise, CRC hashing algorithm is adopted. Default is zero. Bit 14 – Over written address. Default is zero, which means over written address is not allowed whenever the same addresses entry condition occurred after hashing algorithm implementation finished. 02H Bit 15 - Must be set to zero. Back Pressure and Back- Bit 2 ~ 0 - Must be “ 0 0 1 ”. off Bit 6 ~ 4 - Must be “ 1 0 1 “. Bit 11 ~ 8 –Jam number for BP algorithm 1 Bit 13 ~ 12 – BP mode 00 : disable BP 01 : BP jam 10 : BP jam ALL ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 9 11 : BP carrier Bit 14 – 1 (Default) Bit 15 – 0 (Default) Auto-negotiation monitor Bit 7 ~ 0 – N-WAY monitor disable port [7:0]. 0 : Enable (Default) Bit 15 ~ 8 - Port disable port [7:0]. 0 : Enable (Default) Speed and Half/Full Bit 7 ~ 0 – Full/half operation. Each bit presents dedicated port number. Lower Duplex setting when bit is intended for smaller port number. 1 stands for full duplex, 0 N-Way monitor disable for half duplex. Bit 15 ~ 8 – Speed setting for port [7:0]. Speed operation, 10Mbps or 100Mbps. One bit per port. 1 stands for 100Mbps, 0 for 10Mbps. 4 Port-Groups Operation Bit 7 ~ 0 – Port group II [7:0], Default is 00h. (1) Bit 15 ~ 8 – Port group I [7:0], Default is FFh. 4 Port-Groups Operation Bit 7 ~ 0 – Port group IV [7:0], Default is 00h. (2) Bit 15 ~ 8 – Port group III [7:0], Default is 00h. 802.3x flow control Bit 7 ~ 0 – Per port BP enabled port [7:0], 1 stands for Enable (Default). If and Back pressure enabled, it must be in half duplex mode. enable Bit 15 ~ 8 – Per port 802.3x flow control enabled port [7:0]. 0 stands for Disable (by pin) 802.3x flow control Bit 7 ~ 0 – Force 802.3x flow control on (ignore AN) port [7:0]. If enabled, it must be in full duplex. 0 stands for disable (Default). Bit 15 ~ 8 – Write FC-bit (10th bit) of MII register4 port [7:0], 1 stands for Enable (Default). Reserved Must be set to 112H Reserved Must be set to 132H Reserved Must be set to B2H Reserved Must be set to D2H Reserved Must be set to 150H Reserved Must be set to 170H Reserved Must be set to 150H Reserved Must be set to 170H Reserved Must be set to e8H Reserved Must be set to c8H Reserved Bit 7~0 - Must be set to 18H Bit 15~8 – Must be set to 0cH Priority Frame operation Bit 7 ~ 0 – Auto turn off BP/FC, if get priority packet port [7:0]. 0 stands for disable (Default) Bit 11 ~ 8 –Round-robin(sequential) number of high and low priority frame For example as follows: bit11 bit10 bit9 bit8 0 0 0 0 Weighted ratio is unlimited 0 0 0 1 Weighted ratio 1:1 0 0 1 0 Weighted ratio 2:1 1 0 0 0 Weighted ratio 8:1 (Default) Bit 13 – Must be set to 0. Bit 14 –Must be set to 0. Bit 15 – Priority is enabled, 1 stands for enable (Default). 15H TOS priority port 16H VLAN ADMtek Incorporated 00/04/25 Bit 15 ~ 8 – Set TOS priority port [7:0], 0 stands for no check (Default). One bit per port. e.g. bit 8 for port 0 and bit 15 for port 7. Bit 7 ~ 0 - Set VLAN priority port [7:0], 0 stands for no check (Default). One bit per port. e.g. bit 0 for port 0 and bit 7 for port 7. 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 10 17H TOS bit map 18H TOS bit map 19H TOS bit map 1AH TOS bit map 1BH PHY operation (1) 1CH PHY operation (2) 1DH Reserved ADMtek Incorporated 00/04/25 Bit 15 ~ 8 – First, ADM6308 will check the specific bits recorded in the type field of packet format to verify the VLAN status of packets, then set the threshold of VLAN. The default of threshold is 4. If threshold ¡ Ù 4, the packet is high priority. Bit 15 ~ 0 - TOS bit map [63:48](tos_pri)(tos_pri_drop), Default is 0. First, ADM6308 will check the specific bits recorded in the type field of TCP/IP packet format, to verify the TOS status of packets, then Implement the bits mapping for priority setting of each port. Bit 15 ~ 0 - TOS bit map [47:32](tos_pri)(tos_pri_drop), Default is 0. First, ADM6308 will check the specific bits recorded in the type field of TCP/IP packet format, to verify the TOS status of packets, then Implement the bits mapping for priority setting of each port. Bit 15 ~ 0 - TOS bit map [31:16](tos_pri)(tos_pri_drop), Default is 0. First, ADM6308 will check the specific bits recorded in the type field of TCP/IP packet format, to verify the TOS status of packets, then Implement the bits mapping for priority setting of each port. Bit 15 ~ 0 - TOS bit map [15: 0](tos_pri)(tos_pri_drop), Default is 0. First, ADM6308 will check the specific bits recorded in the type field of TCP/IP packet format, to verify the TOS status of packets, then Implement the bits mapping for priority setting of each port. Bit 4 ~ 0 – PHY rewrite register address. These bits present PHY register address selection. Bit 7 – PHY rewrite. Default is zero (Disable ). Bit 12 ~ 8 – PHY start ID. Default is 00H. This means PHY IDs range from 00 H to 07H in sequence if default value is set. Remember start ID always has to remain consistent with the first port ID setting in PHY. Bit 15 ~ 13 – N/A. Bit 15 ~ 0 – PHY rewrite data. After PHY rewrite register address is selected, the register in each port is set to rewrite data. Must be set to 10dH 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 11 Function Description ADM6308 is a high performance, low cost, quality assurance 8-port Fast Ethernet Controller dedicated to 8-port switch solutions. This chip operates at 50MHz and fully complies with IEEE 802 series specifications, including MAC and Physical layers. The switch operations include forwarding scheme, packet filtering, address learning, buffer management, LED display, etc. Packets from Reduced MII interface should be stored in the memory. Then, source address learning, packet filtering, and retransmission to known or unknown port(s) is implemented based on real application. Reset and Restart When ADM6308 is on, it starts in embedded memory self-test mode. Port Interface 10/100Mbps Reduced MII Interface Each port of ADM6308 supports Reduced MII interfaces, which uses six pins, TXE0~7, TXD0~7[1:0], RXDV0~7, RXD0~7[1:0]. Feature setting can be chosen by configuration pin. The RMII specification has the following characteristics: 1. It supports 10Mbps and 100Mbps data rates 2. A single clock reference sources from the MAC to PHY (or from an external source) 3. It provides independent 2-bit wide (di-bit) transmit and receive data paths RMII Specification Signals Signal Name Direction with respect to PHY REFCLK Input Direction with respect Usage to the MAC Input or Output Synchronous clock reference for receive, transmit and control interface RXDV Output Input Carrier Sense RXD[1:0] Output Input Receive Data TXE Input Output Transmit Enable TXD[1:0] Input Output Transmit Data All detail pin description (please see pin assignment). In addition, ADM6308 also provides the MII mode at port 0 only. The relevant settings are described in the previous pages of pin description. Buffer Management The buffer memory is embedded in ADM6308 for eight port switch operations, which are designed based on output queuing and dynamic shared memory management architecture. Media Access Control ADM6308 implements all functions of IEEE 802.3 MAC protocol such as frame formatting, collision handling, etc. ADM6308 generates 56-bit preamble and Start of Frame delimiter while a packet is being sent. In half-duplex mode, listening before transmitting allows to prevent traffic jam. Whenever a collision occurs, packet will be delayed for a random time, then be resent. EEPROM or Dynamic configured by 8051 EEPROM is a configuration option for 8-port switch setting. This setting can also be called through Recall pin triggered by the controller like 8051. 1. EEPROM recall after power-on is reset. ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 12 2. The configuration can be changed without a reset. Toggling the “recall” pin will read the EEPROM again, while 8051 will emulate the signal like EEPROM Operation Modes Reduced MII interface to PHYs or transceivers can operate at 10/100Mbps full or half-duplex mode. To keep a consistent operation speed, these two parts (PHY and switching controller) will be automatically adjusted the mode through MDC/MDIO pins. ADM6308 also provides fixed speed and operation mode configured by EEPROM, and dynamic configuration by the controller like 8051. All modes support full wire speed operations without any interference. Automatic Address Learning, Forwarding, and Filtering Function Address Recognition ADM6308 provides 1Kbytes embedded MAC address table to implement the address recognition. Self-learning bridge function is based on source address packets field. Look-up table and two different hashing algorithms strengthen the bridge ability with high performance assurance. Configurable aging time is also supported. An entry of hashing table is calculated by 32-bit polynomial (called CRC hashing function) or direct mapping (called simple hashing function), as well as MAC address (called input data). Direct mapping function is allocated the lowest 10 bits of SA/DA address as buffer address entry. Hashing function selection is set to bit 13 of offset 01H in EEPROM. Each DA (Destination Address) passes through hashing function and gets a 10-bit entry point of embedded SRAM. If the record is empty, the packet is broadcast, treated as an unknown frame. Otherwise, the record is read, then MAC address in storage and DA from current packet are compared. If the two addresses are the same, a port number is decided, and the packet is forwarded to the assigned port. If the two addresses are different, the incoming packet is also treated as an unknown packet. A broadcast packet will pass through the other ports without address recognition. Learning Process Address learning process is composed of SA packets and a hashing function described above. For each incoming packet, ADM6308 will check and see whether the packet is errorless and whether the content of the entry address in SRAM is assigned. If it is, the packet will be compared to source MAC address, and the port number. If both fields match the packet information, aging status is revised to new learnt address. If MAC addresses matches, but the port number is different, port number is re-assigned. When the entry collides, the new SA address is ignored and the record keeps the old one. Last possibility, if the record is free, MAC address and port number of the incoming packet are stored. The following diagram describes the general operations of address learning and recognition. DA or SA CRC or Direct Mapping Hashing Function [0:9] Address Entry Point AAA-1 AAA AAA+1 Address Look-up Table Fig. 1 Address Learning and Recognition Forwarding Scheme ADM6308 forwarding scheme adopts store-and-forward method. Each determined outgoing packet in the buffer of incoming port is directly sent to the assigned port. The forwarding scheme of unknown packets is treated the same as broadcast packet. ADM6308 also requires first- in-first-out service, to prevent packets disorder. IEEE 802.3 Congestion Control In half duplex operation, ADM6308 supports back pressure feature. When the buffer is full, jam packet or 802.3x control frame is sent to the connected segment, which is called back - pressure. ADM6308 implements Alternative back - pressure based on either one of three algorithms described in EEPROM section. If free blocks in the buffer memory match or are below the threshold, jam packet is directly transmitted regardless of routing decision. ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 13 In Full duplex flow control, ADM6308 follows IEEE 802.3x standard. The delay time in PAUSE frame can be set to zero or to the maximum value. The feature allows ADM6308 to handle remote-side PAUSE frame. In full duplex flow control, the state machine and threshold values are described in EEPROM, too. 6 octets 6 octets Destination Address Source Address 2 octets 2 octets 2octets Type Opcode Pause Time 42 octets PAD Fig 2 IEEE 802.3x PAUSE Frame Format The diagram shown above is IEEE 802.3x Pause frame format. All fields are listed below. Destination Address: destination MAC address (Generally the content is 0x0180C2000001) Source Address: source MAC address Type: the PAUSE frame type is 0x8808 Opcode : the value is fixed, 0x0001 (PAUSE operation) Pause Time: Number of slot-time PAD: All zeroes In ADM6308, if a PAUSE frame is received from a certain port with DA 0x0180C2000001 or 0xFFFFFFFFFFFF, ADM6308 will stop the ports transmission of packets and the timer until timeout or another PAUSE frame with zero time. If the buffer is full and in full duplex mode, ADM6308 will send PAUSE frame with the maximum delay time, to defer receiving packet. When enough buffer is released, PAUSE frame with zero delay is sent. Auto-negotiation Operations When MDC/MDIO pins do not communicate with transceivers, ADM6308 can be set to 10/100Mbps or half/full duplex mode independently. Otherwise, ADM6308 can adjust its speed itself according to auto-negotiation with PHYceiver. Priority Frame (CoS) Operations ADM6308 can set the packets as high priority as follows: Port Number (set by pin), VLAN tag, TCP/IP TOS/DS (both can be set by EEPROM or 8051-like controller) and the scheme of weighted round robin. The priority setting by port means that all the packets received by the port will be priority frames; ADM6308 can also judge the priority of frames by checking the specific bits of VLAN tag or TCP/IP TOS/DS included in the frame format. ADM6308 will check the specific bits recorded in the type field of packet format to ensure the VLAN or TCP/IP TOS/DS status of packets, then set the threshold of VLAN or TCP/IP TOS/DS to declare the priority of packets. In addition, the scheme of weighted round robin is used for judging the high and low priority of frames, which utilizes the notion of weighted ratio of priority frame vs. normal frame to decide the frame priority level. When the port receives the priority frame, back pressure & 802.3x flow control will be turned off until no priority frame occurs within 1 or 2 seconds, then turn on back pressure and 802.3x flow control again. VLAN and Broadcast Storming Prevention ADM6308 supports VLAN function to ease the administration of logical groups of stations that can communicate as if they were on the same LAN, and move, add or change in numbers of these groups. ADM6308 also supports 4 port-groups scheme to effectively prevent the broadcast storming from interfering with the whole transmission efficiency between ports. The 8 ports can be divided into 4 groups while broadcast storming is starting, then the broadcast frames to be transmitted to the destination port belonging to other groups will be prohibited. During this time, the ports belonging to different groups are independent. Only the destination port of broadcast frames in the same group will be allowed. Furthermore, the scheme of port-group dividing is very flexible. The overlapped port-groups are allowed during some operations, for example, one port can be shared by two groups, and all the other operations between these two groups remain independent except for the overlapped port. Only the overlapped port could use the same DA for two different VLAN port-groups. ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 14 Inter-Frame Gap IFG is the idle time between any two continuous packets from the same port. The default value of 10Mbps is 9.6usec and 0.96usec for 100Mbps. IFG mode can only be from CRS to TXE. MDC, MDIO Interface Olive plus PHY MDC MDC MDIO MDIO Fig. 3 A specific application of Serial Management Interface There are two pins of Serial Management Interface for ADM6308. MDC (Management Data Clock) is an input pin. It functions MII interface of PHY device. The MDIO pin is a bi-directional I/O pin of MII interface to PHY device. If the following conditions are true, ADM6308 will set bit 1 of register 4 to 1 and bit 9 of register 0 to 1 in connected transceiver. First, IEEE 802.3x flow control is enabled. Then, the port number of Flow Control Write in EEPROM offset 05H is enabled. Then, ADM6308 is in full duplex simultaneously with the Transceiver. After write operation through MDIO, auto-negotiation is restarted and ADM6308 can gain the information of remote 802.3x flow control. Finally, the ultimate operation of flow control is set. LED Interface ADM6308 supports one LED only assigned to Pin 46, which represents the buffer as full and RAM test fault. When ADM6308 is reset, LED is off. While in testing mode, LED is on. If the test for embedded data buffer & address table fails, the LED will flash once, for about 1.6 sec, and then stay on. Next, if the testing for the other embedded memory fails, LED will flash twice, for about 1.6sec. After RAM tests are successful, LED status is down, for about 3.2sec. minimum. If back -pressure or full duplex flow control is set, the buffer full LED will flash every 200ms, then stay on for 3.2sec based on jam packet or if PAUSE frame is sent. If an arrival packet is dropped, the LED will flash every 50ms, then stay on for 3.2sec. ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 15 Absolute Maximum Ratings Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection -0.5 V to 2.7 V -0.5 V to VCC + 0.3 V -0.5 V to VCC + 0.3 V -65 °C to 150 °C(-85°F to 302°F) 0°C to 70°C(32°F to 158°F) 2000V DC Specifications Parameter Vcc Icc Vil Vih Iil Iih Vol Voh Cinp Lpinp Description Condition Supply Voltage Power Supply Vcc = 2.5V Input LOW Voltage Input HIGH Voltage Input LOW Leakage Current Vin = 0.8V Input HIGH Leakage Current Vin = 2.0V Output LOW Voltage Iout =2~8mA Output HIGH Voltage Iout =-2~-8mA Input Pin Capacitance Pin Inductance Min Typical Max Units 2.3 2.5 2.7 420 0.8 3.8 10 10 0.4 V mA V V uA uA V V pF nH -0.5 2.0 -10 -10 . 2.4 5 N/A 8 AC Specifications EEPROM Timing t21 EECK t24 t22 EECS EEDI t25 t26 EEDO Parameter Description Condition Min t21 t22 EECK (50% duty cycle) EECS/EEDI delay from falling of EECK idle time of two EECS EEDO valid before rising of EECK EEDO hold after rising of EECK Clock = 50MHz Clock = 50MHz 620 100 ns ns Clock = 50MHz 4000 100 30 ns ns ns t24 t25 t26 ADMtek Incorporated 00/04/25 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Max Units Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 16 RMII Transmit and Receive Timing REF_CLK TX_EN TXD(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x x 0 TXD(0) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x 0 Preamble Data SFD REF_CLK CRS_DV RXD(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x x 0 RXD(0) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 x x x x x x 0 /J/ Symbol Tsu Thold ADMtek Incorporated 00/04/25 /K/ Preamble Parameter REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, Data setup to REF_CLK rising edge TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, Data hold from REF_CLK rising edge SFD Min Type Max Units 65 MHz % 50 35 4 ns 2 ns 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 Data Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential Olive plus Specification 17 ADM6308 Package 80 51 50 81 ADMtek plus e Olive b HD D ADM6308 xxxxxxxxxxxxxxxx 31 100 1 30 E HE A2 c L A A1 y L1 SYMBO L inch MIN NOM MAX MIN NOM MAX A - - 0.134 - - 3.40 A1 0.010 - A2 0.098 0.107 b 0.009 C 0.004 D E 0.547 0.783 e L y 00/04/25 0.25 - 0.114 2.50 2.72 2.90 0.012 0.015 0.22 0.30 0.38 - 0.008 0.09 - 0.20 0.551 0.555 13.9 14 14.1 0.787 0.791 19.9 20.00 20.1 - 0.026 BSC 0.018 L1 ADMtek Incorporated mm 0.024 - 0 3.5 - 0.65 BSC 0.030 0.45 0.063 REF - * HD=17.2mm * HE=23.2mm 0.60 0.75 1.60 REF 0.003 - - 7 0 3.5 1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Version : 1.10 0.076 7 Tel : (03)578-8879 Fax : (03)578-8871 ADMtek Incorporated Confidential