NCP1200 PWM Current−Mode Controller for Low−Power Universal Off−Line Supplies Housed in SOIC−8 or PDIP−8 package, the NCP1200 represents a major leap toward ultra−compact Switchmode Power Supplies. Due to a novel concept, the circuit allows the implementation of a complete offline battery charger or a standby SMPS with few external components. Furthermore, an integrated output short−circuit protection lets the designer build an extremely low−cost AC−DC wall adapter associated with a simplified feedback scheme. With an internal structure operating at a fixed 40 kHz, 60 kHz or 100 kHz, the controller drives low gate−charge switching devices like an IGBT or a MOSFET thus requiring a very small operating power. Due to current−mode control, the NCP1200 drastically simplifies the design of reliable and cheap offline converters with extremely low acoustic generation and inherent pulse−by−pulse control. When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the skip cycle mode and provides excellent efficiency at light loads. Because this occurs at low peak current, no acoustic noise takes place. Finally, the IC is self−supplied from the DC rail, eliminating the need of an auxiliary winding. This feature ensures operation in presence of low output voltage or shorts. Features • • • • • • • • • • • • No Auxiliary Winding Operation Internal Output Short−Circuit Protection Extremely Low No−Load Standby Power Current−Mode with Skip−Cycle Capability Internal Leading Edge Blanking 250 mA Peak Current Source/Sink Capability Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz Direct Optocoupler Connection Built−in Frequency Jittering for Lower EMI SPICE Models Available for TRANsient and AC Analysis Internal Temperature Shutdown Pb−Free Packages are Available • AC−DC Adapters • Offline Battery Chargers • Auxiliary/Ancillary Power Supplies (USB, Appliances, TVs, etc.) December, 2004 − Rev. 13 MARKING DIAGRAMS 8 SOIC−8 D SUFFIX CASE 751 8 200Dy ALYW 1 1 8 PDIP−8 P SUFFIX CASE 626 1200Pxxx AWL YYWW 8 1 1 xxx y = Device Code: 40, 60 or 100 = Device Code: 4 for 40 6 for 60 1 for 100 A = Assembly Location L = Wafer Lot Y, YY = Year W, WW = Work Week PIN CONNECTIONS Adj 1 8 HV FB 2 7 NC CS 3 6 VCC GND 4 5 Drv (Top View) ORDERING INFORMATION Typical Applications Semiconductor Components Industries, LLC, 2004 http://onsemi.com 1 See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Publication Order Number: NCP1200/D NCP1200 C3 10 F 400 V * + 1 6.5 V @ 600 mA D2 1N5819 HV 8 Adj 2 FB NC 7 3 CS VCC 6 M1 MTD1N60E 4 GND Drv 5 + C2 470 F/10 V Rf 470 EMI Filter + C5 10 F Rsense D8 5 V1 Universal Input *Please refer to the application information section Figure 1. Typical Application ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Description 1 Adj Adjust the Skipping Peak Current This pin lets you adjust the level at which the cycle skipping process takes place. 2 FB Sets the Peak Current Setpoint By connecting an Optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 CS Current Sense Input This pin senses the primary current and routes it to the internal comparator via an L.E.B. 4 GND The IC Ground 5 Drv Driving Pulses The driver’s output to an external MOSFET. 6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 10 F. 7 NC No Connection This un−connected pin ensures adequate creepage distance. 8 HV Generates the VCC from the Line Connected to the high−voltage rail, this pin injects a constant current into the VCC bulk capacitor. http://onsemi.com 2 NCP1200 Adj 8 1 HV Current Source 75.5 k FB 1.4 V + 2 HV Skip Cycle Comparator UVLO High and Low Internal Regulator Internal VCC − 7 NC 29 k Current Sense Ground 8k 4 + − Vref 5.2 V Set 40, 60 or 100 kHz Clock 250 ns L.E.B. 3 Q Flip−Flop DCmax = 80% Q 6 Reset VCC + 60 k 5 − 1V 20 k Drv ±110 mA Overload? Fault Duration Figure 2. Internal Circuit Architecture ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ MAXIMUM RATINGS Rating Symbol Value Units Power Supply Voltage VCC 16 V Thermal Resistance Junction−to−Air, PDIP−8 version Thermal Resistance Junction−to−Air, SOIC version RJA RJA 100 178 °C/W Maximum Junction Temperature Typical Temperature Shutdown TJmax 150 140 °C − Tstg −60 to +150 °C ESD Capability, HBM Model (All Pins except VCC and HV) − 2.0 kV ESD Capability, Machine Model − 200 V Maximum Voltage on Pin 8 (HV), pin 6 (VCC) Grounded − 450 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 F − 500 V Minimum Operating Voltage on Pin 8 (HV) − 30 V Storage Temperature Range Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 3 NCP1200 ELECTRICAL CHARACTERISTICS (For typical values TJ = +25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC= 11 V unless otherwise noted) Rating Pin Symbol Min Typ Max Unit VCC Increasing Level at Which the Current Source Turns−off 6 VCCOFF 10.3 11.4 12.5 V VCC Decreasing Level at Which the Current Source Turns−on 6 VCCON 8.8 9.8 11 V VCC Decreasing Level at Which the Latchoff Phase Ends 6 VCClatch − 6.3 − V Internal IC Consumption, No Output Load on Pin 5 6 ICC1 − 710 880 Note 1 A Internal IC Consumption, 1 nF Output Load on Pin 5, FSW = 40 kHz 6 ICC2 − 1.2 1.4 Note 2 mA Internal IC Consumption, 1 nF Output Load on Pin 5, FSW = 60 kHz 6 ICC2 − 1.4 1.6 Note 2 mA Internal IC Consumption, 1 nF Output Load on Pin 5, FSW = 100 kHz 6 ICC2 − 1.9 2.2 Note 2 mA Internal IC Consumption, Latchoff Phase 6 ICC3 − 350 − A High−voltage Current Source, VCC = 10 V 8 IC1 2.8 4.0 − mA High−voltage Current Source, VCC = 0 V 8 IC2 − 4.9 − mA Output Voltage Rise−time @ CL = 1 nF, 10−90% of Output Signal 5 Tr − 67 − ns Output Voltage Fall−time @ CL = 1 nF, 10−90% of Output Signal 5 Tf − 28 − ns Source Resistance (drive = 0, Vgate = VCCHMAX − 1 V) 5 ROH 27 40 61 Sink Resistance (drive = 11 V, Vgate = 1 V) 5 ROL 5 12 25 Input Bias Current @ 1 V Input Level on Pin 3 3 IIB − 0.02 − A Maximum internal Current Setpoint 3 ILimit 0.8 0.9 1.0 V Default Internal Current Setpoint for Skip Cycle Operation 3 ILskip − 350 − mV Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 100 160 ns Leading Edge Blanking Duration 3 TLEB − 230 − ns Oscillation Frequency, 40 kHz Version − fOSC 36 42 48 kHz Oscillation Frequency, 60 kHz Version − fOSC 52 61 70 kHz Oscillation Frequency, 100 kHz Version − fOSC 86 103 116 kHz Built−in Frequency Jittering, FSW = 40 kHz − fjitter − 300 − Hz/V Built−in Frequency Jittering, FSW = 60 kHz − fjitter − 450 − Hz/V Built−in Frequency Jittering, FSW = 100 kHz − fjitter − 620 − Hz/V Maximum Duty Cycle − Dmax 74 80 87 % Internal Pullup Resistor 2 Rup − 8.0 − k Pin 3 to Current Setpoint Division Ratio − Iratio − 4.0 − − Default skip mode level 1 Vskip 1.1 1.4 1.6 V Pin 1 internal output impedance 1 Zout − 25 − k DYNAMIC SELF−SUPPLY (All Frequency Versions, Otherwise Noted) INTERNAL CURRENT SOURCE DRIVE OUTPUT CURRENT COMPARATOR (Pin 5 Un−loaded) INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1 k) FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1 k) SKIP CYCLE GENERATION 1. Max value @ TJ = −25°C. 2. Max value @ TJ = 25°C, please see characterization curves. http://onsemi.com 4 NCP1200 60 11.70 50 11.60 40 11.50 VCCOFF (V) LEAKAGE (A) 100 kHz 30 11.40 40 kHz 20 11.30 10 11.20 0 −25 0 25 50 75 100 11.10 −25 125 60 kHz 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. HV Pin Leakage Current vs. Temperature Figure 4. VCC OFF vs. Temperature 9.85 125 900 100 kHz 9.80 850 60 kHz 800 9.70 ICC1 (A) VCCON (V) 9.75 9.65 9.60 40 kHz 750 700 9.55 650 9.50 9.45 −25 100 kHz 60 kHz 40 kHz 0 25 50 75 100 600 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. VCC ON vs. Temperature Figure 6. ICC1 vs. Temperature 2.10 110 104 100 kHz 1.90 125 100 kHz 98 92 FSW (kHz) ICC2 (mA) 1.70 1.50 60 kHz 1.30 86 80 74 68 60 kHz 62 56 40 kHz 1.10 50 40 kHz 44 0.90 −25 0 25 50 75 100 38 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. ICC2 vs. Temperature Figure 8. Switching Frequency vs. TJ http://onsemi.com 5 125 NCP1200 6.50 460 430 6.45 6.40 370 ICC3 (A) VCCLATCHOFF (V) 400 6.35 340 310 280 6.30 250 6.25 220 6.20 −25 0 25 50 75 100 190 −25 125 100 Figure 10. ICC3 vs. Temperature 125 1.00 Source CURRENT SETPOINT (V) 75 Figure 9. VCC Latchoff vs. Temperature 40 30 20 Sink 10 0 25 50 75 100 0.96 0.92 0.88 0.84 0.80 −25 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. DRV Source/Sink Resistances Figure 12. Current Sense Limit vs. Temperature 86.0 1.33 84.0 DUTY−MAX (%) 1.34 1.32 Vskip (V) 50 TEMPERATURE (°C) 50 1.31 1.30 1.29 1.28 −25 25 TEMPERATURE (°C) 60 0 −25 0 82.0 80.0 78.0 76.0 0 25 50 75 100 74.0 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Vskip vs. Temperature Figure 14. Max Duty Cycle vs. Temperature http://onsemi.com 6 125 NCP1200 APPLICATIONS INFORMATION INTRODUCTION The NCP1200 implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC−DC adapters, auxiliary supplies etc. Due to its high−performance High−Voltage technology, the NCP1200 incorporates all the necessary components normally needed in UC384X based supplies: timing components, feedback devices, low−pass filter and self−supply. This later point emphasizes the fact that ON Semiconductor’s NCP1200 does NOT need an auxiliary winding to operate: the product is naturally supplied from the high−voltage rail and delivers a VCC to the IC. This system is called the Dynamic Self−Supply (DSS). Dynamic Self−Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with a bunch of simple logical equations: POWER−ON: IF VCC < VCCOFF THEN Current Source is ON, no output pulses IF VCC decreasing > VCCON THEN Current Source is OFF, output is pulsing IF VCC increasing < VCCOFF THEN Current Source is ON, output is pulsing Typical values are: VCCOFF = 11.4 V, VCCON = 9.8 V To better understand the operational principle, Figure 15’s sketch offers the necessary light: VCCOFF = 11.4 V VCC 10.6 V Avg. VCCON = 9.8 V ON OFF Current Source Output Pulses 10.00M 30.00M 50.00M 70.00M 90.00M Figure 15. The Charge/Discharge Cycle Over a 10 F VCC Capacitor . 0.16 = 256 mW. If for design reasons this contribution is still too high, several solutions exist to diminish it: 1. Use a MOSFET with lower gate charge Qg 2. Connect pin through a diode (1N4007 typically) to one of the mains input. The average value on pin 8 The DSS behavior actually depends on the internal IC consumption and the MOSFET’s gate charge, Qg. If we select a MOSFET like the MTD1N60E, Qg equals 11 nC (max). With a maximum switching frequency of 48 kHz (for the P40 version), the average power necessary to drive the MOSFET (excluding the driver efficiency and neglecting various voltage drops) is: Fsw Qg V cc 2*V mains PEAK. Our power contribution becomes example drops to: 160 mW. with Fsw = maximum switching frequency Qg = MOSFET’s gate charge VCC = VGS level applied to the gate To obtain the final driver contribution to the IC consumption, simply divide this result by VCC: Idriver = Fsw Qg = 530 A. The total standby power consumption at no−load will therefore heavily rely on the internal IC consumption plus the above driving current (altered by the driver’s efficiency). Suppose that the IC is supplied from a 400 V DC line. To fully supply the integrated circuit, let’s imagine the 4 mA source is ON during 8 ms and OFF during 50 ms. The IC power contribution is therefore: 400 V . 4 mA Dstart 1N4007 C3 4.7 F 400 V EMI Filter + NCP1200 1 HV 8 Adj 2 FB NC 7 3 CS VCC 6 4 GND Drv 5 Figure 16. A simple diode naturally reduces the average voltage on pin 8 http://onsemi.com 7 NCP1200 3. Permanently force the VCC level above VCCH with an auxiliary winding. It will automatically disconnect the internal startup source and the IC will be fully self−supplied from this winding. Again, the total power drawn from the mains will significantly decrease. Make sure the auxiliary voltage never exceeds the 16 V limit. When FB is above the skip cycle threshold (1.4 V by default), the peak current cannot exceed 1 V/Rsense. When the IC enters the skip cycle mode, the peak current cannot go below Vpin1 / 4 (Figure 19). The user still has the flexibility to alter this 1.4 V by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. Skipping Cycle Mode The NCP1200 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 18 ). Suppose we have the following component values: Lp, primary inductance = 1 mH FSW, switching frequency = 48 kHz Ip skip = 300 mA (or 350 mV / Rsense) The theoretical power transfer is therefore: P1 P2 P3 Figure 18. Output pulses at various power levels (X = 5 s/div) P1<P2<P3 Max Peak Current 1 Lp Ip 2 Fsw 2.2 W 2 If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 2.2 . 0.1 = 220 mW. To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight: Skip Cycle Current Limit FB 4.8 V 3.8 V Figure 19. The skip cycle takes place at low peak currents which guarantees noise free operation Normal Current Mode Operation Skip Cycle Operation Ipmin = 350 mV / Rsense 1.4 V Figure 17. Feedback Voltage Variations http://onsemi.com 8 NCP1200 Overload Operation In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is interesting to implement a true short−circuit protection. A short−circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler LED. As a result, the FB pin level is pulled up to 4.1 V, as internally imposed by the IC. The peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated effects. Please note that this can also happen in case of feedback loss, e.g. a broken optocoupler. To account for this situation, the NCP1200 hosts a dedicated overload detection circuitry. Once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty cycle. The system recovers when the fault condition disappears. During the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. This period of time depends on normal output load conditions and the maximum peak current allowed by the system. The time−out used by this IC works with the VCC decoupling capacitor: as soon as the VCC decreases from the VCCOFF level (typically 11.4 V) the device internally watches for an overload current situation. If this condition is still present when VCCON is reached, the controller stops the driving pulses, prevents the self−supply current source to restart and puts all the circuitry in standby, consuming as little as 350 A typical (ICC3 parameter). As a result, the VCC level slowly discharges toward 0. When this level crosses 6.3 V typical, the controller enters a new startup phase by turning the current source on: VCC rises toward 11.4 V and again delivers output pulses at the UVLOH crossing point. If the fault condition has been removed before UVLOL approaches, then the IC continues its normal operation. Otherwise, a new fault cycle takes place. Figure 20 shows the evolution of the signals in presence of a fault. Power Dissipation The NCP1200 is directly supplied from the DC rail through the internal DSS circuitry. The current flowing through the DSS is therefore the direct image of the NCP1200 current consumption. The total power dissipation can be evaluated using: (V HVDC 11 V) ICC2. If we operate the device on a 250 VAC rail, the maximum rectified voltage can go up to 350 VDC. As a result, the worse case dissipation occurs on the 100 kHz version which will dissipate 340 . 1.8 mA@Tj = −25°C = 612 mW (however this 1.8 mA number will drop at higher operating temperatures). Please note that in the above example, ICC2 is based on a 1 nF capacitor loading pin 5. As seen before, ICC2 will depend on your MOSFET’s Qg: ICC2 = ICC1 + Fsw x Qg. Final calculations shall thus account for the total gate−charge Qg your MOSFET will exhibit. A DIP8 package offers a junction−to−ambient thermal resistance of RJ−A 100°C/W. The maximum power dissipation can thus be computed knowing the maximum operating ambient temperature (e.g. 70°C) together with the maximum allowable junction temperature (125°C): Pmax T Jmax T Amax = 550 mW. As we can see, we do not R RJA reach the worse consumption budget imposed by the 100 kHz version. Two solutions exist to cure this trouble. The first one consists in adding some copper area around the NCP1200 DIP8 footprint. By adding a min−pad area of 80 mm2 of 35 copper (1 oz.) RJ−A drops to about 75°C/W which allows the use of the 100 kHz version. The other solutions are: 1. Add a series diode with pin 8 (as suggested in the above lines) to drop the maximum input voltage down to 222 V ((2 350)/pi) and thus dissipate less than 400 mW 2. Implement a self−supply through an auxiliary winding to permanently disconnect the self−supply. SOIC−8 package offers a worse RJ−A compared to that of the DIP8 package: 178°C/W. Again, adding some copper area around the PCB footprint will help decrease this number: 12 mm x 12 mm to drop RJ−A down to 100°C/W with 35 copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 copper thickness (2 oz.). One can see, we do not recommend using the SOIC package for the 100 kHz version with DSS active as the IC may not be able to sustain the power (except if you have the adequate place on your PCB). However, using the solution of the series diode or the self−supply through the auxiliary winding does not cause any problem with this frequency version. These options are thoroughly described in the AND8023/D. http://onsemi.com 9 NCP1200 VCC Regulation Occurs Here 11.4 V Latchoff Phase 9.8 V 6.3 V Time Drv Driver Pulses Driver Pulses Time Internal Fault Flag Fault is Relaxed Time Fault Occurs Here Startup Phase Figure 20. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes. If the fault persists when VCC reached UVLOL, then the controller cuts everything off until recovery. Calculating the VCC Capacitor As the above section describes, the fall down sequence depends upon the VCC level: how long does it take for the VCC line to go from 11.4 V to 9.8 V? The required time depends on the startup sequence of your system, i.e. when you first apply the power to the IC. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 11.4 V to 9.8 V, otherwise the supply will not properly start. The test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. Let’s suppose that this time corresponds to 6ms. Therefore a VCC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including the MOSFET drive, establishes at 1.5 mA, we can calculate the required capacitor using the following formula: Protecting the Controller Against Negative Spikes As with any controller built upon a CMOS technology, it is the designer’s duty to avoid the presence of negative spikes on sensitive pins. Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. Sometimes, the injection can be so strong that internal parasitic SCRs are triggered, engendering irremediable damages to the IC if they are a low impedance path is offered between VCC and GND. If the current sense pin is often the seat of such spurious signals, the high−voltage pin can also be the source of problems in certain circumstances. During the turn−off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its VCC capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense. Unfortunately, if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low (e.g. the MOSFET Rdson + Rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. Since we are talking about ms pulses, the amount of injected charge (Q = I x t) immediately latches the controller which brutally discharges its VCC capacitor. If this VCC capacitor is of sufficient value, its stored energy damages the controller. Figure 21 depicts a typical negative shot occurring on the HV pin where the brutal VCC discharge testifies for latchup. t V C, with V = 2V. Then for a wanted t of 10 ms, i C equals 8 F or 10 F for a standard value. When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 350 A typical. This appends at VCC = 9.8 V and it remains stuck until VCC reaches 6.5 V: we are in latchoff phase. Again, using the calculated 10 F and 350 A current consumption, this latchoff phase lasts: 109 ms. http://onsemi.com 10 NCP1200 Figure 21. A negative spike takes place on the Bulk capacitor at the switch−off sequence Another option (Figure 23) consists in wiring a diode from VCC to the bulk capacitor to force VCC to reach UVLOlow sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. For security reasons, two diodes can be connected in series. Simple and inexpensive cures exist to prevent from internal parasitic SCR activation. One of them consists in inserting a resistor in series with the high−voltage pin to keep the negative current to the lowest when the bulk becomes negative (Figure 22). Please note that the negative spike is clamped to –2 x Vf due to the diode bridge. Please refer to AND8069/D for power dissipation calculations. 3 Rbulk > 4.7 k 2 + Cbulk 1 8 2 7 3 6 4 5 3 + Cbulk 1 + CVCC Figure 22. A simple resistor in series avoids any latchup in the controller 1 8 2 7 3 6 4 5 D3 1N4007 1 + CVCC Figure 23. or a diode forces VCC to reach UVLOlow sooner A Typical Application Figure 24 depicts a low−cost 3.5 W AC−DC 6.5 V wall adapter. This is a typical application where the wall−pack must deliver a raw DC level to a given internally regulated apparatus: toys, calculators, CD players etc. Due to the inherent short−circuit protection of the NCP1200, you only need a bunch of components around the IC, keeping the final cost at an extremely low level. The transformer is available from different suppliers as detailed on the following page. http://onsemi.com 11 NCP1200 R7 Clamping Network L5 330 H L4 2.2 H 6.5 V @ 600 mA Rclamp C3 + 4.7 F 400 V C2 4.7 F 400 V D3 1N5819 + Clamp 1 Dclamp HV 8 Adj 2 FB NC 7 3 CS VCC 6 4 GND Drv 5 Universal Input M1 MTD1N60E R9 10 C10 4.7 F/ 10 V R2 220 Optional Networks CSnubber R6 2.8 C9 10 F C5 470 F/ 10 V + Snubber RSnubber + L6 330 H T1 NCP1200 + IC1 SFH615A−2 D6 5 V1 Figure 24. A typical AC−DC wall adapter showing the reduced part count due to the NCP1200 T1: Lp = 2.9 mH, Np:Ns = 1:0.08, leakage = 80 H, E16 core, NCP1200P40 To help designers during the design stage, several manufacturers propose ready−to−use transformers for the above application, but can also develop devices based on your particular specification: Atelier Special de Bobinage 125 cours Jean Jaures 38130 ECHIROLLES FRANCE Tel.: 33 (0)4 76 23 02 24 Fax: 33 (0)4 76 22 64 89 Email: [email protected] ref. 1: NCP1200−10 W−UM: 10 W for USB (Lp = 1.8 mH, 60 kHz, 1:0.1, RM8 pot core) Coilcraft 1102 Silver Lake Road Cary, Illinois 60013 USA Tel: (847) 639−6400 Fax: (847) 639−1469 Email: [email protected] http://www.coilcraft.com ref. 1: Y8844−A: 3.5 W version (Lp = 2.9 mH, Lleak = 65 H, E16) ref. 2: Y8848−A: 10 W version (Lp = 1.8 mH, Lleak = 45 H, 1:01, E core) Eldor Corporation Headquarter Via Plinio 10, 22030 Orsenigo (Como) Italia Tel.: +39−031−636 111 Fax : +39−031−636 280 Email: [email protected] www.eldor.it ref. 1: 2262.0058C: 3.5 W version (Lp = 2.9 mH, Lleak = 80 H, E16) ref. 2: 2262.0059A: 5 W version (Lp = 1.6 mH, Lleak = 45 H, E16) EGSTON GesmbH Grafenbergerstrae 37 3730 Eggenburg Austria Tel.: +43 (2984) 2226−0 Fax : +43 (2984) 2226−61 Email: [email protected] http://www.egston.com/english/index.htm ref. 1: F0095001: 3.5 W version (Lp = 2.7 mH, Lleak = 30 H, sandwich configuration, E16) http://onsemi.com 12 NCP1200 Improving the Output Drive Capability The NCP1200 features an asymmetrical output stage used to soften the EMI signature. Figure 25 depicts the way the driver is internally made: 1 8 2 7 3 NCP1200 6 4 5 2N2222 Rd To Gate VCC Q 2 2N2907 7 40 Figure 26. Improving Both Turn−On and Turn−Off Times 1 12 Q\ 8 1 5 2 3 NCP1200 7 3 6 4 5 1N4148 To Gate 2N2907 Figure 25. The higher ON resistor slows down the MOSFET while the lower OFF resistor ensures fast turn−off. In some cases, it is possible to expand the output drive capability by adding either one or two bipolar transistors. Figures 26, 27, and 28 give solutions whether you need to improve the turn−on time only, the turn−off time or both. Rd is there to damp any overshoot resulting from long copper traces. It can be omitted with short connections. Results showed a rise fall time improvement by 5X with standard 2N2222/2N2907: Figure 27. Improving Turn−Off Time Only 8 1 2 NCP1200 7 3 6 4 5 2N2222 To Gate 1N4148 Figure 28. Improving Turn−On Time Only http://onsemi.com 13 NCP1200 Vripple: the clamping ripple, could be around 20 V Another option lies in implementing a snubber network which will damp the leakage oscillations but also provide more capacitance at the MOSFET’s turn−off. The peak voltage at which the leakage forces the drain is calculated by: If the leakage inductance is kept low, the MTD1N60E can withstand accidental avalanche energy, e.g. during a high−voltage spike superimposed over the mains, without the help of a clamping network. If this leakage path permanently forces a drain−source voltage above the MOSFET BVdss (600 V), a clamping network is mandatory and must be built around Rclamp and Clamp. Dclamp shall react extremely fast and can be a MUR160 type. To calculate the component values, the following formulas will help you: Rclamp = 2 V clamp (V clamp L leak V max Ip clamp L leak C lump where Clump represents the total parasitic capacitance seen at the MOSFET opening. Typical values for Rsnubber and Csnubber in this 4W application could respectively be 1.5 k and 47 pF. Further tweaking is nevertheless necessary to tune the dissipated power versus standby power. (V out Vf sec) N) Ip 2 Fsw V C clamp V ripple Fsw R Available Documents “Implementing the NCP1200 in Low−cost AC−DC Converters”, AND8023/D. “Conducted EMI Filter Design for the NCP1200’’, AND8032/D. “Ramp Compensation for the NCP1200’’, AND8029/D. TRANSient and AC models available to download at: http://onsemi.com/pub/NCP1200 NCP1200 design spreadsheet available to download at: http://onsemi.com/pub/NCP1200 clamp with: Vclamp: the desired clamping level, must be selected to be between 40 V to 80 V above the reflected output voltage when the supply is heavily loaded. Vout + Vf: the regulated output voltage level + the secondary diode voltage drop Lleak: the primary leakage inductance N: the Ns:Np conversion ratio FSW: the switching frequency ORDERING INFORMATION Marking Package Shipping† NCP1200P40 1200P40 PDIP−8 50 Units / Rail NCP1200P40G 1200P40 PDIP−8 (Pb−Free) 50 Units / Rail 200D4 SOIC−8 2500 Units /Reel 200D4 SOIC−8 (Pb−Free) 2500 Units /Reel NCP1200P60 1200P60 PDIP−8 50 Units / Rail NCP1200P60G 1200P60 PDIP−8 (Pb−Free) 50 Units / Rail 200D6 SOIC−8 2500 Units /Reel 200D6 SOIC−8 (Pb−Free) 2500 Units /Reel NCP1200P100 1200P100 PDIP−8 50 Units / Rail NCP1200P100G 1200P100 PDIP−8 (Pb−Free) 50 Units / Rail 200D1 SOIC−8 2500 Units / Reel 200D1 SOIC−8 (Pb−Free) 2500 Units / Reel Device NCP1200D40R2 Type FSW = 40 kHz NCP1200D40R2G NCP1200D60R2 FSW = 60 kHz NCP1200D60R2G NCP1200D100R2 NCP1200D100R2G FSW = 100 kHz †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 14 NCP1200 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 DIM A B C D G H J K M N S SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCP1200 PACKAGE DIMENSIONS PDIP−8 P SUFFIX CASE 626−05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 −B− 1 4 F −A− NOTE 2 L C J −T− MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10 0.030 0.040 N SEATING PLANE D H DIM A B C D F G H J K L M N M K G 0.13 (0.005) M T A M B M The product described herein (NCP1200), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 16 For additional information, please contact your local Sales Representative. NCP1200/D