NCP1207 PWM Current−Mode Controller for Free Running Quasi−Resonant Operation The NCP1207 combines a true current mode modulator and a demagnetization detector to ensure full borderline/critical Conduction Mode in any load/line conditions and minimum drain voltage switching (Quasi−Resonant operation). Due to its inherent skip cycle capability, the controller enters burst mode as soon as the power demand falls below a predetermined level. As this happens at low peak current, no audible noise can be heard. An internal 8.0 s timer prevents the free−run frequency to exceed 100 kHz (therefore below the 150 kHz CISPR−22 EMI starting limit), while the skip adjustment capability lets the user select the frequency at which the burst foldback takes place. The Dynamic Self−Supply (DSS) drastically simplifies the transformer design in avoiding the use of an auxiliary winding to supply the NCP1207. This feature is particularly useful in applications where the output voltage varies during operation (e.g. battery chargers). Due to its high−voltage technology, the IC is directly connected to the high−voltage DC rail. As a result, the short−circuit trip point is not dependent upon any VCC auxiliary level. The transformer core reset detection is done through an auxiliary winding which, brought via a dedicated pin, also enables fast Over−Voltage Protection (OVP). Once an OVP has been detected, the IC permanently latches−off. Finally, the continuous feedback signal monitoring implemented with an over−current fault protection circuitry (OCP) makes the final design rugged and reliable. http://onsemi.com MARKING DIAGRAMS 8 SO−8 D1, D2 SUFFIX CASE 751 8 1 1 8 PDIP−8 N SUFFIX CASE 626 1 1 1207/P A WL, L YY, Y WW, W Free−Running Borderline/Critical Mode Quasi−Resonant Operation Current−Mode with Adjustable Skip−Cycle Capability No Auxiliary Winding VCC Operation Auto−Recovery Over Current Protection Latching Over Voltage Protection External Latch Triggering, e.g. Via Over−Temperature Signal 500 mA Peak Current Source/Sink Capability Internal 1.0 ms Soft−Start Internal 8.0 s Minimum TOFF Adjustable Skip Level Internal Temperature Shutdown Direct Optocoupler Connection SPICE Models Available for TRANsient Analysis Pb−Free Package is Available AC/DC Adapters for Notebooks, etc. Offline Battery Chargers Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.) Auxiliary Power Supplies (USB, Appliances, TVs, etc.) Semiconductor Components Industries, LLC, 2004 February, 2004 − Rev. 5 = Device Code = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS Typical Applications • • • • 1207P AWL YYWW 8 Features • • • • • • • • • • • • • • 1207 ALYW 1 Dmg 1 8 HV FB 2 7 NC CS 3 6 VCC Gnd 4 5 Drv (Top View) ORDERING INFORMATION Device Package Shipping† NCP1207DR2 SOIC−8 2500/Tape & Reel SOIC−8 (Pb−Free) 2500/Tape & Reel PDIP−8 50 Units/Tube NCP1207DR2G NCP1207P †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCP1207/D NCP1207 Vout + + OVP and Demag NCP1207 1 8 2 7 3 6 4 5 * Gnd Universal Network + *Please refer to the application information section Figure 1. Typical Application ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Description 1 Demag Core reset detection and OVP The auxiliary FLYBACK signal ensures discontinuous operation and offers a fixed overvoltage detection level of 7.2 V. 2 FB Sets the peak current setpoint By connecting an Optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. By bringing this pin below the internal skip level, device shuts off. 3 CS Current sense input and skip cycle level selection This pin senses the primary current and routes it to the internal comparator via an L.E.B. By inserting a resistor in series with the pin, you control the level at which the skip operation takes place. 4 Gnd The IC ground 5 Drv Driving pulses 6 VCC Supplies the IC 7 NC − 8 HV High−voltage pin − The driver’s output to an external MOSFET. This pin is connected to an external bulk capacitor of typically 10 F. This unconnected pin ensures adequate creepage distance. Connected to the high−voltage rail, this pin injects a constant current into the VCC bulk capacitor. http://onsemi.com 2 NCP1207 4.5 s Delay − OVP 7.0 mA PON + Demag + /1.44 + 5.0 V 8.0 s Blanking S − + VCC Resd Demag HV − + Rint 10 V + 50 mV Q Driver: src = 20 sink = 10 VCC S* R* R Q 12 V, 10 V, 5.3 V (fault) To Internal Supply Drv 4.2 V Fault Mngt. Soft−Start = 1 ms + GND /3 FB − 1.0 V Overload? 5.0 s Timeout 200 A when Drv is OFF 380 ns L.E.B. Timeout Reset CS Demag *S and R are level triggered whereas S is edge triggered. R has priority over the other inputs. Figure 2. Internal Circuit Architecture ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ MAXIMUM RATINGS Rating Symbol Value Units VCC, Drv 16 V Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (VCC) Pin 5 (Drv) and Pin 1 (Demag) − −0.3 to 10 V Maximum Current into all pins except VCC (6), HV (8) and Demag (1) when 10 V ESD diodes are activated − 5.0 mA Maximum Current in Pin 1 Idem +3.0/−2.0 mA Thermal Resistance, Junction−to−Case RJC 57 °C/W Thermal Resistance, Junction−to−Air, SOIC version RJA 178 °C/W Thermal Resistance, Junction−to−Air, DIP8 version RJA 100 °C/W TJMAX 150 °C Temperature Shutdown − 155 °C Hysteresis in Shutdown − 30 °C Storage Temperature Range − −60 to +150 °C ESD Capability, HBM Model (All pins except HV) − 2.0 kV ESD Capability, Machine Model − 200 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F VHVMAX 500 V Minimum Voltage on Pin 8 (HV), Pin 6 (VCC) decoupled to ground with 10 F VHVMIN 40 V Power Supply Voltage Maximum Junction Temperature http://onsemi.com 3 NCP1207 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V unless otherwise noted) Rating Pin Symbol Min Typ Max Unit DYNAMIC SELF−SUPPLY Vcc Increasing Level at which the Current Source Turns−off 6 VCCOFF 10.8 12 12.9 V Vcc Decreasing Level at which the Current Source Turns−on 6 VCCON 9.1 10 10.6 V Vcc Decreasing Level at which the Latch−off Phase Ends 6 VCClatch − 5.3 − V Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz 6 ICC1 − 1.0 1.3 (Note 1) mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz 6 ICC2 − 1.6 2.0 (Note 1) mA Internal IC Consumption in Latch−off Phase 6 ICC3 − 330 − A High−voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA High−voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output Signal 5 Tr − 40 − ns Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output Signal 5 Tf − 20 − ns Source Resistance 5 ROH 12 20 36 Sink Resistance 5 ROL 5.0 10 19 INTERNAL START−UP CURRENT SOURCE (TJ 0°C) DRIVE OUTPUT CURRENT COMPARATOR (Pin 5 Unloaded) Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB − 0.02 − A Maximum Internal Current Setpoint 3 ILimit 0.92 1.0 1.12 V Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 100 160 ns Leading Edge Blanking Duration 3 TLEB − 380 − ns Internal Current Offset Injected on the CS Pin during OFF Time 3 Iskip − 200 − A Sampling Delay after ON Time 1 Tsample − 4.5 − s OVP Internal Reference Level 1 Vref 6.4 7.2 8.0 V OVERVOLTAGE SECTION (VCC = 11 V) FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k) Internal Pull−up Resistor 2 Rup − 20 − k Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − − Internal Soft−start − Tss − 1.0 − ms DEMAGNETIZATION DETECTION BLOCK Input Threshold Voltage (Vpin 1 Decreasing) 1 Vth 35 50 90 mV Hysteresis (Vpin 1 Decreasing) 1 VH − 20 − mV Input Clamp Voltage High State (Ipin 1 = 3.0 mA) Low State (Ipin 1 = −2.0 mA) 1 1 VCH VCL 8.0 −0.9 10 −0.7 12 −0.5 V V Demag Propagation Delay 1 Tdem − 210 − ns Internal Input Capacitance at Vpin 1 = 1.0 V 1 Cpar − 10 − pF Minimum TOFF (Internal Blanking Delay after TON) 1 Tblank − 8.0 − s Timeout After Last Demag Transition 1 Tout − 5.0 − s Pin 1 Internal Impedance 1 Rint − 28 − k 1. Max value at TJ = 0°C. http://onsemi.com 4 NCP1207 13.2 11.2 12.8 10.8 VCCON (V) VCCOFF (V) 12.4 12.0 11.6 10.4 10 9.6 11.2 9.2 10.8 0 25 50 75 100 8.8 −25 125 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 4. VCCON Threshold versus Temperature 1.6 2.3 1.4 2.1 1.2 1.9 1.0 1.5 0.6 1.3 0 25 50 75 100 1.1 −25 125 125 1.7 0.8 0.4 −25 0 Figure 3. VCCOFF Threshold versus Temperature ICC2 (mA) ICC1 (mA) 10.4 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. Current Consumption (No Load) versus Temperature Figure 6. Current Consumption (Loaded by 1 nF) versus Temperature 125 1.20 12 1.15 10 Ilimit (V) IC1 (mA) 1.10 8.0 6.0 1.05 1.00 4.0 2.0 −25 0.95 0 25 50 75 100 0.90 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. HV Current Source at VCC = 10 V versus Temperature Figure 8. Maximum Current Setpoint versus Temperature http://onsemi.com 5 125 NCP1207 40 20 35 18 16 30 ROL () ROH () 14 25 20 15 12 10 8.0 6.0 10 4.0 5 0 −25 0 25 50 75 100 2.0 0 −25 125 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Drive Source Resistance versus Temperature Figure 10. Drive Sink Resistance versus Temperature 120 125 8.0 100 7.5 Vref (V) VTH (mV) 80 60 7.0 40 6.5 20 0 −25 0 25 50 75 100 6.0 −25 125 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Demagnetization Detection Threshold versus Temperature Figure 12. OVP Threshold versus Temperature 10 7.0 9.5 6.6 6.2 Tout (s) 9.0 Toff (s) 0 8.5 8.0 5.8 5.4 5.0 7.5 4.6 7.0 4.2 6.5 −25 0 25 50 75 100 3.8 −25 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Minimum Toff versus Temperature Figure 14. Demagnetization Detection Timeout versus Temperature http://onsemi.com 6 NCP1207 1.5 60 1.4 50 1.3 Rint (k) Tss (s) 40 1.2 1.1 20 1.0 10 0.9 0.8 −25 30 0 25 50 75 100 0 −25 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Internal Soft−start versus Temperature Figure 16. DMG Pin Internal Resistance versus Temperature http://onsemi.com 7 NCP1207 Application Information Introduction The NCP1207 implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint whereas the core reset detection triggers the turn−on event. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC/DC adapters, consumer electronics, auxiliary supplies, etc. Thanks to its high−performance High−Voltage technology, the NCP1207 incorporates all the necessary components / features needed to build a rugged and reliable Switch−Mode Power Supply (SMPS): • • Transformer core reset detection: borderline / critical • • • VRIPPLE = 2 V VCCOFF = 12 V VCC • Dynamic Self−Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with some simple logical equations: POWER−ON: IF VCC < VCCOFF THEN Current Source is ON, no output pulses IF VCC decreasing > VCCON THEN Current Source is OFF, output is pulsing IF VCC increasing < VCCOFF THEN Current Source is ON, output is pulsing Typical values are: VCCOFF = 12 V, VCCON = 10 V To better understand the operational principle, Figure 17’s sketch offers the necessary light. VCCON = 10 V CURRENT SOURCE • operation is ensured whatever the operating conditions are. As a result, there are virtually no primary switch turn−on losses and no secondary diode recovery losses. The converter also stays a first−order system and accordingly eases the feedback loop design. Quasi−resonant operation: by delaying the turn−on event, it is possible to re−start the MOSFET in the minimum of the drain−source wave, ensuring reduced EMI / video noise perturbations. In nominal power conditions, the NCP1207 operates in Borderline Conduction Mode (BCM) also called Critical Conduction Mode. Dynamic Self−Supply (DSS): due to its Very High Voltage Integrated Circuit (VHVIC) technology, ON Semiconductor’s NCP1207 allows for a direct pin connection to the high−voltage DC rail. A dynamic current source charges up a capacitor and thus provides a fully independent VCC level to the NCP1207. As a result, there is no need for an auxiliary winding whose management is always a problem in variable output voltage designs (e.g. battery chargers). Overvoltage Protection (OVP): by sampling the plateau voltage on the demagnetization winding, the NCP1207 goes into latched fault condition whenever an over−voltage condition is detected. The controller stays fully latched in this position until the VCC is cycled down 4.0 V, e.g. when the user un−plugs the power supply from the mains outlet and re−plugs it. External latch trip point: by externally forcing a level on the OVP greater than the internal setpoint, it is possible to latch−off the IC, e.g. with a signal coming from a temperature sensor. Adjustable skip cycle level: by offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. This point guarantees a noise−free operation with cheap transformer. This option also offers the ability to fix the maximum switching frequency when entering light load conditions. Over Current Protection (OCP): by continuously monitoring the FB line activity, NCP1207 enters burst mode as soon as the power supply undergoes an overload. The device enters a safe low power operation which prevents from any lethal thermal runaway. As soon as the default disappears, the power supply resumes operation. Unlike other controllers, overload detection is performed independently of any auxiliary winding level. In presence of a bad coupling between both power and auxiliary windings, the short circuit detection can be severely affected. The DSS naturally shields you against these troubles. ON OFF Output Pulses Figure 17. The Charge/Discharge Cycle Over a 10 F VCC Capacitor http://onsemi.com 8 NCP1207 The DSS behavior actually depends on the internal IC consumption and the MOSFET’s gate charge Qg. If we select a MOSFET like the MTP2N60E, Qg equals 22 nC (max). With a maximum switching frequency selected at 75 kHz, the average power necessary to drive the MOSFET (excluding the driver efficiency and neglecting various voltage drops) is: Fsw ⋅ Qg ⋅ VCC with: Fsw = maximum switching frequency Qg = MOSFET’s gate charge VCC = VGS level applied to the gate To obtain the output current, simply divide this result by VCC: Idriver = FSW ⋅ Qg = 1.6 mA. The total standby power consumption at no−load will therefore heavily rely on the internal IC consumption plus the above driving current (altered by the driver’s efficiency). Suppose that the IC is supplied from a 350 VDC line. The current flowing through pin 8 is a direct image of the NCP1207 consumption (neglecting the switching losses of the HV current source). If ICC2 equals 2.3 mA @ TJ = 60°C, then the power dissipated (lost) by the IC is simply: 350 V x 2.3 mA = 805 mW. For design and reliability reasons, it would be interested to reduce this source of wasted power that increase the die temperature. This can be achieved by using different methods: 1. Use a MOSFET with lower gate charge Qg. 2. Connect pin 8 through a diode (1N4007 typically) to one of the mains input. The average value on pin 8 When using Figure 18 option, it is important to check the absence of any negative ringing that could occur on pin 8. The resistor in series should help to damp any parasitic LC network that would ring when suddenly applying the power to the IC. Also, since the power disappears during 10 ms (half−wave rectification), CVCC should be calculated to supply the IC during these holes in the supply 3. Permanently force the VCC level above VCCH with an auxiliary winding. It will automatically disconnect the internal start−up source and the IC will be fully self−supplied from this winding. Again, the total power drawn from the mains will significantly decrease. Make sure the auxiliary voltage never exceeds the 16 V limit. Skipping Cycle Mode The NCP1207 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 19) and follows the following formula: 1 Lp Ip 2 Fsw D burst with: 2 2. Our power contribution becomes mainsPEAK example drops to: 223 V x 2.3 mA = 512 mW. If a resistor is installed between the mains and the diode, you further force the dissipation to migrate from the package to the resistor. The resistor value should account for low−line startups. V HV Lp = primary inductance Fsw = switching frequency within the burst Ip = peak current at which skip cycle occurs Dburst = burst width / burst recurrence CURRENT SENSE SIGNAL (mV) 1N4007 5 MAINS 1 2 Cbulk 1 8 2 7 3 6 4 5 6 Figure 18. A simple diode naturally reduces the average voltage on pin 8 300 MAX PEAK CURRENT NORMAL CURRENT MODE OPERATION SKIP CYCLE CURRENT LIMIT 200 100 0 WIDTH RECURRENCE Figure 19. The skip cycle takes place at low peak currents which guaranties noise free operation http://onsemi.com 9 NCP1207 DRIVER current sense comparator permanently resets the latch and the next clock cycle (given by the demagnetization detection) is ignored: we are skipping cycles as shown by Figure 21. As soon as the feedback voltage goes up again, there can be two situations: the recurrent period is small and a new demagnetization detection (next wave) signal triggers the NCP1207. To the opposite, in low output power conditions, no more ringing waves are present on the drain and the toggling of the current sense comparator together with the internal 5 s timeout initiates a new cycle start. In normal operating conditions, e.g. when the drain oscillations are generous, the demagnetization comparator can detect the 50 mV crossing and gives the “green light”, alone, to re−active the power switch. However, when skip cycle takes place (e.g. at low output power demands), the re−start event slides along the drain ringing waveforms (actually the valley locations) which decays more or less quickly, depending on the Lprimary−Cparasitic network damping factor. The situation can thus quickly occur where the ringing becomes too weak to be detected by the demagnetization comparator: it then permanently stays locked in a given position and can no longer deliver the “green light” to the controller. To help in this situation, the NCP1207 implements a 5 s timeout generator: each time the 50 mV crossing occurs, the timeout is reset. So, as long as the ringing becomes too low, the timeout generator starts to count and after 5 s, it delivers its “green light”. If the skip signal is already present then the controller re−starts; otherwise the logic waits for it to set the drive output high. Figure 21 depicts these two different situations: DRIVER = HIGH ? I = 0 DRIVER = LOW ? I = 200 A RESET Rskip − + 3 Rsense 2 + Figure 20. A patented method allows for skip level selection via a series resistor inserted in series with the current The skip level selection is done through a simple resistor inserted between the current sense input and the sense element. Every time the NCP1207 output driver goes low, a 200 A source forces a current to flow through the sense pin (Figure 20): when the driver is high, the current source is off and the current sense information is normally processed. As soon as the driver goes low, the current source delivers 200 A and develops a ground referenced voltage across Rskip. If this voltage is below the feedback voltage, the current sense comparator stays in the high state and the internal latch can be triggered by the next clock cycle. Now, if because of a low load mode the feedback voltage is below Rskip level, then the Drain Signal Timeout Signal Demag Re−start Current Sense and Timeout Re−start Drain Signal Timeout Signal 5 s 5 s Figure 21. When the primary natural ringing becomes too low, the internal timeout together with the sense comparator initiates a new cycle when FB passes the skip level. http://onsemi.com 10 NCP1207 Demagnetization Detection The core reset detection is done by monitoring the voltage activity on the auxiliary winding. This voltage features a FLYBACK polarity. The typical detection level is fixed at 50 mV as exemplified by Figure 22. DRAIN VOLTAGE (V) 400 DEMAG SIGNAL (V) 7.0 5.0 POSSIBLE RE−STARTS 300 200 100 0 3.0 Figure 24. The NCP1207 Operates in Borderline / Critical Operation 1.0 50 mV 0V Overvoltage Protection The overvoltage protection works by sampling the plateau voltage 4.5 s after the turn−off sequence. This delay guarantees a clean plateau, providing that the leakage inductance ringing has been fully damped. If this would not be the case, the designer should install a small RC damper across the transformer primary inductance connections. Figure 25 shows where the sampling occurs on the auxiliary winding. −1.0 Figure 22. Core reset detection is done through a dedicated auxiliary winding monitoring TO INTERNAL COMPARATOR Rint Rdem Resd 2 ESD2 1 1 5 ESD1 4 Aux SAMPLING HERE 4 8.0 3 DEMAG SIGNAL (V) Resd + Rint = 28 k Figure 23. Internal Pad Implementation An internal timer prevents any re−start within 8.0 s further to the driver going−low transition. This prevents the switching frequency to exceed (1 / (TON + 8.0 s)) but also avoid false leakage inductance tripping at turn−off. In some cases, the leakage inductance kick is so energetic, that a slight filtering is necessary. The 1207 demagnetization detection pad features a specific component arrangement as detailed by Figure 23. In this picture, the zener diodes network protect the IC against any potential ESD discharge that could appear on the pins. The first ESD diode connected to the pad, exhibits a parasitic capacitance. When this parasitic capacitance (10 pF typically) is combined with Rdem, a re−start delay is created and the possibility to switch right in the drain−source wave exists. This guarantees QR operation with all the associated benefits (low EMI, no turn−on losses etc.). Rdem should be calculated to limit the maximum current flowing through pin 1 to less than +3 mA/−2 mA. If during turn−on, the auxiliary winding delivers 30 V (at the highest line level), then the minimum Rdem value is defined by: (30 V + 0.7 V) / 2 mA = 14.6 k. This value will be further increased to introduce a re−start delay and also a slight filtering in case of high leakage energy. Figure 24 portrays a typical VDS shot at nominal output power. 6.0 4.0 2.0 4.5 s 0 Figure 25. A voltage sample is taken 4.5 s after the turn−off sequence When an OVP condition has been detected, the NCP1207 enters a latch−off phase and stops all switching operations. The controller stays fully latched in this position and the DSS is still active, keeping the VCC between 5.3 V/12 V as in normal operations. This state lasts until the VCC is cycled down 4 V, e.g. when the user unplugs the power supply from the mains outlet. By default, the OVP comparator is biased to a 5 V reference level and pin1 is routed via a divide by 1.44 network. As a result, when Vpin1 reaches 7.2 V, the OVP comparator is triggered. The threshold can thus be adjusted by either modifying the power winding to auxiliary winding turn ratios to match this 7.2 V level, or insert a resistor from pin1 to ground to cope with your design requirement. http://onsemi.com 11 NCP1207 Latching Off the NCP1207 In certain cases, it can be very convenient to externally shut down permanently the NCP1207 via a dedicated signal, e.g. coming from a temperature sensor. The reset occurs when the user unplugs the power supply from the mains outlet. To trigger the latch−off, a CTN (Figure 26) or a simple NPN transistor (Figure 27) can do the work. Power Dissipation The NCP1207 is directly supplied from the DC rail through the internal DSS circuitry. The DSS being an auto−adaptive circuit (e.g. the ON/OFF duty−cycle adjusts itself depending on the current demand), the current flowing through the DSS is therefore the direct image of the NCP1207 current consumption. The total power dissipation can be evaluated using: (VHVDC 11 V) ICC2. If we operate the device on a 250 Vac rail, the maximum rectified voltage can go up to 350 Vdc. As a result, the worse case dissipation occurs at the maximum switching frequency and the highest line. The dissipation is actually given by the internal consumption of the NCP1207 when driving the selected MOSFET. The best method to evaluate this total consumption is probably to run the final circuit from a 50 Vdc source applied to pin 8 and measure the average current flowing into this pin. Suppose that we find 2.0 mA, meaning that the DSS duty−cycle will be 2.0/7.0 = 28.6%. From the 350 Vdc rail, the part will dissipate: 350 V 2.0 mA 700 mW (however this 2.0 mA number will drop at higher operating junction temperatures). A DIP8 package offers a junction−to−ambient thermal resistance RJA of 100°C/W. The maximum power dissipation can thus be computed knowing the maximum operating ambient temperature (e.g. 70°C) together with the maximum allowable junction temperature (125°C): CTN NCP1207 Aux 1 8 2 7 3 6 4 5 Figure 26. A simple CTN triggers the latch−off as soon as the temperature exceeds a given setpoint NCP1207 ON/OFF Aux 1 8 2 7 P max 3 6 4 5 do not reach the worse consumption budget imposed by the operating conditions. Several solutions exist to cure this trouble: • The first one consists in adding some copper area around the NCP1207 DIP8 footprint. By adding a min pad area of 80 mm2 of 35 m copper (1 oz.), RJA drops to about 75°C/W. Maximum power then grows up to 730 mW. • A resistor Rdrop needs to be inserted with pin 8 to a) avoid negative spikes at turn−off (see below) b) split the power budget between this resistor and the package. The resistor is calculated by leaving at least 50 V on pin 8 at minimum input voltage (suppose 100 Vdc in Figure 27. A simple transistor arrangement allows to trigger the latch−off by an external signal Shutting Off the NCP1207 Shutdown can easily be implemented through a simple NPN bipolar transistor as depicted by Figure 28. When OFF, Q1 is transparent to the operation. When forward biased, the transistor pulls the FB pin to ground (VCE(sat) ≈ 200 mV) and permanently disables the IC. A small time constant on the transistor base will avoid false triggering (Figure 28). V 50 V our case): Rdrop bulkmin 7.1 k. The 7.0 mA power dissipated by the resistor is thus: NCP1207 10 k ON/OFF Q1 3 2 1 Tjmax TAmax 550 mW. As we can see, we RJA Pdrop VdropRMS 2Rdrop 1 8 2 7 3 6 4 5 10 nF IDSS Rdrop DSSduty cycle Rdrop 2 7.0 mA 7.1 k 0.286 7.1 k 2 99.5 mW Please refer to the application note AND8069 available from www.onsemi.com/pub/ncp1200. Figure 28. A simple bipolar transistor totally disables the IC http://onsemi.com 12 NCP1207 • If the power consumption budget is really too high for the hosts a dedicated overload detection circuitry. Once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty−cycle. The system recovers when the fault condition disappears. During the start−up phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. This period of time depends on normal output load conditions and the maximum peak current allowed by the system. The time−out used by this IC works with the VCC decoupling capacitor: as soon as the VCC decreases from the VCCOFF level (typically 12 V) the device internally watches for an overload current situation. If this condition is still present when the VCCON level is reached, the controller stops the driving pulses, prevents the self−supply current source to restart and puts all the circuitry in standby, consuming as little as 330 A typical (ICC3 parameter). As a result, the VCC level slowly discharges toward 0. When this level crosses 5.3 V typical, the controller enters a new startup phase by turning the current source on: VCC rises toward 12 V and again delivers output pulses at the VCCOFF crossing point. If the fault condition has been removed before VCCON approaches, then the IC continues its normal operation. Otherwise, a new fault cycle takes place. Figure 29 shows the evolution of the signals in presence of a fault. DSS alone, connect a diode between the auxiliary winding and the VCC pin which will disable the DSS operation (VCC 10 V). The SOIC package offers a 178°C/W thermal resistor. Again, adding some copper area around the PCB footprint will help decrease this number: 12 mm 12 mm to drop RJA down to 100°C/W with 35 m copper thickness (1 oz.) or 6.5 mm 6.5 mm with 70 m copper thickness (2 oz.). As one can see, we do not recommend using the SO−8 package and the DSS if the part operates at high switching frequencies. In that case, an auxiliary winding is the best solution. Overload Operation In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is interesting to implement a true short−circuit protection. A short−circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the Optocoupler LED. As a result, the FB pin level is pulled up to 4.2 V, as internally imposed by the IC. The peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated effects. Please note that this can also happen in case of feedback loss, e.g. a broken Optocoupler. To account for this situation, NCP1207 VCC REGULATION OCCURS HERE 12 V 10 V LATCH−OFF PHASE 5.3 V TIME DRV DRIVER PULSES TIME If the fault is relaxed during the Vcc natural fall down sequence, the IC automatically resumes. If the fault still persists when Vcc reached VCCON, then the controller cuts everything off until recovery. INTERNAL FAULT FLAG FAULT IS RELAXED STARTUP PHASE TIME FAULT OCCURS HERE Figure 29. Soft−Start The NCP1207 features an internal 1 ms soft−start to soften the constraints occurring in the power supply during start−up. It is activated during the power on sequence. As soon as VCC reaches VCCOFF , the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 V). The soft−start is also activated during the over current burst (OCP) sequence. Every restart attempt is followed by a soft−start activation. Generally speaking, the soft−start will be activated when VCC ramps up either from zero (fresh power−on sequence) or 5.3 V, the latch−off voltage occurring during OCP. http://onsemi.com 13 NCP1207 HV Calculating the Vcc Capacitor As the above section describes, the fall down sequence depends upon the VCC level: how long does it take for the VCC line to go from 12 V to 10 V? The required time depends on the start−up sequence of your system, i.e. when you first apply the power to the IC. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12 V to 10 V, otherwise the supply will not properly start. The test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. Let’s suppose that this time corresponds to 6.0 ms. Therefore a VCC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including the MOSFET drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET), we can calculate the required capacitor using the following NCP1207 + Cbulk 1 8 2 7 3 6 4 5 D1 1N4007 + Figure 30. Operation Shots Below are some oscilloscope shots captured at Vin = 120 VDC with a transformer featuring a 800 H primary inductance. formula: t V C, with V = 2.0 V. Then for a wanted i t of 10 ms, C equals 9.0F or 22F for a standard value. When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 330 A typical. This happens at VCC = 10 V and it remains stuck until VCC reaches 5.3 V: we are in latch−off phase. Again, using the calculated 22 F and 330 A current consumption, this latch−off phase lasts: 313 ms. HV Pin Recommended Protection When the user unplugs a power supply built with a QR controller such as the NCP1207, two phenomena can appear: 1. A negative ringing can take place on pin8 due to a resonance between the primary inductance and the bulk capacitor. As any CMOS device, the NCP1207 is sensitive to negative voltages that could appear on it’s pins and could create an internal latch−up condition. 2. When the bulk capacitor discharges, the internal latch is reset by the voltage developed over the sense resistor and the ON time expands as less voltage is available. When the high−voltage rail becomes too low, the gate drives permanently stays high since no reset occurs. This situation is not desirable in many applications. For the above reasons, we strongly recommend to add a high−voltage diode like a 1N4007 between the bulk capacitor and the VCC pin. When the bulk level collapses, it naturally shuts the controller down and eradicates the two above problems. Figure 31. This plot gathers waveforms captured at three different operating points: 1st upper plot: free run, valley switching operation, Pout = 26 W 2nd middle plot: min Toff clamps the switching frequency and selects the second valley 3rd lowest plot: the skip slices the second valley pattern and will further expand the burst as Pout goes low http://onsemi.com 14 NCP1207 VGATE (5 V/div) VCC (5 V/div) VRsense (200 mV/div) 200 A X RSKIP VGATE (5 V/div) Current Sense Pin (200 mV/div) Figure 32. Figure 33. This picture explains how the 200 A internal offset current creates the skip cycle level. The short−circuit protection forces the IC to enter burst in presence of a secondary overload. http://onsemi.com 15 NCP1207 PACKAGE DIMENSIONS 8 PDIP−8 N SUFFIX CASE 626−05 ISSUE L 5 −B− 1 4 F −A− NOTE 2 L C J −T− N SEATING PLANE D H M K G 0.13 (0.005) M T A M B M http://onsemi.com 16 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10 0.030 0.040 NCP1207 PACKAGE DIMENSIONS (SO−8) D1, D2 SUFFIX CASE 751−07 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07 −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches SO−8 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCP1207 The product described herein (NCP1207), may be covered by one or more of the following U.S. patents: 6,385,060; 6,385,061. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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