ETC PLL103-02XI

PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
FEATURES
•
•
•
Generates 24 output buffer from one input.
Supports up to four DDR DIMMS or 2 SDRAM
DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V or 3.3V Supply range.
Enhanced DDR and SDRAM Output Drive
selected by I2C.
Available in 48 pin SSOP.
BLOCK DIAGRAM
DDR0T
SDATA
SCLK
I2C
Control
FBOUT
1
48
SEL_DDR
VDD3.3_2.5
GND
2
3
47
46
VDD2.5
GND
DDR0T
DDR0C
4
5
45
44
DDR11T
DDR11C
DDR1T_SDRAM0
DDR1C_SDRAM1
6
43
42
DDR10T
DDR10C
41
40
VDD2.5
GND
39
38
DDR9T
DDR9C
37
36
VDD2.5
PD#
35
34
GND
DDR8T
33
32
DDR8C
VDD2.5
VDD3.3_2.5
GND
7
8
9
PLL103-02
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•
•
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PIN CONFIGURATION
DDR2T_SDRAM2
DDR2C_SDRAM3
10
11
VDD3.3_2.5
BUF_IN
12
13
GND
DDR3T_SDRAM4
14
15
DDR3C_SDRAM5
VDD3.3_2.5
16
17
GND
DDR4T_SDRAM6
18
19
31
30
GND
DDR7T
DDR4C_SDRAM7
DDR5T
20
21
29
28
DDR7C
DDR6T
DDR5C
VDD3.3_2.5
22
23
27
26
DDR6C
GND
SDATA
24
25
SCLK
DDR0C
DDR1T_SDRAM0
Note: #: Active Low
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
BUF_IN
DDR4C_SDRAM7
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DESCRIPTIONS
The PLL103-02 is designed as a 3.3V/2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS
or to support 2 unbuffered standard SDRAM DIMMS
and 2 DDR DIMMS. The PLL103-02 can be used in
conjunction with the PLL202-04 or similar clock
synthesizer for the VIA Pro 266 chipset.
The PLL103-02 also has an I2C interface, which can
enable or disable each output clock. When power up,
all output clocks are enabled (has internal pull up).
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
PD#
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 1
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
PIN DESCRIPTIONS
Name
Number
Type
Description
FBOUT
1
O
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.
BUF_IN
13
I
Reference input from chipset. 3.3V input for STANDARD SDRAM mode;
2.5V input for DDR-ONLY mode.
PD
36
I
Power Down Control input. When low, it will tri-state all outputs.
SEL_DDR
48
I
Input configure for DDR-ONLY mode or STANDARD SDRAM mode.
1 = DDR-ONLY mode (when VDD3.3_2.5 select 2.5V); 0 =
STANDARD SDRAM mode (when VDD3.3_2.5 select 3.3V). In
DDR-ONLY mode, pin 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21, 22, 27,
28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as
DDR outputs. In STANDARD SDRAM mode, pin 6, 7, 11, 15, 16, 19
and 20 will be configured as STANDARD SDRAM outputs. Pin 27,
28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as
DDR outputs. Pin 4, 5, 21 and 22 will be Tri-stated.
DDR[0,5:11]T
4,21,28,30,34,
39,43,45
O
These outputs provide True copies of BUF_IN.
DDR[0,5:11]C
5,22,27,29,33,
38,42,44
O
These outputs provide complementary copies of BUF_IN.
DDR[1:4]T_SDRA
M [0,2,4,6]
6,10,15,19
O
When SEL_DDR=1, these outputs provide DDR mode outputs; when
SEL_DDR=0, these outputs provide standard SDRAM mode outputs.
Voltage swing depends on VDD3.3_2.5.
DDR[1:4]C_SDRA
M [1,3,5,7]
7,11,16,20
O
When SEL_DDR=1, these outputs provide complementary copies of
BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM
mode outputs. Voltage swing depends on VDD3.3_2.5.
VDD3.3_2.5
2,8,12,17,23
P
When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode is selected; when
VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode is selected.
VDD2.5
32,37,41,47
P
2.5V power supply.
GND
3,9,14,18,26,
31,35,40,46
P
Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 2
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
Address Assignment
Receiver/Transmitter
Data Transfer Rate
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
1
0
0
1
_
Provides both slave write and
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
48
1
SEL_DDR ( I2C is ready only, value is set through pin48 )
Bit 6
-
0
Enhanced SDRAM Drive. 1 = Enhanced 25%
Bit 5
-
0
Enhanced DDR Drive. 1 = Enhanced 25%
Bit 4
-
0
Reserved
Bit 3
45, 44
1
DDR11T, DDR11C
Bit 2
43, 42
1
DDR10T, DDR10C
Bit 1
39, 38
1
DDR9T, DDR9C
Bit 0
34, 33
1
DDR8T, DDR8C
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 3
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
2. BYTE 7: Outputs Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
30, 29
1
DDR7T, DDR7C
Bit 6
28, 27
1
DDR6T, DDR6C
Bit 5
21, 22
1
DDR5T, DDR5C
Bit 4
19, 20
1
DDR4T_SDRAM6, DDR4C_SDRAM7
Bit 3
15, 16
1
DDR3T_SDRAM4, DDR3C_SDRAM5
Bit 2
10, 11
1
DDR2T_SDRAM2, DDR2C_SDRAM3
Bit 1
6, 7
1
DDR1T_SDRAM0, DDR1C_SDRAM1
Bit 0
4, 5
1
DDR0T, DDR0C
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 4
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
V SS - 0.5
7.0
V
Input Voltage, dc
VI
V SS - 0.5
V DD + 0.5
V
Output Voltage, dc
VO
V SS - 0.5
V DD + 0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature
TA
0
70
°C
2
KV
Supply Voltage
ESD Voltage
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V DD3.3
3.135
3.465
V
Supply Voltage
V DD2.5
2.375
2.625
V
C IN
5
pF
C OUT
6
pF
Input Capacitance
Output Capacitance
3. Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
Input High Voltage
V IH
All Inputs except I2C
Input Low Voltage
V IL
All inputs except I2C
Input High Current
I IH
Input Low Current
I IL
MAX.
UNITS
2.0
V DD +0.3
V
V SS -0.3
0.8
V
V IN = V DD
TBM
uA
V IN = 0
TBM
uA
Output High
Voltage
V OH
IOL = -12mA,
Output Low
Voltage
V OL
IOL = 12mA,
Output High
Current
I OH
VDD = 2.375V, VOUT=1V
Output Low
Current
I OL
VDD = 2.375V, VOUT=1.2V
MIN.
VDD = 2.375V
TYP.
1.7
V
VDD = 2.375V
0.6
-18
26
V
-32
mA
35
mA
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 5
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
3. Electrical Specifications (Continued)
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current
(DDR-only mode)
I DD
Unloaded outputs, 133MHz
TBM
mA
Supply Current
(SDRAM mode)
I DD
Unloaded outputs, 133MHz
TBM
mA
Supply Current
I DDS
PD = 0
TBM
mA
Output Crossing
Voltage
V OC
(VDD/2)
-0.1
(VDD/2)+
0.1
V
Output Voltage
Swing
V OUT
1.1
VDD-0.4
V
55
%
170
MHz
Duty Cycle
DT
Measured @ 1.5V
45
Max. Operating
Frequency
VDD/2
50
66
Rising Edge Rate
T OR
Measured @
0.4V ~ 2.4V
1.0
1.5
2.0
V/ns
Falling Edge Rate
T OF
Measured @
2.4V ~ 0.4V
1.0
1.5
2.0
V/ns
Clock Skew ( pin to
pin )
T SKEW
100
ps
Stabilization Time
T ST
0.1
ms
All outputs equally loaded
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 6
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
PACKAGE INFORMATION
0.400 - 0.410
0.292 - 0.299
10.160 - 10.414
7.417 - 7.959
0.008 - 0.0135
0.025
0.203 - 0.343
0.835
0.015
(0.381)
0.010 - 0.016
(0.25 - 0.41)
0.620 - 0.630
(15.75 - 16.00)
0.088 - 0.096
(2.250 - 2.450)
45 0
0.097 - 0.104
(2.467 - 2.642)
30-6 0
0.050
MIN
(1.346)
0.008 - 0.016
(0.20 - 0.41)
48PIN SSOP
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL103-02 X C
PART NUMBER
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
X=SSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 7