PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • • • • • • • • • PIN CONFIGURATION Generates 24 output buffers from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps. 2.5V Supply range. Enhanced DDR Output Drive selected by I2C. Available in 48 pin SSOP. DDR0T SDATA SCLK I2C Control DDR0C 48 N/C 2 3 47 46 VDD2.5 GND DDR0T 4 45 DDR11T DDR0C DDR1T DDR1C VDD2.5 5 6 7 8 44 43 42 41 DDR11C DDR10T DDR10C VDD2.5 GND DDR2T DDR2C 9 10 11 40 39 38 GND DDR9T DDR9C VDD2.5 BUF_IN 12 13 37 36 VDD2.5 PD# GND DDR3T 14 35 GND 34 33 DDR8T DDR8C 32 31 30 VDD2.5 GND DDR7T DDR1T DDR3C 15 16 DDR1C VDD2.5 GND DDR4T 17 18 19 DDR4C DDR4C DDR5T DDR5C VDD2.5 20 21 22 23 29 28 27 26 DDR7C DDR6T DDR6C GND DDR5T SDATA 24 25 SCLK DDR2T DDR2C DDR3T DDR3C DDR4T BUF_IN 1 PLL103-02 BLOCK DIAGRAM FBOUT VDD2.5 GND DDR5C DDR6T Note: #: Active Low DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T DDR10C DDR11T DDR11C PD# DESCRIPTION The PLL103-02 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 can be used in conjunction with a clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When powered up, all output clocks are enabled (have internal pull ups). 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1 PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS PIN DESCRIPTIONS Name Number Type FBOUT BUF_IN PD N/C 1 13 36 48 4,6,10,15,19, 21,28,30,34, 39,43,45 5,7,11,16,20, 22,27,29,33, 38,42,44 2,8,12,17,23, 32,37,41,47 3,9,14,18,26, 31,35,40,46 O I I Feedback clock for chipset. Reference input from chipset. Power Down Control input. When low, it will tri-state all outputs. Not connected. O These outputs provide True copies of BUF_IN. O These outputs provide complementary copies of BUF_IN. P 2.5V power supply. P Ground. DDR[0:11]T DDR[0:11]C VDD2.5 GND Description 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2 PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS I2C BUS CONFIGURATION SETTING A6 1 Address Assignment Slave Receiver/Transmitter Data Transfer Rate A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _ Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). Data Protocol I2C CONTROL REGISTERS 1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Bit Bit Bit Bit Bit Bit Bit Bit 48 45, 44 43, 42 39, 38 34, 33 1 0 0 0 1 1 1 1 7 6 5 4 3 2 1 0 Description Reserved Reserved Enhanced DDR Drive. 1 = Enhanced 25% Reserved DDR11T, DDR11C DDR10T, DDR10C DDR9T, DDR9C DDR8T, DDR8C 2. BYTE 7: Outputs Register (1=Enable, 0=Disable) Bit Pin# Bit Bit Bit Bit Bit Bit Bit Bit 30, 28, 21, 19, 15, 10, 6, 4, 7 6 5 4 3 2 1 0 29 27 22 20 16 11 7 5 Default 1 1 1 1 1 1 1 1 Description DDR7T, DDR6T, DDR5T, DDR4T, DDR3T, DDR2T, DDR1T, DDR0T, DDR7C DDR6C DDR5C DDR4C DDR3C DDR2C DDR1C DDR0C 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3 PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model V DD VI VO TS TA TJ MIN. V SS -0.5 V SS -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Operating Conditions PARAMETERS Supply Voltage Input Capacitance Output Capacitance SYMBOL MIN. MAX. UNITS V DD2.5 C IN C OUT 2.375 2.625 5 6 V pF pF 3. Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Output High Current Output Low Current V IH V IL I IH I IL All Inputs except I2C All inputs except I2C V IN = V DD V IN = 0 V OH IOL = -12mA, VDD = 2.375V V OL IOL = 12mA, VDD = 2.375V I OH VDD = 2.375V, VOUT=1V -18 -32 mA I OL VDD = 2.375V, VOUT=1.2V 26 35 mA 2.0 V SS -0.3 MAX. UNITS V DD +0.3 0.8 TBM TBM V V uA uA 1.7 V 0.6 V Note: TBM: To be measured 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 4 PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS 3. Electrical Specifications (Continued) PARAMETERS Supply Current Output Crossing Voltage Output Voltage Swing Duty Cycle Max. Operating Frequency Rising Edge Rate Falling Edge Rate Clock Skew ( pin to pin ) Stabilization Time SYMBOL I DDS CONDITIONS MIN. PD = 0 V OC (VDD/2) -0.1 V OUT 1.1 DT TYP. Measured @ 1.5V 45 VDD/2 50 66 T OR T OF T SKEW T ST Measured @ Measured @ 0.4V ~ 2.4V 2.4V ~ 0.4V All outputs equally loaded 1.0 1.0 1.5 1.5 MAX. UNITS TBM (VDD/2)+ 0.1 mA VDD-0.4 V 55 % 170 MHz 2.0 2.0 V/ns V/ns 100 ps 0.1 ms V Note: TBM: To be measured 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5 PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS PACKAGE INFORMATION 0.400 - 0.410 0.292 - 0.299 10.160 - 10.414 7.417 - 7.959 0.008 - 0.0135 0.025 0.203 - 0.343 0.835 0.015 (0.381) 0.620 - 0.630 (15.75 - 16.00) 0.010 - 0.016 (0.25 - 0.41) 0.088 - 0.096 (2.250 - 2.450) 45 0 0.097 - 0.104 (2.467 - 2.642) 30-60 0.050 MIN (1.346) 0.008 - 0.016 (0.20 - 0.41) 48PIN SSOP ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL103-02 X C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE X=SSOP Order Number Marking Package Option PLL103-02XC-R PLL103-02XC P103-02XC P103-02XC SSOP - Tape and Reel SSOP - Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 6