PLL205-01 Motherboard Clock Generator for AMD - K7 FEATURES • • • • • • • Generates all clock frequencies for VIA K7 chip sets requiring multiple CPU clocks and high speed SDRAM buffers. Support one pair of differential CPU clocks, one open-drain CPU, 6 PCI and 13 high-speed SDRAM buffers for 3-DIMM applications. One 24_48MHz clock and one 48MHz clock. Two14.318MHz reference clocks. Power management control to stop CPU, and Power down Mode from I2C programming. Support 2-wire I2C serial bus interface with builtin Vendor ID, Device ID and Revision ID. Single byte micro-step linear Frequency Programming via I2C with Glitch free smooth switching. Spread Spectrum ±0.25% center spread, 0 to −0.5% downspread. 50% duty cycle with low jitter. Available in 300 mil 48 pin SSOP. VDD0 REF0//CPU_STOP#^ GND XIN XOUT VDD1 PCI5/MODE*^ PCI0/FS3*^ GND PCI1/SEL24_48*^ PCI2 PCI3 PCI4 VDD2 SDRAMIN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK 1 2 48 47 3 4 46 45 5 44 6 7 43 42 8 9 41 40 10 11 12 13 14 15 16 PLL205-01 • • • PIN CONFIGURATION REF1/FS2*^ GND CPUT1 GND CPUC0 CPUT0 VDD3 PD#^ SDRAM12 GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0*^ 24_48MHz/FS1*^ 39 38 37 36 35 34 33 17 18 32 31 19 20 30 29 21 22 28 27 23 24 26 25 Note: ^: Pull up, #: Active Low * : Bi-directional latched at power-up BLOCK DIAGRAM I/O MODE CONFIGURATION VDD1 XIN XOUT XTAL OSC REF(0:1) CPUT(0:1) SDATA SCLK I2C Logic 0 (INPUT) CPU_STOP POWER GROUP VDD1: REF(0:1), XIN, XOUT • VDD2: PCI(0:5) PCI(0:4) • VDD3: SDRAM(0:12) PCI5 • VDD4: 48MHz, 24_48MHz VDD4 48Mhz KEY SPECIFICATIONS 24_48Mhz • CPU Cycle to Cycle jitter: 250ps. VDD3 • PCI to PCI output skew: 500ps. SDRAM(0:11) • CPU to CPU output skew: ±175ps SDRAM12 • SDRAM to SDRAM output skew: 250ps. • CPU to PCI skew (CPU leads): 0 ~ 3 ns. PLL2 ÷2 REF0 • VDD2 PD 1 (OUTPUT) VDD0: PLL CORE Logic PLL1 SST PIN 2 • CPUC0 Control FS (0:3)* MODE (Pin 7) SDRAMIN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 1 PLL205-01 Motherboard Clock Generator for AMD - K7 PIN DESCRIPTIONS Name Number Type Description VDD0 1 P Power supply for PLL CORE. VDD1 6 P Power supply for REF0, REF1, and crystal oscillator. VDD2 14 P Power supply for PCI (0:5). VDD3 19,30,36,42 P Power supply for SDRAM (0:12). VDD4 27 P Power supply for 24_48MHz and 48MHz. GND 3,9,16,22, 33,39,45,47 P Ground. XIN 4 I 14.318MHz crystal input that has internal loads cap (36pF) and feedback resistor from XOUT. XOUT 5 O 14.318MHz crystal output. It has internal load cap (36pF). REF0//CPU_STOP 2 B Multiplexed pin controlled by MODE signal. When CPU_STOP is low, it will halt CPUT (0:1), CPUC0 and SDRAM (0:11) outputs. In output mode, this pin will generate buffered reference clock output. PCI5/MODE 7 B At power-up, MODE function will be activated. When MODE is Low, Pin 2 is input for CPU_STOP. When high, Pin 2 is output for REF0. After input data latched, this pin will generate PCI bus clock. PCI0/FS3 8 B At power-up, this pin is input pin and will determine CPU clock frequency. After input sampling, this pin will generate output clocks. FS3 has internal pull up (high by default). PCI1/SEL24_48 10 B At power-up, this pin will select 24MHz (when high) or 48MHz (when low) for pin25 output. After input sampling, this pin is PCI output. It has internal pull up resistor. PCI(2:4) 11,12,13 O PCI clock outputs. SDRAMIN 15 I Buffer input pin: The signal provided to this input pin is buffered to 13 SDRAM outputs. SDRAM(0:11) 17,18,20,21,28, 29,31,32,34,35, 37,38 O SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin. SDATA 23 B SCLK 24 I 24_48MHz/FS1, 24MHz/FS0 25,26 B At power-up, these pins are input pins and will determine the CPU clock frequency. FS0, FS1 have internal pull up (high by default). SDRAM12 40 O When CPU_STOP is low, this pin is still free running. When the power down is low, this SDRAM will be stopped. PD# 41 I When low, it will stop all clock outputs. It has internal pull-up resistor. CPUT(0:1) 43,46 O “True” clocks of differential pair open-drain CPU outputs. CPUC0 44 O “Complementary” clocks of differential pair open-drain CPU outputs. REF1/FS2 48 B Buffered reference clock output after input data latched during power-up. Serial data inputs for serial interface port. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 2 PLL205-01 Motherboard Clock Generator for AMD - K7 FREQUENCY (MHz) SELECTION TABLE I2C Byte0 Bit2 FS3 FS2 FS1 FS0 CPU PCI 0 default 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 124.0 75.0 83.3 66.8 103.0 112.0 133.3 100.0 41.3 37.5 41.7 33.4 34.3 37.3 44.4 33.3 120.0 115.0 110.0 105.0 140.0 150.0 124.0 133.3 40.0 38.3 36.7 35.0 35.0 37.5 31.0 33.3 ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 90.0 92.5 95.0 97.5 101.5 127.0 136.5 100.0 120.0 117.5 122.0 107.5 145.0 155.0 130.0 133.3 30.0 30.8 31.7 32.5 33.8 42.3 34.1 33.3 40.0 39.2 40.7 35.8 36.3 38.7 32.5 33.3 ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% 0 to -0.5% 0 to -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% 0 to -0.5% Spread Spectrum Modulation POWER MANAGEMENT CPU_STOP 0 CPUC0 Stopped Low CPUT (0:1) Stopped Low SDRAM (0:11) Stopped Low SDRAM12 Running CRYSTAL Running VCO Running 1 Running Running Running Running Running Running 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 3 PLL205-01 Motherboard Clock Generator for AMD - K7 POWER MANAGEMENT (Continued) PD 0 CPUC0 Stopped Low CPUT (0:1) Stopped Low SDRAM (0:11) Stopped Low SDRAM12 Stopped Low CRYSTAL Stopped VCO Stopped 1 Running Running Running Running Running Running I2C BUS CONFIGURATION SETTING Address Assignment Slave Receiver/Transmitter Data Transfer Rate A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 _ Provides both slave write and readback functionality Standard mode at 100kbits/s The serial bits will be read or sent by the clock driver in the following order Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Serial Bits Reading Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0 Data Protocol This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). I2C CONTROL REGISTERS 1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 8 0 FS3 ( see Frequency selection Table ) Bit 6 48 1 FS2 ( see Frequency selection Table ) Bit 5 25 0 FS1 ( see Frequency selection Table ) Bit 4 26 0 FS0 ( see Frequency selection Table ) Bit 3 - 0 Frequency selection control bit 1=Via I2C, 0=Via External jumper Bit 2 - 0 FS4 ( see Frequency selection Table ) Bit 1 - 1 0=Normal 1=Spread Spectrum enable Bit 0 - 0 0=Normal 1=Tristate Mode for all outputs 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 4 PLL205-01 Motherboard Clock Generator for AMD - K7 BYTE 1: CPU Clock Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - 1 Reserved Bit 6 - 1 Reserved Bit 5 - 1 Reserved Bit 4 - 1 Reserved Bit 3 40 1 SDRAM12 ( Active/Inactive ) Bit 2 - 1 Reserved Bit 1 43,44 1 CPUT0, CPUC0 ( Active/Inactive ) Bit 0 46 1 CPUT1 ( Active/Inactive ) 3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - 1 Reserved Bit 6 7 1 PCI5 ( Active/Inactive ) Bit 5 - 1 Reserved Bit 4 13 1 PCI4 ( Active/Inactive ) Bit 3 12 1 PCI3 ( Active/Inactive ) Bit 2 11 1 PCI2 ( Active/Inactive ) Bit 1 10 1 PCI1 ( Active/Inactive ) Bit 0 8 1 PCI0 ( Active/Inactive ) 4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - 1 Reserved Bit 6 - 1 Reserved Bit 5 26 1 48MHz ( Active/Inactive ) Bit 4 25 1 24_48MHz ( Active/Inactive ) Bit 3 17 1 SDRAM11 ( Active/Inactive ) Bit 2 18 1 SDRAM10 ( Active/Inactive ) Bit 1 20 1 SDRAM9 ( Active/Inactive ) Bit 0 21 1 SDRAM8 ( Active/Inactive ) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 5 PLL205-01 Motherboard Clock Generator for AMD - K7 5. BYTE 4: SDRAM Clock Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 28 1 SDRAM7 ( Active/Inactive ) Bit 6 29 1 SDRAM6 ( Active/Inactive ) Bit 5 31 1 SDRAM5 ( Active/Inactive ) Bit 4 32 1 SDRAM4 ( Active/Inactive ) Bit 3 34 1 SDRAM3 ( Active/Inactive ) Bit 2 35 1 SDRAM2 ( Active/Inactive ) Bit 1 37 1 SDRAM1 ( Active/Inactive ) Bit 0 38 1 SDRAM0 ( Active/Inactive ) 6. BYTE 5: Peripheral Clock Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - X Inverted Power-up latched FS3 value (Read only) Bit 6 - X Inverted Power-up latched FS2 value (Read only) Bit 5 - X Inverted Power-up latched FS1 value (Read only) Bit 4 - X Inverted Power-up latched FS0 value (Read only) Bit 3 - 1 Reserved Bit 2 - X Inverted Power-up latched SEL24_48MHz value (Read only) Bit 1 48 1 REF1 ( Active/Inactive ) Bit 0 2 1 REF0 ( Active/Inactive ) 7. BYTE 6: Revision ID and Vendor ID Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - 0 Revision ID Bit 3* Bit 6 - 0 Revision ID Bit 2* Bit 5 - 0 Revision ID Bit 1* Bit 4 - 0 Revision ID Bit 0* Bit 3 - 0 Vendor ID Bit 3* Bit 2 - 0 Vendor ID Bit 2* Bit 1 - 1 Vendor ID Bit 1* Bit 0 - 1 Vendor ID Bit 0* Note: *: Default value at power-up 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 6 PLL205-01 Motherboard Clock Generator for AMD - K7 8. BYTE 7: Linear Programming (M) Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - 0 Linear programming sign bit ( 0 is “+”, 1 is “−” ) Bit 6 - 0 Linear programming magnitude bit 6 (MSB) Bit 5 - 0 Linear programming magnitude bit 5 Bit 4 - 0 Linear programming magnitude bit 4 Bit 3 - 0 Linear programming magnitude bit 3 Bit 2 - 0 Linear programming magnitude bit 2 Bit 1 - 0 Linear programming magnitude bit 1 Bit 0 - 0 Linear programming magnitude bit 0 (LSB) 9. BYTE 8: Device ID Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - 0 Reserved Bit 6 - 0 Device ID Bit 6* Bit 5 - 0 Device ID Bit 5* Bit 4 - 0 Device ID Bit 4* Bit 3 - 0 Device ID Bit 3* Bit 2 - 0 Device ID Bit 2* Bit 1 - 1 Device ID Bit 1* Bit 0 - 0 Device ID Bit 0* Note: *: Default value at power-up 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 7 PLL205-01 Motherboard Clock Generator for AMD - K7 PROGRAMMING OF CPU FREQUENCY To simplify traditional loop counter setting, the PLL205-01 device incorporates SMART-BYTE ™ technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum performance. Detail of PLL205-01's dual mode frequency programming method is described below: 1. ROM-table Frequency Programming: The pre-defined 32 frequencies found in Frequency table can be accessed either through 5 external jumpers or by setting internal I2C register in BYTE0. 2. Micro-step Linear Frequency Programming: CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other bus frequencies will be changed proportionally with the rate that CPU frequency change. The formula is as follow: F CPU = F CPU.ROM-Table ± α (=0.22) * M Where: 1. M is magnitude factor defined in I2C Byte 7.bit(0:6) 2. ± (sign bit) of M is defined in I2C Byte7.bit 7 3. α is a constant α = 0.22 FREQUENCY PROGRAMMING EXAMPLE: 1. Procedures to program target CPU frequency to 139.0 Mhz: A. Locate the closest CPU frequency from Frequency-ROM table: 136.5 B. α = 0.22 C. Solve M (Linear Magnitude factor) in integer: M = (F CPU - F CPU - ROMTABLE ) / α = (139 – 136.5) / 0.22 = 11 D. Program I2C register: 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 FS3 FS2 FS1 FS0 CTR FS4 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 Sign M6 M5 M4 M3 M2 M1 M0 Setting of I2C.BYTE0 Setting of M = +11 in I2C.BYTE7 F CPU = 136.5 + (0.22) * 11 = 138.92 ( % of frequency increased = 1.8 % ) F PCI = 34.1 * (1+1.8%) = 34.7 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 8 PLL205-01 Motherboard Clock Generator for AMD - K7 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V DD V SS - 0.5 7 V Input Voltage, dc VI V SS - 0.5 V DD + 0.5 V Output Voltage, dc VO V SS - 0.5 V DD + 0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature TA 0 70 °C Junction Temperature TJ 115 °C 2 KV Supply Voltage ESD Voltage Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC/DC Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Input High Voltage V IH 2.0 V DD +0.3 V Input Low Voltage V IL V SS -0.3 0.8 V Input High Current I IH 5 uA Input Low Current I IL1 Logic inputs without internal pull-up on SCLK, V IN = 0V Input Low Current I IL2 Logic inputs with internal pull-up resistors, V IN = 0V Power Down PD Pull-up resistor R pu V IN = V DD -5 uA -200 uA 600 Pin 2,7,8,10,25,26,48 120 uA Kohm C L =0 pF @ 66MHz Operating Supply Current I DD C L =0 pF @ 100MHz 180 mA 16 Mhz 5 PF 45 PF C L =0 pF @ 133MHz Input frequency Input Capacitance FI V DD = 3.3V C IN Logic Inputs C INX XIN & XOUT pins 12 27 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 14.318 Rev 03/07/00 Page 9 PLL205-01 Motherboard Clock Generator for AMD - K7 2. Output Buffer Electrical Specifications Unless otherwise stated, all power supplies = 3.3V±5%, and ambient temperature range T A = 0°C to 70°C PARAMETERS Output Rise time SYMBOL OUTPUTS REF(0:1) Measured @ 0.4V ~ 2.4V, C L =20pf, 3.3V±5% 4 PCI(0:5) Measured @ 0.4V ~ 2.4V, C L =30pf, 3.3V±5% 2 24_48MHz, 48MHz Measured @ 0.4V ~ 2.4V, C L =20pf, 3.3V±5% 4 CPU (Open Drain) Measured @ 1.2V ~ 0.3V, C L =20pf, 3.3V±5% Measured @ 2.4V ~ 0.4V, C L =20pf, 3.3V±5% 0.9 Measured @ 2.4V ~ 0.4V, C L =30pf, 3.3V±5% Measured @ 2.4V ~ 0.4V, C L =20pf, 3.3V±5% 2 T OF 24_48MHz, 48MHz Clock Skew T SKEW REF(0:1),CPU, PCI(0:5) V T = 50% 24_48MHz, 48MHz V T = 1.5V ns 4 45 55 PCI to PCI 200 CPU V T = 50% VO = VX PCI(0:5) Z0 4 200 CPU to PCI REF(0:1) REF1 UNITS ns CPU to CPU CPU to AGP Output Impedance MAX. 0.9 T OR DT TYP. Measured @ 0.3V ~ 1.2V, C L =20pf, 3.3V±5% PCI(0:5) Duty Cycle MIN. CPU (Open Drain) REF(0:1) Output Fall time CONDITIONS 0 3 -500 500 % ps ns 50 30 V DD =3.3V±5% 24_48MHz, 48MHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 40 Ohm 40 40 Rev 03/07/00 Page 10 PLL205-01 Motherboard Clock Generator for AMD - K7 2. Output Buffer Electrical Specifications, continued Unless otherwise stated, all power supplies = 3.3V±5%, and ambient temperature range T A = 0°C to 70°C PARAMETERS SYMBOL OUTPUTS CONDITIONS MIN. TYP. MAX. UNITS CPU REF(0:1) Output High Current I OH PCI(0:5) -22 V OH = 2.0V 24_48MHz -22 48MHz -22 CPU V OL = 0.4V REF(0:1) Output Low Current I OL PCI(0:5) 24_48MHz Jitter, Absolute Jitter (cycle to cycle) J sigma J Abs J cyc-cyc AC Differential Voltage V DIF DC Differential Voltage V DIF Differential Crossover Voltage mA 20 16 V OL = 0.8V 48MHz Jitter, One Sigma -16 19 mA 16 16 REF,48MHz,24MHz V T = 1.5V CPU V T = 50% REF,48MHz,24MHz V T = 1.5V CPU VT = VX 250 PCI Measured @ 1.5V 250 CPU (Open Drain) VX 0.5 ns -250 250 ps -1 1 ns ps 0.4 V pullup +0.6 V 0.2 V pullup +0.6 V 550 1100 mV Note: V pullup = 1.5V (external); V DIF specifies the minimum input differential voltages (V TR -V CP ) required for switching, where V TR is the “true” input level and V CP is the “complement” input level. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/07/00 Page 11 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. 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