Atmel SAM D21EL / SAM D21GL SMART ARM-Based Microcontroller DATASHEET SUMMARY Description The Atmel® | SMART™ SAM D21L is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor. The SAM D21L devices are offered in 32- and 48-pins packages with up 64KB Flash and 8KB of SRAM and are designed to operate at a maximum frequency of 48MHz and reach 2.46 Coremark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The Atmel SAM D21L devices provide the following features: In-system programmable Flash, twelve-channel direct memory access (DMA) controller, 12 channel Event System, programmable interrupt controller, up to 38 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and three 24-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and other control applications. The series provide up to five Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN slave; up to eighteen-channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, four analog comparators with window mode, programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM D21L devices have two software-selectable sleep modes, idle and standby. In idle mode the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are stopped expect those selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The Atmel SAM D21L devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits. Atmel-42348NS–SAM-D21L_Summary–04/2016 SMART Features z Processor z ARM Cortex-M0+ CPU running at up to 48MHz z Single-cycle hardware multiplier z Micro Trace Buffer (MTB) z Memories z 32/64KB in-system self-programmable Flash z 4/8KB SRAM Memory z System z Power-on reset (POR) and brown-out detection (BOD) z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M) z External Interrupt Controller (EIC) z 16 external interrupts z One non-maskable interrupt z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface z Low Power z Idle and standby sleep modes z SleepWalking peripherals z Peripherals z 12-channel Direct Memory Access Controller (DMAC) z 12-channel Event System z Up to five 16-bit Timer/Counters (TC), configurable as either: z One 16-bit TC with compare/capture channels z One 8-bit TC with compare/capture channels z One 32-bit TC with compare/capture channels, by using two TCs z Three 24-bit Timer/Counters for Control (TCC), with extended functions: z Up to four compare channels with optional complementary output z Generation of synchronized pulse width modulation (PWM) pattern across port pins z Deterministic fault protection, fast decay and configurable dead-time between complementary output z Dithering that increase resolution with up to 5 bit and reduce quantization error z 32-bit Real Time Counter (RTC) with clock/calendar function z Watchdog Timer (WDT) z CRC-32 generator z Up to five Serial Communication Interfaces (SERCOM), each configurable to operate as either: z USART with full-duplex and single-wire half-duplex configuration z I2C up to 3.4MHz z SPI z LIN slave z One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 18 channels z Differential and single-ended input z 1/2x to 16x programmable gain stage z Automatic offset and gain error compensation z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z 10-bit, 350ksps Digital-to-Analog Converter (DAC) z Four Analog Comparators (AC) with window compare function z I/O z Up to 38 programmable I/O pins z Packages z 32-pin TQFP, QFN z 48-pin QFN z Operating Voltage z 1.62V – 3.63V Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 2 1. Configuration Summary SAM D21ExL SAM D21GxL Pins 32 48 General Purpose I/O-pins (GPIOs) 26 38 Flash 64/32KB 64KB SRAM 8/4KB 8KB Timer Counter (TC) instances 3 5 Waveform output channels per TC instance 2 2 Timer Counter for Control (TCC) instances 3 3 8/4/2 8/4/2 DMA channels 12 12 Serial Communication Interface (SERCOM) instances 5 5 Analog-to-Digital Converter (ADC) channels 14 18 Analog Comparators (AC) 4 4 Digital-to-Analog Converter (DAC) channels 1 1 Yes Yes 1 1 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values 16 16 Waveform output channels per TCC Real-Time Counter (RTC) RTC alarms RTC compare values External Interrupt lines Maximum CPU frequency Packages Oscillators 48MHz QFN TQFP QFN 0.4-32MHz crystal oscillator (XOSC) 32.768kHz internal oscillator (OSC32K) 32kHz ultra-low-power internal oscillator (OSCULP32K) 8MHz high-accuracy internal oscillator (OSC8M) 48MHz Digital Frequency Locked Loop (DFLL48M) 96MHz Fractional Digital Phased Locked Loop (FDPLL96M) Event System channels 12 12 SW Debug Interface Yes Yes Watchdog Timer (WDT) Yes Yes Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 3 2. Ordering Information SAMD 21 E 15 L - M F T Product Family Package Carrier SAMD = General Purpose Microcontroller No character = Tray (Default) T = Tape and Reel Product Series 21 = Cortex M0 + CPU, Basic Feature Set + DMA + Analog/PWM optimized Package Grade O Pin Count U = -40 - 85 C Matte Sn Plating N = -40 - 105 C Matte Sn Plating F = -40 - 125 C Matte Sn Plating O E = 32 Pins G = 48 Pins O Package Type Flash Memory Density A = TQFP M = QFN 16 = 64KB 15 = 32KB Device Variant A = Default Variant L = Pinout optimized for analog and PWM. 2.1 SAM D21ExL Ordering Code FLASH (bytes) SRAM (bytes) ATSAMD21E15L-MNT 32K 4K ATSAMD21E16L-MNT 64K 8K 32K 4K 125°C 64K 8K 125°C FLASH (bytes) SRAM (bytes) Temp.Range Package Carrier Type ATSAMD21G16L-MUT 64K 8K 85°C QFN48 Tape & Reel ATSAMD21G16L-MNT 64K 8K 105°C QFN48 Tape & Reel ATSAMD21E15L-AFT ATSAMD21E15L-MFT ATSAMD21E16L-AFT ATSAMD21E16L-MFT 2.2 Temp.Range Package Carrier Type 105°C QFN32 Tape & Reel TQFP32 QFN32 TQFP32 QFN32 Tape & Reel Tape & Reel SAM D21GxL Ordering Code Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 4 Block Diagram SWCLK CORTEX-M0+ PROCESSOR Fmax 48 MHz SERIAL WIRE SWDIO MEMORY TRACE BUFFER IOBUS DEVICE SERVICE UNIT M 64/32KB NVM 8/4KB RAM NVM CONTROLLER Cache SRAM CONTROLLER M S S PERIPHERAL ACCESS CONTROLLER S AHB-APB BRIDGE B S S AHB-APB BRIDGE A AHB-APB BRIDGE C PERIPHERAL ACCESS CONTROLLER PERIPHERAL ACCESS CONTROLLER SYSTEM CONTROLLER DMA PAD0 PAD1 PAD2 PAD3 5x 6 SERCOM x SERCOM VREF BOD33 DMA M HIGH SPEED BUS MATRIX PORT OSCULP32K OSC32K DMA OSC8M 5 x TIMER / COUNTER 8 x Timer Counter WO0 WO1 XOSC FDPLL96M DMA POWER MANAGER CLOCK CONTROLLER RESETN RESET CONTROLLER SLEEP CONTROLLER 3x TIMER / COUNTER FOR CONTROL WO0 WO1 PORT DFLL48M XIN XOUT EVENT SYSTEM 3. (2) WOn AIN[19..0] DMA 18-CHANNEL 12-bit ADC 350KSPS VREFA VREFB CMP[1..0] GCLK_IO[7..0] REAL TIME COUNTER WATCHDOG TIMER EXTINT[15..0] NMI 4x ANALOG COMPARATORS GENERIC CLOCK CONTROLLER DMA AIN[3..0] VOUT 10-bit DAC VREFA EXTERNAL INTERRUPT CONTROLLER 1. Some products have different number of SERCOM instances, Timer/Counter instances and ADC signals. 2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines. Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 5 Pinout 4.1 SAM D21GxL 4.1.1 QFN48 48 47 46 45 44 43 42 41 40 39 38 37 PB03 PB02 PB01 PB00 PA31 PA30 VDDIN VDDCORE GND PA28 RESETN PA27 4. 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO GND PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 PA08 PA09 PA10 PA11 VDDIO GND PB10 PB11 PA12 PA13 PA14 PA15 PA02 PA03 PB04 PB05 GNDANA VDDANA PB08 PB09 PA04 PA05 PA06 PA07 DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY REGULATED OUTPUT SUPPLY RESET PIN Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 6 SAM D21ExL 4.2.1 QFN32 / TQFP32 32 31 30 29 28 27 26 25 PB03 PB02 PA31 PA30 VDDIO VDDCORE GND RESETN 4.2 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 PA25 PA24 PA23 PA22 PA19 PA18 PA17 PA16 VDDIO/ANA GND PA08 PA09 PA10 PA11 PA14 PA15 9 10 11 12 13 14 15 16 PA02 PA03 PB04 PB05 PA04 PA05 PA06 PA07 Digital Pin Analog Pin Oscillator Pin Ground Input Supply Regulated Output Supply Reset Pin Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 7 5. Product Mapping Figure 5-1. Atmel | SMART SAM D21L Product Mapping Global Memory Space Code 0x00000000 0x00000000 Internal Flash Code 0x00400000 0x1FFFFFFF 0x20000000 SRAM 0x20008000 Internal RWW section AHB-APB Bridge C SRAM 0x42000000 Internal SRAM 0x42000400 AHB-APB 0x42000800 AHB-APB Bridge A 0x42000C00 PAC2 0x20000000 0x20001FFF Undefined EVSYS SERCOM0 0x40000000 0x40000000 Peripherals AHB-APB Bridge B 0x43000000 Reserved 0x60000000 SERCOM1 0x42001000 0x41000000 SERCOM2 0x42001400 SERCOM3 0x42000000 AHB-APB Bridge C 0x42FFFFFF 0x42001800 Reserved 0x42001C00 Reserved System Undefined 0xE0000000 0x42002000 Reserved 0x60000200 Reserved 0xE000E000 TCC0 0x42002400 SCS 0xE0000000 0xE000F000 System Reserved 0xE00FF000 0xFFFFFFFF TCC1 0x42002800 TCC2 0x42002C00 ROMTable 0xE0100000 TC3 0x42003000 Reserved 0xFFFFFFFF AHB-APB Bridge A 0x41002000 0x41004000 0x41004400 0x41004800 0x41005000 0x41006000 Reserved 0x42005000 MTB EIC 0x41007000 0x40001C00 DAC 0x42004C00 Reserved RTC 0x40001800 AC 0x42004800 DMAC WDT 0x40001400 ADC 0x42004400 PORT GCLK 0x40001000 Reserved 0x42004000 NVMCTRL SYSCTRL 0x40000C00 Reserved 0x42003C00 DSU PM 0x40000800 Reserved 0x40FFFFFF 0x42003800 PAC1 PAC0 0x40000400 TC5 AHB-APB Bridge B 0x41000000 0x40000000 TC4 0x42003400 Reserved 0x42005400 Reserved 0x41FFFFFF AC1 0x42005800 Reserved 0x42FFFFFF This figure represents the full configuration of the Atmel® SAM D21 with maximum flash and SRAM capabilities and a full set of peripherals. Refer to the “Configuration Summary” on page 3 for details. Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 8 6. Processor And Architecture 6.1 Cortex M0+ Processor The Atmel | SMART SAM D21L implements the ARM® Cortex™-M0+ processor, which is based on the ARMv6 Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and upward compatible to Cortex-M3 and M4 processors. For more information refer to www.arm.com. 6.1.1 Cortex M0+ Configuration Features Configuration option Atmel | SMART SAM D21L configuration Interrupts External interrupts 0-32 32 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Absent(1) Memory Protection Unit Not present or 8-region Not present Reset all registers Present or absent Absent Instruction fetch width 16-bit only or mostly 32-bit 32-bit Note: 1. All software run in privileged mode only The ARM Cortex-M0+ core has two bus interfaces: z Single 32-bit AMBA®-3 AHB-Lite™ system interface that provides connections to peripherals and all system memory, including flash and RAM z Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 9 7. Packaging Information 7.1 Thermal Considerations 7.1.1 Thermal Resistance Data Table 7-1 summarizes the thermal resistance data depending on the package. Table 7-1. 7.1.2 Thermal Resistance Data Package Type θJA θJC 32-pin TQFP 64.7 °C/W 23.1 °C/W 32-pin QFN 40.9 °C/W 15.2 °C/W 48-pin QFN 32.0°C/W 10.9 °C/W Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. T J = T A + ( P D × θ JA ) 2. T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) where: z θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 7-1. z θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 7-1. z θHEATSINK = cooling device thermal resistance (°C/W), provided in the device datasheet. z PD = device power consumption (W). z TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 10 7.2 Package Drawings 7.2.1 48-pin QFN Table 7-2. Device and Package Maximum Weight 140 Table 7-3. mg Package Characteristics Moisture Sensitivity Level Table 7-4. MSL3 Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 11 7.2.2 32-pin TQFP Table 7-5. Device and Package Maximum Weight 100 Table 7-6. mg Package Characteristics Moisture Sensitivity Level Table 7-7. MSL3 Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 12 7.2.3 32-pin QFN Table 7-8. Device and Package Maximum Weight 90 Table 7-9. mg Package Characteristics Moisture Sensitivity Level MSL3 Table 7-10. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 13 7.3 Soldering Profile The following table gives the recommended soldering profile from J-STD-20. Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max Preheat Temperature 175°C +/-25°C 150-200°C Time Maintained Above 217°C 60-150s Time within 5°C of Actual Peak Temperature 30s Peak Temperature Range 260°C Ramp-down Rate 6°C/s max Time 25°C to Peak Temperature 8 minutes max A maximum of three reflow passes is allowed per component. SVNREVISION Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 14 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 SAM D21ExL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SAM D21GxL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 4.2 SAM D21GxL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SAM D21ExL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1 7.2 7.3 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Atmel | SMART SAM D21L [DATASHEET SUMMARY] Atmel-42348NS–SAM-D21L_Summary–04/2016 15 ARM Connected Logo Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: Atmel-42348NS-SAM-D21L_Summary_04/2016. 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