Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES • • • • • • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of six differential outputs. Track spread spectrum clocking for EMI reduction. Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled. Two independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ±100ps. Support 2-wire I 2 C serial bus interface. CLKCO 1 28 CLKT0 VDD 2 3 27 26 CLKT1 CLKC1 4 5 GND SCLK 6 7 CLK_INT N/C 8 9 PLL102-109 • • PIN CONFIGURATION 25 24 GND CLKC5 CLKT5 CLKC4 23 22 CLKT4 VDD SDATA 21 20 N/C FB_INT 19 18 FB_OUTT ADDR_SEL AVDD AGND 10 11 VDD 12 13 17 16 CLKT3 CLKC3 14 15 GND CLKT2 CLKC2 2.5V Operating Voltage. Available in 28-Pin 209mil SSOP. DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AV DD to ground. BLOCK DIAGRAM Programmable Skew Channel -600~+800ps ±200ps step Control Logic AV DD -300~+400ps ±100ps step Programmable Delay Channel CLK_INT (0~2.5ns) +170ps step FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT5 CLKC5 PLL FB_INT AV DD -300~+400ps ±100ps step 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 Rev 02/26/03 Page 1 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver PIN DESCRIPTIONS Name Number Type Description VDD 3,12,23 PWR 2.5V power supply. GND 6,15,28 PWR Ground AVDD 10 PWR Analog power supply (2.5V). AGND 11 PWR Analog ground. CLKT(0:5) 2,4,13,17,24,26 OUT “True” clocks of differential pair outputs. CLKC(0:5) 1,5,14,16,25,27 OUT “Complementary” clocks of differential pair outputs. CLK_INT 8 IN ADDR_SEL 18 IN N/C 9,21 - FB_OUTT 19 OUT FB_INT 20 IN SDATA 22 I/O SCLK 7 IN Single-ended 3.3V tolerant input. If ADDR_SEL=0(default) Write condition (0xD4) or a read condition (0xD5) If ADDR_SEL=1, Write condition (0xD6) or a read condition (0xD7) Not connected. “True” feedback output. Dedicated for external feedback. It switches at the same frequency as the CLK_INT. “True” feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. Serial data input for serial interface port. Functionality INPUTS OUTPUTS PLL State AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT 2.5V (Nom) L H L H L On 2.5V (Nom) H L H L H On GND L H L H L Bypass/Off GND H L H L H Bypass/Off 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 2 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver I2C BUS CONFIGURATION SETTING Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 _ Slave Receiver/Transmitter Provides both slave write and read back functionality Data Transfer Rate Standard mode at 100kbits/s Data Protocol This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD4) or a read condition (0xD5). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). I2C CONTROL REGISTERS 1. BYTES 0 TO 4 are reserved power up default =1. 2. BYTE 5: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 - - Reserved Bit 6 - - Reserved Bit 5 26,27 1 CLKT5, CLKC5 (1= active, 0=inactive) Bit 4 24,25 1 CLKT4, CLKC4 (1= active, 0=inactive) Bit 3 16,17 1 CLKT3, CLKC3 (1= active, 0=inactive) Bit 2 13,14 1 CLKT2, CLKC2 (1= active, 0=inactive) Bit 1 4,5 1 CLKT1, CLKC1 (1= active, 0=inactive) Bit 0 1,2 1 CLKT0, CLKC0 (1= active, 0=inactive) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 3 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver TABLE 1: Output Signals SKEW Programming Summary: DDR Skew Setting (± ± 100ps/step) FBOUT Skew Setting (± ± 200ps/step) 111 +400ps +800ps 110 +300ps Bit<2:0> +600ps Setting applies to the following outputs: +400ps 1. DDRA: CLK0, CLK1, CLK5 2. DDRB: CLK2, CLK3, CLK4. Default 101 +200ps 100 +100ps 011 Default 010 -100ps 001 -200ps -400ps 000 -300ps -600ps Setting applies to the following outputs: +200ps 1. FB_OUTT -200ps 3. BYTE 6: SKEW Register (1=Enable, 0=Disable) Bit Name Default Bit 7 - - Reserved Bit 6 - - Reserved Bit 5 Bit 4 Bit 3 Skew DDRA Bit <2> 0 Bit <1> 1 Bit <0> 1 Description These three bits will adjust timing of DDRA signals (CLK0, CLK1, CLK5) either positive or negative delay up to +400ps or –300ps with ±100ps per step. (see Table 1) Bit 2 - - - Reserved Bit 1 - - - Reserved Bit 0 - - - Reserved 4. BYTE 7: SKEW Register (1=Enable, 0=Disable) Bit Name Default Bit 7 DDR-SKEWEN 1 1= disable, 0= enable Bit 6 FBOUT-SKEWEN 1 1= disable, 0= enable Bit <2> 0 Bit <1> 1 Bit <0> 1 Bit 5 Bit 4 Bit 3 Skew DDRC Description These three bits will adjust timing of DDRC signals (CLK2, CLK3, CLK4) either positive or negative delay up to +400ps or –300ps with ±100ps per step. (see Table 1) Bit 2 - - - Reserved Bit 1 - - - Reserved Bit 0 - - - Reserved 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 4 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver 5. BYTE 8: Outputs Register (1=Enable, 0=Disable) Bit Name Default Bit 7 - 1 Bit 6 Bit 5 Bit 4 Skew FBOUT Bit 3 Bit <2> 0 Bit <1> 1 Bit <0> 1 Bit <3> 0 Bit 2 Delay Bit <2> 0 Bit 1 CLKINT Bit <1> 0 Bit <0> 0 Bit 0 Description Reserved These three bits will adjust timing of FBOUTT signal either positive or negative delay up to +800ps or –600ps with ±200ps per step. (see Table 1) These four bits will program the propagation delay from CLK_INT to the input of PLL within the range between 0ps and 2.5ns with 170ps step size. (see Table 2) TABLE 2: CLK_INT Delay Programming Summary: Bit<3:0> CLK_INT to CLK Delay 1111 +2,550 ps 1110 +2,380 ps 1101 +2,210 ps 1100 +2,040 ps 1011 +1,870 ps 1010 +1,700 ps 1001 +1,530 ps 1000 +1,360 ps 0111 +1,190 ps 0110 +1,020 ps 0101 +850 ps 0100 +680 ps 0011 +510 ps 0010 +340 ps 0001 +170 ps 0000 Default 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 5 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver TABLE 3: Output Drive Strength Programming Summary: Bit<2:0> Programming Setting 111 +40% 110 +30% 101 +20% Setting applies to the following outputs 100 +10% 011 Default 010 -10% 1. DDRA (CLK0, CLK1, CLK5) 2. DDRB (CLK2, CLK3, CLK4) 3. FBOUT 001 -20% 000 -30% 6. Byte 9: Buffer Drive Strength Control Register Bit Name Default Bit 7 - 1 Reserved. Bit 6 - 1 Reserved. Bit 5 Description Bit <2> 0 DDRA Strength Bit <1> 1 Bit <0> 1 Bit 2 - - - Reserved Bit 1 - - - Reserved Bit 0 - - - Reserved Bit 4 Bit 3 These three bits will program drive strength for CLK0, CLK1 and CLK5 output clocks (see Table 3). 7. Byte 10: Buffer Drive Strength Control Register Bit Name Default Bit 7 - 1 Reserved. Bit 6 - 1 Reserved. Bit 5 Description Bit <2> 0 DDRC Strength Bit <1> 1 Bit <0> 1 Bit 2 - - - Reserved Bit 1 - - - Reserved Bit 0 - - - Reserved Bit 4 Bit 3 These three bits will program drive strength for CLK2, CLK3 and CLK4 output clocks (see Table 3). 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 6 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver 8. Byte 11: Buffer Drive Strength Control Register Bit Name Default Bit 7 - 1 Reserved. Bit 6 - 1 Reserved. Bit 5 - 1 Reserved. Bit 4 - 1 Reserved. Bit 3 - 1 Reserved. Bit 2 Bit 1 Bit 0 FBOUTT Strength Bit <2> 0 Bit <1> 1 Bit <0> 1 Description These three bits will program drive strength for FBOUTT output clock (see Table 3). 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 7 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. V CC - 0.5 3.6 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V Storage Temperature TS -65 150 °C Maximum power dissipation at T A = 55 0 C in still air PW 0.7 W Supply Voltage Range UNITS Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. Electrical Characteristics PARAMETERS SYMBOL CONDITIONS I DD2.5 CL = 0 pF (Fclk=100Mhz) I DDPD CL = 0 pF 100 uA High Impedance output current I OZ VDD=2.7V, V OUT =VDD or GND ±10 uA Input clamp voltage V IK I in = -18mA -1.2 V Input Capacitance C IN V I = VDD or GND 2 pF Output Capacitance C OUT V O = VDD or GND 3 pF High level output voltage V OH Low level output voltage V OL Output differential-pair crossing voltage V OC Operating supply current MIN. TYP. MAX. 250 UNITS mA VDD = Min to Max, I OH = -1mA VDD-0.1 V VDD = 2.3V, I OH = -12mA 1.7 V VDD = Min to Max, I OL = 1mA 0.1 V VDD = 2.3V, I OL = 12mA 0.6 V (VDD/ 2)+0.2 V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 (VDD/2)0.2 Rev 02/26/03 Page 8 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver 3. Recommended Operating Conditions PARAMETERS SYMBOL MIN. TYP. MAX. UNITS Output supply voltage V CC 2.3 2.5 2.7 V Analog Supply voltage A CC 2.3 2.5 2.7 V High level input voltage V IH 0.7 x V CC Low level input voltage V IL Operating free-air temperature TA V 0.3 x V CC V 70 °C 0 4. Timing requirements SYMBOL PARAMETERS MIN. MAX. UNITS F CLK Input clock frequency 66 266 MHz D IN Input clock duty cycle 40 60 % TS Stabilization time after power up 0.1 ms 5. Switching Characteristics PARAMETERS SYMBOL CONDITIONS Low to high level propagation delay time T PLH CLK_INT to any output 0 High to low level propagation delay time T PHL CLK_INT to any output 0 Jitter (peak to peak) T p-p Jitter (cycle to cycle) T cyc-cyc Phase error MIN. TYP. MAX. UNITS ns t (phase error) Output to output skew T oskew Pulse skew T pskew Duty Cycle DT Rise time, Fall time t r, t f 66MHz 120 100/133/200/266MHz 75 66MHz 110 100/133/200/266MHz 65 All differential input and output terminals are terminated with 120Ω/16pF -150 66MHz to 100MHz 49.5 50.5 101MHz to 266MHz 49 51 Load = 120Ω/16pF 650 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 ps ps 150 100 ps 100 800 950 % ps Rev 02/26/03 Page 9 Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver PACKAGE INFORMATION Package SSOP (QSOP) 209mil Pins# E 28 E1 mm inches Unit min A e B max min 2.0 max 0.079 A1 0.05 0.002 B 0.25 0.38 0.01 0.015 C 0.09 0.25 0.004 0.010 D 9.9 10.5 0.390 0.413 E 7.40 8.20 0.291 0.323 E1 5.00 5.60 0.197 0.220 D C A A1 L e 0.65BSC 0.0256BSC 28PIN SSOP L 0.55 0.95 0.022 0.038 ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL102-109 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/26/03 Page 10