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tCYC
PWEL
E
PWEH
tf
tr
VIHT
VILT
R/W
tAS
tAH
tAH
tAS
CS1–CS3
D/I
VIHT
VILT
tDHR
tDDR
VIHT
VILT
DB0–DB7
1!5$#
tCYC
E
VIHT
VILT
PWEL
PWEH
tf
tAH
tr
R/W
VIHT
VILT
tAS
tAS
CS1–CS3
D/I
tAH
VIHT
VILT
tDSW
VIHT
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DB0–DB7
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tDHW
+11
MPU Interface (GND = 0V, VCC = 2.7 to 5.5V, Ta = –30 to +75°C)*
Item
Symbol
Min
Typ
Max
Unit
E cycle time
t CYC
1000
—
—
ns
E high level width
PWEH
450
—
—
ns
E low level width
PWEL
450
—
—
ns
E rise time
tr
—
—
25
ns
E fall time
tf
—
—
25
ns
Address setup time
t AS
140
—
—
ns
Address hold time
t AH
10
—
—
ns
Data setup time
t DSW
200
—
—
ns
Data delay time
t DDR
—
—
320
ns
Data hold time (write)
t DHW
10
—
—
ns
Data hold time (read)
t DHR
20
—
—
ns
0
1
Set Y address
Status read
1
1
0
0
0
0
0
D/I
1
0
1
0
Read data
Write data
Busy 0
0
1
1
0
1
1
1
1
1
ON/ Reset 0
OFF
Y address (0–63)
1
1
0
0
Page (0–7)
Display start line (0–63)
1
0
1/0
1: Reset
0: Normal
Reads data DB0 (LSB)
to DB7 (MSB) from the
display RAM to the data
bus.
Has access to the
address of the display
RAM specified in
advance. After the
access, Y address is
increased by 1.
1: Internal operation
0: Ready
Writes data DB0 (LSB)
to DB7 (MSB) on the
data bus into display
RAM.
Busy
ON/OFF 1: Display off
0: Display on
RESET
Reads the status.
Sets the Y address in the Y address counter.
Sets the page (X address) of RAM at the page
(X address) register.
Specifies the RAM line displayed at the top of the
screen.
Controls display on/off. RAM data and internal
status are not affected. 1: on, 0: off.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Functions
Note: Busy time varies with the frequency (fCLK) of ø1, and ø2.
(1/fCLK ≤ TBUSY ≤ 3/fCLK)
1
0
Set page (X address)
Read display data
0
Display start line
0
0
Display on/off
Write display data
R/W
Instructions
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