S6B0108 64 CH SEGMENT DRIVER FOR DOT MATRIX LCD June. 2000. Ver. 0.0 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION The S6B0108 is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal display system in combination with the S6B0107 (64 channel common driver). FEATURES • Dot matrix LCD segment driver with 64 channel output • Input and output signal - Input: 8 bit parallel display data control signal from MPU divided bias voltage (V0R, V0L, V2R, V2L, V3R, V3L, V5R, V5L) - Output: 64 channel for LCD driving. • Display data is stored in display data RAM from MPU. • Interface RAM - Capacity: 512 bytes (4096 bits) - RAM bit data: RAM bit data = 1: On RAM bit data = 0: Off • Applicable LCD duty: 1/32-1/64 • LCD driving voltage: 8V-17V (VDD-VEE) • Power supply voltage: + 5V ± 10% • Interface Drivers Common Segment S6B0107 Other S6B0108 • High voltage CMOS process. • Bare chip available 2 Controller MPU 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 DB<0:7> Output Register 8 Display On/Off I/O Buffer Input Register CLK2 CLK1 BLOCK DIAGRAM 8 CS1B CS2B CS3 R/W RS E RSTB Instruction Decoder Busy 1 6 3 Y-Counter ADC 6 Y-Counter 6 X-Decoder 64 Display Data RAM 512 × 8 = 4096bits 8 8 Page Selector FRM 6 Z-Decoder CL Display Start Line Register 64 64 Data Latch 64 V0L V0R V2L V3L V2R LCD Driver V3R V5L V5R S1 S2 S63 S64 M 3 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 3 VDD 2 M 1 ADC 100 FRM 99 E 98 CLK1 97 CLK2 96 CL 95 RS 94 R/W 93 RSTB 92 CS1B 91 CS2B 90 CS3 89 NC 88 NC 87 NC 86 DB7 85 DB6 84 DB5 83 DB4 82 DB3 81 DB2 80 DB1 79 DB0 78 VSS PAD DIAGRAM 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Y (0, 0) X Chip size: 4090 × 4020 PAD size: 100 × 100 Unit : µm S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 There is mark of S6B0108 on the bottom left in the chip. 4 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 PAD CENTER COORDINATES PAD Number PAD Name 1 Coordinate Coordinate Pad Name X Coordinate X Y Pad Number Y Pad Number Pad Name X Y ADC -1140 1845 35 S38 -687 -1845 69 S4 1882 791 2 M -1275 1845 36 S37 -562 -1845 70 S3 1882 916 3 VDD -1410 1845 37 S36 -437 -1845 71 S2 1882 1041 4 V3R -1882 1809 38 S35 -312 -1845 72 S1 1882 1166 5 V2R -1882 1684 39 S34 -187 -1845 73 VEE1 1882 1310 6 V5R -1882 1559 40 S33 -62 -1845 74 V0L 1882 1435 7 V0R -1882 1434 41 S32 62 -1845 75 V5L 1882 1559 8 VEE2 -1882 1309 42 S31 187 -1845 76 V2L 1882 1684 9 S64 -1882 1165 43 S30 312 -1845 77 V3L 1882 1809 10 S63 -1882 1040 44 S29 437 -1845 78 VSS 1412 1845 11 S62 -1882 915 45 S28 562 -1845 79 DB0 1277 1845 12 S61 -1882 790 46 S27 687 -1845 80 DB1 1142 1845 13 S60 -1882 665 47 S26 812 -1845 81 DB2 1007 1845 14 S59 -1882 540 48 S25 937 -1845 82 DB3 882 1845 15 S58 -1882 415 49 S24 1062 -1845 83 DB4 757 1845 16 S57 -1882 290 50 S23 1187 -1845 84 DB5 632 1845 17 S56 -1882 165 51 S22 1487 -1845 85 DB6 507 1845 18 S55 -1882 40 52 S21 1882 -1379 86 DB7 382 1845 19 S54 -1882 -84 53 S20 1882 -1239 87 NC 20 S53 -1882 -209 54 S19 1882 -1099 88 NC 21 S52 -1882 -334 55 S18 1882 -959 89 NC 22 S51 -1882 -459 56 S17 1882 -834 90 CS3 245 1845 23 S50 -1882 -584 57 S16 1882 -709 91 SC2B 120 1845 24 S49 -1882 -709 58 S15 1882 -584 92 SC1B -5 1845 25 S48 -1882 -834 59 S14 1882 -459 93 RSTB -130 1845 26 S47 -1882 -959 60 S13 1882 -334 94 R/W -255 1845 27 S46 -1882 -1099 61 S12 1882 -209 95 RS -380 1845 28 S45 -1882 -1239 62 S11 1882 -84 96 CL -505 1845 29 S44 -1882 -1379 63 S10 1882 41 97 P2 -630 1845 30 S43 -1487 -1845 64 S9 1882 166 98 P1 -755 1845 31 S42 -1187 -1845 65 S8 1882 291 99 E -880 1845 32 S41 -1062 -1845 66 S7 1882 416 100 FRM -1005 1845 33 S40 -937 -1845 67 S6 1882 541 34 S39 -812 -1845 68 S5 1882 666 5 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION Table 1. Pin Description Pin Number QFP(TQFP) 3(1) 78(76) 73(71), 8(6) Symbol VDD VSS VEE1.2 Input / Output Power Description For internal logic circuit (+5V ± 10%) GND (0V) For LCD driver circuit VSS = 0V, VDD = +5V ± 10%, VDD-VEE = 8V - 17V VEE1 and VEE2 is connected by the same voltage. Bias supply voltage terminals to drive the LCD. 74(72), 7(5) 76(74), 5(3) 77(75), 4(2) 75(73), 6(4) V0L, V0R V2L, V2R V3L, V3R V5L, V5R Power 92(89) 91(87) 90(86) CS1B CS2B CS3 Input Chip selection In order to interface data for input or output, the terminals have to be CS1B = L, CS2B = L, and CS3 = H. 2(100) M Input Alternating signal input for LCD driving. Input Address control signal to determine the relation between Y address of display RAM and terminals from which the data is output. ADC = H → Y0: S1 - Y63: S64 ADC = L → Y0: S64 - Y63: S1 Input Synchronous control signal. Presets the 6-bit Z counter and synchronizes the common signal with the frame signal when the frame signal becomes high. 1(99) 100(98) 6 ADC FRM Select Level Non-Select Level V0L(R), V5L(R) V2L(R), V3L(R) V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be connected by the same voltage. 99(97) E Input Enable signal. Write mode (R/W = L) → data of DB<0:7> is latched at the falling edge of E. Read mode (R/W = H) → DB<0:7> appears the reading data while E is at high level. 98(96) 97(95) CLK1 CLK2 Input 2 phase clock signal for internal operation. Used to execute operations for input/output of display RAM data and others. 96(94) CL Input Display synchronous signal. Display data is latched at rising time of the CL signal and increments the Z-address counter at the CL falling time. 95(93) RS Input Data or Instruction. RS = H → DB<0:7>: Display RAM data RS = L → DB<0:7>: Instruction data 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 Table 1. Pin Description (Continued) Pin Number QFP(TQFP) 94(92) Symbol R/W Input / Output Input Description Read or Write. R/W = H → Data appears at DB<0:7> and can be read by the CPU while E = H, CS1B = L, CS2B = L and CS3 = H . R/W = L → Display data DB<0:7> can be written at falling of E when CS1B = L, CS2B = L and CS3 = H. 79-86 (77-84) DB0-DB7 Input/Output Data bus. Three state I/O common terminal. LCD segment driver output. Display RAM data 1: On Display RAM data 0: Off (relation of display RAM data & M) 72-9 (70-7) M S1-S64 Output Data Output Level L H L V2 H V0 L V3 H V5 Reset signal. When RSTB=L, 93(91) 87(85), 88(88) 89(90) RSTB NC Input - ON / OFF register becomes set by 0. (display off) – Display start line register becomes set by 0 (Z-address 0 set, display from line 0) After releasing reset, this condition can be changed only by instruction. No connection. (open) 7 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Note Operating voltage VDD -0.3 to +7.0 V (1) Supply voltage VEE VDD-19.0 to VDD+0.3 V (4) VB -0.3 to VDD+0.3 V (1), (3) VLCD VEE-0.3 to VDD+0.3 V (2) Operating temperature TOPR -30 to +85 °C Storage temperature TSTG -55 to +125 °C Driver supply voltage NOTES: 1. Based on VSS = 0V. 2. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE. 3. 4. 8 Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0 - DB7. Applies to V0L(R), V2L(R), V3L(R) and V5L(R). Voltage level: VDD ≥ V0L = V0R ≥ V2L = V2R ≥ V3L = V3R ≥ V5L = V5R ≥ VEE. 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, VDD-VEE = 8 to 17V, Ta =-30 to +85°° C) Characteristic Input high voltage Input low voltage Symbol Condition Min Typ Max Unit Note VIH1 - 0.7VDD - VDD V (1) VIH2 - 2.0 - VDD V (2) VIL1 - 0 - 0.3VDD V (1) VIL2 - 0 - 0.8 V (2) Output high voltage VOH IOH = -200µA 2.4 - - V (3) Output low voltage VOL IOL = 1.6mA - - 0.4 V (3) Input leakage current ILKG VIN = VSS - VDD -1.0 - 1.0 µA (4) Three-state(off) input current ITSL VIN = VSS - VDD -5.0 - 5.0 µA (5) Driver input leakage current IDIL VIN = VEE - VDD -2.0 - 2.0 µA (6) IDD1 During display - - 100 µA (7) IDD2 During access Access cycle = 1MHz - - 500 µA (7) RON VDD-VEE = 15V ILOAD = ± 0.1mA - - 7.5 KΩ (8) Operating current On resistance NOTES: 1. CL, FRM, M RSTB, CLK1, CLK2 2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7 3. DB0 - DB7 4. Except DB0 - DB7 5. DB0 - DB7 at high impedance 6. V0L(R), V2L(R), V3L(R), V5L(R) 7. 1/64 duty, FCLK = 250kHz, frame frequency = 70HZ, output: no load 8. VDD - VEE = 15.5V V0L(R) > V2L(R) = VDD - 2/7 (VDD-VEE) > V3L(R) = VEE + 2/7 (VDD-VEE) > V5L(R) 9 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD AC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, Ta =-30 to +85°° C) Clock Timing Characteristic Symbol Min Typ Max Unit CLK1, CLK2 cycle time tCY 2.5 - 20 µs CLK1 "low" level width tWL1 625 - - CLK2 "low" level width tWL2 625 - - CLK1 "high" level width tWH1 1875 - - CLK2 "high" level width tWH2 1875 - - CLK1-CLK2 phase difference tD12 625 - - CLK2-CLK1 phase difference tD21 625 - - CLK1, CLK2 rise time tR - - 150 CLK1, CLK2 fall time tF - - 150 ns tCY tWH1 tF CLK1 tR 0.7VDD 0.3VDD tWL1 CLK2 tD12 tD21 0.7VDD 0.3VDD tF tWL2 tWH2 tR Figure 1. External Clock Waveform 10 tCY 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 Display Control Timing Characteristic Symbol Min Typ Max Unit FRM delay time tDF -2 - +2 us M delay time tDM -2 - +2 us CL "low" level width tWL 35 - - us CL "high" level width tWH 35 - - us tWL 0.7VDD 0.3VDD tWH tDF tDF 0.7VDD 0.3VDD tDM 0.7VDD 0.3VDD Figure 2. Display Control Waveform 11 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD MPU Interface Characteristic Symbol Min Typ Max Unit tC 1000 - - ns E high level width tWH 450 - - ns E low level width tWL 450 - - ns E rise time tR - - 25 ns E fall time tF - - 25 ns Address set-up time tASU 140 - - ns Address hold time tAH 10 - - ns Data set-up time tDSU 200 - - ns Data delay time tD - - 320 ns Data hold time (write) tDHW 10 - - ns Data hold time (read) tDHR 20 - - ns E cycle tC E 2.0V 0.8V tWL tWH tR tF tASU tAH tASU tAH R/W CS1B, CS2B, CS3, RS 0.8V 2.0V tDSU tDHW DB0 - 7 Figure 3. MPU Write Timing 12 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 tC E tWL tWH tR R/W tF tASU tAH tASU tAH CS1B, CS2B, CS3, RS tD tDHR DB0 - 7 Figure 4. MPU Read Timing 13 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD OPERATING PRINCIPLES AND METHODS I/O BUFFER Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS1B-CS3. INPUT REGISTER Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then Writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. OUTPUT REGISTER Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS = H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W = H, RS = L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. RS L H 14 R/W Function L Instruction H Status read (busy check) L Data write (from input register to display data RAM) H Data read (from display data RAM to output register) 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 RESET The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. • Display off • Display start line register become set by 0. (Z-address 0) While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. The Conditions of power supply at initial power up are shown in table 1. Table 2. Power Supply Initial Conditions Item Symbol Min Typ Max Unit Reset time tRS 1.0 - - us Rise time tR - - 200 ns VDD 4.5V tRS tR RSTB 0.7VDD 0.3VDD 15 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD Busy Flag Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high, S6B0108 is in internal operating. When busy flag is low, S6B0108 can accept the data or instruction. DB7 indicates busy flag of the S6B0108. RS R/W E Address N Output register DB0-DB7 N+1 N+2 Data at address N Busy check Write address N Busy check Read data Busy (dummy) check Data at address N+1 Read data Busy at address check N Data read address N + 1 Busy Check E Busy Flag T Busy 1/fCLK < T Busy < 3/fCLK fCLK is CLK1, CLK2 frequency Busy Flag 16 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 Display ON / OFF Flip - Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flipflop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal. X Page Register X page register designates pages of the internal display data RAM. Count function is not available. An address is set by instruction. Y Address Counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. Display Data RAM Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid crystal display, write data 1. The other way, off state, writes 0. Display data RAM address and segment output can be controlled by ADC signal. • ADC = H → Y-address 0:S1 - Y address 63:S64 • ADC = L → Y-address 0:S64 - Y address 63:S1 ADC terminal connect the VDD or VSS. Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen. 17 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD DISPLAY CONTROL INSTRUCTION The display control instructions control the internal state of the S6B0108. Instruction is received from MPU to S6B0108 for the display control. The following table shows various instructions. Instruction Display on/off RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L L L L L H Set page (X address) L L H L Display start line (Z address) L L H H Set address H H H H H L/H (Y address) Status read L H Busy L H H Sets the X address at the X address register. Page (0 - 7) Indicates the display data RAM displayed at the top of the screen. Display start line (0 - 63) On / Off Reset L L Controls the display on or off. Internal status and display RAM data is not affected. L: OFF, H: ON Sets the Y address in the Y address counter. Y address (0 - 63) H Function L L Read status. BUSY L: Ready H: In operation ON/OFF L: Display ON H: Display OFF RESET L: Normal H: Reset Write display data H L Write data Writes data (DB0:7) into display data RAM. After writing instruction, Y address is increased by 1 automatically. Read display data H H Read data Reads data (DB0: 7) from display data RAM to the data bus. 18 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 DISPLAY ON / OFF RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 1 1 D The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1. SET ADDRESS (Y ADDRESS) S R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Y address (AC0 - AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data. SET PAGE (X ADDRESS) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 AC2 AC1 AC0 X address(AC0 - AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set. DISPLAY START LINE (Z ADDRESS) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 Z address (AC0 - AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others(1/32 - 1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. 19 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD STATUS READ RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY 0 ON/OFF RESET 0 0 0 0 • BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. • ON/OFF When ON/OFF is 1, the display is OFF. When ON/OFF is 0, the display is ON. • RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition. WRITE DISPLAY DATA RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Writes data (D0 - D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. READ DISPLAY DATA RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Reads data (D0 - D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically. 20 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 APPLICATION CIRCUIT 1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT R1 R2 From MPU V0 V5 V1 V4 VEE V0R , V0L V5R , V5L V1R , V1L V4R , V4L VEE S6B0107 VDD VDD SHL FS MS PCLK2 SD2 DS1 VSS DIO1 DIO2 M FRM CLK1 CLK2 CL2 - Open Open M FRM CLK1 CLK2 CL2 S6B0108 VDD ADC VDD V0R , V0L V5R , V5L V2R , V2L V3R , V3L VEE1 , VEE2 VSS V0 V5 V2 V3 VEE VSS S64 S1 SEG1 COM1 C1 DB7 RSTB CS1B CS2B CS3 R/W RS E DB0 C CR R - SEG64 LCD COM64 C64 VDD V0 R1 V1 R1 V2 R2 V3 R1 V4 R1 V5 VEE 21 S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD TIMING DIAGRAM (1/64 DUTY) CLK1 1 2 3 48 49 CLK2 64 Input 1 2 3 64 1 2 3 64 1 CL FRM 1 Frame 1 Frame M V0 V1 C1 V4 V4 V5 V1 Common C2 V4 V5 V0 V1 V1 V4 V4 V5 V0 V0 V1 V1 C64 V4 V4 V5 V0 V2 S1 V3 V5 V0 Segment V2 V3 V2 S64 V2 V3 V3 V5 22 64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 LCD PANEL INTERFACE APPLICATION CIRCUIT S6B0108 No. 1 S1 ..... S64 ..... S6B0107 (master) C1 C2 C3 Cf Rf S6B0108 No. 2 S1 ..... S64 ..... ..... S6B0108 No. 8 S1 ..... S64 ..... COM1 COM2 COM3 CR R C64 COM64 LCD Panel C1 C2 C3 (128 × 512dots) COM65 COM66 COM67 C64 S6B0107 (slave) COM128 ..... S1 ..... S64 No. 9 S6B0108 ..... S1 ..... S64 No. 10 S6B0108 ..... ..... S1 ..... S64 No. 16 S6B0108 23