TI UCC3808N-1

 SLUS168D – APRIL 1999 – REVISED AUGUST 2002
D Dual Output Drive Stages in Push-Pull
D
D
D
D
D
D
D
D OR N PACKAGE
(TOP VIEW)
Configuration
130-µA Typical Starting Current
1-mA Typical Run Current
Operation to 1-MHz
Internal Soft Start
On Chip Error Amplifier With 2-MHz Gain
Bandwidth Product
On Chip VDD Clamping
Output Drive Stages Capable Of 500-mA
Peak Source Current, 1-A Peak Sink Current
COMP
FB
CS
RC
1
8
2
7
3
6
4
5
VDD
OUTA
OUTB
GND
PW PACKAGE
(TOP VIEW)
1
2
3
4
OUTA
VDD
COMP
FB
description
8
7
6
5
OUTB
GND
RC
CS
The UCC3808 is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The UCC3808
contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency current-mode switching
power supplies with minimal external parts count.
The UCC3808 dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 60 ns to 200 ns
depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than
50%. (continued)
block diagram
FB
COMP
CS
2
1
3
22 k Ω
OVERCURRENT
COMPARATOR
PEAK CURRENT
COMPARATOR
8
VDD
7
OUTA
6
OUTB
5
GND
14 V
0.75 V
0.5 V
2.0 V
2.2 V
VDD OK
OSCILLATOR
S
Q
PWM
LATCH
R
1.2R
VDD–1 V
Q
S
S
Q
Q
R
R
T
Q
PWM
COMPARATOR
VDD
0.5 V
R
SOFT START
VOLTAGE
REFERENCE
SLOPE = 1 V/ms
4
Note: Pinout shown is for SOIC and PDIP packages. TSSOP pinout is different.
RC
UDG-02116
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
! " #$%! " &$'(# ! ) !%*
)$#!" # ! "&%## !" &% !+% !%" %, " "!$%!"
"! ) ) - !.* )$#! &#%""/ )%" ! %#%"" (. #($)%
!%"!/ (( & %!%"*
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1
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
description (continued)
The UCC3808 family offers a variety of package temperature range options, and choice of undervoltage lockout
levels. The family has UVLO thresholds and hysteresis options for off-line and battery powered systems. Thresholds
are shown in the table below.
Table 1.
Part Number
Turn on Threshold
Turn off Threshold
UCCx808–1
12.5 V
8.3 V
UCCx808–2
4.3 V
4.1 V
ORDERING INFORMATION
Packaged Devices
TA = TJ
40°C to 85°C
–40°C
UVLO Option
SOIC (D)
PDIP (N)
TSSOP (PW)
12.5 V/8.3 V
UCC2808D–1
UCC2808N–1
UCC2808PW–1
4.3 V/4.1 V
UCC2808D–2
UCC2808N–2
UCC2808PW–2
12.5 V/8.3 V
UCC3808D–1
UCC3808N–1
UCC3808PW–1
0°C to 70°C
4.3 V/4.1 V
UCC3808D–2
UCC3808N–2
UCC3808PW–2
† D (SOIC–8) and PW (TSSOP–8) packages are available taped and reeled. Add TR suffix to device type (e.g.
UCC3808DTR–1) to order quantities of 2500 devices per reel for SOIC-8 and 2000 devices per reel for TSSOP-8.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage (IDD ≤ 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OUTA/OUTB source current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 A
OUTA/OUTB sink current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A
Analog inputs (FB, CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD+0.3 V, not to exceed 6 V
Power dissipation at TA = 25°C (N Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Power dissipation at TA = 25°C (D Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
Power dissipation at TA = 25°C (PW Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power Supply Control Data Book (TI Literature
Number SLUD003) for thermal limitations and considerations of packages.
2
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SLUS168D – APRIL 1999 – REVISED AUGUST 2002
electrical characteristics, TA = 0°C to 70°C for the UCC3808–x, –40°C to 85°C for the UCC2808–x and –55°C
to 125°C for the UCC1808–x, VDD = 10 V (See Note 6), 1 µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF,
TA = TJ, (unless otherwise specified)
oscillator section
PARAMETER
TEST CONDITIONS
Oscillator frequency
Oscillator amplitude/VDD
See Note 1
MIN
TYP
MAX
UNITS
175
194
213
kHz
0.44
0.5
0.56
V/V
error amplifier section
PARAMETER
Input voltage
TEST CONDITIONS
COMP = 2 V
MIN
1.95
Input bias current
–1
Open loop voltage gain
60
COMP sink current
FB = 2.2 V,
COMP = 1 V
COMP source current
FB = 1.3 V,
COMP = 3.5 V
TYP
2
MAX
UNITS
2.05
V
1
µA
80
dB
0.3
2.5
mA
–0.2
–0.5
mA
PWM section
PARAMETER
TEST CONDITIONS
Maximum duty cycle
Measured at OUTA or OUTB
Minimum duty cycle
COMP = 0 V
MIN
48%
TYP
49%
MAX
UNITS
50%
0%
current sense section
PARAMETER
TEST CONDITIONS
Gain
See Note 2
Maximum input signal
COMP = 5 V,
See Note 3
CS to output delay
COMP = 3.5 V,
CS from 0 to 600 mV
CS source current
TYP
MAX
CS = 0 V
UNITS
1.9
2.2
2.5
0.45
0.5
0.55
V
100
200
ns
0.7
0.75
0.8
V
0.35
0.8
1.2
V
–200
Over current threshold
COMP to CS offset
MIN
V/V
nA
NOTES: 1. Measured at RC. Signal amplitude tracks VDD.
DV
COMP , 0 v V
v 0.4 V,
2. Gain is defined by: A +
CS
DV
CS
3. Parameter measured at trip point of latch with FB at 0V.
4. Start threshold and zener shunt threshold track one another.
5. For UCCx808–1, set VDD above the start threshold before setting at 10 V.
6. Does not include current in the external oscillator network.
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3
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
electrical characteristics, TA = 0°C to 70°C for the UCC3808–x, –40°C to 85°C for the UCC2808–x and –55°C
to 125°C for the UCC1808–x, VDD = 10 V (See Note 6), 1 µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF,
TA = TJ, (unless otherwise specified)
output section
PARAMETER
TEST CONDITIONS
OUT low level
I = 100 mA
OUT high level
I = –50 mA,
Rise time
Fall time
MIN
TYP
MAX
UNITS
0.5
1
V
0.5
1
V
CL = 1 nF
25
60
ns
CL = 1 nF
25
60
ns
VDD – OUT
undervoltage lockout section
PARAMETER
TEST CONDITIONS
UCCx808–1,
Start threshold
Minim m operating voltage
Minimum
oltage after start
H steresis
Hysteresis
MIN
See Note 6
TYP
MAX
UNITS
11.5
12.5
13.5
V
UCCx808–2
4.1
4.3
4.5
V
UCCx808–1
7.6
8.3
9
V
UCCx808–2
3.9
4.1
4.3
V
UCCx808–1
3.5
4.2
5.1
V
UCCx808–2
0.1
0.2
0.3
V
soft start section
PARAMETER
COMP rise time
TEST CONDITIONS
FB = 1.8 V,
MIN
rise from 0.5 V to 4 V
TYP
3.5
MAX
20
UNITS
ms
overall section
PARAMETER
TEST CONDITIONS
Startup current
VDD < start threshold
Operating supply current
FB = 0 V,
CS = 0 V,
VDD zener shunt voltage
IDD = 10 mA,
See Note 4
MIN
See Note 5 and 6
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13
MAX
UNITS
260
µA
1
2
mA
14
15
V
130
NOTES: 1. Measured at RC. Signal amplitude tracks VDD.
DV
COMP , 0 v V
v 0.4 V,
2. Gain is defined by: A +
CS
DV
CS
3. Parameter measured at trip point of latch with FB at 0V.
4. Start threshold and zener shunt threshold track one another.
5. For UCCx808–1, set VDD above the start threshold before setting at 10 V.
6. Does not include current in the external oscillator network.
4
TYP
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
pin descriptions
COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the
UCC3808 is a true low-output impedance, 2-MHz operational amplifier. As such, the COMP pin can both source and
sink current. However, the error amplifier is internally current limited, so that zero duty cycle can be externally forced
by pulling COMP to GND.
The UCC3808 family features built-in full cycle soft start. Soft start is implemented as a clamp on the maximum COMP
voltage.
CS: The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended
for fault sensing. Exceeding the overcurrent threshold will cause a soft start cycle.
FB: The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray
capacitance as small as possible.
GND: Reference ground and power ground for all functions. Due to high currents, and high frequency operation of
the UCC3808, a low impedance circuit board ground plane is highly recommended.
OUTA and OUTB: Alternating high current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak source current, and 1-A peak sink current.
The output stages switch at half the oscillator frequency, in a push/pull configuration. When the voltage on the RC
pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two
outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at the same
time. This dead time is typically 60 ns to 200 ns and depends upon the values of the timing capacitor and resistor.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external
schottky clamp diodes are not required.
RC: The oscillator programming pin. The UCC3808’s oscillator tracks VDD and GND internally, so that variations in
power supply rails minimally affect frequency stability. Figure 1 shows the oscillator block diagram.
Only two components are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor (tied
to the RC and GND). The approximate oscillator frequency is determined by the simple formula:
f
OSCILLATOR
+ 1.41
RC
where frequency is in hertz, resistance in ohms, and capacitance in farads. The recommended range of timing
resistors is between 10 kΩ and 200 kΩ and range of timing capacitors is between 100 pF and 1000 pF. Timing resistors
less than 10 kΩ should be avoided.
For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from VDD
as short as possible, and the leads between timing components and RC as short as possible. Separate ground and
VDD traces to the external timing network are encouraged.
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply current
will be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total VDD current
is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average OUT current can be calculated from:
I
OUT
+ Qg
F, where F is frequency
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with
an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
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5
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
pin descriptions (continued)
UDG–97009
NOTE: The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but
both stages are off during the RC fall time. The output stages switch a ½ the oscillator frequency, with guaranteed duty
cycle of < 50% for both outputs.
Figure 1. Block Diagram for Oscillator
APPLICATION INFORMATION
A 200-kHz push-pull application circuit with a full wave rectifier is shown in Figure 2. The output, VO, provides 5 V
at 75 W maximum and is electrically isolated from the input. Since the UCC3808 is a peak current mode controller
the 2N2222A emitter following amplifier (buffers the CT waveform) provides slope compensation which is necessary
for duty ratios greater than 50%. Capacitor decoupling is very important with a single ground IC controller, and a 1
µF is suggested as close to the IC as possible. The controller supply is a series RC for start-up, paralleled with a bias
winding on the output inductor used in steady state operation.
Isolation is provided by an optocoupler with regulation done on the secondary side using the UC3965 Precision
Reference with Low Offset Error Amplifier. Small signal compensation with tight voltage regulation is achieved using
this part on the secondary side. Many choices exist for the output inductor depending on cost, volume, and
mechanicall strength. Several design options are iron powder, molypermalloy (MPP), or a ferrite core with an air gap
as shown here. The main power transformer is a low profile design, EFD size 25, using Magnetics Inc. P material
which is a good choice at this frequency and temperature. The input voltage may range from 36 V dc to 72 V dc.
6
www.ti.com
ER28
8:2
32CTQ030
NS1
NP1
NS2
EF25 7µH
680 µF
0.01 µF
VIN
36 V TO 72 V
–
LOOP B
+
4700 µF
0.47 µF
1000 pF
–
BYV
28–200
62 Ω
62 Ω
BYV
28–200
1000 pF
200 Ω
LOOP A
COMP
51 kΩ
1/4 W
19.1 kΩ
IRF640
IRF640
4700 pF 20 kΩ
12
10 Ω
2.2 Ω
470 pF
DF02SGICT
2.2 Ω
1 mH
3
10 µF
0.1 µF
2
19.1 kΩ
2 kΩ
0.2 Ω
20 kΩ
VDD
8
330 pF
OUTA OUTB GND
7
6
PRIMARY
GROUND
5
UCC3808D-1
1
2
COMP FB
3
CS
240 Ω
4
RC
RC
4.99 kΩ
86.6 kΩ
CURRENT
SENSE
4.99 kΩ
2N2907
4
H11A1
U3
3
5
2
6
1
20 kΩ
330 pF
432 Ω
0.1 µF
0.01 µF
1 kV
UDG-00142
7
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
2.80 kΩ
1 TL431
0.1 µF
APPLICATION INFORMATION
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Figure 2. Typical Application Diagram: 48-V In, 5-V, 50-W Output
NP2
VO
5 V 50 W
+
SLUS168D – APRIL 1999 – REVISED AUGUST 2002
APPLICATION INFORMATION
FREQUENCY
vs
TIMING RESISTOR
IDD
vs
OSCILLATOR FREQUENCY
CS OFFSET
vs
TEMPERATURE
1.2
1000
14
C
CT=100pF
10
100
IDD – mA
Frequency – kHz
CT=330pF
CT=220pF
IDD With 1 nF
Load
8
6
0.6
4
IDD Without
Load
CT=560pF
2
0
0.2
0
0
0
50
100
150
200
250
0
200
600
400
800
1000
1200
–55
–35
–15
5
25
45
RT – Timing Resistor – kΩ
Oscillator Frequency – kHz
Temperature – °C
Figure 3
Figure 4
Figure 5
ERROR AMPLIFIER GAIN AND PHASE
RESPONSE
vs
FREQUENCY
DEAD TIME
vs
TIMING RESISTOR
90
180
80
160
120
CT=1000pF
140
60
120
Phase
50
100
40
80
30
60
20
Dead Time – ns
70
Phase Margin - Degrees
100
Gain dB
0.8
CT=1000pF
CT=820pF
CT=820pF
80
CT=560pF
60
40
CT=100pF
CT=220pF
CT=330pF
40
20
Gain
10
20
0
8
1.0
0.4
10
0
1
COMP – CS Offset – V
VDD = 10 V, T = 25
12
100
10000
1000000
0
0
20
40
60
Frequency – Hz
RT – Timing Resistor – kΩ
Figure 6
Figure 7
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80
100
65
85
105
125
PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC2808D-1
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-1
UCC2808D-1G4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-1
UCC2808D-2
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-2
UCC2808D-2G4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-2
UCC2808DTR-1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-1
UCC2808DTR-1G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-1
UCC2808DTR-2
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-2
UCC2808DTR-2G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
2808-2
UCC2808N-1
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UCC2808N-1
UCC2808N-1G4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UCC2808N-1
UCC2808N-2
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UCC2808N-2
UCC2808N-2G4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UCC2808N-2
UCC3808D-1
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3808-1
UCC3808D-1G4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3808-1
UCC3808D-2
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3808-2
UCC3808D-2G4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3808-2
UCC3808DTR-1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(3808-1 ~ UCC3808)
D-1
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC3808DTR-1G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(3808-1 ~ UCC3808)
D-1
UCC3808DTR-2
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3808-2
UCC3808DTR-2G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3808-2
UCC3808N-1
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UCC3808N-1
UCC3808N-1G4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UCC3808N-1
UCC3808N-2
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UCC3808N-2
UCC3808N-2G4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UCC3808N-2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC3808-2 :
• Military: UCC1808-2
NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC2808DTR-1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UCC2808DTR-2
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UCC3808DTR-1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UCC3808DTR-2
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC2808DTR-1
SOIC
D
8
2500
340.5
338.1
20.6
UCC2808DTR-2
SOIC
D
8
2500
340.5
338.1
20.6
UCC3808DTR-1
SOIC
D
8
2500
340.5
338.1
20.6
UCC3808DTR-2
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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