UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 ADVANCED REGULATING PULSE WIDTH MODULATORS FEATURES • • • • DESCRIPTION Complete PWM Power Control Circuitry Uncommitted Outputs for Single-Ended or Push-Pull Applications Low Standby Current . . . 8 mA Typical Interchangeable With SG1524, SG2524 and SG3524, Respectively The UC1524, UC2524 and UC3524 incorporate on a single monolithic chip all the functions required for the construction of regulating power supplies, inverters or switching regulators. They can also be used as the control element for high-power-output applications. The UC1524 family was designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless voltage doublers and polarity converter applications employing fixedfrequency, pulse-width modulation techniques. The dual alternating outputs allow either single-ended or push-pull applications. Each device includes an on-chip reference, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted output transistors, a high-gain comparator, and current-limiting and shut-down circuitry. The UC1524 is characterized for operation over the full military temperature range of –55°C to 125°C. The UC2524 and UC3524 are designed for operation from –25°C to 85°C and 0°C to 70°C, respectively. BLOCK DIAGRAM VIN 15 VREF OSC OUT 16 3 +5V TO ALL REFERENCE INTERNAL 12 +5V CA Q RT 6 CT 7 R OSC Q 11 EA 13 CB 14 EB 5 –SENSE 4 +SENSE (RAMP) +5V INV INPUT +5V 1 COMPARATOR – NI INPUT GROUND 2 EA + 8 10k CL 1k 10 9 SHUTDOWN COMPENSATION Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 CONNECTION DIAGRAM VREF VIN EB CB CA EA S/D COMP 16 15 14 13 12 11 10 9 REFERENCE S/D REGULATOR ERROR CURRENT AMP AMP 2 3 – + + – 1 OSCILLATOR 4 5 CL CL INV INPUT NON INV OSC OUT INPUT SENSE(+) SENSE (–-) 6 RT 7 8 CT GND ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) UNIT VCC Supply voltage (1) (2) 40 V Collector output current 50 mA Current through CT terminalg –50 mA Power dissipation (1) (2) (3) 100 mA Reference output current TA = 25°C (3) 1000 mW TC = 25°C (3) 2000 mW Operating junction temperature range –55°C to 150°C Storage temperature range –65°C to +150°C All voltage values are with respect to the ground terminal, pin 8. The reference regulator may be bypassed for operation from a fixed 5 V supply by connecting the VCC and reference output pins both to the supply voltage. In this configuration the maximum supply voltage is 6 V. Consult packaging section of data book for thermal limitations and considerations of package. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC MAX UNIT Supply voltage 8 40 V Reference output current 0 20 mA –0.03 –2 mA Current through CT terminal RT Timing resistor CT Timing capacitor Operating ambient temperature range 2 NOM 1.8 100 kΩ 0.001 0.1 µF UC1524 –55 125 UC2524 –25 85 UC3524 0 70 °C UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 ELECTRICAL CHARACTERISTICS these specifications apply for TA = –55°C to 125°C for the UC1524, –25°C to 85°C for the UC2524, and 0°C to 70°C for the UC3524, VIN = 20 V, and f = 20 kHz, TA = TJ, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UC1524/UC2524 UC3524 UNIT MIN TYP MAX MIN TYP MAX 4.8 5.0 5.2 4.6 5.0 5.4 V REFERENCE SECTION Output voltage Line regulation VIN = 8 V to 40 V 10 20 10 30 mV Load regulation IL = 0 mA to 20 mA 20 50 20 50 mV Ripple rejection f = 120 Hz, TJ = 25°C 66 Short circuit current limit VREF = 0, TJ = 25°C Temperature stability Over operating temperature range Long term stability TJ = 125°C, t = 1000 Hrs 66 100 0.3% dB 100 1% 0.3% mA 1% 20 20 mV kHz OSCILLATOR SECTION Maximum frequency CT = 1 nF, RT = 2 kΩ 300 300 Initial accuracy RT and CT constant 5% 5% Voltage stability VIN = 8 V to 40 V, TJ = 25°C Temperature stability Over operating temperature range Output amplitude Pin 3, TJ = 25°C 3.5 3.5 V Output pulse width CT = 0.01 mfd, TJ = 25°C 0.5 0.5 µs Input offset voltage VCM = 2.5 V 0.5 5 2 10 mV Input bias current VCM = 2.5 V 2 10 2 10 µA 1% 1% 5% 5% ERROR AMPLIFIER SECTION Open loop voltage gain 72 80 1.8 60 3.4 80 1.8 dB Common mode voltage TJ = 25°C 3.4 Common mode rejection ratio TJ = 25°C Small signal bandwidth AV = 0 dB, TJ = 25°C Output voltage TJ = 25°C 0.5 3.8 0.5 3.8 % Each output on 0% 45% 0% 45% V 70 70 dB 3 3 MHz V COMPARATOR SECTION Duty-cycle Input threshold Zero duty-cycle Maximum duty-cycle Input bias current 1 1 3.5 3.5 1 1 V µA CURRENT LIMITING SECTION Sense voltage Pin 9 = 2 V with error amplifier set for maximum out, TJ = 25°C 190 Sense voltage T.C. Common mode voltage 200 210 180 0.2 TJ = –55°C to 85°C for the –1 V to 1 V limit TJ = 25°C 200 220 0.2 –1 1 –0.3 1 –1 mV mV/°C 1 V OUTPUT SECTION (EACH OUTPUT) Collector-emitter voltage 40 40 V Collector leakage current VCE = 40 V 0.1 50 0.1 50 µA Saturation voltage IC = 50 mA 1 2 1 2 V Emitter output voltage VIN = 20 V Rise Time RC = 2 kΩ, TJ = 25°C 0.2 Fall Time RC = 2 kΩ, TJ = 25°C 0.1 Total standby current (Note) VIN = 40 V 17 18 8 17 18 V 0.2 µs µs 0.1 10 8 10 mA 3 UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 PRINCIPLES OF OPERATION The UC1524 is a fixed-frequency pulse-width-modulation voltage regulator control circuit. The regulator operates at a frequency that is programmed by one timing resistor (RT), and one timing capacitor (CT), RT establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing linear control of the output pulse width by the error amplifier. The UC1524 contains an on-board 5 V regulator that serves as a reference as well as powering the UC1524’s internal control circuitry and is also useful in supplying external support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common-mode range of the error amplifier or an external reference may be used. The power supply output is sensed by a second resistor divider network to generate a feedback signal to the error amplifier. The amplifier output voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator is then steered to the appropriate output pass transistor (Q1 or Q2) by the pulse-steering 4 flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure both outputs are never on simultaneously during the transition times. The width of the blanking pulse is controlled by the valve of CT. The outputs may be applied in a push-pull configuration in which their frequency is half that of the base oscillator Note that for buck regulator topologies, the two outputs can be wire-ORed for an effective 0-90% duty cycle range. With this connection, the output frequency is the same as the oscillator frequency. The output of the error amplifier shares a common input to the comparator with the current limiting and shutdown circuitry and can be overridden by signals from either of these inputs. This common point is also available externally and may be employed to control the gain of, or to compensate, the error amplifier or to provide additional control to the regulator. UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS OPEN-LOOP VOLTRAGE AMPLIFICATION OF ERROR AMPLIFIER vs FREQUENCY OSCILLATOR FREQUENCY vs TIMING COMPONENTS 90 1M 80 RF = 1M 60 RF = 300 k 50 RF = 100 k 40 RF = 30 k 30 20 10 0 VIN = 20 V TJ = 25 C CT = 0.003 mF 70 CT = 0.01 mF 100 k 10 k CT = 0.003 mF 1k RF is Resistance From Pin 9 to Ground CT = 0.1 mF NOTE: Value of RF Below 30 kW Will Began to Limit Maximum Duty-Cycle −10 100 100 1k 1M 10 k 100 k f − Frequency − Hz 10 M 1 50 5 10 20 RT − Timing Resistor − kW Figure 2. OUTPUT DEAD TIME vs TIMING CAPACITANCE VALUE OUTPUT SATURATION VOLTAGE vs LOAD CURRENT 100 4 VIN = 20 V TJ = 25 C VCC = 20 V 3.5 Collector-To-Emitter Voltage − V 4 1 0.4 3 2.5 TJ = 125 C 2 TJ = 25 C 1.5 TJ = −55 C 1 0.5 NOTE: Dead Time = Blanking Pulse Width Plus Outplay Delay 0.1 0.001 2 Figure 1. 10 Output Dead Time − µs CT = 0.001 mF VIN = 20 V TJ = 25 C Osscilator Frequency − Hz Open-Loop Voltage Amplification − dB RF = 0 0.004 0.01 CT − Capacitance − Figure 3. 0.04 F 0.1 0 20 40 60 80 100 Load Current − mA Figure 4. 5 UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 APPLICATION INFORMATION OSCILLATOR SYNCHRONOUS OPERATIONS The oscillator controls the frequency of the UC1524 and is programmed by RT and CT according to the approximate formula: 1.18 f R C T T (1) When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration RT CT must be selected for a clock period slightly greater than that of the external clock. where RT is in kΩ CT is in µF f is in kHz If two or more UC1524 regulators are to operated synchronously, all oscillator output terminals should be tied together, all CT terminals connected to single timing capacitor, and the timing resistor connected to a single RT, terminal. Practical values of CT fall between 1 nF and 100 nF. Practical values of RT fall between 1.8 kΩ and 100 kΩ. This results in a frequency range typically from 120 Hz to 500 kHz. REF 16 1N916 COMP 9 GND 8 5k BLANKING The output pulse of the oscillator is used as a blanking pulse at the output. This pulse width is controlled by the value of CT. If small values of CT are required for frequency control, the oscillator output pulse width may still be increased by applying a shunt capacitance of up to 100 pF from pin 3 to ground. If still greater dead-time is required, it should be accomplished by limiting the maximum duty cycle by clamping the output of the error amplifier. This can easily be done with the circuit in Figure 5. Figure 5. Error Amplifier Clamp The other RT terminals can be left open or shorted to VREF. Minimum lead lengths should be used between the CT terminals. V+ +5V, 5A +28 V PIC600 5k R2 5k 15 1 12 2 11 16 13 5k 0.1 mF 5k 3k 6 0.02 mF UC1524 14 7 4 3 5 10 9 500 mF 1.5 k 0.001 mF 9 50 k V− 0.1 Figure 6. Single-Ended LC Switching Regulator Circuit 6 UC1524 UC2524 UC3524 www.ti.com SLUS180E – NOVEMBER 1999 – REVISED OCTOBER 2005 V+ +28 V 15 VIN 5k 1k 1W UC1524 5k 1 5k 2 INV INPUT CA NON INV INPUT EA 12 1k 1W 2N4150 5k 0.1 mF 16 2k 6 0.1 mF 7 3 10 CB VREF RT EB CT CLSENSE(+) OSC OUT CLSENSE(−) COMP SD 5V 5A 11 13 100 20T 5T 100 20T 5T 14 + 1500 mF 2N4150 4 0.1 k 5 9 0.001 mF 500 mF GND 8 50 k Figure 7. Push-Pull Transformer Coupled Circuit 2k 1W IS 2k 1W VIN 15 Osc. OUT VREF 16 12 13 11 5 4 UC1524 3 8 6 7 2 RAMP VIN 8-40 V 1 N.I. INPUT 9 INV. INPUT 2k 10 COMP 2k 4 SHUT Down OUTPUT CURRENT LIMET 10 k 10 k 0.1 R1 1k C1 1k Figure 8. Open Loop Test Circuit 7 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UC1524J OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 UC1524J/80937 OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 UC1524J883B OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 UC2524DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2524DW UC2524DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2524DW UC2524J OBSOLETE CDIP J 16 TBD Call TI Call TI -25 to 85 UC2524N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 UC2524N UC2524NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 UC2524N UC3524-W ACTIVE WAFERSALE YS 0 TBD Call TI Call TI UC3524D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3524D UC3524DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3524D UC3524DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3524DW UC3524DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3524DW UC3524DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3524DW UC3524DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3524DW UC3524J OBSOLETE CDIP J 16 TBD Call TI Call TI 0 to 70 UC3524N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3524N UC3524NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3524N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF UC1524, UC3524 : • Catalog: UC3524 • Military: UC1524 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UC3524DWTR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC3524DWTR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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