TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 4-17V 3A Step-Down Converter with DCS-ControlTM Check for Samples: TLV62130, TLV62130A FEATURES DESCRIPTION • • • • • • • • • • • • • • • The TLV62130 is an easy to use synchronous step down DC-DC converter optimized for applications with high power density. A high switching frequency of typically 2.5MHz allows the use of small inductors and provides fast transient response as well as high output voltage accuracy by utilization of the DCSControl™ topology. 1 2 DCS-Control ™Topology Input Voltage Range: 4 to 17V Up to 3A Output Current Adjustable Output Voltage from 0.9 to 5V Pin-Selectable Output Voltage (nominal, + 5%) Programmable Soft Start and Tracking Seamless Power Save Mode Transition Quiescent Current of 19µA (typ.) Selectable Operating Frequency Power Good Output 100% Duty Cycle Mode Short Circuit Protection Over Temperature Protection For Improved Feature Set, see TPS62130 Available in a 3 × 3 mm, QFN-16 Package • • • The output voltage startup ramp is controlled by the soft-start pin, which allows operation as either a standalone power supply or in tracking configurations. Power sequencing is also possible by configuring the Enable and open-drain Power Good pins. In Power Save Mode, the devices show quiescent current of about 19μA from VIN. Power Save Mode, entered automatically and seamlessly if load is small, maintains high efficiency over the entire load range. In Shutdown Mode, the device is turned off and shutdown current consumption is less than 2μA. APPLICATIONS • • With its wide operating input voltage range of 4V to 17V, the devices are ideally suited for systems powered from either a Li-Ion or other batteries as well as from 12V intermediate power rails. It supports up to 3A continuous output current at output voltages between 0.9V and 5V (with 100% duty cycle mode). Standard 12V Rail Supplies POL Supply from Single or Multiple Li-Ion Battery Embedded Systems LDO replacement Mobile PC's, Tablet, Modems, Cameras The device is packaged in a 16-pin QFN package measuring 3 × 3 mm (RGT). spacing 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN PG 3.3V / 3A 100k 750k 22uF TLV62130 SS/TR 3.3nF FB DEF AGND FSW PGND 240k Figure 1. Typical Application and Efficiency 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCS-Control is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA -40°C to 85°C (1) (2) (3) PART NUMBER (2) PACKAGE adjustable TLV62130 16-Pin QFN TLV62130RGT VUBI adjustable TLV62130A (3) 16-Pin QFN TLV62130ARGT VUNI OUTPUT VOLTAGE ORDERING PACKAGE MARKING For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet. Contact the factory to check availability of other fixed output voltage versions. While TLV62130 has PG=High Z, TLV62130A features PG=Low, when device is in shutdown through EN, UVLO or Thermal Shutdown. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Pin voltage range (2) MIN MAX AVIN, PVIN –0.3 20 EN, SS/TR –0.3 VIN+0.3 SW –0.3 VIN+0.3 DEF, FSW, FB, PG, VOS –0.3 7 V 10 mA Power Good sink current PG Temperature range ESD rating (3) (1) (2) (3) Operating junction temperature range, TJ –40 125 Storage temperature range, Tstg –65 150 HBM Human body model CDM Charge device model UNIT V V °C 2 kV 0.5 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TLV62130 THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance θJC(TOP) Junction-to-case(top) thermal resistance θJB Junction-to-board thermal resistance 11 ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 10 θJC(BOTTOM) Junction-to-case(bottom) thermal resistance 3.5 (1) UNITS RGT 16 PINS 29.1 15 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS MIN Supply Voltage, VIN (at AVIN and PVIN) 4 TYP MAX UNIT 17 V Operating free air temperature, TA –40 85 °C Operating junction temperature, TJ –40 125 °C 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=12V and TA=25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range (1) 17 V IQ Operating quiescent current EN=High, IOUT=0mA, device not switching 19 27 µA ISD Shutdown current (2) EN=Low 1.5 4 µA 2.7 2.8 VUVLO TSD 4 Falling Input Voltage Undervoltage lockout threshold 2.6 Hysteresis 200 Thermal shutdown temperature 160 Thermal shutdown hysteresis V mV °C 20 CONTROL (EN, DEF, FSW, SS/TR, PG) VH High level input threshold voltage (EN, DEF, FSW) VL Low level input threshold voltage (EN, DEF, FSW) ILKG Input leakage current (EN, DEF, FSW) VTH_PG Power good threshold voltage VOL_PG Power good output low IPG=-2mA ILKG_PG Input leakage current (PG) VPG=1.8V ISS/TR SS/TR pin source current 0.9 EN=VIN or GND; DEF, FSW=VOUT or GND V 0.3 V 0.01 1 µA Rising (%VOUT) 92 95 98 Falling (%VOUT) 87 90 94 0.07 0.3 1 400 nA 2.5 2.7 µA 2.3 % V POWER SWITCH RDS(ON) ILIMF High-side MOSFET ON-resistance VIN≥6V Low-side MOSFET ON-resistance VIN≥6V High-side MOSFET forward current limit (3) VIN =12V, TA= 25°C 3.6 90 mΩ 40 mΩ 4.2 A OUTPUT VREF Internal reference voltage (4) ILKG_FB Input leakage current (FB) VFB=0.8V Output voltage range VIN ≥ VOUT DEF (Output voltage programming) DEF=0 (GND) VOUT DEF=1 (VOUT) VOUT+5% VOUT (1) (2) (3) (4) (5) (6) 0.8 1 0.9 V 100 nA 5.0 V Initial output voltage accuracy (5) PWM mode operation, VIN ≥ VOUT +1V Load regulation (6) VIN=12V, VOUT=3.3V, PWM mode operation 0.05 %/A Line regulation (6) 4V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM mode operation 0.02 %/V –2.5 2.5 % The device is still functional down to Under Voltage Lockout (see parameter VUVLO). Current into AVIN+PVIN pin. This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short Circuit Protection section). This is the voltage regulated at the FB pin. This is the accuracy provided by the device itself (line and load regulation effects are not included). Line and load regulation depend on external component selection and layout (see Figure 16 and Figure 17). Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 3 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com DEVICE INFORMATION SW 3 PG 4 PGND VOS EN 13 Exposed Thermal Pad 5 6 7 8 DEF 2 14 FSW SW 15 AGND 1 16 FB SW PGND RGT PACKAGE (TOP VIEW) 12 PVIN 11 PVIN 10 AVIN 9 SS/TR Terminal Functions PIN (1) NAME NO. I/O DESCRIPTION SW 1,2,3 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. PG 4 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires pull-up resistor; goes high impedance, when device is switched off) FB 5 I Voltage feedback. Connect resistive voltage divider to this pin. AGND 6 FSW 7 I Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz (2) for typical operation) (3) DEF 8 I Output Voltage Scaling (Low = nominal, High = nominal + 5%) (3) SS/TR 9 I Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing. AVIN 10 I Supply voltage for control circuitry. Connect to same source as PVIN. PVIN 11,12 I Supply voltage for power stage. Connect to same source as AVIN. 13 I Enable input (High = enabled, Low = disabled) (3) 14 I Output voltage sense pin and connection for the control loop circuitry. EN VOS PGND 15,16 Exposed Thermal Pad (1) (2) (3) (4) 4 Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane. Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane (4). Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability. For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections. Connect FSW to VOUT or PG in this case. An internal pull-down resistor keeps logic level low, if pin is floating. See recommended layout shown in Figure 40. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 FUNCTIONAL BLOCK DIAGRAM PG Soft start Thermal Shtdwn UVLO AVIN PVIN PVIN PG control HS lim comp EN* SW SS/TR power control control logic gate drive SW DEF* SW FSW* comp LS lim VOS direct control & compensation ramp _ FB comparator + timer tON error amplifier DCS - ControlTM * This pin is connected to a pull down resistor internally (see Detailed Description section). AGND PGND PGND Figure 2. TLV62130 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 5 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION List of Components REFERENCE DESCRIPTION IC 17V, 3A Step-Down Converter, QFN MANUFACTURER L1 2.2µH, 0.165 x 0.165 in Cin 10µF, 25V, Ceramic Standard Cout 22µF, 6.3V, Ceramic Standard Cs 3300pF, 25V, Ceramic R1 depending on Vout R2 depending on Vout R3 100kΩ, Chip, 0603, 1/16W, 1% TLV62130RGT, Texas Instruments XFL4020-222MEB, Coilcraft Standard spacing VIN L1 CIN PVIN SW AVIN VOS EN PG FB VOUT R3 R1 COUT TLV62130 SS/TR CSS FB PG DEF AGND FSW PGND R2 Figure 3. Measurement Setup TYPICAL CHARACTERISTICS Table of Graphs DESCRIPTION FIGURE Efficiency vs Output Current, vs Input Voltage 4 - 15 Output voltage vs Output current (Load regulation), vs Input Voltage (Line regulation) 16, 17 vs Input Voltage 18 vs Output Current 19 Quiescent Current vs Input Voltage 20 Shutdown Current vs Input Voltage Power FET RDS(on) vs Input Voltage (High-Side, Low-Side) Output Voltage Ripple vs output Current Maximum Output Current vs Input Voltage Power Supply Rejection Ratio (PSSR) vs Frequency Switching Frequency 21 24 25 26, 27 PWM-PSM-PWM Mode Transition Waveforms Maximum Ambient Temperature 6 Submit Documentation Feedback 22, 23 28 Load Transient Response 29 - 31 Startup 32, 33 Typical PWM Mode Operation 34 Typical Power Save Mode Operation 35 vs Load Current 36 vs Power Dissipation 37 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 70.0 VIN=12V VIN=17V Efficiency (%) Efficiency (%) 80.0 60.0 50.0 40.0 30.0 IOUT=10mA 50.0 IOUT=1mA IOUT=1A IOUT=100mA 40.0 0.0 0.0001 0.001 0.01 0.1 Output Current (A) 1 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 0.0 10 7 8 9 10 G001 11 12 13 Input Voltage (V) 14 15 16 Figure 5. Efficiency with 1.25MHz, Vout=5V EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 70.0 60.0 VIN=17V 50.0 VIN=12V 40.0 30.0 60.0 IOUT=10mA 50.0 IOUT=1mA 17 G001 Figure 4. Efficiency with 1.25MHz, Vout=5V Efficiency (%) Efficiency (%) 60.0 30.0 20.0 IOUT=1A IOUT=100mA 40.0 30.0 20.0 0.0 0.0001 0.001 0.01 0.1 Output Current (A) 1 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=5.0V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 0.0 10 7 8 9 10 G001 11 12 13 Input Voltage (V) 14 15 16 Figure 7. Efficiency with 2.5MHz, Vout=5V EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 VIN=12V 60.0 VIN=17V VIN=5V 50.0 40.0 30.0 17 G001 Figure 6. Efficiency with 2.5MHz, Vout=5V Efficiency (%) Efficiency (%) 70.0 70.0 60.0 IOUT=1A IOUT=100mA IOUT=10mA IOUT=1mA 50.0 40.0 30.0 20.0 0.0 0.0001 0.001 0.01 0.1 Output Current (A) 1 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 10 0.0 4 5 6 G001 Figure 8. Efficiency with 1.25MHz, Vout=3.3V 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 Figure 9. Efficiency with 1.25MHz, Vout=3.3V Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 7 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 70.0 60.0 VIN=12V 50.0 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VIN=17V VIN=5V 40.0 30.0 0.0 0.0001 IOUT=1A 40.0 0.001 0.01 0.1 Output Current (A) 1 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 10.0 0.0 10 4 5 6 7 8 G001 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 Figure 10. Efficiency with 2.5MHz, Vout=3.3V Figure 11. Efficiency with 2.5MHz, Vout=3.3V EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 VIN=12V 60.0 50.0 Efficiency (%) Efficiency (%) IOUT=1mA IOUT=10mA 20.0 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 10.0 VIN=17V VIN=5V 40.0 30.0 70.0 IOUT=1A 60.0 IOUT=100mA 50.0 IOUT=10mA IOUT=1mA 40.0 30.0 20.0 0.0 0.0001 0.001 0.01 0.1 Output Current (A) 1 VOUT=1.8V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=1.8V L=2.2uH (XFL4020) Cout=22uF 10.0 10.0 0.0 10 4 5 6 7 8 G001 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 Figure 12. Efficiency with 1.25MHz, Vout=1.8V Figure 13. Efficiency with 1.25MHz, Vout=1.8V EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs INPUT VOLTAGE 100.0 100.0 90.0 90.0 80.0 80.0 70.0 60.0 VIN=12V Efficiency (%) Efficiency (%) IOUT=100mA 50.0 30.0 20.0 VIN=17V 50.0 VIN=5V 40.0 30.0 70.0 60.0 IOUT=1A 50.0 IOUT=100mA 40.0 IOUT=10mA IOUT=1mA 30.0 20.0 0.0 0.0001 0.001 0.01 0.1 Output Current (A) 1 10.0 10 0.0 4 5 6 G001 Figure 14. Efficiency with 1.25MHz, Vout=0.9V Submit Documentation Feedback VOUT=0.9V L=2.2uH (XFL4020) Cout=22uF 20.0 VOUT=0.9V L=2.2uH (XFL4020) Cout=22uF 10.0 8 60.0 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G001 Figure 15. Efficiency with 1.25MHz, Vout=0.9V Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs INPUT VOLTAGE 3.40 3.40 Output Voltage (V) Output Voltage (V) VIN=17V 3.35 VIN=12V 3.30 VIN=5V 3.25 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 3.20 0.0001 0.001 0.01 0.1 Output Current (A) 1 IOUT=100mA 3.25 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 4 7 10 13 Input Voltage (V) 16 G001 Figure 16. Output Voltage Accuracy (Load Regulation) Figure 17. Output Voltage Accuracy (Line Regulation) SWITCHING FREQUENCY vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 4 IOUT=2A 3.5 IOUT=3A Switching Frequency (MHz) 3.5 3 2.5 2 IOUT=0.5A IOUT=1A 1.5 1 VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 0.5 0 4 6 8 10 12 Input Voltage (V) 14 16 3 2.5 2 1.5 1 0 18 0 0.5 G000 1 1.5 2 Output Current (A) 2.5 Figure 19. Switching Frequency INPUT CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE 5.0 45.0 4.5 40.0 4.0 35.0 30.0 25°C 25.0 85°C 20.0 15.0 10.0 3.5 85°C 3.0 2.5 2.0 1.5 1.0 −40°C 5.0 6.0 3 G000 Figure 18. Switching Frequency 50.0 0.0 3.0 VIN=12V, VOUT=3.3V L=2.2uH (XFL4020) FSW=Low 0.5 Input Current (µA) Switching Frequency (MHz) IOUT=1A G001 4 Input Current (µA) 3.30 3.20 10 IOUT=10mA IOUT=1mA 3.35 −40°C 25°C 0.5 9.0 12.0 15.0 Input Voltage (V) 18.0 20.0 0.0 3.0 6.0 G001 Figure 20. Quiescent Current Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A 9.0 12.0 15.0 Input Voltage (V) 18.0 20.0 G001 Figure 21. Shutdown Current Submit Documentation Feedback 9 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com STATIC DRAIN-SOURCE-RESISTANCE (RDSon) vs INPUT VOLTAGE STATIC DRAIN-SOURCE-RESISTANCE (RDSon) vs INPUT VOLTAGE 100.0 200.0 160.0 125°C RDSon Low−Side (mΩ) RDSon High−Side (mΩ) 180.0 140.0 120.0 85°C 100.0 25°C 80.0 −10°C 60.0 −40°C 40.0 80.0 125°C 60.0 85°C 25°C 40.0 −10°C 20.0 −40°C 20.0 0.0 0.0 3.0 6.0 9.0 12.0 Input Voltage (V) 15.0 0.0 0.0 18.0 20.0 Output Current (A) Output Voltage Ripple (V) VOUT=3.3V, L=2.2uH (XFL4020) Cout=22uF VIN=17V VIN=5V 0.02 0.01 0.3 0.6 0.9 1.2 1.5 1.8 2.1 Output Current (A) 2.4 2.7 3 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 G001 −40°C 25°C 85°C VOUT=3.3V L=2.2uH (XFL4020) Cout=22uF 4 5 6 7 G000 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) G000 Figure 24. Output Voltage Ripple Figure 25. Maximum Output Current POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 100 100 90 VIN=12V 90 VIN=5V 80 VIN=5V 80 VIN=12V 70 70 VIN=17V PSRR (dB) PSRR (dB) 18.0 20.0 OUTPUT CURRENT vs INPUT VOLTAGE VIN=12V 60 50 40 30 VIN=17V 60 50 40 30 20 20 VOUT=3.3V, IOUT=1A L=2.2uH (XFL4020) Cin=10uF, Cout=22uF 10 10 100 1k 10k Frequency (Hz) Submit Documentation Feedback VOUT=3.3V, IOUT=0.1A L=2.2uH (XFL4020) Cin=10uF, Cout=22uF 10 100k 1M 0 10 100 G000 Figure 26. Power Supply Rejection Ratio, fSW=2.5MHz 10 15.0 OUTPUT VOLTAGE vs OUTPUT CURRENT 0.03 0 9.0 12.0 Input Voltage (V) Figure 23. Low-Side Switch Resistance 0.04 0 6.0 Figure 22. High-Side Switch Resistance 0.05 0 3.0 G001 1k 10k Frequency (Hz) 100k 1M G000 Figure 27. Power Supply Rejection Ratio, fSW=2.5MHz Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 OUTPUT VOLTAGE vs TIME OUTPUT VOLTAGE vs TIME Figure 28. PWM-PSM-Transition (VIN=12V, VOUT=3.3V with 50mV/div) Figure 29. Load Transient Response (IOUT= 0.5 to 3 to 0.5 A, VIN=12V, VOUT=3.3V) OUTPUT VOLTAGE vs TIME OUTPUT VOLTAGE vs TIME Figure 30. Load Transient Response of Figure 29, rising edge Figure 31. Load Transient Response of Figure 29, falling edge Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 11 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 12 www.ti.com OUTPUT VOLTAGE vs TIME OUTPUT VOLTAGE vs TIME Figure 32. Startup into 100mA (VIN=12V, VOUT=3.3V) Figure 33. Startup into 3A (VIN=12V, VOUT=3.3V) PWM SIGNALS vs TIME POWER SAVE MODE SIGNALS vs TIME Figure 34. Typical Operation in PWM Mode (IOUT=1A) Figure 35. Typical Operation in Power Save Mode (IOUT=10mA) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 AMBIENT TEMPERATURE vs OUTPUT POWER 125 125 115 115 Free−Air Temperature (°C) Free−Air Temperature (°C) AMBIENT TEMPERATURE vs OUTPUT CURRENT 105 95 85 TLV62130 EVM L=2.2uH (XFL4020) VIN=12V, VOUT=3.3V 75 65 55 0 0.5 1 105 95 85 TLV62130 EVM L=2.2uH(XFL4020) VIN=12V, VOUT=3.3V 75 65 1.5 2 2.5 Output Current (A) 3 3.5 55 0 2 G000 Figure 36. Maximum Ambient Temperature (fSW=2.5MHz) 4 6 8 Output Power (W) 10 12 G000 Figure 37. Maximum Ambient Temperature (fSW=2.5MHz) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 13 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com DETAILED DESCRIPTION Device Operation The TLV62130 synchronous switched mode power converters are based on DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage. An internal current limit supports nominal output currents of up to 3A. The TLV62130 offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. Pulse Width Modulation (PWM) Operation The TLV62130 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current. Power Save Mode Operation The TLV62130's built in Power Save Mode will be entered seamlessly, if the load current decreases. This secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor current is discontinuous. In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency. The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions. TLV62130 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as: t ON = VOUT × 400ns V IN (1) For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using tON, the typical peak inductor current in Power Save Mode can be approximated by: I LPSM ( peak ) = (V IN - VOUT ) × t ON L (2) When VIN decreases to typically 15% above VOUT, the TLV62130 won't enter Power Save Mode, regardless of the load current. The device maintains output regulation in PWM mode. 14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 100% Duty-Cycle Operation The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off. The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as: spacing VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL ) (3) where IOUT is the output current, RDS(on) is the RDS(on) of the high-side FET and RL is the DC resistance of the inductor used. Enable / Shutdown (EN) When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. An internal pulldown resistor of about 400kΩ is connected and keeps EN logic low, if the pin is floating. It is disconnected if the pin is High. Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple power rails. Soft Start / Tracking (SS/TR) The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See Figure 32 and Figure 33 for typical startup operation. Connecting SS/TR directly to AVIN provides fastest startup behavior. The TLV62130 can start into a pre-biased output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias voltage. As long as the output is below about 0.5V a reduced current limit of typically 1.6A is set internally. If the device is set to shutdown (EN=GND), undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup sequence as set by the SS/TR connection. A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage in both directions up and down (see APPLICATION INFORMATION). Current Limit And Short Circuit Protection The TLV62130 device is protected against heavy load and short circuit events. If a short circuit is detected (VOUT drops below 0.5V), the current limit is reduced to 1.6A typically. If the output voltage rises above 0.5V, the device will run in normal operation again. At heavy loads, the current limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off. Avoiding shoot through current, the low-side FET will be switched on to sink the inductor current. The high-side FET will turn on again, only if the current in the low-side FET has decreased below the low side current limit threshold. The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit can be calculated as follows: Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 15 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 I peak ( typ ) = I LIMF + www.ti.com VL × t PD L (4) where ILIMF is the static current limit, specified in the ELECTRICAL CHARACTERISTICS, L is the inductor value, VL is the voltage across the inductor (VIN - VOUT) and tPD is the internal propagation delay. The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high side switch peak current can be calculated as follows: I peak (typ ) = I LIMF + (VIN - VOUT )× 30ns L (5) Power Good (PG) The TLV62130 has a built in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or thermal shutdown. TLV62130A features PG=Low in this case and can be used to actively discharge Vout (see Figure 50). VIN must remain present for the PG pin to stay Low. Pin-Selectable Output Voltage (DEF) The output voltage of the TLV62130 devices can be increased by 5% above the nominal voltage by setting the DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed information on voltage margining using TLV62130 can be found in SLVA489. A pull down resistor of about 400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after initially set to Low. The resistor is disconnected if the pin is set High. Frequency Selection (FSW) To get high power density with very small solution size, a high switching frequency allows the use of small external components for the output filter. However switching losses increase with the switching frequency. If efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally connected to the pin, acting the same way as at the DEF Pin (see above). Under Voltage Lockout (UVLO) If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV. Thermal Shutdown The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C (typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal shut down temperature. (1) 16 Maximum allowed voltage is 7V. Therefore, it's recommended to connect it to VOUT or PG, not VIN. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 APPLICATION INFORMATION The following information is intended to be a guideline through the individual power supply design process. Programming The Output Voltage The TLV62130 can be programmed for output voltages from 0.9V to 5V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from Equation 6 (see Figure 3). It is recommended to choose resistor values which allow a current of at least 2uA, meaning the value of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy and most robust design. æV ö R1 = R 2 çç OUT - 1÷÷ è V REF ø (6) In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V. External Component Selection The external components have to fulfill the needs of the application, but also the stability criteria of the devices control loop. The TLV62130 is optimized to work within a range of external components. The LC output filters inductance and capacitance have to be considered together, creating a double pole, responsible for the corner frequency of the converter (see Output Filter And Loop Stability). Table 1 can be used to simplify the output filter component selection. Table 1. Recommended LC Output Filter Combinations (1) 4.7µF 10µF 22µF 47µF 100µF 200µF √ √ √ √ (2) √ √ √ √ √ √ 400µF 0.47µH 1µH 2.2µH √ 3.3µH √ √ 4.7µH (1) (2) The values in the table are nominal values. This LC combination is the standard value and recommended for most applications. spacing The TLV62130 can be run with an inductor as low as 1µH. FSW should be set Low in this case. However, for applications running with the low frequency setting (FSW=High) or with low input voltages, 2.2µH is recommended. More detailed information on further LC combinations can be found in SLVA463. Inductor Selection The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static load conditions. spacing I L(max) = I OUT (max) + DI L(max) = VOUT DI L(max) 2 V æ ç 1 - OUT ç V IN (max) ×ç L ×f ç (min) SW ç è (7) ö ÷ ÷ ÷ ÷ ÷ ø Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A (8) Submit Documentation Feedback 17 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com where IL(max) is the maximum inductor current, ΔIL is the Peak to Peak Inductor Ripple Current, L(min) is the minimum effective inductor value and fSW is the actual PWM Switching Frequency. spacing Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also useful to get lower ripple current, but increases the transient response time and size as well. The following inductors have been used with the TLV62130 and are recommended for use: Table 2. List of Inductors (1) Type Inductance [µH] Current [A] (1) Dimensions [LxBxH] mm MANUFACTURER XFL4020-102ME_ 1.0 µH, ±20% 4.7 4 x 4 x 2.1 Coilcraft XFL4020-152ME_ 1.5 µH, ±20% 4.2 4 x 4 x 2.1 Coilcraft XFL4020-222ME_ 2.2 µH, ±20% 3.8 4 x 4 x 2.1 Coilcraft IHLP1212BZ-11 1.0 µH, ±20% 4.5 3 x 3.6 x 2 Vishay IHLP1212BZ-11 2.2 µH, ±20% 3.0 3 x 3.6 x 2 Vishay SRP4020-3R3M 3.3µH, ±20% 3.3 4.8 x 4 x 2 Bourns VLC5045T-3R3N 3.3µH, ±30% 4.0 5 x 5 x 4.5 TDK Lower of IRMS at 40°C rise or ISAT at 30% drop. spacing The inductor value also determines the load current at which Power Save Mode is entered: I load ( PSM ) = 1 DI L 2 (9) Using Equation 8, this current level can be adjusted by changing the inductor value. Capacitor Selection Output Capacitor The recommended value for the output capacitor is 22uF. The architecture of the TLV62130 allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see SLVA463). Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low ripple. Input Capacitor For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied from the same input source, it's required to place a capacitance of 0.1uF from AVIN to AGND, to avoid potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required. 18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 Soft Start Capacitor A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor required for a given soft-start ramp time for the output voltage is given by: C SS = t SS × 2.5mA 1.25V [F ] (10) where CSS is the capacitance (F) required at the SS/TR pin and tSS is the desired soft-start ramp time (s). spacing NOTE DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. spacing Tracking Function If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 38. spacing VFB » 0.64 × VSS / TR (11) VSS/TR [V] 1.2 0.8 0.4 0.2 0.4 0.6 0.8 VFB [V] Figure 38. Voltage Tracking Relationship Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V. If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero, independent of the tracking voltage. Figure 39 shows how to connect devices to get ratiometric and simultaneous sequencing by using the tracking function. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 19 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com spacing VOUT1 PVIN SW AVIN VOS EN PG TLV62130 SS/TR FB DEF AGND FSW PGND PVIN SW AVIN VOS VOUT2 PG EN R1 TLV62130 SS/TR R2 FB DEF AGND FSW PGND Figure 39. Sequence for Ratiometric and Simultaneous Startup The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as VOUT1. A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing circuits are found in SLVA470. Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider tolerance than specified. Output Filter And Loop Stability The TLV62130 is internally compensated to be stable with L-C filter combinations corresponding to a corner frequency to be calculated with Equation 12: f LC = 1 2p L × C (12) Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for use. Different values may work, but care has to be taken on the loop stability which will be affected. More information including a detailed LC stability matrix can be found in SLVA463. The TLV62130 device includes an internal 25pF feedforward capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the feedback divider, per equation Equation 13 and Equation 14: spacing f zero = 1 2p × R1 × 25 pF (13) spacing f pole = 20 1 2p × 25 pF æ 1 1 × çç + è R1 R 2 Submit Documentation Feedback ö ÷÷ ø (14) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 spacing Though the TLV62130 is stable without the pole and zero being in a particular location, adjusting their location to the specific needs of the application can provide better performance in Power Save mode and/or improved transient response. An external feedforward capacitor can also be added. A more detailed discussion on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466. Layout Considerations A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TLV62130 demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 40 for the recommended layout of the TLV62130, which is designed for common external ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output capacitor. Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g. SW). As they carry information about the output voltage, they should be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane. The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. The recommended layout is implemented on the EVM and shown in its Users Guide, SLAU416. Additionally, the EVM Gerber data are available for download here, SLVC394. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 21 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 GND C www.ti.com R2 8 C PVIN AVIN 7 R1 6 5 9 4 10 3 11 2 12 1 13 CIN 14 15 PG 16 EN L1 to GND plane VOUT COUT to AGND GND Figure 40. Layout Example THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad • Introducing airflow in the system For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (SZZA017), and (SPRA953). The TLV62130 is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance. If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation. Experimental data, taken from the TLV62130 EVM, shows the maximum ambient temperature (without additional cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see Figure 36). 22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 Application Example As Power LED Supply The TLV62130 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid excessive power loss. Since this pin provides 2.5µA, the feedback pin voltage can be adjusted by an external resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TLV62130. Figure 41 shows an application circuit, tested with analog dimming: spacing (4 .. 17) V 2.2µH PVIN SW AVIN VOS EN 4.7uF PG ADIM 22uF TLV62130 SS/TR 187k FB DEF AGND FSW PGND 0.1R Figure 41. 3A Single LED Power Supply The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15. spacing V FB = 0.64 × 2.5mA × R SS / TR (15) spacing The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used. More information is available in the Application Note SLVA451. Application Example As Inverting Power Supply The TLV62130 can be used as inverting power supply by rearranging external circuitry as shown in Figure 42. As the former GND node now represents a voltage level below system ground, the voltage difference between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16). spacing V IN + VOUT £ V IN max (16) spacing 10uF 2.2µH (4 .. 12)V PVIN SW AVIN VOS 680k 10uF PG EN TLV62130 SS/TR 22uF FB 3.3nF DEF AGND FSW PGND 130k -5V Figure 42. -5V Inverting Power Supply Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 23 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com spacing The transfer function of the inverting power supply configuration differs from the buck mode transfer function, incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469. Typical Applications spacing spacing spacing 1 / 2.2 µH (5 .. 17)V 10uF PVIN SW AVIN VOS EN 5V / 3A 100k PG 680k 22uF TLV62130 FB SS/TR 3.3nF DEF AGND FSW PGND 130k Figure 43. 5V/3A Power Supply spacing spacing spacing 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN 3.3V / 3A 100k PG 750k 22uF TLV62130 FB SS/TR 3.3nF DEF AGND FSW PGND 240k Figure 44. 3.3V/3A Power Supply spacing spacing spacing 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN 2.5V / 3A 100k PG 510k 22uF TLV62130 SS/TR 3.3nF FB DEF AGND FSW PGND 240k Figure 45. 2.5V/3A Power Supply spacing 24 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 spacing spacing 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN 1.8V / 3A 100k PG 300k 22uF TLV62130 FB SS/TR 3.3nF DEF AGND FSW PGND 240k Figure 46. 1.8V/3A Power Supply spacing spacing 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN 1.5V / 3A 100k PG 130k 22uF TLV62130 FB SS/TR 3.3nF DEF AGND FSW PGND 150k Figure 47. 1.5V/3A Power Supply spacing spacing 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN 1.2V / 3A 100k PG 75k 22uF TLV62130 SS/TR 3.3nF FB DEF AGND FSW PGND 150k Figure 48. 1.2V/3A Power Supply spacing spacing Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 25 TLV62130, TLV62130A SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 www.ti.com 1 / 2.2 µH (4 .. 17)V 10uF PVIN SW AVIN VOS EN 1V / 3A 100k PG 51k 22uF TLV62130 SS/TR 3.3nF FB DEF AGND FSW PGND 200k Figure 49. 1V/3A Power Supply Active Output Discharge spacing The TLV62130A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown. Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 50). The discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability, keep the maximum current into the PG pin less than 10mA. spacing (4 .. 17)V 1 / 2.2 µH PVIN Vout / 3A SW TLV62130A AVIN 10uF 3.3nF VOS EN PG SS/TR FB DEF AGND FSW PGND R3 R1 22uF R2 Figure 50. Discharge Vout through PG pin 26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A TLV62130, TLV62130A www.ti.com SLVSB74B – FEBRUARY 2012 – REVISED JUNE 2013 REVISION HISTORY Changes from Original (February 2012) to Revision A Page • Changed text in Tablenote 3 of Terminal Functions table .................................................................................................... 4 • Added text to Power Save Mode Operation section for clarification. ................................................................................. 14 • Changed Layout Considerations description for clarification. ............................................................................................. 21 Changes from Revision A (February 2013) to Revision B Page • Added device TLV62130A to data sheet .............................................................................................................................. 1 • Added device version TLV62130A to Ordering Info table .................................................................................................... 2 • Added text to Power Good (PG) section regarding TLV62130A function .......................................................................... 16 • Added additional option to Pin-Selectable Output Voltage (DEF) section footnote. ........................................................... 16 • Added text to Frequency Selection (FSW) section regarding pin control. .......................................................................... 16 • Added application example with regard to new version TLV62130A ................................................................................. 26 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TLV62130 TLV62130A Submit Documentation Feedback 27 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TLV62130ARGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 VUNI TLV62130ARGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 VUNI TLV62130RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 VUBI TLV62130RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 VUBI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TLV62130ARGTR QFN RGT 16 TLV62130ARGTT QFN RGT TLV62130RGTR QFN RGT TLV62130RGTT QFN RGT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV62130ARGTR QFN RGT 16 3000 552.0 367.0 36.0 TLV62130ARGTT QFN RGT 16 250 552.0 185.0 36.0 TLV62130RGTR QFN RGT 16 3000 552.0 367.0 36.0 TLV62130RGTT QFN RGT 16 250 552.0 185.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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