TI TPS61258YFFT

TPS61253, TPS61254, TPS61256, TPS61258
www.ti.com
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
3.5-MHz HIGH EFFICIENCY STEP-UP CONVERTER IN CHIP SCALE PACKAGING
Check for Samples: TPS61253, TPS61254, TPS61256, TPS61258
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
93% Efficiency at 3.5MHz Operation
22µA Quiescent Current in Standby Mode
36µA Quiescent Current in Normal Operation
Wide VIN Range From 2.3V to 5.5V
VIN ≥ VOUT Operation
IOUT ≥800mA at VOUT = 4.5V, VIN ≥2.65V
IOUT ≥1000mA at VOUT = 5.0V, VIN ≥3.3V
IOUT ≥1500mA (Peak) at VOUT = 5.0V, VIN ≥3.3V
±2% Total DC Voltage Accuracy
Light-Load PFM Mode
Selectable Standby Mode or True Load
Disconnect During Shutdown
Thermal Shutdown and Overload Protection
Only Three Surface-Mount External
Components Required
Total Solution Size <25mm2
9-Pin NanoFreeTM (CSP) Packaging
APPLICATIONS
•
•
•
Cell Phones, Smart-Phones
Mono and Stereo APA Applications
USB Charging Port (5V)
spacer
spacer
VO = 5.0 V
100
DESCRIPTION
The TPS6125x device provides a power supply
solution for battery-powered portable applications.
Intended for low-power applications, the TPS6125x
supports up to 800-mA load current from a battery
discharged as low as 2.65V and allows the use of low
cost chip inductor and capacitors.
With a wide input voltage range of 2.3V to 5.5V, the
device supports applications powered by Li-Ion
batteries with extended voltage range. Different fixed
voltage output versions are available from 3.15V to
5.0V.
The TPS6125x operates at a regulated 3.5-MHz
switching frequency and enters power-save mode
operation at light load currents to maintain high
efficiency over the entire load current range. The
PFM mode extends the battery life by reducing the
quiescent current to 36μA (typ) during light load
operation.
In addition, the TPS6125x device can also maintain
its output biased at the input voltage level. In this
mode, the synchronous rectifier is current limited
allowing external load (e.g. audio amplifier) to be
powered with a restricted supply. In this mode, the
quiescent current is reduced to 22µA. Input current in
shutdown mode is less than 1µA (typ), which
maximizes battery life.
The TPS6125x offers a very small solution size due
to minimum amount of external components. It allows
the use of small inductors and input capacitors to
achieve a small solution size. During shutdown, the
load is completely disconnected from the battery.
90
80
L
Efficiency - %
70
VIN
2.65 V .. 4.85 V
60
50
1 μH
VOUT
5.0 V @ 700mA
TPS61256
SW
VOUT
VIN
BP
EN
GND
40
CI
4.7 μF
.
30
CO
10 uF
20
ut
utp
IO
50.1
25.1
12.6
6.2
3.2
1.6
0.8
0.4
0.2
3.0
ge V
2 .7
.
0.1
3.6
Volt
a
3.3
put
4.2
V I In
3.9
4.8
4.5
5.4
5.1
0
nt
rre
100.1
199.6
398.1
794.3
10
Figure 2. Smallest Solution Size Application
A
-m
Cu
-O
Figure 1. Efficiency vs. Load Current
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS61253, TPS61254, TPS61256, TPS61258
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTION
TA
–40°C to 85°C
(1)
(2)
(3)
PART NUMBER (1)
OUTPUT
VOLTAGE
DEVICE
SPECIFIC FEATURES
ORDERING (2)
PACKAGE
MARKING
CHIP CODE
TPS61253
5.0V
Supports 5V, up to 1500mA peak loading
down to 3.3V input voltage
TPS61253YFF
SBF
TPS61254
4.5V
Supports 4.5V/800mA loading
down to 2.65V input voltage
TPS61254YFF
QWR
TPS61255 (3)
3.75V
TPS61255YFF
QWS
TPS61256
5.0V
TPS61256YFF
RAV
TPS61257 (3)
4.3V
TPS61257YFF
RAO
TPS61258
4.5V
Supports 4.5V, up to 1500mA peak loading
down to 3.3V input voltage
TPS61258YFF
SAZ
TPS61259 (3)
5.1V
Supports 5.1V, up to 1500mA peak loading
down to 3.3V input voltage
TPS61259YFF
SAY
Supports 5V/900mA loading
down to 3.3V input voltage
For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
The YFF package is available in tape and reel. Add a R suffix (e.g. TPS61254YFFR) to order quantities of 3000 parts. Add a T suffix
(e.g. TPS61254YFFT) to order quantities of 250 parts.
Product preview.Contact TI factory for more information
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Input voltage
Input current
Voltage at VIN (2), VOUT (2), SW (2), EN (2), BP (2)
Continuous average current into SW
Peak current into SW
–0.3 to 7
V
1.8
A
(3)
(4)
3.5
Power dissipation
Operationg temperature range, TA
Temperature range
ESD rating
(1)
(2)
(3)
(4)
(5)
(6)
2
(6)
A
Internally limited
(5)
–40 to 85
°C
Operating virtual junction, TJ
–40 to 150
°C
Storage temperature range, Tstg
–65 to 150
°C
Human Body Model - (HBM)
2000
V
Charge Device Model - (CDM)
1000
V
Machine Model - (MM)
200
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
Limit the junction temperature to 105°C for continuous operation at maximum output power.
Limit the junction temperature to 125°C for 5% duty cycle operation.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
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SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
RECOMMENDED OPERATING CONDITIONS
MIN
VI
Input voltage range
NOM
MAX
TPS61253
2.65 (1)
4.85
TPS61254
2.5
4.35
TPS61256
2.5
4.85
TPS61257
2.5
4.15
TPS61258
2.65 (1)
4.35
TPS61259
2.65 (1)
4.85
V
Ω
RL
Minimum resistive load for start-up
L
Inductance
0.7
1.0
2.9
µH
CO
Output capacitance
3.5
5
50
µF
TA
Ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
TPS6125X
UNIT
55
Up to 1000mA peak output current.
THERMAL INFORMATION
TPS6125x
THERMAL METRIC (1)
YFF
UNIT
9 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
θJCbot
Junction-to-case (bottom) thermal resistance
(1)
110
35
°C/W
50
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 4.5V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to
85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT
= 4.5V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
Operating quiescent current
into VIN
IQ
Operating quiescent current
into VOUT
Standby mode quiescent current
into VIN
VUVLO
Shutdown current
TPS6125x
Under-voltage lockout threshold
30
45
µA
7
15
µA
IOUT = 0mA, VIN = VOUT = 3.6V
EN = GND, BP = VIN
Device not switching
11
20
µA
9.5
15
µA
TPS6125x
Standby mode quiescent current
into VOUT
ISD
IOUT = 0mA, VIN = 3.6V
EN = VIN, BP = GND
Device not switching
TPS6125x
Copyright © 2011–2012, Texas Instruments Incorporated
0.85
5.0
μA
Falling
2.0
2.1
V
Hysteresis
0.1
EN = GND, BP = GND
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ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 4.5V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to
85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT
= 4.5V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ENABLE, BYPASS
VIL
Low-level input voltage
VIH
High-level input voltage
Ilkg
Input leakage current
TPS6125x
0.4
V
0.5
µA
1.0
V
Input connected to GND or VIN
OUTPUT
Regulated DC output voltage
Regulated DC output voltage
Regulated DC output voltage
TPS61253
TPS61254
TPS61256
VOUT
Regulated DC output voltage
TPS61257
2.3V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop
4.92
5
5.08
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1000mA
PFM/PWM operation
4.85
5
5.2
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1500mA
PFM/PWM operation
Pulsed load test; Pulse width ≤ 20ms;
Duty cycle ≤ 10%
4.75
5
5.2
2.3V ≤ VIN ≤ 4.35V, IOUT = 0mA
PWM operation. Open Loop
4.43
4.5
4.57
4.4
4.5
4.65
4.92
5
5.08
4.9
5
5.2
4.23
4.3
4.37
4.2
4.3
4.45
4.43
4.5
4.57
4.3
4.5
4.65
2.3V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop
5.02
5.1
5.18
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1500mA
PFM/PWM operation
Pulsed load test; Pulse width ≤ 20ms;
Duty cycle ≤ 10%
4.75
5.1
5.3
2.65V ≤ VIN ≤ 4.35V, 0mA ≤ IOUT ≤ 800mA
PFM/PWM operation
2.3V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop
2.65V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 700mA
PFM/PWM operation
2.3V ≤ VIN ≤ 4.15V, IOUT = 0mA
PWM operation. Open loop.
2.65V ≤ VIN ≤ 4.15V, 0mA ≤ IOUT ≤ 800mA
PFM/PWM operation
2.3V ≤ VIN ≤ 4.35V, IOUT = 0mA
PWM operation. Open Loop
Regulated DC output voltage
Regulated DC output voltage
TPS61258
TPS61259
Power-save mode output ripple
voltage
Standby mode output ripple
voltage
ΔVOUT
PWM mode output ripple voltage
Power-save mode output ripple
voltage
Standby mode output ripple
voltage
PWM mode output ripple voltage
4
TPS61254
TPS61258
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TPS61253
TPS61256
TPS61259
3.3V ≤ VIN ≤ 4.35V, 0mA ≤ IOUT ≤ 1500mA
PFM/PWM operation
Pulsed load test; Pulse width ≤ 20ms;
Duty cycle ≤ 10%
V
V
V
V
V
V
PFM operation, IOUT = 1mA
45
EN = GND, BP = VIN, IOUT = 0mA
80
PWM operation, IOUT = 200mA
20
PFM operation, IOUT = 1mA
50
EN = GND, BP = VIN, IOUT = 0mA
80
PWM operation, IOUT = 200mA
20
mVpk
mVpk
Copyright © 2011–2012, Texas Instruments Incorporated
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SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VIN = 2.3V to 5.5V, VOUT = 4.5V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to
85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT
= 4.5V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SWITCH
rDS(on)
Ilkg
High-side MOSFET on resistance
Low-side MOSFET on resistance
Reverse leakage current into
VOUT
Switch valley current limit
ILIM
Pre-charge mode current limit
(linear mode)
Overtemperature protection
Overtemperature hysteresis
170
TPS6125x
mΩ
100
TPS6125x
EN = GND, BP = GND
TPS61253
TPS61258
TPS61259
EN = VIN, BP = GND. Open Loop
TPS61254
TPS61256
TPS61257
EN = VIN, BP = GND. Open Loop
TPS6125x
EN = GND, BP = VIN
3.5
3300
µA
3620 3900
mA
1900
165
TPS6125x
2150 2400
215
265
mA
140
°C
20
°C
OSCILLATOR
fOSC
Oscillator frequency
TPS6125x
VIN = 3.6V VOUT = 4.5V
3.5
MHz
TPS6125x
BP = GND, IOUT = 0mA.
Time from active EN to start switching
70
µs
TPS61253
TPS61254
TPS61256
TPS61258
TPS61259
BP = GND, IOUT = 0mA.
Time from active EN to VOUT
400
µs
TIMING
Start-up time
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PIN ASSIGNMENTS
BOTTOM VIEW
TOP VIEW
A1
A2
A3
A3
A2
A1
B1
B2
B3
B3
B2
B1
C1
C2
C3
C3
C2
C1
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
This is the mode selection pin of the device and is only of relevance when the device is disabled
(EN = Low). This pin must not be left floating and must be terminated. Refer to Table 3 for more
details.
BP
C3
I
BP = Low: The device is in true shutdown mode.
BP = High: The output is biased at the input voltage level with a maximum load current capability of
ca. 150mA. In standby mode, the device only consumes a standby current of 22µA (typ).
EN
B3
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
mode. Pulling this pin high enables the device. This pin must not be left floating and must be
terminated.
I
GND
C1, C2
SW
B1, B2
I/O
VIN
A3
I
Power supply input.
A1, A2
O
Boost converter output.
VOUT
Ground pin.
This is the switch pin of the converter and is connected to the drain of the internal Power MOSFETs.
FUNCTIONAL BLOCK DIAGRAM
SW
VIN
NMOS
PMOS
Valley
Current
Sense
Modulator
Softstart
EN
Control
Logic
BP
Error
Amplifier
Gate Driver
VOUT
VREF
Thermal
Shutdown
Undervoltage
Lockout
GND
6
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SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
PARAMETER MEASUREMENT INFORMATION
L
1 μH
VIN
CI
4.7 μF
TPS6125x
SW
VOUT
VIN
BP
EN
VOUT
CO
10 uF
GND
EN
BP
Shutdown, True Load Disconnect (SD)
0
0
Standby Mode, Output Pre-Biased (SM)
0
1
Boost Operating Mode (BST)
1
X
Table 2. List of Components
REFERENCE
DESCRIPTION
PART NUMBER, MANUFACTURER
L (1)
1.0μH, 1.8A, 48mΩ, 3.2 x 2.5 x 1.0mm max. height
LQM32PN1R0MG0, muRata
(2)
L
1.0μH, 3.7A, 37mΩ, 3.2 x 2.5 x 1.2mm max. height
DFE322512C, TOKO
CI
4.7μF, 6.3V, 0402, X5R ceramic
GRM155R60J475M, muRata
CO
10μF, 6.3V, 0603, X5R ceramic
GRM188R60J106ME84, muRata
(1)
(2)
Inductor used to characterize TPS61254YFF, TPS61255YFF, TPS61256YFF and TPS61257YFF devices.
Inductor used to characterize TPS61253YFF, TPS61258YFF and TPS61259YFF devices.
Copyright © 2011–2012, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
η
vs Output current
Efficiency
3, 4, 5, 7
vs Input voltage
6
vs Output current
8, 9, 10, 11, 12, 16
VO
DC output voltage
IO
Maximum output current
vs Input voltage
ΔVO
Peak-to-peak output ripple voltage
vs Output current
ICC
Supply current
vs Input voltage
20, 21
DC pre-charge current
vs Differential input-output voltage
22, 23
Valley current limit
vs Temperature
24, 25
MOSFET rDS(on)
vs Temperature
26
ILIM
rDS(on)
vs Input voltage
13
14, 15
17, 18, 19
PFM operation
27
PWM operation
28
Combined line/load transient response
29
Load transient response
30, 32
AC load transient response
31, 33
Start-up
34, 35
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
95
100
90
90
85
VI = 3.3 V
VI = 2.7 V VI = 3 V
80
VI = 3.6 V
VI = 2.5 V
70
Efficiency - %
Efficiency - %
85
75
VI = 4.5 V
VO = 5 V (TPS61256)
95 PFM/PWM Operation
VI = 4.5 V
VI = 3.6 V
80
75
70
65
65
60
60
VO = 4.5 V
55
VI = 2.7 V
VI = 3 V
VI = 3.3 V
VI = 2.5 V
55
PFM/PWM Operation
50
0.1
8
1
10
100
1000
50
0.1
1
10
100
IO - Output Current - mA
IO - Output Current - mA
Figure 3.
Figure 4.
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1000
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SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100
95
100
VI = 4.5 V
VI = 4.2 V
98
VO = 5 V
PFM/PWM Operation
96
90
94
VI = 3.3 V
92
VI = 3.6 V
90
Efficiency - %
Efficiency - %
85
80
75
70
IO = 100 mA
86
84
82
IO = 800 mA
78
60
76
VO = 5 V (TPS61253),
IO = Pulse Operation (tpulse = 20 ms, d = 10%),
PFM/PWM Operation
0
1
10
100
1000
IO - Output Current - mA
10000
Figure 5.
Figure 6.
EFFICIENCY
vs
OUTPUT CURRENT
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VI = 2.7 V
VI = 4.5 V
VI = 3.3 V
VI = 3 V
80
70
60
72
70
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI - Input Voltage - V
4.59
100
90
74
VO - DC Output Voltage - V
55
Efficiency - %
IO = 10 mA
88
80
65
50
IO = 300 mA
VI = 4.5 V
VI = 3.6 V
50
40
30
4.55
VI = 2.5 V
4.50
VI = 3.6 V
4.46
20
0
0.01
VO = 4.5 V
PFM/PWM Operation
VO ~ VI
Standby Operation
10
0.1
1
10
IO - Output Current - mA
Figure 7.
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100
4.41
0.1
1
10
100
1000
IO - Output Current - mA
Figure 8.
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DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4.545
VO = 5 V (TPS61256)
PFM/PWM Operation
5.1
VO = 4.5 V
PWM Operation
VO - DC Output Voltage - V
VO - DC Output Voltage - V
5.15
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VI = 5 V
VI = 4.5 V
5.05
VI = 2.5 V
VI = 3.6 V
5
VI = 4.5 V
4.5
VI = 2.5 V
4.455
VI = 2.7 V
VI = 3 V
VI = 3.3 V
4.41
VI = 3.6 V
VI = 4.2 V
4.95
0.1
1
10
100
4.365
500
1000
IO - Output Current - mA
5.05
Figure 10.
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VO = 5 V (TPS61256)
PWM Operation
5.1
VI = 3.6 V
VI = 4.2 V
5.05
VI = 2.5 V
4.95 V = 2.7 V
I
VI = 3 V
VI = 3.3 V
1900
VO = 5 V (TPS61253),
IO = Pulse Operation (tpulse = 20 ms, d = 10%),
PWM Operation
VI = 4.5 V
VI = 4.2 V
VO - DC Output Voltage - V
VO - DC Output Voltage - V
900 1100 1300 1500 1700
IO - Output Current - mA
Figure 9.
5
4.9
700
VI = 4.5 V
5
4.95
4.9
VI = 3 V
VI = 3.3 V
VI = 3.6 V
4.85
4.85
4.8
4.8
500
700
900 1100 1300 1500 1700
IO - Output Current - mA
Figure 11.
10
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1900
4.75
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
IO - Output Current - mA
Figure 12.
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DC OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5.55
5.5
MAXIMUM OUTPUT CURRENT
vs
INPUT VOLTAGE
2300
VO = 5 V
PFM/PWM Operation
2100
5.4
IO - Maximum Output Current - mA
VO - DC Output Voltage - V
5.45
IO = 800 mA
5.35
IO = 500 mA
5.3
5.25
5.2
5.15
IO = 100 mA
IO = 10 mA
5.1
5.05
1900
TA = 85°C
1300
1100
900
700
500
2.5 2.75
3
3.25 3.5 3.75 4 4.25 4.5 4.75
VI - Input Voltage - V
Figure 13.
Figure 14.
MAXIMUM OUTPUT CURRENT
vs
INPUT VOLTAGE
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3000
5
4.6
2600
VO - DC Output Voltage - V
4.4
2400
TA = -40 °C
2200
TA = 25 °C
1800
TA = 65 °C
1600
TA = 85 °C
1400
5
VO ~ VI
Standby Operation
4.8
2800
IO - Maximum Output Current - mA
TA = 25°C
1500
4.95
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI - Input Voltage - V
VI = 4.5 V
VI = 4.2 V
4.2
4
3.8
VI = 3.6 V
3.6
3.4
VI = 3.3 V
3.2
VI = 3 V
3
2.8
VI = 2.7 V
2.6
1200
1000
TA = -40°C
1700
5
2000
VO = 5 V (TPS61256)
PWM Operation
VO = 5 V (TPS61253),
IO = Pulse Operation (tpulse = 20 ms, d = 10%)
PWM Operation
800
2.5 2.75
3
3.25 3.5 3.75 4 4.25 4.5 4.75
VI - Input Voltage - V
Figure 15.
Copyright © 2011–2012, Texas Instruments Incorporated
2.4
5
2.2
2
0
VI = 2.5 V
20 40 60 80 100 120 140 160 180 200 220 240
IO - Output Current - mA
Figure 16.
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PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
60
50
VI = 3.3 V
45
VI = 3.6 V
40
35
30
25
VI = 4.5 V
20
15
10
5 CO = 10μF 6.3V (0603) X5R, muRata GRM188R60J106ME84D
0
0
VO - Peak-to-Peak Output Ripple Voltage - mV
VI = 2.7 V
55
VO = 5 V (TPS61256)
PFM/PWM Operation
50
VI = 2.7 V
45
VI = 3.3 V
40
35
30
VI = 3.6 V
VI = 4.5 V
25
20
15
10
5 CO = 22μF 10V (1210) X5R, muRata GRM32ER71A226K
0
0
100 200 300 400 500 600 700 800 900 1000
IO - Output Current - mA
100 200 300 400 500 600 700 800 900 1000
IO - Output Current - mA
Figure 17.
Figure 18.
PEAK-TO-PEAK OUTPUT RIPPLE VOLTAGE
vs
OUTPUT CURRENT
SUPPLY CURRENT
vs
INPUT VOLTAGE
60
80
50
75 VO = 5 V
IO = 0 mA
70
45
65
VO = 5 V (TPS61253)
55 PFM/PWM Operation
40
60
VI = 3.3 V
35
VI = 3.6 V
30
25
20
VI = 4.5 V
15
10
CO = x2 10 mF 6.3 V (0603) X5R,
muRata GRM188R60J106ME84D
5
0
200
400
600
800 1000 1200
IO - Output Current - mA
Figure 19.
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1400
TA = 85°C
TA = 25°C
55
50
45
40
35
30
0
12
VO - Peak-to-Peak Output Ripple Voltage - mV
VO = 5 V (TPS61256)
55 PFM/PWM Operation
Supply Current - mA
VO - Peak-to-Peak Output Ripple Voltage - mV
60
TA = -40°C
25
20
15
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
VI - Input Voltage - V
Figure 20.
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SUPPLY CURRENT
vs
INPUT VOLTAGE
DC PRE-CHARGE CURRENT
vs
DIFFERENTIAL INPUT-OUTPUT VOLTAGE
45
VI ~ VO
40 IO = 0 mA
Standby Operation
TA = 25°C
TA = 85°C
30
25
20
15
10
5
250
245
240
235
230
225
220
215
210
205
200
195
190
185
180
175
170
165
160
155
150
0
Figure 21.
Figure 22.
DC PRE-CHARGE CURRENT
vs
DIFFERENTIAL INPUT-OUTPUT VOLTAGE
VALLEY CURRENT LIMIT
25
Sample Size = 200
VIN = 3.6 V
TJ = 130°C
20
VI = 3.6 V,
TA = 85°C
VI = 3.6 V,
TA = 25°C
VI = 3.6 V,
TA = -40°C
TJ = 25°C
15
TJ = -20°C
10
5
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6
Differential Input - Output Voltage - V
1900
1925
1950
1975
2000
2025
2050
2075
2100
2125
2150
2175
2200
2225
2250
2275
2300
2325
2350
2375
2400
DC Pre-Charge Current - mA
0
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI - Input Voltage - V
Sample Percentage - %
Supply Current - mA
35
DC Pre-Charge Current - mA
TA = -40°C
250
245
240
235
230
225
VI = 2.7 V,
220
T
A = 25°C
VI = 4.5 V,
215
TA = 25°C
210
205
200
195
VI = 3.6 V,
190
TA = 25°C
185
180
175
170
165
160
155
150
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5
Differential Input - Output Voltage - V
ILIM - Valley Current Limit - mA
Figure 23.
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Figure 24.
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MOSFET rDS(on)
vs
TEMPERATURE
VALLEY CURRENT LIMIT
25
200
TPS61253
VIN = 3.6 V,
Sample Size = 200
VO = 5 V
180
TJ = 125°C
RDS(on) - On-Resistance - mW
Sample Percentage - %
20
TJ = 25°C
15
TJ = -20°C
10
5
160
Rectifier MOSFET
140
120
100
Switch MOSFET
80
60
40
0
3300
3325
3350
3375
3400
3425
3450
3475
3500
3525
3550
3575
3600
3625
3650
3675
3700
3725
3750
3775
3800
3825
3850
3875
3900
20
ILIM - Valley Current Limit - mA
0
-30
-10
10
30
50
70
90
TJ - Junction Temperature - °C
Figure 25.
Figure 26.
POWER-SAVE MODE OPERATION
PWM OPERATION
VI = 3.6 V,
VO = 5.0 V,
IO = 40 mA
Figure 27.
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110
130
VI = 3.6 V,
VO = 5.0 V,
IO = 200 mA
Figure 28.
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SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
COMBINED LINE/LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
VO = 5.0 V
50 to 500 mA Load Step
VI = 3.6 V,
VO = 5.0 V
50mA to 500mA
Load Step
3.3V to 3.9V Line Step
Figure 29.
Figure 30.
AC LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE IN
PFM/PWM OPERATION
0 to 400mA Load Sweep
VI = 3.6 V,
VO = 5.0 V
50 to 500 mA Load Step
VI = 3.6 V,
VO = 5.0 V
CO = 22μF 10V (1210) X5R, muRata
Figure 31.
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Figure 32.
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AC LOAD TRANSIENT RESPONSE
VI = 3.6 V,
VO = 5.0
START-UP
0 to 400mA Load
VI = 3.6 V,
VO = 5.0 V,
IO = 0 mA
CO = 22μF 10V (1210) X5R, muRata
Figure 33.
Figure 34.
START-UP
VI = 2.7 V
VI = 4.5 V
VI = 3.6 V
VO = 5.0 V,
IO = 0 mA
Figure 35.
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SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
DETAILED DESCRIPTION
OPERATION
The TPS6125x synchronous step-up converter typically operates at a quasi-constant 3.5-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6125x converter
operates in power-save mode with pulse frequency modulation (PFM).
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to
achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time.
At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps
up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer
has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally,
the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.
In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain
amount above the input voltage. The TPS6125x device operates differently as it can smoothly transition in and
out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits
even though the converter is subject to an input voltage that tends to be excessive. In this operation mode, the
output current capability of the regulator is limited to ca. 150mA. Refer to the typical characteristics section (DC
Output Voltage vs. Input Voltage) for further details.
The current mode architecture with adaptive slope compensation provides excellent transient load response,
requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while
minimizing the number of external components.
POWER-SAVE MODE
The TPS6125X integrates a power-save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage.
It ramps up the output voltage with several pulses and goes into power save mode once the output voltage
exceeds the set threshold voltage.
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode.
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STANDBY MODE
The TPS6125x device is able to maintain its output biased at the input voltage level. In so called standby mode
(EN = 0, BP = 1), the synchronous rectifier is current limited to ca. 150mA allowing an external load (e.g. audio
amplifier) to be powered with a restricted supply. The output voltage is slightly reduced due to voltage drop
across the rectifier MOSFET and the inductor DC resistance. The device consumes only a standby current of
22µA (typ).
Table 3. Operating Mode Control
OPERATING MODE
EN
BP
Shutdown, True Load Disconnect (SD)
0
0
Standby Mode, Output Pre-Biased (SM)
0
1
1
0
1
1
Boost Operating Mode (BST)
CURRENT LIMIT OPERATION
The TPS6125x device employs a valley current limit sensing scheme. Current limit detection occurs during the
off-time by sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by
Equation 1.
IOUT(CL) = (1 - D) g (IVALLEY +
1
DIL )
2
(1)
The duty cycle (D) can be estimated by Equation 2
V gh
D = 1 - IN
VOUT
(2)
and the peak-to-peak current ripple (ΔIL) is calculated by Equation 3
V
D
DIL = IN g
L
f
(3)
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the
current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism).
When the current limit is reached the output voltage decreases during further load increase.
Figure 36 illustrates the inductor and rectifier current waveforms during current limit operation.
IL
Current Limit
Threshold
Rectifier
Current
IPEAK
IVALLEY = ILIM
IOUT(CL)
DIL
IOUT(DC)
Increased
Load Current
IIN(DC)
f
Inductorr
Current
IIN(DC)
DIL
ΔI L =
V IN D
×
L f
Figure 36. Inductor/Rectifier Currents in Current Limit Operation
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ENABLE
The TPS6125x device starts operation when EN is set high and starts up with the soft-start sequence. For proper
operation, the EN pin must be terminated and must not be left floating.
Pulling the EN and BP pins low forces the device in shutdown, with a shutdown current of typically 1µA. In this
mode, true load disconnect between the battery and load prevents current flow from VIN to VOUT, as well as
reverse flow from VOUT to VIN.
Pulling the EN pin low and the BP pin high forces the device in standby mode, refer to the STANDBY MODE
section for more details.
LOAD DISCONNECT AND REVERSE CURRENT PROTECTION
Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will
be discharge during shutdown. The advantage of TPS6125x is that this converter is disconnecting the output
from the input of the power supply when it is disabled (so called true shutdown mode). In case of a connected
battery it prevents it from being discharge during shutdown of the converter.
SOFTSTART
The TPS6125x device has an internal softstart circuit that limits the inrush current during start-up. The first step
in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the output
capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (approx. 200mA)
during this phase. This mechanism is used to limit the output current under short-circuit condition.
Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start
system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the
output voltage is reached, the regulation loop takes control and full current operation is permitted.
UNDERVOLTAGE LOCKOUT
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage
lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO
threshold plus its hysteresis of 100 mV at typ. 2.1V.
THERMAL REGULATION
The TPS6125x device contains a thermal regulation loop that monitors the die temperature during the pre-charge
phase. If the die temperature rises to high values of about 110 °C, the device automatically reduces the current
to prevent the die temperature from increasing further. Once the die temperature drops about 10 °C below the
threshold, the device will automatically increase the current to the target value. This function also reduces the
current during a short-circuit condition.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 140°C (typ.) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the
thermal shutdown minus its hysteresis, the device continuous the operation.
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APPLICATION INFORMATION
INDUCTOR SELECTION
A boost converter normally requires two main passive components for storing energy during the conversion, an
inductor and an output capacitor are required. It is advisable to select an inductor with a saturation current rating
higher than the possible peak current flowing through the power switches.
The inductor peak current varies as a function of the load, the input and output voltages and can be estimated
using Equation 4.
IOUT
VIN g D
V gh
IL(PEAK) =
+
with D = 1 - IN
2gfgL
(1 - D) g h
VOUT
(4)
Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce it's reliability.
When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating,
series resistance, and operating temperature. The inductor DC current rating should be greater (by some margin)
than the maximum input average current, refer to Equation 5 and CURRENT LIMIT OPERATION section for
more details.
IL(DC) =
VOUT
1
g
g IOUT
VIN
h
(5)
The TPS6125x series of step-up converters have been optimized to operate with a effective inductance in the
range of 0.7µH to 2.9µH and with output capacitors in the range of 10µF to 47µF. The internal compensation is
optimized for an output filter of L = 1µH and CO = 10µF. Larger or smaller inductor values can be used to
optimize the performance of the device for specific operating conditions. For more details, see the CHECKING
LOOP STABILITY section.
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e.
quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following frequencydependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
The following inductor series from different suppliers have been used with the TPS6125x converters.
Table 4. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS (in mm)
HITACHI METALS
KSLI-322512BL1-1R0
3.2 x 2.5 x 1.2 max. height
LQM32PN1R0MG0
3.2 x 2.5 x 1.0 max. height
LQM2HPN1R0MG0
2.5 x 2.0 x 1.0 max. height
DFE322512C-1R0
3.2 x 2.5 x 1.2 max. height
MURATA
TOKO
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OUTPUT CAPACITOR
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly
recommended. This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC.
To get an estimate of the recommended minimum output capacitance, Equation 6 can be used.
CMIN =
IOUT g (VOUT
-
VIN )
f g DV g VOUT
(6)
Where f is the switching frequency which is 3.5MHz (typ.) and ΔV is the maximum allowed output ripple.
With a chosen ripple voltage of 20mV, a minimum effective capacitance of 9μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
Equation 7
VESR = IOUT g RESR
(7)
An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This
is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V
and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive
at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause
lower output voltage ripple as well as lower output voltage drop during load transients but the total output
capacitance value should not exceed ca. 50µF.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 10µF X5R 6.3V 0603 MLCC capacitor would typically show an
effective capacitance of less than 4µF (under 5V bias condition, high temperature).
In applications featuring high pulsed load currents (e.g. TPS61253 based solution) it is recommended to run the
converter with a reasonable amount of effective output capacitance, for instance x2 10µF X5R 6.3V 0603 MLCC
capacitors connected in parallel.
INPUT CAPACITOR
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible
to the device. While a 4.7μF input capacitor is sufficient for most applications, larger values may be used to
reduce input current ripple without limitations.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
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CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted
when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
LAYOUT CONSIDERATIONS
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to the ground pins of the IC.
BP
GND
U1
COUT
EN
CIN
GND
VOUT
VIN
L1
Figure 37. Suggested Layout (Top)
22
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61253 TPS61254 TPS61256 TPS61258
TPS61253, TPS61254, TPS61256, TPS61258
www.ti.com
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
As power demand in portable designs is more and more important, designers must figure the best trade-off
between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction
temperature can increase significantly which could lead to bad application behaviors (i.e. premature thermal
shutdown or worst case reduce device reliability).
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists (e.g. TPS61253 or TPS61259 based solutions), special care must be
paid to thermal dissipation issues in board design. The device operating junction temperature (TJ) should be kept
below 125°C.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS61253 TPS61254 TPS61256 TPS61258
23
TPS61253, TPS61254, TPS61256, TPS61258
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
www.ti.com
TYPICAL APPLICATION
CLASS-D APA
Audio Input
1 μH
VIN
2.65 V .. 4.35 V
Audio Input
TPS61254
L
SW
VOUT
VIN
BP
EN
GND
4.5 V / VIN
EN IHF
EN HP
10 uF
4.7 μF
CLASS-AB APA
Audio Input
Audio Input
EN DC/DC
EN HP
AUDIO AMPLIFIER (HANDS-FREE, HEADPHONE)
Figure 38. Combined Audio Amplifier Power Supply
L
VIN
3.3 V .. 4.8 V
TPS61256
1 μH
5.0 V, up to 750mA
SW
VOUT
VIN
BP
EN
GND
10 uF
4.7 μF
Class-D APA
Audio Input
Audio Input
EN
EN APA
EN DC/DC
Figure 39. "Boosted" Audio Power Supply
CLASS-D APA
Audio Input L
L
1 μH
VIN
3.3 V .. 4.35 V
Audio Input L
TPS61253
5 V, up to 1500mA
SW
VOUT
VIN
BP
EN
GND
EN APA
10 uF (x2)
10 μF
CLASS-D APA
Audio Input R
EN DC/DC
Audio Input R
EN APA
HIGH-POWER CLASS-D AUDIO AMPLIFIER
Figure 40. "Boosted" Stereo Audio Power Supply
24
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61253 TPS61254 TPS61256 TPS61258
TPS61253, TPS61254, TPS61256, TPS61258
www.ti.com
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
4.7µF
CLASS-D APA
Audio Input L
Audio Input L
EN APA
TPS61253
L
1 μH
5 V, up to 1500mA
SW
VOUT
VIN
BP
EN
GND
4.7µF
VIN
3.3 V .. 4.35 V
10 µF (x2)
10 μF
CLASS-D APA
Audio Input R
Audio Input R
EN DC/DC
EN APA
HIGH-POWER CLASS-D AUDIO AMPLIFIER
TPD4S214
VOTG_IN
VUSB
VBUS
100nF
Data
4.7µF
5V, 500mA
USB-OTG Port
EN
DET
D+
FLT
D-
ADJ
ID
GND
VIO
USB PHY
Figure 41. Single Cell Li-Ion Power Solution for Tablet PCs featuring
"Boosted" Audio Power Supply and USB-OTG I/F
TPS22945
IN
OUT
5V HDMI Power
1 μF
100nF
Data
5V, 100mA
HDMI Port
Data
5V, 500mA
USB Port #1
Data
5V, 500mA
USB Port #2
Enable DC/DC
Enable USB, HDMI
VIO
OC
≥ 1000µs
≥ 0µs
Enable HDMI
ON
GND
L
VIN
3.2 V .. 5.25 V
1 μH
TPS61259
L
TPS2052B
IN
VOUT
OUT1
5V USB Power
100nF
VIN
BP
EN
GND
100nF
150µF
(1)(2)
150µF
(1)(2)
10 uF
4.7 μF
OC1
Enable USB1
EN1
OUT2
5V USB Power
OC2
Enable USB2
100nF
EN2
GND
Enable DC/DC
(1)
Requirement for USB host applications.
Downstream facing ports should be bypassed with 120µF min. per hub.
(2)
Bypass capacitor should be tantalum type (>10V rated voltage).
VIO
Figure 42. Single Cell Li-Ion Power Solution for Tablet PCs featuring x2 USB Host Ports, HDMI I/F
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS61253 TPS61254 TPS61256 TPS61258
25
TPS61253, TPS61254, TPS61256, TPS61258
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
www.ti.com
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
D
A3
A2
A1
B3
B2
B1
C3
C2
C1
CHIP SCALE PACKAGE
(TOP VIEW)
YMS
CC
LLLL
A1
E
Code:
•
YM - 2 digit date code
•
S - assembly site code
•
CC - chip code (see ordering table)
•
LLLL - lot trace code
PACKAGE DIMENSIONS
The dimensions for the YFF-9 package are shown in Table 5. See the package drawing at the end of this data
sheet.
Table 5. YFF-9 Package Dimensions
26
Packaged Devices
D
E
TPS6125xYFF
1.206 ±0.03 mm
1.306 ±0.03 mm
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS61253 TPS61254 TPS61256 TPS61258
TPS61253, TPS61254, TPS61256, TPS61258
www.ti.com
SLVSAG8B – SEPTEMBER 2011 – REVISED MAY 2012
REVISION HISTORY
Note: Page numbers of current revision may differ from previous versions.
Changes from Original (September 2011) to Revision A
•
Page
Changed device TPS61256 to production status ................................................................................................................. 2
Changes from Revision A (October 2011) to Revision B
Page
•
Added TPS61253 and TPS61258 to data sheet header as production devices .................................................................. 1
•
Changed devices TPS61253 and TPS61258 to production status ...................................................................................... 2
•
Changed graphic entity for Figure 5 ..................................................................................................................................... 9
•
Changed graphic entity for Figure 12 ................................................................................................................................. 10
•
Changed graphic entity for Figure 15 ................................................................................................................................. 11
•
Changed graphic entity for Figure 25 ................................................................................................................................. 14
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS61253 TPS61254 TPS61256 TPS61258
27
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS61253YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61253YFFT
ACTIVE
DSBGA
YFF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61254YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61254YFFT
ACTIVE
DSBGA
YFF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61256YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61256YFFT
ACTIVE
DSBGA
YFF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61258YFFR
ACTIVE
DSBGA
YFF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TPS61258YFFT
ACTIVE
DSBGA
YFF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS61253YFFR
DSBGA
YFF
9
3000
180.0
8.4
TPS61254YFFR
DSBGA
YFF
9
3000
180.0
TPS61254YFFT
DSBGA
YFF
9
250
180.0
TPS61256YFFR
DSBGA
YFF
9
3000
TPS61256YFFT
DSBGA
YFF
9
TPS61258YFFR
DSBGA
YFF
TPS61258YFFT
DSBGA
YFF
1.41
1.31
0.69
4.0
8.0
Q1
8.4
1.41
1.31
0.69
4.0
8.0
Q1
8.4
1.41
1.31
0.69
4.0
8.0
Q1
180.0
8.4
1.41
1.31
0.69
4.0
8.0
Q1
250
180.0
8.4
1.41
1.31
0.69
4.0
8.0
Q1
9
3000
180.0
8.4
1.41
1.31
0.69
4.0
8.0
Q1
9
250
180.0
8.4
1.41
1.31
0.69
4.0
8.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS61253YFFR
DSBGA
YFF
9
3000
210.0
185.0
35.0
TPS61254YFFR
DSBGA
YFF
9
3000
210.0
185.0
35.0
TPS61254YFFT
DSBGA
YFF
9
250
210.0
185.0
35.0
TPS61256YFFR
DSBGA
YFF
9
3000
210.0
185.0
35.0
TPS61256YFFT
DSBGA
YFF
9
250
210.0
185.0
35.0
TPS61258YFFR
DSBGA
YFF
9
3000
210.0
185.0
35.0
TPS61258YFFT
DSBGA
YFF
9
250
210.0
185.0
35.0
Pack Materials-Page 2
X: Max = 1.356 mm, Min =1.256 mm
Y: Max = 1.256 mm, Min =1.156 mm
X: Max = 1.356 mm, Min =1.256 mm
Y: Max = 1.256 mm, Min =1.156 mm
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