TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 3A High Efficient Synchronous Step Down Converter with DCS™ Control Check for Samples: TLV62090 FEATURES DESCRIPTION • • • • • • • • • • • • • • The TLV62090 device is a high frequency synchronous step down converter optimized for small solution size, high efficiency and suitable for battery powered applications. To maximize efficiency, the converter operates in PWM mode with a nominal switching frequency of 1.4 MHz and automatically enters Power Save Mode operation at light load currents. When used in distributed power supplies and point of load regulation, the device allows voltage tracking to other voltage rails and tolerates output capacitors ranging from 10 µF up to 150 µF and beyond. Using the DCS™ Control topology the device achieves excellent load transient performance and accurate output voltage regulation. 1 2 2.5 V to 5.5 V Input Voltage Range DCS™ Control 95% Converter Efficiency Power Save Mode 20 µA Operating Quiescent Current 100% Duty Cycle for Lowest Dropout 1.4 MHz Typical Switching Frequency 0.8 V to VIN Adjustable Output Voltage Output Discharge Function Adjustable Softstart Two Level Short Circuit Protection Output Voltage Tracking Wide Output Capacitance Selection Available in 3x3mm 16 Pin QFN Package The output voltage start-up ramp is controlled by the softstart pin, which allows operation as either a standalone power supply or in tracking configurations. Power sequencing is also possible by configuring the Enable and Power Good pins. In Power Save Mode, the device operates at typically 20 µA quiescent current. Power Save Mode is entered automatically and seamlessly maintaining high efficiency over the entire load current range. APPLICATIONS • • • • • Distributed Power Supplies Notebook, Netbook Computers Hard Disk Drivers Processor Supply Battery Powered Applications 100 12 11 C1 22mF 10 3 C3 10nF 13 7 8 PVIN SW SW PVIN AVIN VOS 1 Vout 1.8V/3A R1 200k 2 C2 22mF 16 DEF FB 5 EN PG 4 CP SS CN AGND 6 R2 160k R3 500k Power Good 9 C4 10nF PGND PGND 14 95 L1 1mH 90 Efficiency (%) TLV62090 Vin 2.5V to 5.5V 85 80 75 70 65 60 55 15 50 100m VOUT = 3.3 V L = 1 µH f = 1.4 MHz 1 VIN = 3.7 V VIN = 4.2 V VIN = 5 V 10 100 I load (mA) 1k 10k G002 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) TA ORDERING PACKAGE PACKAGE MARKING -40°C to 85°C TLV62090 RGT SBV For detailed ordering information please see the PACKAGE OPTION ADDENDUM section at the end of the datasheet. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN Voltage range Power Good sink current ESD rating –0.3 7 SW, PG –0.3 VIN+0.3 V PG 1 mA Human Body Model 2 kV 500 V Charged Device Model V See the Thermal Table Operating junction temperature range, TJ –40 Operating ambient temperature range, TA Storage temperature range, Tstg (2) UNIT PVIN, AVIN, FB, SS, EN, DEF, VOS (2) Continuous total power dissipation (1) MAX 150 °C –40 85 °C –65 150 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION TPS62090 THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance 47 θJCtop Junction-to-case (top) thermal resistance 60 θJB Junction-to-board thermal resistance 20 ψJT Junction-to-top characterization parameter 1.5 ψJB Junction-to-board characterization parameter 20 θJCbot Junction-to-case (bottom) thermal resistance 5.3 (1) UNITS QFN (16 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS (1) MIN TYP MAX UNIT VIN Input voltage range VIN 2.5 5.5 V TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C (1) 2 See the application section for further information Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS VIN = 3.6V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range IQIN Quiescent current Not switching, FB = FB +5 %, Into PVIN and AVIN 20 Isd Shutdown current Into PVIN and AVIN 0.6 5 Undervoltage lockout threshold VIN falling 2.2 2.3 UVLO 2.5 2.1 Undervoltage lockout hysteresis Thermal shutdown Temperature rising Thermal shutdown hysteresis 5.5 V µA µA V 200 mV 150 ºC 20 ºC Control SIGNAL EN VH High level input voltage VIN = 2.5 V to 6 V VL Low level input voltage VIN = 2.5 V to 6 V Ilkg Input leakage current EN = GND or VIN RPD Pull down resistance 1 V 10 0.4 V 100 nA 400 kΩ Softstart ISS Softstart current 6.3 7.5 8.7 µA POWER GOOD Vth Power good threshold VL Low level voltage IPG PG sinking current Ilkg Leakage current Output voltage rising 95% Output voltage falling 90% I(sink) = 1mA 0.4 V 1 mA 100 nA VPG = 3.6V 10 High side FET on-resistance ISW = 500 mA 50 mΩ Low side FET on-resistance ISW = 500 mA 40 mΩ POWER SWITCH RDS(on) ILIM High side FET switch current limit fs Switching frequency 3.7 IOUT = 3 A 4.6 5.5 1.4 A MHz OUTPUT Vs Output voltage range Rod Output discharge resistor VFB Feedback regulation voltage 0.8 EN = GND, VOUT = 1.8 V VIN V 200 Ω 0.8 V VIN ≥ VOUT + 1 V, TPS62090 adjustable output version IOUT = 1 A, PWM mode -1.4% +1.4% IOUT = 0 mA, VOUT ≥ 1.2 V, PFM mode -1.4% +3% IOUT = 0 mA, VOUT < 1.2V, PFM mode -1.4% VFB Feedback voltage accuracy (1) (2) IFB Feedback input bias current VFB = 0.8V, TPS62090 adjustable output version Line regulation VOUT = 1.8 V, PWM operation 0.016 %/V Load regulation VOUT = 1.8 V, PWM operation 0.04 %/A (1) (2) +3.7% 10 100 nA For output voltages < 1.2 V, use a 2 x 22 µF output capacitance to achieve +3% output voltage accuracy in PFM mode. Conditions: L = 1 µH, COUT = 22 µF. For more information, see the Power Save Mode Operation section of this data sheet. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 3 TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 www.ti.com DEVICE INFORMATION PG 4 EN 14 13 12 11 Exposed Thermal Pad* 10 5 6 7 8 CN 3 PGND DEF 15 CP 2 PGND SW 16 AGND 1 FB SW VOS 16 PIN 3x3mm QFN TOP VIEW 9 PVIN PVIN AVIN SS NOTE: *The exposed Thermal Pad is connected to AGND. PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. SW 1, 2 I Switch pin of the power stage. DEF 3 I This pin is used for internal logic and needs to be pulled high. This pin should not be left floating. PG 4 O Power good open drain output. This pin is high impedance if the output voltage is within regulation. This pin is pulled low if the output is below its nominal value. The pull up resistor can not be connected to any voltage higher than the input voltage of the device. FB 5 Feedback pin of the device. AGND 6 Analog ground. CP 7 Internal charge pump flying capacitor. Connect a 10 nF capacitor between CP and CN. CN 8 Internal charge pump flying capacitor. Connect a 10 nF capacitor between CP and CN. SS 9 AVIN 10 PVIN 11,12 EN 13 PGND 14,15 VOS 16 Thermal Pad 4 I Soft-start control pin. A capacitor is connected to this pin and sets the softstart time. Leaving this pin floating sets the minimum start-up time. Bias supply input voltage pin. Power supply input voltage pin. Device enable. To enable the device this pin needs to be pulled high. Pulling this pin low disables the device. This pin has an active pull down resistor of typically 400 kΩ. Power ground connection. Output voltage sense pin. This pin needs to be connected to the output voltage. The exposed thermal pad is connected to AGND. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 FUNCTIONAL BLOCK DIAGRAM CP PG PVIN CN Charge Pump for Gate driver VFB Hiccup current limit #32 counter VREF High Side Current Sense Bandgap Undervoltage Lockout Thermal shutdown AVIN PVIN EN M1 400 kΩ SW MOSFET Driver Anti Shoot Through Converter Control Logic AGND SW DEF M2 PGND PGND Comparator ramp Timer ton Direct Control and Compensation VOS Error Amplifier FB Vref 0.8V Vin DCS - Control™ 200Ω Iss Voltage clamp Vref SS ÷1.56 EN Output voltage discharge logic M3 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 5 TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 www.ti.com Table 1. List of components REFERENCE DESCRIPTION MANUFACTURER TLV62090 High efficient step down converter Texas Instruments L1 Inductor: 1uH Coilcraft XFL4020-102 C1 Ceramic capacitor: 22uF (6.3V, X5R, 0805) C2 Ceramic capacitor: 22uF (6.3V, X5R, 0805) C3, C4 Ceramic capacitor Standard R1, R2, R3 Resistor Standard TLV62090 Vin 2.5V to 5.5V 12 11 C1 10 3 13 L1 1 PVIN SW PVIN SW AVIN VOS DEF FB EN PG 4 CP SS CN AGND 6 Vout 2 R1 16 R2 5 C3 7 8 C2 R3 Power Good 9 C4 PGND PGND 14 15 Figure 1. Parametric Measurement Circuit 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS FIGURE vs load current (VO = 3.3 V) Figure 2 Efficiency vs load current (VO = 1.8 V) Figure 3 Efficiency vs load current (VO = 1.05 V) Figure 4 Output voltage vs load current (VO = 1.8 V) Figure 5 High Side FET on-resistance vs input voltage Figure 6 Switching frequency vs load current (VO = 1. 8 V) Figure 7 Switching frequency vs input voltage (VO = 1.8 V) Figure 8 Quiescent current vs input voltage ( VO = 1.8 V) Figure 9 PWM operation VO = 1.8 V Figure 10 PFM operation VO = 1.8 V Figure 11 Load sweep VO = 1.8 V Figure 12 Start-up VO = 1.8 V, CSS = 10 nF Figure 13 Shutdown VO = 1.8 V Figure 14 Hiccup short circuit protection VO = 1.8 V Figure 15 Hiccup Short circuit protection VO = 1.8 V, recovery after short circuit Figure 16 Load transient response VO = 1.8 V, 300 mA to 2.5 A Figure 17 Load transient response VO = 1.8 V, 300 mA to 2.5 A Figure 18 Load transient response VO = 1.8 V, 20 mA to 1 A Figure 19 100 100 95 95 90 90 85 85 Efficiency (%) Efficiency (%) Efficiency 80 75 70 65 60 55 50 100m 80 75 70 65 VOUT = 3.3 V L = 1 µH f = 1.4 MHz 1 VIN = 3.7 V VIN = 4.2 V VIN = 5 V 10 100 I load (mA) 1k 55 50 100m 10k 1.83 95 1.825 Output Voltage (V) Efficiency (%) 90 85 80 75 70 55 50 100m VOUT = 1.05 V L = 1.0 µH f = 1.4 MHz 1 10 100 I load (mA) VIN = 2.7 V VIN = 3.7 V VIN = 4.2 V VIN = 5 V 1k 1.82 VOUT = 1.8 V L = 1 µH f = 1.4 MHz 1k 10k G003 VIN = 5.0 V VIN = 4.2 V VIN = 3.7 V 1.815 1.81 1.805 1.8 1.795 10k 1.79 100m G005 Figure 4. Efficiency vs Load Current 10 100 I load (mA) Figure 3. Efficiency vs Load Current 100 60 1 G002 Figure 2. Efficiency vs Load Current 65 VIN = 2.7 V VIN = 3.7 V VIN = 4.2 V VIN = 5 V VOUT = 1.8 V L = 1 µH f = 1.4 MHz 60 1 10 100 I load (mA) 1k 10k G007 Figure 5. Output Voltage vs Load Current Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 7 TLV62090 www.ti.com 70 1600 60 1400 1200 50 Frequency (kHz) Resistance (Ω) SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 40 30 20 2 2.5 3 3.5 4 4.5 5 Input Voltage (V) 5.5 6 VOUT = 1.8 V L = 1 µH f = 1.4 MHz 800 600 400 TA = 85°C TA = 25°C TA = −40°C 10 0 1000 VIN = 3.6 V VIN = 4.2 V VIN = 2.8 V 200 0 6.5 0 400m 800m 1.2 1.6 2 Load Current (A) G024 Figure 6. High Side FET On-Resistance vs Input Voltage 2.4 2.8 3.2 G009 Figure 7. Switching Frequency vs Load Current 2 25 1.75 20 Current (µA) Frequency (MHz) 1.5 1.25 1 0.75 VOUT = 1.8 V L = 1 µH f = 1.4 MHz IOUT = 1 A 0.5 0.25 0 2 2.5 3 3.5 4 4.5 Voltage (V) 5 5.5 6 15 10 VOUT = 1.8 V L = 1 µH f = 1.4 MHz 5 6.5 0 2 G010 Figure 8. Switching Frequency vs Input Voltage Vsw 2 V/div Vo 20 mV/div Vo 20 mV/div Vin = 3.7 V Vo=1.8 V/3 A f = 1.4 MHz, L = 1 µH 400 ns/div Iinductor 500 mA/div G012 Figure 10. PWM Operation 8 3 3.5 4 4.5 Voltage (V) 5 5.5 6 6.5 G011 Figure 9. Quiescent Current vs Input Voltage Vsw 2 V/div Iinductor 1 A/div 2.5 TA = 85 °C TA = 25 °C TA = −40 °C Vin = 3.7 V Vo = 1.8 V/100 mA f = 1.4 MHz, L = 1 µH 1 µs/div G013 Figure 11. PFM Operation Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 Vo 20 mV/div Io 1 A/div Iinductor 500 mA/div VEN 2 V/div Vo 1 V/div Vin = 3.7 V Vo = 1.8 V f = 1.4 MHz, L = 1 µH Vin = 3.7 V Vo = 1.8 V/600 mA L = 1 µH Css = 10 nF Iinductor 50 mA/div 200 µs/div 400 µs/div G015 Figure 12. Load Sweep Vin = 3.7 V Vo = 1.8 V/no load L = 1 µH Io 2 A/div Iinductor 200 mA/div Iinductor 1 A/div 2 ms/div Vin = 3.7 V Vo = 1.8 V f = 1.4 MHz, L = 1 µH Vo 1 V/div VEN 2 V/div Vo 1 V/div 40 µs/div G018 Figure 14. Shutdown G019 Figure 15. Hiccup Short Circuit Protection Vo 1 V/div Vo 50 mV/div Io 2 A/div Io 1 A/div Vin = 3.7 V Vo = 1.8 V f = 1.4 MHz, L = 1 µH Iinductor 1 A/div Iinductor 1 A/div 400 µs/div Vin = 3.7 V Vo = 1.8 V,0.3 A to 2.5 A f = 1.4 MHz, L = 1 µH Co = 22 µF 4 µs/div G020 Figure 16. Hiccup Short Circuit Protection G021 Figure 17. Load Transient Response Vo 50 mV/div Vo 50 mV/div Iinductor 1 A/div G017 Figure 13. Start-Up Io 1 V/div Vin = 3.7 V Vo = 1.8 V, 0.3 A to 2.5 A f = 1.4 MHz, L = 1 µH Co = 22 µF Iinductor 500 A/div 40 µs/div G022 Figure 18. Load Transient Response Vin = 3.7 V Vo = 1.8 V, 20 mA to 1 A f = 1.4 MHz, L = 1 µH Co = 22 µF 100 µs/div Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 G023 Figure 19. Load Transient Response 9 TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 www.ti.com DETAILED DESCRIPTION Operation The TLV62090 synchronous switched mode converter is based on DCS™ Control (Direct Control with Seamless transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of hysteretic and voltage mode control. The DCS™ Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load conditions and in Power Save Mode at light load currents. In PWM, the converter operates with its nominal switching frequency of 1.4 MHz having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC quiescent current to achieve high efficiency over the entire load current range. DCS™ Control supports both operation modes (PWM and PFM) using a single building block having a seamless transition from PWM to Power Save Mode without effects on the output voltage. The TLV62090 offers excellent DC voltage regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits. PWM Operation At medium to heavy load currents, the device operates with pulse width modulation (PWM) at a nominal switching frequency of 1.4 MHz. As the load current decreases, the converter enters the Power Save Mode operation reducing its switching frequency. The device enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). Power Save Mode Operation As the load current decreases, the converter enters Power Save Mode operation. During Power Save Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current while maintaining high efficiency. The Power Save Mode is based on a fixed on-time architecture following Equation 1. V OUT × 360ns × 2 V IN 2×I OUT f = æ ö V -V V V 2 IN OUT OUT ÷ x IN ton ç 1 + ç ÷ V L OUT è ø ton = (1) In Power Save Mode the output voltage rises slightly above the nominal output voltage in PWM mode, as shown in Figure 5. This effect can be reduced by increasing the output capacitance or the inductor value. This effect can also be reduced by programming the output voltage of the TLV62090 lower than the target value. As an example, if the target output voltage is 3.3 V, then the TLV62090 can be programmed to 3.3V - 0.8%. As a result the output voltage accuracy is now -2.2% to +2.2% instead of -1.4% to 3%. The output voltage accuracy in PFM operation is reflected in the electrical specification table and given for a 22 µF output capacitance. Low Dropout Operation (100% Duty Cycle) The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage where the output voltage falls below its nominal regulation value is given by: VIN(min) = VOUT(max) + IOUT x ( RDS(on) + RL ) 10 (2) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 Where RDS(on) = High side FET on-resistance RL = DC resistance of the inductor VOUT(max) = nominal output voltage plus maximum output voltage tolerance Softstart (SS) To minimize inrush current during start up, the device has an adjustable softstart depending on the capacitor value connected to the SS pin. The device charges the softstart capacitor with a constant current of typically 7.5 µA. The feedback voltage follows this voltage with a fraction of 1.56 until the internal reference voltage of 0.8 V is reached. The softstart operation is completed once the voltage at the softstart capacitor has reached typically 1.25 V. The soft-start time can be calculated using Equation 3. The larger the softstart capacitor the longer the softstart time. The relation between softstart voltage and feedback voltage can be estimated using Equation 4. 1.25V tSS = CSS x 7.5μA (3) VFB = VSS 1.56 (4) This is also the case for the fixed output voltage option having the internal regulation voltage. Leaving the softstart pin floating sets the minimum start-up time. Start-up Tracking (SS) The softstart pin can also be used to implement output voltage tracking with other supply rails. The internal reference voltage follows the voltage at the softstart pin with a fraction of 1.56 until the internal reference voltage of 0.8 V is reached. The softstart pin can be used to implement output voltage tracking as shown in Figure 20. TLV62090 Vin 2.5V to 5.5V 12 11 C1 22mF 10 3 C3 10nF 13 7 8 V1 Output of external DC DC converter PVIN SW PVIN SW AVIN VOS 1 L1 1mH 2 Vout 1.5V/3A R1 140k C2 22mF 16 DEF FB 5 EN PG 4 CP SS CN AGND 6 9 R2 160k R3 500k Power Good PGND PGND 14 15 R3 59k R4 43k Figure 20. Output Voltage Tracking In Figure 20, the output V2 tracks the voltage applied to V1. The voltage tracks simultaneously when following conditions are met: R3 R1 = x 1.56 R4 R2 (5) As the fraction of R3/R4 becomes larger the voltage V1 ramps up faster than V2, and if it gets smaller then the ramp is slower than V2. R4 needs to be determined first using Equation 6. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 11 TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 R4 = www.ti.com 1.25V 300μA (6) In the calculation of R4, 300 µA current is used to achieve sufficient accuracy by taking into account the typical 7.5 µA soft-start current. After determining R4, R3 can be calculated using Equation 5. Short Circuit Protection (Hiccup-Mode) The device is protected against hard short circuits to GND and over-current events. This is implemented by a two level short circuit protection. During start-up and when the output is shorted to GND the switch current limit is reduced to 1/3 of its typical current limit of 4.6 A. Once the output voltage exceeds typically 0.6 V the current limit is released to its nominal value. The full current limit is implemented as a hiccup current limit. Once the internal current limits is triggered 32 times the device stops switching and starts a new start-up sequence after a typical delay time of 66 µS passed by. The device will go through these cycles until the high current condition is released. Output Discharge Function To make sure the device starts up under defined conditions, the output gets discharged via the VOS pin with a typical discharge resistor of 200 Ω whenever the device shuts down. This happens when the device is disabled or if thermal shutdown, undervoltage lockout or short circuit hiccup-mode is triggered. Power Good Output (PG) The power good output is low when the output voltage is below its nominal value. The power good will become high impedance once the output is within 5% of regulation. The PG pin is an open drain output and is specified to typically sink up to 1 mA. This output requires a pull-up resistor to be monitored properly. The pull-up resistor cannot be connected to any voltage higher than the input voltage of the device. Undervoltage Lockout (UVLO) To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts down the device at input voltages lower than typically 2.2 V with a 200 mV hysteresis. Thermal Shutdown The device goes into thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C hysteresis. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 APPLICATION INFORMATION DESIGN PROCEDURE The first step is the selection of the output filter components. To simplify this process, and Table 2 outline possible inductor and capacitor value combinations. Table 2. Output Filter Selection INDUCTOR VALUE [µH] (1) OUTPUT CAPACITOR VALUE [µF] (2) 10 0.47 22 47 100 150 √ √ √ √ 1.0 √ √ (3) √ √ √ 2.2 √ √ √ √ √ 3.3 (1) (2) (3) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and –30%. Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and –50%. Typical application configuration. Other check mark indicates alternative filter combinations Inductor Selection The inductor selection is affected by several parameter like inductor ripple current, output voltage ripple, transition point into Power Save Mode, and efficiency. See Table 3 for typical inductors. Table 3. Inductor Selection INDUCTOR VALUE COMPONENT SUPPLIER SIZE (LxWxH mm) Isat/DCR 0.6 µH Coilcraft XAL4012-601 4 x 4 x 2.1 7.1A/9.5 mΩ 1 µH Coilcraft XAL4020-102 4 x 4 x 2.1 5.9A/13.2 mΩ 1 µH Coilcraft XFL4020-102 4 x 4 x 2.1 5.1 A/10.8 mΩ 0.47 µH TOKO DFE252012 R47 2.5 x 2 x 1.2 3.7A/39 mΩ 1 µH TOKO DFE252012 1R0 2.5 x 2 x 1.2 3.0A/59 mΩ 0.68 µH TOKO DFE322512 R68 3.2 x 2.5 x 1.2 3.5A/37 mΩ 1 µH TOKO DFE322512 1R0 3.2 x 2.5 x 1.2 3.1A/45 mΩ In addition, the inductor has to be rated for the appropriate saturation current and DC resistance (DCR). The inductor needs to be rated for a saturation current as high as the typical switch current limit, of 4.6 A or according to Equation 7 and Equation 8. Equation 7 and Equation 8 calculate the maximum inductor current under static load conditions. The formula takes the converter efficiency into account. The converter efficiency can be taken from the data sheet graph`s or 80% can be used as a conservative approach. The calculation must be done for the maximum input voltage where the peak switch current is highest. I =I + L OUT ΔI L 2 (7) æ ö V V OUT x ç 1 - OUT ÷ ç η V x η÷ IN è ø I =I + L OUT 2x f xL (8) where ƒ = Converter switching frequency (typical 1.4 MHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as an conservative assumption) Note: The calculation must be done for the maximum input voltage of the application Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current. A margin of 20% needs to be added to cover for load transients during operation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 13 TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 www.ti.com Input and Output Capacitor Selection For best output and input voltage filtering, low ESR ceramic capacitors are recommended. The input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device. A 22 µF or larger input capacitor is recommended. The output capacitor value can range from 10 µF up to 150 µF and beyond. The recommended typical output capacitor value is 22 µF and can vary over a wide range as outline in the output filter selection table. Setting the Output Voltage The output voltage is set by an external resistor divider according to the following equations: R1 ö R1 ö æ æ VOUT = VFB ´ ç 1 + = 0.8 V ´ ç 1 + ÷ R2 ø R2 ÷ø è è (9) V 0.8 V R2 = FB = » 160 kΩ IFB 5 μA (10) æV ö æV ö R1 = R2 ´ ç OUT - 1÷ = R2 ´ ç OUT - 1÷ è 0.8V ø è VFB ø (11) When sizing R2, in order to achieve low quiescent current and acceptable noise sensitivity, use a minimum of 5 µA for the feedback current IFB. Larger currents through R2 improve noise sensitivity and output voltage accuracy. Layout Guideline It is recommended to place all components as close as possible to the IC. The VOS connection is noise sensitive and needs to be routed as short and directly to the output terminal of the inductor. The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a single joint connection at the exposed thermal pad of the package. This minimizes switch node jitter. The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of switching waveforms into other traces and circuits. See the evaluation module User Guide (SLVU670) for an example of component placement, routing and thermal design. TYPICAL APPLICATIONS TLV62090 Vin 2.5V to 5.5V 12 11 C1 22mF 10 3 C3 10nF 13 7 8 PVIN SW PVIN SW AVIN VOS 1 L1 1mH Vout 1.8V/3A R1 200k 2 C2 22mF 16 DEF FB 5 EN PG 4 CP SS CN AGND 6 R2 160k R3 500k Power Good 9 C4 10nF PGND PGND 14 15 Figure 21. 1.8 V Adjustable Version 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 TLV62090 www.ti.com SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 L1 1mH TLV62090 Vin 2.5V to 5.5V 12 11 C1 22mF 10 3 C3 10nF 13 7 8 PVIN SW PVIN SW AVIN VOS Vout 1.5V/3A 1 R1 140k 2 C2 22mF 16 DEF FB 5 EN PG 4 CP SS CN AGND 6 R2 160k R3 500k Power Good 9 C4 10nF PGND PGND 14 15 Figure 22. 1.5 V Adjustable Version L1 1uH TLV62090 Vin 2.5V to 5.5V 12 11 C1 22mF 10 3 C3 10nF 13 7 8 PVIN SW PVIN SW AVIN VOS Vout 1.2V/3A 1 R1 75k 2 C2 22mF 16 DEF FB 5 EN PG 4 CP SS CN AGND 6 R2 150k R3 500k Power Good 9 C4 10nF PGND PGND 14 15 Figure 23. 1.2 V Adjustable Version Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 15 TLV62090 SLVSBB9B – MARCH 2012 – REVISED APRIL 2012 www.ti.com L1 1mH TLV62090 Vin 2.5V to 5.5V 12 11 C1 22mF 10 3 C3 10nF 13 7 8 PVIN SW PVIN SW AVIN VOS Vout 1.05V/3A 1 R1 68k 2 C2 22mF 16 DEF FB 5 EN PG 4 CP SS CN AGND 6 R2 220k R3 500k Power Good 9 C4 10nF PGND PGND 14 15 Figure 24. 1.05 V Adjustable Version REVISION HISTORY Changes from Original (March 2012) to Revision A Page • Changed Vin From: 2.5V to 6V To: 2.5V to 5.5V in Figure 1 ............................................................................................... 6 • Changed Vin From: 2.5V to 6V To: 2.5V to 5.5V in Figure 20 ........................................................................................... 11 • Changed Vin From: 2.5V to 6V To: 2.5V to 5.5V in Figure 21, Figure 22, Figure 23, and Figure 24 ................................ 14 Changes from Revision A (March 2012) to Revision B • 16 Page Changed the Input voltage range MAX value From: 6V To 5.5V ......................................................................................... 3 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62090 PACKAGE OPTION ADDENDUM www.ti.com 14-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLV62090RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV62090RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV62090RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TLV62090RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV62090RGTR QFN RGT 16 3000 346.0 346.0 29.0 TLV62090RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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