UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 High Speed PWM Controller PRELIMINARY FEATURES DESCRIPTION • Compatible with Voltage or Current Mode Control Methods • Practical Operation at Switching Frequencies to 4MHz • 50ns Propagation Delay to Output • High Current Complementary Outputs • Programmable Dead Time and Frequency Oscillator The UCC3829 is a BiCMOS High Speed PWM Controller IC. It is optimized for high frequency switched mode power supply applications. The IC can be used in both voltage mode and current mode control applications. Care was given to minimizing the propagation delays through the comparators and logic circuitry while maximizing the bandwidth and slew rate of the error amplifier. The oscillator frequency and deadtime can be programmed via two external resistors and a capacitor. The undervoltage lockout threshold can be programmed using an external resistor divider. The current limit and overcurrent threshold can be set externally. The IC is available in push-pull (-1), single ended (-2), or complementary (-3) output configuration. • Pulse by Pulse Current Limiting • Latched Overcurrent Comparator with Full Cycle Restart • Programmable Undervoltage Lockout (UVLO) • Adjustable Blanking for Leading Edge Noise Tolerance Fault protection circuitry includes undervoltage detection for the internal bias supply, and overcurrent detection. The fault detection logic sets a latch that ensures full discharge of the soft start capacitor before allowing a restart. While the fault latch is set, the outputs are in a low state. In the event of continuous faults, the soft start capacitor is fully charged before discharging to insure that the fault frequency does not exceed the designed soft start period. BLOCK DIAGRAM BISYNC 9 18 VDD 15 OUTA 14 OUTB 13 PGND 11 CL+ 12 CL– 17 UVLO 23 VREF VBIAS RT1 8 CT 7 RT2 CLOCK S Q R Q > Q T 6 Q VBIAS 4V LEB 19 1.5V 1.2V RAMP 5 0.9V PWCONT 4 EAOUT 3 NINV 1 INV 2 1.25V VBIAS 14.2V/9V SS 10 1V S RD Q GND 18 3V/2.5V Q 3V REFERENCE 2.1V UDG-98043 SLUS390 - MARCH 1998 UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Current (OUTA, OUTB, PGND, VCC) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulsed (0.5µsec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.2V Analog Inputs INV, NINV, RAMP, SS . . . . . . . . . . . . . . . . . . . . . –0.3 to 7V CL+, CL-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to 3V Error Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . . 5mA Error Amplifier Output Capacitance . . . . . . . . . . . . . . . . . . 20pF Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C UCC 829 – TEMPERATURE & PACKAGE SELECTION GUIDE TABLE TEMPERATURE RANGE Unless otherwise indicated, voltages are referenced to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. AVAILABLE PACKAGES UCC1829-X –55°C to +125°C J UCC2829-X –40°C to +85°C N, DW, Q UCC3829-X 0°C to +70°C N, DW, Q PART VERSION TABLE PART NUMBER OUTPUT OUT A/B PHASE OUTPUT FREQUENCY UCCX829-1 Push-Pull 180° Out of Phase FCT/2 UCCX829-2 Dual Single-Ended In Phase FCT UCCX829-3 Non-Overlapping Complimentary OUTB = OUTA FCT CONNECTION DIAGRAMS DIL-20, SOIC-20 (Top View) N, DW and J Packages PLCC-20 (Top View) Q Package NINV NINV 1 20 VREF INV 2 19 LEB EAOUT 3 18 GND PWCONT 4 17 UVLO RAMP 5 16 INV EAOUT 3 VDD RT2 6 15 OUTA CT 7 14 OUTB RT1 8 13 PGND BISYNC 9 12 CL– SS 10 11 CL+ VREF LEB 1 20 19 PWCONT 4 18 GND RAMP 5 17 UVLO RT2 6 16 VDD CT 7 15 OUTA RT1 8 14 OUTB 9 BISYNC SS 2 2 10 11 12 13 PGND CL– CL+ UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, RT1 = 34.8kΩ, CT = 470pF, RT2 = 392Ω, VDD = 12V, Over Full Temperature Range and TA = TJ. PARAMETER TEST CONDITIONS MIN TYP TJ = 25°C, No Load, Output Off 2.97 3 Over Temperature, No Load, Output Off 2.94 MAX UNITS Reference Section Output Voltage Line Regulation VDD = 5V to 14.5V, Output Off, No Load, (Note 2) 35 V 3.06 V 50 mV Load Regulation 0 < IREF < 5mA 10 mV Total Output Variation Line, Load, Temperature = 0°C to 70°C, (Note 1) 2.93 3.07 V Line, Load, Temperature = –55°C to +125°C, (Note 1) 2.90 3.10 V VREF = 0 –25 Initial Accuracy TJ = 25°C 360 Total Variation Line, Temperature (Note 1) 320 Short Circuit Current 2 3.03 mA Oscillator Section Temperature Stability TMIN < TA < TMAX (Note 1) Initial Accuracy, 1MHz RT1 = 25.7k, CT = 150pF, TJ = 25°C, (Note 1) 0.9 Total Variation, 1MHz RT1 = 25.7k, CT = 150pF, Line, Temperature (Note 1) 0.8 Ramp Peak Voltage 1.8 Ramp Valley Voltage Peak To Peak Voltage 0.85 BISYNC Output Source Current VBISYNC = VDD – 0.5V BISYNC Output Sink Current VBISYNC = 0.5V BISYNC Input Threshold 400 440 kHz 480 kHz 5 10 % 1 1.1 MHz 1.2 MHz 2 2.2 V 1 1.5 V 1 1.15 V –2 –1.5 mA 2 V 5 mV 60 140 1 1.5 A Error Amplifier Section Input Offset Voltage Input Bias Current –1 Input Offset Current Open Loop Gain 70 CMRR 1.5V < VCM < 4.5V PSRR 5V < VDD < 14.5V 75 Output Sink Current VEAOUT = 1V 300 Output Source Current VEAOUT = 4V Output High Voltage IEAOUT = –300µA Output Low Voltage IEAOUT = 300µA Gain Bandwidth Product VDD = 12V, TJ = 25°C µA nA 80 dB 75 dB dB µA 500 –500 3 –300 5 0.6 Slew Rate 1 250 µA V 1 V 5 7 MHz 1.5 2 V/µs PWM Comparator Section Input Bias Current V(RAMP) –60 Minimum Duty Cycle 400kHz Maximum Duty Cycle (UCCX829-1) 400kHz, RT2 Resistor = 200Ω 42.5 Maximum Duty Cycle (UCCX829-2, -3) 400kHz, RT2 Resistor = 200Ω 85 1 0 Delay to Output µA % % % 50 100 ns –10 µA Current Limit Fault Section Soft Start Charge Current Soft Start Complete Threshold –40 SS Pin (Note 1) 3 3 V UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, RT1 = 34.8kΩ, CT = 470pF, RT2 = 392Ω, VDD = 12V, Over Full Temperature Range and TA = TJ. PARAMETER TEST CONDITIONS MIN TYP Restart Discharge Current 10 Restart Threshold 0.8 1 MAX UNITS 40 µA 1.2 V Current Limit Threshold Relative to CL– 0.8 0.875 1.1 V Overcurrent Threshold Relative to CL– 1.1 1.25 1.4 V Current Limit Delay to Output 50 100 ns VDD = 5V 100 400 ns Output Low Saturation IOUT = 200mA 0.5 1.0 V Output High Saturation IOUT = –100mA 0.5 1.0 V UVLO Output Low Saturation At 10mA 0.1 0.5 V Rise Time CLOAD = 1nF, TJ = 25°C 20 40 ns Fall Time CLOAD = 1nF, TJ = 25°C 10 20 ns Output Section (OUTA, OUTB) Output Source Current VOUT = 0, TJ = 25°C (Note 1) Output Sink Current VOUT = 12V, TJ = 25°C (Note 1) Complementary Delay Time (Delay 2) (UCCX829 -3 Only) (Note 1) –0.75 A 1.5 A 50 150 ns 3.1 V Undervoltage Lockout UVLO Enable Threshold 2.9 3 UVLO Hysteresis 0.3 0.5 0.7 V VDD UVLO Enable Threshold 13.5 14.5 V VDD UVLO Hysteresis 3.5 7 V Supply Section VDD Range No Load 14.5 V Startup Current VUVLO = 2V, VDD = 13.5V 4.25 3 5 mA IDD 400kHz, No Load 8 12 mA Note 1: Guaranteed by design. Not 100% tested in production. Note 2: Refer to Figure 1. TYPICAL CHARACTERISTIC CURVES 3.025 3.05 3.020 3.04 3.015 3.03 3.010 3.02 3.005 3.01 VREF [V] VREF [V] 3.030 3.000 2.995 3 2.99 2.990 2.98 2.985 2.97 2.980 2.96 2.975 2.95 -75 2.970 5.0 6.0 7.0 8.0 9.0 -50 -25 0 25 50 TEMPERATURE [°C] 10.0 11.0 12.0 13.0 14.0 15.0 VDD [V] Figure 1. Reference vs. VDD Figure 2. Reference vs. Temperature 4 75 100 125 UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 PIN DESCRIPTIONS phase. The UCC3829 -3 implements OUTA and OUTB to be non-overlapping complementary outputs during the same clock cycle. The output frequency of the UCC3829-1 is half that of the UCC3829-2 and UCC3829 -3. BISYNC: Combination clock output/sync input pin. The clock signal can be viewed on this pin. If BISYNC is connected to BISYNC of other UCC3829 chips, all the oscillators will run at the highest of all the chips frequencies. The BISYNC pin has a weak pull down and a strong pull up. PGND: Power ground return. The PGND pin should be used as the return for the VDD bypass capacitor and the current sense kelvin CL-. CL+: Current sense input for current limiting. The CL+ and CL- pins are used for current sensing. CL+ is the current signal while CL- is the kelvin return for the sensing function. PWCONT: Pulse width control input. This is connected to the PWM comparator inverting input. CL–: Current sense input kelvin common. RAMP: Ramp input . This is connected to the PWM comparator non-inverting input through a level shifting voltage of approximately 1.25V. CT: Oscillator timing capacitor. A capacitor connected between CT and GND is charged by a current source controlled by RT1. The capacitor is discharged through a resistor connected between CT and RT2. RT1: Oscillator charging current programming resistor. A 1V reference at this pin generates a current through a resistor connected between RT1 and GND. This current is mirrored and ratioed to charge the timing capacitor connected to pin CT. EAOUT: Error amplifier output. This output is normally connected directly to the PWCONT pin. It can also be connected to PWCONT through a resistor divider attenuation network to allow more swing of the error amplifier output. A maximum capacitive load of 20pF with respect to ground must be observed to insure stability of the error amplifier. RT2: Oscillator discharge time programming resistor. The oscillator (and output) dead time can be programmed via this pin. The discharge of the timing capacitor CT is determined by an RC discharge using a resistor connected between RT2 and CT. GND: Logic and analog ground. The GND pin should be used for all signal level returns, except the current sense inputs. SS: Soft start capacitor pin. A capacitor connected to SS determines the time the IC takes to soft start. The nominal SS pin pull up and pull down current is 20µA. The soft start time delay is approximately calculated as: INV: Error amplifier inverting input. LEB: Leading edge blanking programming pin. Connecting a resistor between VREF and LEB and a capacitor between LEB and GND will program a leading edge blanking time according to the RC of the resistor/capacitor combination. Connecting the LEB pin to VDD disables the Leading Edge Blanking function. CSS • 3V 20 µA when charging from 0V. After the SS pin reaches the SS complete threshold of 3V, another SS cycle can be started. The restart time is approximately: NINV: Error amplifier non-inverting input. 2 • CSS • 3V 20 µA OUTA: Output A. The OUTA pin will pull down with approximately 1.5A and pull up with approximately 0.75A. The UCC3829-1 implements push-pull outputs with OUTA and OUTB active on alternating clock cycles. The UCC3829-2 implements OUTA and OUTB being in phase. The UCC3829 -3 implements OUTA and OUTB to be non-overlapping complementary outputs during the same clock cycle. The output frequency of the UCC3829-1 is half that of the UCC3829-2 and UCC3829 -3. UVLO: Undervoltage lockout programming pin. Connecting a resistor divider between VDD, UVLO, and GND sets a VDD value at which the UCC3829 chip will be enabled. When the voltage on the UVLO pin reaches 3V, the chip is enabled. When the voltage on UVLO falls below 2.5V, the chip is disabled. VDD: Voltage supply to IC. VDD is clamped at 14V. VREF: Voltage reference output and filtering. The voltage reference output appears on the VREF pin. It is buffered to drive approximately 5mA and short circuit protected at approximately 25mA. A bypass capacitor of at least 0.1µF must be connected from VREF to ground. OUTB: Output B. The OUTB pin will pull down with approximately 1.5A and pull up with approximately 0.75A. The UCC3829-1 implements push-pull outputs with OUTA and OUTB active on alternating clock cycles. The UCC3829-2 implements OUTA and OUTB being in 5 UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 APPLICATION INFORMATION The approximate equation for the falling edge (TF) of the CT waveform (deadtime period) is: Functional Programmability 9 .3RT 2 VPEAK – RT 1 TF = RT 2CT ln = 9 .3RT 2 VVALLEY – RT 1 Various features of the UCC3829 are user programmable. RT1 and RT2 allow independent programming for oscillator rise and fall times within the normal operational range of the chip. A new feature allows the user to program the voltage that flags an undervoltage fault. The default value of 14V for chip turn-on is selected by tying the UVLO pin to ground. If the user wants to select startup voltage then a resistive divider should be tied from Vdd to ground, with the centerpoint tied to the UVLO pin. The chip will be enabled when the UVLO pin reaches 3V, and disabled below 2.5V. Leading edge blanking can also be optimized to eliminate turn-on noise when current mode control is used or disabled when desired. Assuming that: 9 .3RT 2 9 .3RT 2 << VPEAK and << VVALLEY RT 1 RT 1 We get a simplified equation: TF = RT 2CT ln VPEAK VVALLEY Given a maximum on-time and frequency and assuming an initial value for either RT2 or CT, you can use the TF equation to calculate the other. Once you have a value for CT, you can calculate RT1 using the TR equation. Oscillator The oscillator uses an external capacitor CT and two external resistors RT1 and RT2 to generate the clock frequency and dead time. A precise reference voltage is placed across resistor RT1 to generate a current reference. The current is then mirrored and used to charge the capacitor CT from VVALLEY. When a “peak” threshold is reached, an on chip MOSFET connects the RT2 pin to GND, discharging CT to a “valley” threshold through an external resistor RT2. The CT waveform has a linear ramp shape while charging and an exponential (RC) slope while discharging. The slope of the charging ramp is set by the CT, RT1 combination and the slope of the discharging ramp is set by the values of CT and RT2. Error Amplifier Section The Error Amplifier has both inputs and the output brought out to pins NINV, INV, and EAOUT. The output of the error amplifier can be connected to the inverting input of the PWM comparator via the pin PWCONT. This allows inserting attenuation which enables using the full output swing of the error amplifier. The output of the error amplifier is forced to follow the soft start waveform during soft start. PWM and Output Section The non-inverted input of the PWM comparator is connected to RAMP. The RAMP can be connected to either the CT capacitor for voltage mode control, to the current sense resistor for current mode control, or to a feed forward capacitor for input voltage feed forward control. The CT waveform can be coupled to RAMP to provide slope compensation in the current mode case. The MOSFET switch connected to RAMP provides for the discharge of the feedforward capacitor. There is a short time constant (3ns) filter across the inputs of the PWM comparator to reduce noise. The approximate equation for the rising edge (TR) of the CT waveform (maximum on-time period) is: TR = CTRT 1 VPEAK –VVALLEY 9 .3 The output of the PWM comparator feeds an OR gate which, together with several other fault signals, sets the PWM latch. The latch is in turn reset on every dead time period of the clock waveform. The output of the PWM latch is OR’ed with the clock and the output of the Fault Latch (described below) to feed into the pulse steering Toggle Flip-Flop (TFF). The resulting signal is then steered according to the output configuration of UCC3829. The clock output becomes the deadtime between the outputs. UDG-97016 Figure 3. 6 UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 Output Timing Configurations Leading Edge Blanking Section The timing diagram shows the major differences between the UCC3829-1, -2 and -3 parts. The output of the UCC3829-1 is a push-pull configuration with outputs A and B 180° out of phase and with an output frequency that is half of the CT’s waveform. The Leading Edge Blanking circuit provides a means to insert a blanking period at the beginning of the cycle, providing noise pulse elimination for current mode control applications. This feature is similar to that of the UC3825 and UC3823A/B controllers. When enabled, an external resistor is connected from LEB to VREF. An external capacitor is connected from LEB to either VREF or GND. During the deadtime, LEB is pulled to GND. At the beginning of the cycle, the pin is released and the capacitor charges through the resistor toward VREF. At the threshold VREF/2, a comparator senses the voltage and LEB is removed. The leading edge blanking function can be disabled by connecting LEB to VDD (> VREF). Leading edge blanking is performed by the same MOSFET switch connected to RAMP that is used for voltage feed forward operation. The UCC3829-2 produces dual outputs that are in phase and can be used in situations that require high current drive for single ended designs. A 0.5 resistor should be added in series with each output before they are connected together. The output pulse frequency is equal to the CT waveform frequency in this case. The output drive in the UCC3829-3 has a nonoverlapping complementary configuration. During each clock cycle Output A produces an output pulse, followed by a short delay, and then Output B produces an output pulse. The short delay between Output A and Output B pulses is tcd, the complementary delay time. This ensures that the outputs are never high simultaneously. Current Timing and Protection The current limit and overcurrent functions are accomplished using the pins CL+ and CL–. These two pins provide for differential current level sensing, with the trip points referenced to CL–, rather than GND. The current limit function provides a pulse by pulse current limiting, whereas the overcurrent function is considered a fault condition and initiates a fault logic soft start cycle. TIMING DIAGRAMS PWM CNTL CT The UCC3829 utilizes differential current sensing and separate logic and power ground pins to eliminate some of the noise issues of using current mode control. Devices with only one common ground pin for all stated functions required the combination of power gate drive current and low-level sensing currents in a common trace. Since the current signal needed for control is embedded in the power gate drive current, it is not enough just to separate logic and power ground pins. Differential sensing in UCC3829 referenced to the negative rail allows the cleanest method of sensing current for use in a peak current mode controlled power supply utilizing resistive sensing. Current limiting is done on a cycle by cycle basis when the typical threshold of 0.875V is reached. If the fault level of 1.25V is reached a soft start cycle is initiated. Internal circuitry insures that soft start cycles are completed so that fault currents can be controlled. BISYNC UCC1829-1 OUT A UCC1829-1 OUT B UCC1829-2 OUT A UCC1829-2 OUT B Fault Logic Section UCC1829-3 The fault logic detects and handles various fault conditions in the system. The output of the overcurrent comparator is logically ORed with the output combination of the undervoltage detection circuit ORed with the output of the VREF good circuit. The output of the precision reference voltage VREF is compared to a level (approxi- OUT A UCC 1829-3 OUT B tr tf tcd 7 UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 mately 3 VBE voltages) to determine if the reference is alive. The undervoltage circuit either uses a user programmed level with a 16% hysteresis or an on threshold equal to the VDD clamp voltage and an off threshold of 9V. sink and turns on a 20µA current source to charge the SS capacitor. The under voltage detection is set to a default value of 14V turn on (VDD clamp active value) and 9V turn off when the UVLO pin is tied to GND. This default configuration can be overridden by connecting a resistor divider between VDD and GND to the UVLO pin. The hysteresis for the user set threshold is 16%. Once a fault occurs, a soft start cycle takes place. A fault sets the fault latch. The Q output of the fault latch sets the RS delay latch and turns on the 20µA soft start discharge current sink. The Q output of the fault latch is gated, however, by the output of the SS complete comparator. This insures that a SS cycle cannot start before the previous one has finished. The soft start capacitor then is discharged to 1V which is sensed by the RS delay comparator. The fault latch is then reset. This in turn resets the RS delay latch and turns off the 20µA current During undervoltage lockout, the self biasing outputs are held "OFF" to prevent accidental turn-on of the power switches. Supply Section The incoming voltage supply VDD is clamped by a shunt VDD Clamp circuit at 14V. TYPICAL APPLICATIONS VIN DC SOURCE OR RECTIFIED AC VOUT BIAS SUPPLY 11 CL+ SS 10 12 CLBISYNC 9 13 PGND RT1 8 14 OUTB CT 7 15 OUTA RT2 6 16 VDD RAMP 5 17 UVLO PWCONT 4 18 GND EAOUT 3 19 LEB VREF 20 ISOLATED FEEDBACK INV 2 1 NINV UCC3829-1 UDG-98013 Figure 4. Push-Pull Converter Using UCC3829-1 8 UCC1829-1/-2/-3 UCC2829-1/-2/-3 UCC3829-1/-2/-3 TYPICAL APPLICATIONS (cont.) VIN VOUT UDG-98014 Figure 5. Single Ended Converter with High Power Gate Drive Using UCC3829-2 P/O CT1 VIN VOUT 17 16 15 14 13 12 11 UVLO VDD OUTA OUTB PGND CL- CL+ 18 GND 19 LEB VREF 20 VDD SUPPLY P/O CT1 EAOUT PWCONT RAMP RT2 CT RT1 BISYNC SS 3 4 5 6 7 8 9 10 INV 2 1 NINV UCC3829-3 COMMON UDG-98015 Figure 6. Synchronous Rectifier Controller Using UCC3829-3 For additional information, please see U-128 that details operation and application of some of the features of UC3823A,B and UC3825A,B PWM Controllers. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 9 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC3829DW-1 OBSOLETE SOIC DW 20 TBD Call TI Call TI UCC3829DW-2 OBSOLETE SOIC DW 20 TBD Call TI Call TI UTR Lead/Ball Finish MSL Peak Temp (3) UCC3829DW-3 OBSOLETE TBD Call TI Call TI UCC3829DWTR-1 OBSOLETE SOIC DW 20 TBD Call TI Call TI UCC3829DWTR-2 OBSOLETE SOIC DW 20 TBD Call TI Call TI UCC3829N-1 OBSOLETE PDIP N 20 TBD Call TI Call TI UCC3829N-2 OBSOLETE PDIP N 20 TBD Call TI Call TI UCC3829N-3 OBSOLETE UTR TBD Call TI Call TI UCC3829Q-1 OBSOLETE UTR TBD Call TI Call TI UCC3829Q-2 OBSOLETE UTR TBD Call TI Call TI UCC3829Q-3 OBSOLETE UTR TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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