INTEL 82801GDHICH7DH

Intel® I/O Controller Hub 7 (ICH7)
Family
Datasheet
— For the Intel® 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,
82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O
Controller Hubs
April 2007
Document Number: 307013-003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® I/O Controller Hub 7 (ICH7) Family chipset component may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005–2007, Intel Corporation
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Intel ® ICH7 Family Datasheet
Contents
1
Introduction ............................................................................................................ 39
1.1
Overview ......................................................................................................... 42
1.2
Intel® ICH7 Family High-Level Component Differences ........................................... 50
2
Signal Description ................................................................................................... 51
2.1
Direct Media Interface (DMI) to Host Controller ..................................................... 55
2.2
PCI Express* (Desktop and Mobile Only) .............................................................. 55
2.3
Platform LAN Connect Interface (Desktop and Mobile Only)..................................... 56
2.4
EEPROM Interface (Desktop and Mobile Only)........................................................ 56
2.5
Firmware Hub Interface (Desktop and Mobile Only)................................................ 56
2.6
PCI Interface .................................................................................................... 57
2.7
Serial ATA Interface (Desktop and Mobile Only) ..................................................... 59
2.8
IDE Interface .................................................................................................... 60
2.9
LPC Interface.................................................................................................... 62
2.10 Interrupt Interface ............................................................................................ 62
2.11 USB Interface ................................................................................................... 63
2.12 Power Management Interface.............................................................................. 64
2.13 Processor Interface............................................................................................ 66
2.14 SMBus Interface................................................................................................ 68
2.15 System Management Interface............................................................................ 68
2.16 Real Time Clock Interface ................................................................................... 69
2.17 Other Clocks..................................................................................................... 69
2.18 Miscellaneous Signals ........................................................................................ 70
2.19 AC ’97/Intel® High Definition Audio Link ............................................................... 71
2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................... 72
2.21 Intel® Quick Resume Technology (Intel® ICH7DH Only) ......................................... 72
2.22 General Purpose I/O Signals ............................................................................... 72
2.23 Power and Ground ............................................................................................. 74
2.24 Pin Straps ........................................................................................................ 76
2.24.1 Functional Straps ................................................................................... 76
2.24.2 External RTC Circuitry ............................................................................. 78
3
Intel® ICH7 Pin States............................................................................................. 79
3.1
Integrated Pull-Ups and Pull-Downs ..................................................................... 79
3.2
IDE Integrated Series Termination Resistors.......................................................... 80
3.3
Output and I/O Signals Planes and States............................................................. 81
3.4
Power Planes for Input Signals ............................................................................ 90
4
Intel® ICH7 and System Clock Domains................................................................... 95
5
Functional Description ............................................................................................. 99
5.1
PCI-to-PCI Bridge (D30:F0) ................................................................................ 99
5.1.1 PCI Bus Interface ................................................................................... 99
5.1.2 PCI Bridge As an Initiator ........................................................................ 99
5.1.2.1 Memory Reads and Writes.......................................................... 99
5.1.2.2 I/O Reads and Writes .............................................................. 100
5.1.2.3 Configuration Reads and Writes ................................................ 100
5.1.2.4 Locked Cycles......................................................................... 100
5.1.2.5 Target / Master Aborts ............................................................. 100
5.1.2.6 Secondary Master Latency Timer............................................... 100
5.1.2.7 Dual Address Cycle (DAC) ........................................................ 100
5.1.2.8 Memory and I/O Decode to PCI................................................. 101
5.1.3 Parity Error Detection and Generation ..................................................... 101
5.1.4 PCIRST# ............................................................................................. 101
Intel ® ICH7 Family Datasheet
3
5.2
5.3
5.4
5.5
4
5.1.5 Peer Cycles .......................................................................................... 102
5.1.6 PCI-to-PCI Bridge Model ........................................................................ 102
5.1.7 IDSEL to Device Number Mapping ........................................................... 103
5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 103
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) .......... 103
5.2.1 Interrupt Generation ............................................................................. 103
5.2.2 Power Management............................................................................... 104
5.2.2.1 S3/S4/S5 Support ................................................................... 104
5.2.2.2 Resuming from Suspended State ............................................... 104
5.2.2.3 Device Initiated PM_PME Message ............................................. 104
5.2.2.4 SMI/SCI Generation................................................................. 105
5.2.3 SERR# Generation ................................................................................ 105
5.2.4 Hot-Plug .............................................................................................. 106
5.2.4.1 Presence Detection .................................................................. 106
5.2.4.2 Message Generation ................................................................ 106
5.2.4.3 Attention Button Detection ....................................................... 107
5.2.4.4 SMI/SCI Generation................................................................. 107
LAN Controller (B1:D8:F0) (Desktop and Mobile Only) .......................................... 108
5.3.1 LAN Controller PCI Bus Interface............................................................. 108
5.3.1.1 Bus Slave Operation ................................................................ 109
5.3.1.2 CLKRUN# Signal (Mobile Only).................................................. 110
5.3.1.3 PCI Power Management ........................................................... 110
5.3.1.4 PCI Reset Signal...................................................................... 110
5.3.1.5 Wake-Up Events...................................................................... 111
5.3.1.6 Wake on LAN* (Preboot Wake-Up) ............................................. 112
5.3.2 Serial EEPROM Interface ........................................................................ 112
5.3.3 CSMA/CD Unit ...................................................................................... 113
5.3.3.1 Full Duplex ............................................................................. 113
5.3.3.2 Flow Control ........................................................................... 113
5.3.3.3 VLAN Support ......................................................................... 113
5.3.4 Media Management Interface ................................................................. 113
5.3.5 TCO Functionality ................................................................................. 114
5.3.5.1 Advanced TCO Mode ................................................................ 114
Alert Standard Format (ASF) (Desktop and Mobile Only) ....................................... 115
5.4.1 ASF Management Solution Features/Capabilities ....................................... 116
5.4.2 ASF Hardware Support .......................................................................... 117
5.4.2.1 Intel® 82562EM/EX ................................................................. 117
5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................ 117
5.4.2.3 Legacy Sensor SMBus Devices .................................................. 117
5.4.2.4 Remote Control SMBus Devices ................................................. 117
5.4.2.5 ASF Sensor SMBus Devices....................................................... 117
5.4.3 ASF Software Support ........................................................................... 118
LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 118
5.5.1 LPC Interface ....................................................................................... 118
5.5.1.1 LPC Cycle Types ...................................................................... 119
5.5.1.2 Start Field Definition ................................................................ 119
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ..................................... 120
5.5.1.4 SIZE...................................................................................... 120
5.5.1.5 SYNC..................................................................................... 121
5.5.1.6 SYNC Time-Out ....................................................................... 121
5.5.1.7 SYNC Error Indication .............................................................. 121
5.5.1.8 LFRAME# Usage...................................................................... 122
5.5.1.9 I/O Cycles .............................................................................. 122
5.5.1.10 Bus Master Cycles ................................................................... 122
5.5.1.11 LPC Power Management ........................................................... 122
5.5.1.12 Configuration and Intel® ICH7 Implications................................. 123
5.5.2 SERR# Generation ................................................................................ 123
Intel ® ICH7 Family Datasheet
5.6
5.7
5.8
5.9
5.10
DMA Operation (D31:F0) .................................................................................. 124
5.6.1 Channel Priority ................................................................................... 124
5.6.1.1 Fixed Priority.......................................................................... 125
5.6.1.2 Rotating Priority ..................................................................... 125
5.6.2 Address Compatibility Mode ................................................................... 125
5.6.3 Summary of DMA Transfer Sizes ............................................................. 125
5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by
Words ................................................................................... 126
5.6.4 Autoinitialize........................................................................................ 126
5.6.5 Software Commands............................................................................. 126
LPC DMA (Desktop and Mobile Only) .................................................................. 127
5.7.1 Asserting DMA Requests........................................................................ 127
5.7.2 Abandoning DMA Requests .................................................................... 127
5.7.3 General Flow of DMA Transfers ............................................................... 128
5.7.4 Terminal Count .................................................................................... 128
5.7.5 Verify Mode ......................................................................................... 128
5.7.6 DMA Request Deassertion...................................................................... 129
5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 129
8254 Timers (D31:F0) ..................................................................................... 130
5.8.1 Timer Programming .............................................................................. 131
5.8.2 Reading from the Interval Timer............................................................. 132
5.8.2.1 Simple Read........................................................................... 132
5.8.2.2 Counter Latch Command.......................................................... 132
5.8.2.3 Read Back Command .............................................................. 132
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133
5.9.1 Interrupt Handling................................................................................ 134
5.9.1.1 Generating Interrupts.............................................................. 134
5.9.1.2 Acknowledging Interrupts ........................................................ 134
5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135
5.9.2 Initialization Command Words (ICWx) ..................................................... 135
5.9.2.1 ICW1 .................................................................................... 135
5.9.2.2 ICW2 .................................................................................... 136
5.9.2.3 ICW3 .................................................................................... 136
5.9.2.4 ICW4 .................................................................................... 136
5.9.3 Operation Command Words (OCW) ......................................................... 136
5.9.4 Modes of Operation .............................................................................. 136
5.9.4.1 Fully Nested Mode................................................................... 136
5.9.4.2 Special Fully-Nested Mode........................................................ 137
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 137
5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137
5.9.4.5 Poll Mode ............................................................................... 137
5.9.4.6 Cascade Mode ........................................................................ 138
5.9.4.7 Edge and Level Triggered Mode................................................. 138
5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138
5.9.4.9 Normal End of Interrupt........................................................... 138
5.9.4.10 Automatic End of Interrupt Mode .............................................. 138
5.9.5 Masking Interrupts ............................................................................... 139
5.9.5.1 Masking on an Individual Interrupt Request ................................ 139
5.9.5.2 Special Mask Mode.................................................................. 139
5.9.6 Steering PCI Interrupts ......................................................................... 139
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140
5.10.1 Interrupt Handling................................................................................ 140
5.10.2 Interrupt Mapping ................................................................................ 140
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 141
5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141
5.10.4.1 Edge-Triggered Operation......................................................... 142
Intel ® ICH7 Family Datasheet
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5.11
5.12
5.13
5.14
6
5.10.4.2 Level-Triggered Operation......................................................... 142
5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 142
5.10.4.4 Interrupt Message Format ........................................................ 142
Serial Interrupt (D31:F0) .................................................................................. 143
5.11.1 Start Frame ......................................................................................... 143
5.11.2 Data Frames ........................................................................................ 144
5.11.3 Stop Frame .......................................................................................... 144
5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 144
5.11.5 Data Frame Format ............................................................................... 145
Real Time Clock (D31:F0) ................................................................................. 146
5.12.1 Update Cycles ...................................................................................... 146
5.12.2 Interrupts ............................................................................................ 147
5.12.3 Lockable RAM Ranges............................................................................ 147
5.12.4 Century Rollover ................................................................................... 147
5.12.5 Clearing Battery-Backed RTC RAM ........................................................... 147
Processor Interface (D31:F0) ............................................................................ 149
5.13.1 Processor Interface Signals .................................................................... 149
5.13.1.1 A20M# (Mask A20).................................................................. 149
5.13.1.2 INIT# (Initialization)................................................................ 150
5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric
Error) .................................................................................... 150
5.13.1.4 NMI (Non-Maskable Interrupt) .................................................. 151
5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) ........ 151
5.13.1.6 CPU Power Good (CPUPWRGOOD) ............................................. 151
5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) ...................... 151
5.13.2 Dual-Processor Issues (Desktop Only) ..................................................... 152
5.13.2.1 Signal Differences ................................................................... 152
5.13.2.2 Power Management ................................................................. 152
Power Management (D31:F0) ............................................................................ 153
5.14.1 Features .............................................................................................. 153
5.14.2 Intel® ICH7 and System Power States ..................................................... 153
5.14.3 System Power Planes ............................................................................ 156
5.14.4 SMI#/SCI Generation ............................................................................ 156
5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) .............................. 159
5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ....................... 159
5.14.5 Dynamic Processor Clock Control ............................................................ 159
5.14.5.1 Transition Rules among S0/Cx and Throttling States..................... 160
5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) ................................. 161
5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) .................. 161
5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only) ............. 161
5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................ 161
5.14.6.1 Conditions for Checking the PCI Clock ........................................ 162
5.14.6.2 Conditions for Maintaining the PCI Clock..................................... 162
5.14.6.3 Conditions for Stopping the PCI Clock ........................................ 162
5.14.6.4 Conditions for Re-Starting the PCI Clock ..................................... 162
5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) ............ 162
5.14.7 Sleep States ........................................................................................ 163
5.14.7.1 Sleep State Overview............................................................... 163
5.14.7.2 Initiating Sleep State ............................................................... 163
5.14.7.3 Exiting Sleep States................................................................. 163
5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (
Desktop and Mobile only) ......................................................... 165
5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 165
5.14.8 Thermal Management............................................................................ 166
5.14.8.1 THRM# Signal......................................................................... 166
5.14.8.2 Processor Initiated Passive Cooling ............................................ 166
5.14.8.3 THRM# Override Software Bit ................................................... 167
Intel ® ICH7 Family Datasheet
5.15
5.16
5.17
5.14.8.4 Active Cooling ........................................................................ 167
5.14.9 Event Input Signals and Their Usage ....................................................... 167
5.14.9.1 PWRBTN# (Power Button) ........................................................ 167
5.14.9.2 RI# (Ring Indicator)................................................................ 168
5.14.9.3 PME# (PCI Power Management Event) ....................................... 169
5.14.9.4 SYS_RESET# Signal ................................................................ 169
5.14.9.5 THRMTRIP# Signal.................................................................. 169
5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) ....................................... 170
5.14.10ALT Access Mode .................................................................................. 170
5.14.10.1Write Only Registers with Read Paths in ALT Access Mode............. 171
5.14.10.2PIC Reserved Bits ................................................................... 173
5.14.10.3Read Only Registers with Write Paths in ALT Access Mode............. 173
5.14.11System Power Supplies, Planes, and Signals ............................................ 173
5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173
5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 174
5.14.11.3PWROK Signal ........................................................................ 174
5.14.11.4CPUPWRGD Signal .................................................................. 175
5.14.11.5VRMPWRGD Signal.................................................................. 175
5.14.11.6BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175
5.14.11.7Controlling Leakage and Power Consumption during Low-Power
States ................................................................................... 175
5.14.12Clock Generators.................................................................................. 176
5.14.12.1Clock Control Signals from Intel® ICH7 to Clock
Synthesizer (Mobile/Ultra Mobile Only)....................................... 176
5.14.13Legacy Power Management Theory of Operation ....................................... 177
5.14.13.1APM Power Management (Desktop Only) .................................... 177
5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only) ........... 177
System Management (D31:F0).......................................................................... 178
5.15.1 Theory of Operation.............................................................................. 178
5.15.1.1 Detecting a System Lockup ...................................................... 178
5.15.1.2 Handling an Intruder ............................................................... 178
5.15.1.3 Detecting Improper Firmware Hub Programming ......................... 179
5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179
IDE Controller (D31:F1) ................................................................................... 183
5.16.1 PIO Transfers ....................................................................................... 183
5.16.1.1 PIO IDE Timing Modes ............................................................. 184
5.16.1.2 IORDY Masking....................................................................... 184
5.16.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 184
5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185
5.16.2 Bus Master Function ............................................................................. 185
5.16.2.1 Physical Region Descriptor Format............................................. 185
5.16.2.2 Bus Master IDE Timings ........................................................... 186
5.16.2.3 Interrupts .............................................................................. 186
5.16.2.4 Bus Master IDE Operation ........................................................ 187
5.16.2.5 Error Conditions...................................................................... 188
5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188
5.16.3.1 Operation .............................................................................. 189
5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190
5.16.5 ATA Swap Bay...................................................................................... 190
5.16.6 SMI Trapping ....................................................................................... 190
SATA Host Controller (D31:F2) (Desktop and Mobile Only) .................................... 191
5.17.1 Theory of Operation.............................................................................. 192
5.17.1.1 Standard ATA Emulation .......................................................... 192
5.17.1.2 48-Bit LBA Operation............................................................... 192
5.17.2 SATA Swap Bay Support ........................................................................ 193
5.17.3 Intel® Matrix Storage Technology Configuration (Intel® ICH7R, ICH7DH,
and ICH7-M DH Only) ........................................................................... 193
Intel ® ICH7 Family Datasheet
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5.18
5.19
5.20
8
5.17.3.1 Intel® Matrix Storage Manager RAID Option ROM ........................ 194
5.17.4 Power Management Operation ................................................................ 194
5.17.4.1 Power State Mappings.............................................................. 194
5.17.4.2 Power State Transitions ............................................................ 195
5.17.4.3 SMI Trapping (APM) ................................................................. 196
5.17.5 SATA LED ............................................................................................ 196
5.17.6 AHCI Operation (Intel® ICH7R, ICH7DH, and Mobile Only) ......................... 196
5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................. 197
High Precision Event Timers .............................................................................. 197
5.18.1 Timer Accuracy..................................................................................... 197
5.18.2 Interrupt Mapping................................................................................. 198
5.18.3 Periodic vs. Non-Periodic Modes .............................................................. 198
5.18.4 Enabling the Timers .............................................................................. 199
5.18.5 Interrupt Levels.................................................................................... 199
5.18.6 Handling Interrupts............................................................................... 199
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 200
USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ............................................ 200
5.19.1 Data Structures in Main Memory ............................................................. 200
5.19.2 Data Transfers to/from Main Memory ....................................................... 200
5.19.3 Data Encoding and Bit Stuffing ............................................................... 200
5.19.4 Bus Protocol......................................................................................... 200
5.19.4.1 Bit Ordering............................................................................ 200
5.19.4.2 SYNC Field ............................................................................. 201
5.19.4.3 Packet Field Formats................................................................ 201
5.19.4.4 Address Fields......................................................................... 201
5.19.4.5 Frame Number Field ................................................................ 201
5.19.4.6 Data Field .............................................................................. 201
5.19.4.7 Cyclic Redundancy Check (CRC) ................................................ 201
5.19.5 Packet Formats..................................................................................... 201
5.19.6 USB Interrupts ..................................................................................... 201
5.19.6.1 Transaction-Based Interrupts .................................................... 202
5.19.6.2 Non-Transaction Based Interrupts .............................................. 203
5.19.7 USB Power Management ........................................................................ 204
5.19.8 USB Legacy Keyboard Operation ............................................................. 204
USB EHCI Host Controller (D29:F7).................................................................... 207
5.20.1 EHC Initialization .................................................................................. 207
5.20.1.1 BIOS Initialization ................................................................... 207
5.20.1.2 Driver Initialization .................................................................. 207
5.20.1.3 EHC Resets............................................................................. 208
5.20.2 Data Structures in Main Memory ............................................................. 208
5.20.3 USB 2.0 Enhanced Host Controller DMA ................................................... 208
5.20.4 Data Encoding and Bit Stuffing ............................................................... 208
5.20.5 Packet Formats..................................................................................... 208
5.20.6 USB 2.0 Interrupts and Error Conditions .................................................. 209
5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads................................. 209
5.20.7 USB 2.0 Power Management .................................................................. 210
5.20.7.1 Pause Feature ......................................................................... 210
5.20.7.2 Suspend Feature ..................................................................... 210
5.20.7.3 ACPI Device States .................................................................. 210
5.20.7.4 ACPI System States................................................................. 211
5.20.7.5 Mobile/Ultra Mobile Only Considerations ..................................... 211
5.20.8 Interaction with UHCI Host Controllers..................................................... 211
5.20.8.1 Port-Routing Logic ................................................................... 211
5.20.8.2 Device Connects ..................................................................... 213
5.20.8.3 Device Disconnects.................................................................. 213
5.20.8.4 Effect of Resets on Port-Routing Logic ........................................ 214
Intel ® ICH7 Family Datasheet
5.21
5.22
5.23
5.24
5.25
5.26
5.20.9 USB 2.0 Legacy Keyboard Operation ....................................................... 214
5.20.10USB 2.0 Based Debug Port .................................................................... 214
5.20.10.1 Theory of Operation ............................................................... 215
SMBus Controller (D31:F3) ............................................................................... 219
5.21.1 Host Controller..................................................................................... 220
5.21.1.1 Command Protocols ................................................................ 220
5.21.2 Bus Arbitration..................................................................................... 224
5.21.3 Bus Timing .......................................................................................... 224
5.21.3.1 Clock Stretching ..................................................................... 224
5.21.3.2 Bus Time Out (Intel® ICH7 as SMBus Master)............................. 224
5.21.4 Interrupts / SMI#................................................................................. 225
5.21.5 SMBALERT# ........................................................................................ 226
5.21.6 SMBus CRC Generation and Checking...................................................... 226
5.21.7 SMBus Slave Interface .......................................................................... 226
5.21.7.1 Format of Slave Write Cycle ..................................................... 227
5.21.7.2 Format of Read Command........................................................ 229
5.21.7.3 Format of Host Notify Command ............................................... 231
AC ’97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) ......... 232
5.22.1 PCI Power Management ........................................................................ 234
5.22.2 AC-Link Overview ................................................................................. 234
5.22.2.1 Register Access ...................................................................... 236
5.22.3 AC-Link Low Power Mode....................................................................... 237
5.22.3.1 External Wake Event ............................................................... 238
5.22.4 AC ’97 Cold Reset................................................................................. 239
5.22.5 AC ’97 Warm Reset............................................................................... 239
5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec .......................... 239
Intel® High Definition Audio Overview ................................................................ 240
5.23.1 Intel® High Definition Audio Docking (Mobile Only) ................................... 240
5.23.1.1 Dock Sequence....................................................................... 240
5.23.1.2 Exiting D3/CRST# when Docked ............................................... 241
5.23.1.3 Cold Boot/Resume from S3 When Docked .................................. 242
5.23.1.4 Undock Sequence ................................................................... 242
5.23.1.5 Interaction Between Dock/Undock and Power Management
States ................................................................................... 243
5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST# .................. 243
Intel® Active Management Technology (Intel® AMT) (Desktop and Mobile Only)....... 244
5.24.1 Intel® AMT Features ............................................................................. 244
5.24.2 Intel® AMT Requirements ...................................................................... 244
Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................. 245
5.25.1 SPI Arbitration between Intel® ICH7 and Intel PRO 82573E ....................... 245
5.25.2 Flash Device Configurations ................................................................... 245
5.25.3 SPI Device Compatibility Requirements ................................................... 246
5.25.3.1 Intel® ICH7 SPI Based BIOS Only Configuration Requirements
(Non-Shared Flash Configuration) ............................................. 246
5.25.3.2 Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware
Configuration Requirements (Shared Flash Configuration) ............ 246
5.25.4 Intel® ICH7 Compatible Command Set .................................................... 247
5.25.4.1 Required Command Set for Inter Operability............................... 247
5.25.4.2 Recommended Standard Commands.......................................... 247
5.25.4.3 Multiple Page Write Usage Model ............................................... 248
5.25.5 Flash Protection ................................................................................... 248
5.25.5.1 BIOS Range Write Protection .................................................... 248
5.25.5.2 SMI# Based Global Write Protection .......................................... 249
5.25.5.3 Shared Flash Address Range Protection...................................... 249
Intel® Quick Resume Technology (Digital Home Only) .......................................... 249
5.26.1 Visual Off ............................................................................................ 249
Intel ® ICH7 Family Datasheet
9
5.27
5.26.2 CE-like On/Off ...................................................................................... 249
5.26.3 Intel® Quick Resume Technology Signals (ICH7DH Only)............................ 250
5.26.4 Power Button Sequence (ICH7DH Only) ................................................... 250
Feature Capability Mechanism ........................................................................... 251
6
Register and Memory Mapping ............................................................................... 253
6.1
PCI Devices and Functions ................................................................................ 254
6.2
PCI Configuration Map ...................................................................................... 255
6.3
I/O Map.......................................................................................................... 255
6.3.1 Fixed I/O Address Ranges ...................................................................... 255
6.3.2 Variable I/O Decode Ranges ................................................................... 258
6.4
Memory Map ................................................................................................... 259
6.4.1 Boot-Block Update Scheme .................................................................... 261
7
Chipset Configuration Registers ............................................................................. 263
7.1
Chipset Configuration Registers (Memory Space).................................................. 263
7.1.1 VCH—Virtual Channel Capability Header Register ...................................... 265
7.1.2 VCAP1—Virtual Channel Capability #1 Register ......................................... 265
7.1.3 VCAP2—Virtual Channel Capability #2 Register ......................................... 266
7.1.4 PVC—Port Virtual Channel Control Register............................................... 266
7.1.5 PVS—Port Virtual Channel Status Register ................................................ 266
7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register .............................. 267
7.1.7 V0CTL—Virtual Channel 0 Resource Control Register .................................. 267
7.1.8 V0STS—Virtual Channel 0 Resource Status Register................................... 268
7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register .............................. 268
7.1.10 V1CTL—Virtual Channel 1 Resource Control Register .................................. 269
7.1.11 V1STS—Virtual Channel 1 Resource Status Register................................... 269
7.1.12 RCTCL—Root Complex Topology Capabilities List Register ........................... 270
7.1.13 ESD—Element Self Description Register ................................................... 270
7.1.14 ULD—Upstream Link Descriptor Register .................................................. 270
7.1.15 ULBA—Upstream Link Base Address Register ............................................ 271
7.1.16 RP1D—Root Port 1 Descriptor Register..................................................... 271
7.1.17 RP1BA—Root Port 1 Base Address Register ............................................... 271
7.1.18 RP2D—Root Port 2 Descriptor Register..................................................... 272
7.1.19 RP2BA—Root Port 2 Base Address Register ............................................... 272
7.1.20 RP3D—Root Port 3 Descriptor Register..................................................... 272
7.1.21 RP3BA—Root Port 3 Base Address Register ............................................... 273
7.1.22 RP4D—Root Port 4 Descriptor Register..................................................... 273
7.1.23 RP4BA—Root Port 4 Base Address Register ............................................... 273
7.1.24 HDD—Intel® High Definition Audio Descriptor Register............................... 274
7.1.25 HDBA—Intel® High Definition Audio Base Address Register......................... 274
7.1.26 RP5D—Root Port 5 Descriptor Register..................................................... 274
7.1.27 RP5BA—Root Port 5 Base Address Register ............................................... 275
7.1.28 RP6D—Root Port 6 Descriptor Register..................................................... 275
7.1.29 RP6BA—Root Port 6 Base Address Register ............................................... 275
7.1.30 ILCL—Internal Link Capabilities List Register ............................................. 276
7.1.31 LCAP—Link Capabilities Register ............................................................. 276
7.1.32 LCTL—Link Control Register.................................................................... 277
7.1.33 LSTS—Link Status Register .................................................................... 277
7.1.34 RPC—Root Port Configuration Register ..................................................... 278
7.1.35 RPFN—Root Port Function Number for PCI Express Root Ports
(Desktop and Mobile only) ..................................................................... 279
7.1.36 TRSR—Trap Status Register .................................................................... 280
7.1.37 TRCR—Trapped Cycle Register ................................................................ 280
7.1.38 TWDR—Trapped Write Data Register ........................................................ 280
7.1.39 IOTRn — I/O Trap Register (0-3)............................................................. 281
10
Intel ® ICH7 Family Datasheet
7.1.40
7.1.41
7.1.42
7.1.43
7.1.44
7.1.45
7.1.46
7.1.47
7.1.48
7.1.49
7.1.50
7.1.51
7.1.52
7.1.53
7.1.54
7.1.55
7.1.56
7.1.57
8
TCTL—TCO Configuration Register........................................................... 282
D31IP—Device 31 Interrupt Pin Register.................................................. 283
D30IP—Device 30 Interrupt Pin Register.................................................. 284
D29IP—Device 29 Interrupt Pin Register.................................................. 285
D28IP—Device 28 Interrupt Pin Register (Desktop and Mobile Only) ............ 286
D27IP—Device 27 Interrupt Pin Register.................................................. 287
D31IR—Device 31 Interrupt Route Register.............................................. 287
D30IR—Device 30 Interrupt Route Register.............................................. 289
D29IR—Device 29 Interrupt Route Register.............................................. 290
D28IR—Device 28 Interrupt Route Register.............................................. 292
D27IR—Device 27 Interrupt Route Register.............................................. 293
OIC—Other Interrupt Control Register ..................................................... 294
RC—RTC Configuration Register.............................................................. 295
HPTC—High Precision Timer Configuration Register ................................... 295
GCS—General Control and Status Register ............................................... 296
BUC—Backed Up Control Register ........................................................... 298
FD—Function Disable Register ................................................................ 299
CG—Clock Gating (Mobile/Ultra Mobile Only) ............................................ 301
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) ........................... 303
8.1
PCI Configuration Registers (LAN Controller—B1:D8:F0) ....................................... 303
8.1.1 VID—Vendor Identification Register (LAN Controller—B1:D8:F0) ................. 304
8.1.2 DID—Device Identification Register (LAN Controller—B1:D8:F0) ................. 304
8.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) .................... 305
8.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) .......................... 306
8.1.5 RID—Revision Identification Register (LAN Controller—B1:D8:F0) ............... 307
8.1.6 SCC—Sub Class Code Register (LAN Controller—B1:D8:F0) ........................ 307
8.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0) ...................... 307
8.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ........................ 308
8.1.9 PMLT—Primary Master Latency Timer Register (LAN Controller—B1:D8:F0)... 308
8.1.10 HEADTYP—Header Type Register (LAN Controller—B1:D8:F0) ..................... 308
8.1.11 CSR_MEM_BASE — CSR Memory-Mapped Base
Address Register (LAN Controller—B1:D8:F0)........................................... 309
8.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0)................................................................... 309
8.1.13 SVID — Subsystem Vendor Identification (LAN Controller—B1:D8:F0) ......... 309
8.1.14 SID — Subsystem Identification (LAN Controller—B1:D8:F0)...................... 310
8.1.15 CAP_PTR — Capabilities Pointer (LAN Controller—B1:D8:F0) ...................... 310
8.1.16 INT_LN — Interrupt Line Register (LAN Controller—B1:D8:F0).................... 310
8.1.17 INT_PN — Interrupt Pin Register (LAN Controller—B1:D8:F0) ..................... 311
8.1.18 MIN_GNT — Minimum Grant Register (LAN Controller—B1:D8:F0) .............. 311
8.1.19 MAX_LAT — Maximum Latency Register (LAN Controller—B1:D8:F0) ........... 311
8.1.20 CAP_ID — Capability Identification Register (LAN Controller—B1:D8:F0)...... 311
8.1.21 NXT_PTR — Next Item Pointer (LAN Controller—B1:D8:F0) ........................ 312
8.1.22 PM_CAP — Power Management Capabilities (LAN Controller—B1:D8:F0) ...... 312
8.1.23 PMCSR — Power Management Control/
Status Register (LAN Controller—B1:D8:F0)............................................. 313
8.1.24 PCIDATA — PCI Power Management Data Register
(LAN Controller—B1:D8:F0)................................................................... 314
8.2
LAN Control / Status Registers (CSR) (LAN Controller—B1:D8:F0).......................... 315
8.2.1 SCB_STA—System Control Block Status Word Register
(LAN Controller—B1:D8:F0)................................................................... 316
8.2.2 SCB_CMD—System Control Block Command Word
Register (LAN Controller—B1:D8:F0)....................................................... 317
8.2.3 SCB_GENPNT—System Control Block General Pointer
Register (LAN Controller—B1:D8:F0)....................................................... 319
Intel ® ICH7 Family Datasheet
11
8.2.4
8.2.5
8.2.6
8.3
9
12
PORT—PORT Interface Register (LAN Controller—B1:D8:F0) ....................... 319
EEPROM_CNTL—EEPROM Control Register (LAN Controller—B1:D8:F0)......... 321
MDI_CNTL—Management Data Interface (MDI) Control
Register (LAN Controller—B1:D8:F0) ....................................................... 322
8.2.7 REC_DMA_BC—Receive DMA Byte Count Register
(LAN Controller—B1:D8:F0) ................................................................... 322
8.2.8 EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0) ................................................................... 323
8.2.9 FLOW_CNTL—Flow Control Register (LAN Controller—B1:D8:F0) ................. 323
8.2.10 PMDR—Power Management Driver Register (LAN Controller—B1:D8:F0) ....... 324
8.2.11 GENCNTL—General Control Register (LAN Controller—B1:D8:F0)................. 325
8.2.12 GENSTA—General Status Register (LAN Controller—B1:D8:F0).................... 326
8.2.13 SMB_PCI—SMB via PCI Register (LAN Controller—B1:D8:F0) ...................... 326
8.2.14 Statistical Counters (LAN Controller—B1:D8:F0) ....................................... 327
ASF Configuration Registers (LAN Controller—B1:D8:F0) ....................................... 329
8.3.1 ASF_RID—ASF Revision Identification Register (LAN Controller—B1:D8:F0) .. 330
8.3.2 SMB_CNTL—SMBus Control Register (LAN Controller—B1:D8:F0) ................ 330
8.3.3 ASF_CNTL—ASF Control Register (LAN Controller—B1:D8:F0) ..................... 331
8.3.4 ASF_CNTL_EN—ASF Control Enable Register (ASF Controller—B1:D8:F0) ..... 332
8.3.5 ENABLE—Enable Register (ASF Controller—B1:D8:F0) ............................... 333
8.3.6 APM—APM Register (ASF Controller—B1:D8:F0)........................................ 334
8.3.7 WTIM_CONF—Watchdog Timer Configuration Register
(ASF Controller—B1:D8:F0) ................................................................... 334
8.3.8 HEART_TIM—Heartbeat Timer Register (ASF Controller—B1:D8:F0)............. 335
8.3.9 RETRAN_INT—Retransmission Interval Register
(ASF Controller—B1:D8:F0) ................................................................... 335
8.3.10 RETRAN_PCL—Retransmission Packet Count Limit
Register (ASF Controller—B1:D8:F0) ....................................................... 336
8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register
(ASF Controller—B1:D8:F0) ................................................................... 336
8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register
(ASF Controller—B1:D8:F0) ................................................................... 336
8.3.13 PET_SEQ1—PET Sequence 1 Register (ASF Controller—B1:D8:F0) ............... 337
8.3.14 PET_SEQ2—PET Sequence 2 Register (ASF Controller—B1:D8:F0) ............... 337
8.3.15 STA—Status Register (ASF Controller—B1:D8:F0) ..................................... 338
8.3.16 FOR_ACT—Forced Actions Register (ASF Controller—B1:D8:F0)................... 339
8.3.17 RMCP_SNUM—RMCP Sequence Number Register
(ASF Controller—B1:D8:F0) ................................................................... 340
8.3.18 SP_MODE—Special Modes Register (ASF Controller—B1:D8:F0) .................. 340
8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register
(ASF Controller—B1:D8:F0) ................................................................... 340
8.3.20 PHIST_CLR—Poll History Clear Register (ASF Controller—B1:D8:F0) ............ 341
8.3.21 PMSK1—Polling Mask 1 Register (ASF Controller—B1:D8:F0) ...................... 341
8.3.22 PMSK2—Polling Mask 2 Register (ASF Controller—B1:D8:F0) ...................... 342
8.3.23 PMSK3—Polling Mask 3 Register (ASF Controller—B1:D8:F0) ...................... 342
8.3.24 PMSK4—Polling Mask 4 Register (ASF Controller—B1:D8:F0) ...................... 342
8.3.25 PMSK5—Polling Mask 5 Register (ASF Controller—B1:D8:F0) ...................... 343
8.3.26 PMSK6—Polling Mask 6 Register (ASF Controller—B1:D8:F0) ...................... 343
8.3.27 PMSK7—Polling Mask 7 Register (ASF Controller—B1:D8:F0) ...................... 343
8.3.28 PMSK8—Polling Mask 8 Register (ASF Controller—B1:D8:F0) ...................... 344
PCI-to-PCI Bridge Registers (D30:F0).................................................................... 345
9.1
PCI Configuration Registers (D30:F0) ................................................................. 345
9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0) ............................. 346
9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) ............................. 346
9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) ............................................. 346
Intel ® ICH7 Family Datasheet
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
9.1.10
9.1.11
9.1.12
9.1.13
9.1.14
9.1.15
9.1.16
9.1.17
9.1.18
9.1.19
9.1.20
9.1.21
9.1.22
9.1.23
9.1.24
9.1.25
10
PSTS—PCI Status Register (PCI-PCI—D30:F0).......................................... 347
RID—Revision Identification Register (PCI-PCI—D30:F0)............................ 349
CC—Class Code Register (PCI-PCI—D30:F0) ............................................ 349
PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0) ............... 350
HEADTYP—Header Type Register (PCI-PCI—D30:F0) ................................. 350
BNUM—Bus Number Register (PCI-PCI—D30:F0) ...................................... 350
SMLT—Secondary Master Latency Timer Register (PCI-PCI—D30:F0) ........... 351
IOBASE_LIMIT—I/O Base and Limit Register (PCI-PCI—D30:F0) ................. 351
SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................ 352
MEMBASE_LIMIT—Memory Base and Limit Register (PCI-PCI—D30:F0)........ 353
PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0) ..................................................... 353
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................... 354
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................... 354
CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 354
INTR—Interrupt Information Register (PCI-PCI—D30:F0) ........................... 354
BCTRL—Bridge Control Register (PCI-PCI—D30:F0)................................... 355
SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0)................ 356
DTC—Delayed Transaction Control Register (PCI-PCI—D30:F0) ................... 357
BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) ....................... 359
BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0)..................... 360
SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0).............. 361
SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)......................... 361
LPC Interface Bridge Registers (D31:F0) ............................................................... 363
10.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 363
10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .............................. 364
10.1.2 DID—Device Identification Register (LPC I/F—D31:F0) .............................. 364
10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................................ 365
10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................... 365
10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 366
10.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 366
10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..................................... 367
10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0).................................... 367
10.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................ 367
10.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0) .................................. 367
10.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0)............................. 368
10.1.12CAPP—Capability List Pointer (LPC I/F—D31:F0) ....................................... 368
10.1.13PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................... 368
10.1.14ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ............................. 369
10.1.15GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) ..................... 369
10.1.16GC—GPIO Control Register (LPC I/F — D31:F0) ........................................ 370
10.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0) (Desktop and Mobile Only) .......................................... 370
10.1.18SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ....................... 371
10.1.19PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0) ................................................................................ 372
10.1.20LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) .................. 373
10.1.21LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)................................ 374
10.1.22GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) .... 375
10.1.23GEN2_DEC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0)..... 375
10.1.24GEN3_DEC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0)..... 376
10.1.25GEN4_DEC—LPC I/F Generic Decode Range 4Register (LPC I/F—D31:F0)..... 376
10.1.26FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) ................. 377
Intel ® ICH7 Family Datasheet
13
10.2
10.3
10.4
10.5
10.6
14
10.1.27FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0) .................. 378
10.1.28FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) .. 378
10.1.29BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) .............................. 381
10.1.30FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) ........................ 382
10.1.31FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0) .................. 382
10.1.32FDVER—Feature Detection Version (LPC I/F—D31:F0) ................................ 382
10.1.33FDVCT—Feature Vector Register (LPC I/F—D31:F0) ................................... 383
10.1.34RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) .................. 384
DMA I/O Registers (LPC I/F—D31:F0) ................................................................. 385
10.2.1 DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)................................................................... 386
10.2.2 DMABASE_CC—DMA Base and Current Count Registers (LPC I/F—D31:F0) ... 387
10.2.3 DMAMEM_LP—DMA Memory Low Page Registers (LPC I/F—D31:F0) ............. 387
10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) .............................. 388
10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0)..................................... 388
10.2.6 DMA_WRSMSK—DMA Write Single Mask Register (LPC I/F—D31:F0) ............ 389
10.2.7 DMACH_MODE—DMA Channel Mode Register (LPC I/F—D31:F0) ................. 390
10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0) ................................... 391
10.2.9 DMA Master Clear Register (LPC I/F—D31:F0) .......................................... 391
10.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................ 391
10.2.11DMA_WRMSK—DMA Write All Mask Register (LPC I/F—D31:F0)................... 392
Timer I/O Registers (LPC I/F—D31:F0) ............................................................... 392
10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) ............................... 393
10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0) ................................................................................ 395
10.3.3 Counter Access Ports Register (LPC I/F—D31:F0) ...................................... 396
8259 Interrupt Controller (PIC) Registers (LPC I/F—D31:F0) ................................. 396
10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0) ........................................ 396
10.4.2 ICW1—Initialization Command Word 1 Register (LPC I/F—D31:F0) .............. 397
10.4.3 ICW2—Initialization Command Word 2 Register (LPC I/F—D31:F0) .............. 398
10.4.4 ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 398
10.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 399
10.4.6 ICW4—Initialization Command Word 4 Register (LPC I/F—D31:F0) .............. 399
10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0) .................................................................... 400
10.4.8 OCW2—Operational Control Word 2 Register (LPC I/F—D31:F0) .................. 400
10.4.9 OCW3—Operational Control Word 3 Register (LPC I/F—D31:F0) .................. 401
10.4.10ELCR1—Master Controller Edge/Level Triggered Register (LPC I/F—D31:F0).. 402
10.4.11ELCR2—Slave Controller Edge/Level Triggered Register (LPC I/F—D31:F0) ... 403
Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................ 404
10.5.1 APIC Register Map (LPC I/F—D31:F0) ...................................................... 404
10.5.2 IND—Index Register (LPC I/F—D31:F0) ................................................... 404
10.5.3 DAT—Data Register (LPC I/F—D31:F0) .................................................... 405
10.5.4 EOIR—EOI Register (LPC I/F—D31:F0) .................................................... 405
10.5.5 ID—Identification Register (LPC I/F—D31:F0) ........................................... 406
10.5.6 VER—Version Register (LPC I/F—D31:F0) ................................................. 406
10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)...................................... 407
Real Time Clock Registers (LPC I/F—D31:F0)....................................................... 409
10.6.1 I/O Register Address Map (LPC I/F—D31:F0) ............................................ 409
10.6.2 Indexed Registers (LPC I/F—D31:F0) ...................................................... 410
10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0) .................................. 411
10.6.2.2 RTC_REGB—Register B (General Configuration) (LPC I/F—D31:F0). 412
10.6.2.3 RTC_REGC—Register C (Flag Register) (LPC I/F—D31:F0) ............. 413
Intel ® ICH7 Family Datasheet
10.7
10.8
10.9
10.6.2.4 RTC_REGD—Register D (Flag Register) (LPC I/F—D31:F0) ............ 414
Processor Interface Registers (LPC I/F—D31:F0) ................................................. 415
10.7.1 NMI_SC—NMI Status and Control Register (LPC I/F—D31:F0) .................... 415
10.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register (LPC I/F—D31:F0).................................................................... 416
10.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) ............................. 416
10.7.4 COPROC_ERR—Coprocessor Error Register (LPC I/F—D31:F0) .................... 417
10.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0)................................. 417
Power Management Registers (PM—D31:F0) ....................................................... 418
10.8.1 Power Management PCI Configuration Registers (PM—D31:F0) ................... 418
10.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0) ........................................................................ 419
10.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0) ........................................................................ 420
10.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0) ........................................................................ 422
10.8.1.4 Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0) (Mobile/Ultra Mobile Only) ................................... 424
10.8.1.5 C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile/Ultra Mobile Only) ................................... 425
10.8.1.6 BM_BREAK_EN Register (PM—D31:F0) (Mobile/Ultra Mobile Only) . 426
10.8.1.7 MSC_FUN—Miscellaneous Functionality Register (PM—D31:F0)...... 427
10.8.1.8 EL_STS—Intel® Quick Resume Technology Status Register
(PM—D31:F0) (ICH7DH Only)................................................... 427
10.8.1.9 EL_CNT1—Intel® Quick Resume Technology Control 1 Register
(PM—D31:F0) (ICH7DH Only)................................................... 428
10.8.1.10EL_CNT2—Intel® Quick Resume Technology Control 2 Register
(PM—D31:F0) (ICH7DH Only)................................................... 429
10.8.1.11GPIO_ROUT—GPIO Routing Control Register (PM—D31:F0) .......... 429
10.8.2 APM I/O Decode................................................................................... 430
10.8.2.1 APM_CNT—Advanced Power Management Control Port Register ..... 430
10.8.2.2 APM_STS—Advanced Power Management Status Port Register ...... 430
10.8.3 Power Management I/O Registers ........................................................... 431
10.8.3.1 PM1_STS—Power Management 1 Status Register ........................ 432
10.8.3.2 PM1_EN—Power Management 1 Enable Register.......................... 435
10.8.3.3 PM1_CNT—Power Management 1 Control ................................... 436
10.8.3.4 PM1_TMR—Power Management 1 Timer Register ......................... 437
10.8.3.5 PROC_CNT—Processor Control Register...................................... 437
10.8.3.6 LV2 — Level 2 Register (Mobile/Ultra Mobile Only) ....................... 439
10.8.3.7 LV3—Level 3 Register (Mobile/Ultra Mobile Only)......................... 439
10.8.3.8 LV4—Level 4 Register (Mobile/Ultra Mobile Only)......................... 439
10.8.3.9 PM2_CNT—Power Management 2 Control Register
(Mobile/Ultra Mobile Only)........................................................ 440
10.8.3.10GPE0_STS—General Purpose Event 0 Status Register .................. 440
10.8.3.11GPE0_EN—General Purpose Event 0 Enables Register .................. 444
10.8.3.12SMI_EN—SMI Control and Enable Register ................................. 447
10.8.3.13SMI_STS—SMI Status Register ................................................. 449
10.8.3.14ALT_GP_SMI_EN—Alternate GPI SMI Enable Register ................... 452
10.8.3.15ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................. 452
10.8.3.16GPE_CNTL— General Purpose Control Register ............................ 453
10.8.3.17DEVACT_STS — Device Activity Status Register .......................... 454
10.8.3.18SS_CNT— Intel SpeedStep® Technology
Control Register (Mobile/Ultra Mobile Only) ................................ 455
10.8.3.19C3_RES— C3 Residency Register (Mobile/Ultra Mobile Only) ......... 455
System Management TCO Registers (D31:F0) ..................................................... 456
10.9.1 TCO_RLD—TCO Timer Reload and Current Value Register........................... 456
10.9.2 TCO_DAT_IN—TCO Data In Register........................................................ 457
10.9.3 TCO_DAT_OUT—TCO Data Out Register ................................................... 457
Intel ® ICH7 Family Datasheet
15
10.9.4 TCO1_STS—TCO1 Status Register ........................................................... 457
10.9.5 TCO2_STS—TCO2 Status Register ........................................................... 459
10.9.6 TCO1_CNT—TCO1 Control Register .......................................................... 460
10.9.7 TCO2_CNT—TCO2 Control Register .......................................................... 461
10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers........................................ 461
10.9.9 TCO_WDCNT—TCO Watchdog Control Register .......................................... 462
10.9.10SW_IRQ_GEN—Software IRQ Generation Register ..................................... 462
10.9.11TCO_TMR—TCO Timer Initial Value Register.............................................. 462
10.10 General Purpose I/O Registers (D31:F0) ............................................................. 463
10.10.1GPIO_USE_SEL—GPIO Use Select Register ............................................... 464
10.10.2GP_IO_SEL—GPIO Input/Output Select Register........................................ 464
10.10.3GP_LVL—GPIO Level for Input or Output Register ...................................... 465
10.10.4GPO_BLINK—GPO Blink Enable Register ................................................... 465
10.10.5GPI_INV—GPIO Signal Invert Register ..................................................... 466
10.10.6GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]................................ 466
10.10.7GP_IO_SEL2—GPIO Input/Output Select 2 Register[63:32] ........................ 467
10.10.8GP_LVL2—GPIO Level for Input or Output 2 Register[63:32]....................... 467
11
UHCI Controllers Registers .................................................................................... 469
11.1 PCI Configuration Registers (USB—D29:F0/F1/F2/F3) ........................................... 469
11.1.1 VID—Vendor Identification Register (USB—D29:F0/F1/F2/F3) ..................... 470
11.1.2 DID—Device Identification Register (USB—D29:F0/F1/F2/F3) ..................... 470
11.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/F3) ........................ 470
11.1.4 PCISTS—PCI Status Register (USB—D29:F0/F1/F2/F3) .............................. 471
11.1.5 RID—Revision Identification Register (USB—D29:F0/F1/F2/F3) ................... 471
11.1.6 PI—Programming Interface Register (USB—D29:F0/F1/F2/F3) .................... 472
11.1.7 SCC—Sub Class Code Register (USB—D29:F0/F1/F2/F3) ............................ 472
11.1.8 BCC—Base Class Code Register (USB—D29:F0/F1/F2/F3)........................... 472
11.1.9 MLT—Master Latency Timer Register (USB—D29:F0/F1/F2/F3) .................... 473
11.1.10HEADTYP—Header Type Register (USB—D29:F0/F1/F2/F3) ......................... 473
11.1.11BASE—Base Address Register (USB—D29:F0/F1/F2/F3) ............................. 474
11.1.12SVID — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2/F3) . 474
11.1.13SID — Subsystem Identification Register (USB—D29:F0/F1/F2/F3) ............. 474
11.1.14INT_LN—Interrupt Line Register (USB—D29:F0/F1/F2/F3).......................... 475
11.1.15INT_PN—Interrupt Pin Register (USB—D29:F0/F1/F2/F3) ........................... 475
11.1.16USB_RELNUM—Serial Bus Release Number Register
(USB—D29:F0/F1/F2/F3) ....................................................................... 475
11.1.17USB_LEGKEY—USB Legacy Keyboard/Mouse Control
Register (USB—D29:F0/F1/F2/F3)........................................................... 476
11.1.18USB_RES—USB Resume Enable Register (USB—D29:F0/F1/F2/F3) .............. 478
11.1.19CWP—Core Well Policy Register (USB—D29:F0/F1/F2/F3)........................... 478
11.2 USB I/O Registers ............................................................................................ 479
11.2.1 USBCMD—USB Command Register .......................................................... 480
11.2.2 USBSTS—USB Status Register ................................................................ 483
11.2.3 USBINTR—USB Interrupt Enable Register ................................................. 484
11.2.4 FRNUM—Frame Number Register ............................................................ 484
11.2.5 FRBASEADD—Frame List Base Address Register ........................................ 485
11.2.6 SOFMOD—Start of Frame Modify Register ................................................ 486
11.2.7 PORTSC[0,1]—Port Status and Control Register ........................................ 487
12
SATA Controller Registers (D31:F2) (Desktop and Mobile Only) ............................. 489
12.1 PCI Configuration Registers (SATA–D31:F2)......................................................... 489
12.1.1 VID—Vendor Identification Register (SATA—D31:F2).................................. 491
12.1.2 DID—Device Identification Register (SATA—D31:F2).................................. 491
12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)...................................... 491
12.1.4 PCISTS — PCI Status Register (SATA–D31:F2) .......................................... 492
16
Intel ® ICH7 Family Datasheet
12.1.5 RID—Revision Identification Register (SATA—D31:F2) ............................... 493
12.1.6 PI—Programming Interface Register (SATA–D31:F2) ................................. 493
12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h........... 493
12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h........... 494
12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h........... 494
12.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ......................................... 495
12.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2) ..................... 495
12.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2).................... 495
12.1.10PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)........................................................................ 496
12.1.11PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2) .................................................................................... 496
12.1.12SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) .......................................................................... 496
12.1.13SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1) .......................................................................... 497
12.1.14BAR — Legacy Bus Master Base Address Register (SATA–D31:F2) ............... 497
12.1.15ABAR — AHCI Base Address Register (SATA–D31:F2) ................................ 497
12.1.15.1Non AHCI Capable (Intel® ICH7 Feature Supported
Components Only) .................................................................. 497
12.1.15.2AHCI Capable (Intel® ICH7R, ICH7DH, and Mobile Only) .............. 498
12.1.16SVID—Subsystem Vendor Identification Register (SATA–D31:F2) ................ 498
12.1.17SID—Subsystem Identification Register (SATA–D31:F2)............................. 498
12.1.18CAP—Capabilities Pointer Register (SATA–D31:F2) .................................... 499
12.1.19INT_LN—Interrupt Line Register (SATA–D31:F2)....................................... 499
12.1.20INT_PN—Interrupt Pin Register (SATA–D31:F2) ........................................ 499
12.1.21IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2).......................... 499
12.1.22IDE_TIMS — Slave IDE Timing Register (SATA–D31:F2)............................. 501
12.1.23SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2)................. 502
12.1.24SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2).................. 503
12.1.25IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2) .................... 504
12.1.26PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)........................................................................ 506
12.1.27PC—PCI Power Management Capabilities Register (SATA–D31:F2) ............... 506
12.1.28PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)........................................................................ 507
12.1.29MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 507
12.1.30MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) ......... 507
12.1.31MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2) ....... 508
12.1.32MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............ 509
12.1.33MAP—Address Map Register (SATA–D31:F2)............................................. 509
12.1.34PCS—Port Control and Status Register (SATA–D31:F2) .............................. 510
12.1.35SIR—SATA Initialization Register............................................................. 511
12.1.36SIRI—SATA Indexed Registers Index ....................................................... 512
12.1.37STRD—SATA Indexed Register Data ........................................................ 512
12.1.37.1STTT1—SATA Indexed Registers Index 00h
(SATA TX Termination Test Register 1) ....................................... 513
12.1.37.2STME—SATA Indexed Registers Index C1h
(SATA Test Mode Enable Register) ............................................. 513
12.1.37.3STTT2 — SATA Indexed Registers Index 74h
(SATA TX Termination Test Register 2) ....................................... 514
12.1.38SCAP0—SATA Capability Register 0 (SATA–D31:F2)................................... 514
12.1.39SCAP1—SATA Capability Register 1 (SATA–D31:F2)................................... 515
12.1.40ATC—APM Trapping Control Register (SATA–D31:F2) ................................. 516
12.1.41ATS—APM Trapping Status Register (SATA–D31:F2) .................................. 516
12.1.42SP — Scratch Pad Register (SATA–D31:F2) .............................................. 516
Intel ® ICH7 Family Datasheet
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12.2
12.3
13
18
12.1.43BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ............................ 517
12.1.44BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ......................... 518
12.1.45BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ......................... 519
Bus Master IDE I/O Registers (D31:F2)............................................................... 519
12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ........................... 520
12.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ................................ 521
12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2) ........ 522
12.2.4 AIR—AHCI Index Register (D31:F2)......................................................... 522
12.2.5 AIDR—AHCI Index Data Register (D31:F2) ............................................... 522
AHCI Registers (D31:F2) (Intel® ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) .... 523
12.3.1 AHCI Generic Host Control Registers (D31:F2).......................................... 524
12.3.1.1 CAP—Host Capabilities Register (D31:F2) ................................... 524
12.3.1.2 GHC—Global ICH7 Control Register (D31:F2) .............................. 526
12.3.1.3 IS—Interrupt Status Register (D31:F2) ...................................... 527
12.3.1.4 PI—Ports Implemented Register (D31:F2)................................... 528
12.3.1.5 VS—AHCI Version (D31:F2) ...................................................... 528
12.3.2 Port Registers (D31:F2) ......................................................................... 529
12.3.2.1 PxCLB—Port [3:0] Command List Base Address Register (D31:F2) . 531
12.3.2.2 PxCLBU—Port [3:0] Command List Base Address Upper
32-Bits Register (D31:F2)......................................................... 531
12.3.2.3 PxFB—Port [3:0] FIS Base Address Register (D31:F2) .................. 531
12.3.2.4 PxFBU—Port [3:0] FIS Base Address Upper 32-Bits
Register (D31:F2) ................................................................... 532
12.3.2.5 PxIS—Port [3:0] Interrupt Status Register (D31:F2) .................... 532
12.3.2.6 PxIE—Port [3:0] Interrupt Enable Register (D31:F2) .................... 533
12.3.2.7 PxCMD—Port [3:0] Command Register (D31:F2) ......................... 535
12.3.2.8 PxTFD—Port [3:0] Task File Data Register (D31:F2) ..................... 538
12.3.2.9 PxSIG—Port [3:0] Signature Register (D31:F2) ........................... 538
12.3.2.10PxSSTS—Port [3:0] Serial ATA Status Register (D31:F2)............... 539
12.3.2.11PxSCTL — Port [3:0] Serial ATA Control Register (D31:F2) ............ 540
12.3.2.12PxSERR—Port [3:0] Serial ATA Error Register (D31:F2)................. 541
12.3.2.13PxSACT—Port [3:0] Serial ATA Active (D31:F2) ........................... 542
12.3.2.14PxCI—Port [3:0] Command Issue Register (D31:F2) .................... 543
EHCI Controller Registers (D29:F7) ....................................................................... 545
13.1 USB EHCI Configuration Registers
(USB EHCI—D29:F7)........................................................................................ 545
13.1.1 VID—Vendor Identification Register (USB EHCI—D29:F7) ........................... 546
13.1.2 DID—Device Identification Register (USB EHCI—D29:F7) ........................... 546
13.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F7) .............................. 547
13.1.4 PCISTS—PCI Status Register (USB EHCI—D29:F7) .................................... 548
13.1.5 RID—Revision Identification Register (USB EHCI—D29:F7) ......................... 549
13.1.6 PI—Programming Interface Register (USB EHCI—D29:F7) .......................... 549
13.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F7) .................................. 549
13.1.8 BCC—Base Class Code Register (USB EHCI—D29:F7) ................................ 549
13.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F7)............. 550
13.1.10MEM_BASE—Memory Base Address Register (USB EHCI—D29:F7)............... 550
13.1.11SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F7) ......... 550
13.1.12SID—USB EHCI Subsystem ID Register (USB EHCI—D29:F7)...................... 551
13.1.13CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7) ...................... 551
13.1.14INT_LN—Interrupt Line Register (USB EHCI—D29:F7) ............................... 551
13.1.15INT_PN—Interrupt Pin Register (USB EHCI—D29:F7) ................................. 551
13.1.16PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F7)................................................................. 552
13.1.17NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F7) ................. 552
13.1.18PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F7)............................................................................. 552
Intel ® ICH7 Family Datasheet
13.2
14
13.1.19PWR_CNTL_STS—Power Management Control/
Status Register (USB EHCI—D29:F7) ...................................................... 553
13.1.20DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7) ...... 554
13.1.21NXT_PTR2—Next Item Pointer #2 Register (USB EHCI—D29:F7) ................ 554
13.1.22DEBUG_BASE—Debug Port Base Offset Register (USB EHCI—D29:F7) ......... 554
13.1.23USB_RELNUM—USB Release Number Register (USB EHCI—D29:F7) ............ 555
13.1.24FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F7) .............. 555
13.1.25PWAKE_CAP—Port Wake Capability Register (USB EHCI—D29:F7) ............... 556
13.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F7).................................................. 556
13.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7) ......................................... 557
13.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..... 559
13.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) .................... 560
Memory-Mapped I/O Registers .......................................................................... 561
13.2.1 Host Controller Capability Registers ........................................................ 561
13.2.1.1 CAPLENGTH—Capability Registers Length Register....................... 561
13.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register................................................................................. 562
13.2.1.3 HCSPARAMS—Host Controller Structural Parameters .................... 562
13.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register........ 563
13.2.2 Host Controller Operational Registers ...................................................... 564
13.2.2.1 USB2.0_CMD—USB 2.0 Command Register ................................ 565
13.2.2.2 USB2.0_STS—USB 2.0 Status Register ...................................... 568
13.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ....................... 570
13.2.2.4 FRINDEX—Frame Index Register ............................................... 571
13.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register ........ 572
13.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register .... 572
13.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address Register ..... 573
13.2.2.8 CONFIGFLAG—Configure Flag Register ....................................... 573
13.2.2.9 PORTSC—Port N Status and Control Register .............................. 573
13.2.3 USB 2.0-Based Debug Port Register ........................................................ 577
13.2.3.1 CNTL_STS—Control/Status Register .......................................... 577
13.2.3.2 USBPID—USB PIDs Register ..................................................... 580
13.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ......................... 581
13.2.3.4 CONFIG—Configuration Register ............................................... 581
SMBus Controller Registers (D31:F3) .................................................................... 583
14.1 PCI Configuration Registers (SMBUS—D31:F3) .................................................... 583
14.1.1 VID—Vendor Identification Register (SMBUS—D31:F3) .............................. 583
14.1.2 DID—Device Identification Register (SMBUS—D31:F3) .............................. 584
14.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3) ................................. 584
14.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3) ....................................... 585
14.1.5 RID—Revision Identification Register (SMBUS—D31:F3) ............................ 585
14.1.6 PI—Programming Interface Register (SMBUS—D31:F3) ............................. 586
14.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3) ..................................... 586
14.1.8 BCC—Base Class Code Register (SMBUS—D31:F3).................................... 586
14.1.9 SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3) ................... 586
14.1.10SVID — Subsystem Vendor Identification Register (SMBUS—D31:F2/F4) ..... 587
14.1.11SID — Subsystem Identification Register (SMBUS—D31:F2/F4) .................. 587
14.1.12INT_LN—Interrupt Line Register (SMBUS—D31:F3)................................... 587
14.1.13INT_PN—Interrupt Pin Register (SMBUS—D31:F3) .................................... 587
14.1.14HOSTC—Host Configuration Register (SMBUS—D31:F3)............................. 588
14.2 SMBus I/O Registers ........................................................................................ 588
14.2.1 HST_STS—Host Status Register (SMBUS—D31:F3) ................................... 589
14.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3) .................................. 591
14.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3) ............................. 593
Intel ® ICH7 Family Datasheet
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14.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBUS—D31:F3)................. 593
14.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3)..................................... 593
14.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3)..................................... 593
14.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBUS—D31:F3) ............ 594
14.2.8 PEC—Packet Error Check (PEC) Register (SMBUS—D31:F3) ........................ 594
14.2.9 RCV_SLVA—Receive Slave Address Register (SMBUS—D31:F3) ................... 595
14.2.10SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3) ........................ 595
14.2.11AUX_STS—Auxiliary Status Register (SMBUS—D31:F3).............................. 595
14.2.12AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3) ............................. 596
14.2.13SMLINK_PIN_CTL—SMLink Pin Control Register (SMBUS—D31:F3) .............. 596
14.2.14SMBUS_PIN_CTL—SMBUS Pin Control Register (SMBUS—D31:F3) ............... 597
14.2.15SLV_STS—Slave Status Register (SMBUS—D31:F3)................................... 597
14.2.16SLV_CMD—Slave Command Register (SMBUS—D31:F3)............................. 598
14.2.17NOTIFY_DADDR—Notify Device Address Register (SMBUS—D31:F3) ............ 598
14.2.18NOTIFY_DLOW—Notify Data Low Byte Register (SMBUS—D31:F3)............... 599
14.2.19NOTIFY_DHIGH—Notify Data High Byte Register (SMBUS—D31:F3) ............. 599
15
20
IDE Controller Registers (D31:F1).......................................................................... 601
15.1 PCI Configuration Registers (IDE—D31:F1) ......................................................... 601
15.1.1 VID—Vendor Identification Register (IDE—D31:F1).................................... 602
15.1.2 DID—Device Identification Register (IDE—D31:F1).................................... 602
15.1.3 PCICMD—PCI Command Register (IDE—D31:F1)....................................... 602
15.1.4 PCISTS — PCI Status Register (IDE—D31:F1)........................................... 603
15.1.5 RID—Revision Identification Register (IDE—D31:F1).................................. 603
15.1.6 PI—Programming Interface Register (IDE—D31:F1)................................... 604
15.1.7 SCC—Sub Class Code Register (IDE—D31:F1) .......................................... 604
15.1.8 BCC—Base Class Code Register (IDE—D31:F1) ......................................... 604
15.1.9 CLS—Cache Line Size Register (IDE—D31:F1) .......................................... 604
15.1.10PMLT—Primary Master Latency Timer Register (IDE—D31:F1) ..................... 605
15.1.11PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1) ......................................................................... 605
15.1.12PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) ..... 605
15.1.13SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) ........................................................................... 606
15.1.14SCNL_BAR—Secondary Control Block Base Address
Register (IDE D31:F1) ........................................................................... 606
15.1.15BM_BASE — Bus Master Base Address Register (IDE—D31:F1) ................... 607
15.1.16IDE_SVID — Subsystem Vendor Identification (IDE—D31:F1) ..................... 607
15.1.17IDE_SID — Subsystem Identification Register (IDE—D31:F1) ..................... 607
15.1.18INTR_LN—Interrupt Line Register (IDE—D31:F1) ...................................... 608
15.1.19INTR_PN—Interrupt Pin Register (IDE—D31:F1)........................................ 608
15.1.20IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1) ........................... 608
15.1.21IDE_TIMS — IDE Secondary Timing Register (IDE—D31:F1) ....................... 610
15.1.22SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1) (Desktop and Mobile Only) ............................................... 610
15.1.23SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1) .................. 611
15.1.24SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1) ................... 611
15.1.25IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)...................... 612
15.1.26ATC—APM Trapping Control Register (IDE—D31:F1)................................... 614
15.1.27ATS—APM Trapping Status Register (IDE—D31:F1).................................... 614
15.2 Bus Master IDE I/O Registers (IDE—D31:F1) ....................................................... 615
15.2.1 BMICP—Bus Master IDE Command Register (IDE—D31:F1) ........................ 615
15.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1) ............................. 616
15.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register (IDE—D31:F1) ..... 617
Intel ® ICH7 Family Datasheet
16
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only) ................. 619
16.1 AC ’97 Audio PCI Configuration Space (Audio—D30:F2) ........................................ 619
16.1.1 VID—Vendor Identification Register (Audio—D30:F2) ................................ 620
16.1.2 DID—Device Identification Register (Audio—D30:F2)................................. 620
16.1.3 PCICMD—PCI Command Register (Audio—D30:F2) ................................... 621
16.1.4 PCISTS—PCI Status Register (Audio—D30:F2) ......................................... 622
16.1.5 RID—Revision Identification Register (Audio—D30:F2) .............................. 622
16.1.6 PI—Programming Interface Register (Audio—D30:F2) ............................... 623
16.1.7 SCC—Sub Class Code Register (Audio—D30:F2) ....................................... 623
16.1.8 BCC—Base Class Code Register (Audio—D30:F2) ...................................... 623
16.1.9 HEADTYP—Header Type Register (Audio—D30:F2) .................................... 623
16.1.10NAMBAR—Native Audio Mixer Base Address Register (Audio—D30:F2) ......... 624
16.1.11NABMBAR—Native Audio Bus Mastering Base Address
Register (Audio—D30:F2) ...................................................................... 625
16.1.12MMBAR—Mixer Base Address Register (Audio—D30:F2) ............................. 625
16.1.13MBBAR—Bus Master Base Address Register (Audio—D30:F2)...................... 626
16.1.14SVID—Subsystem Vendor Identification Register (Audio—D30:F2) .............. 626
16.1.15SID—Subsystem Identification Register (Audio—D30:F2)........................... 627
16.1.16CAP_PTR—Capabilities Pointer Register (Audio—D30:F2) ........................... 627
16.1.17INT_LN—Interrupt Line Register (Audio—D30:F2) ..................................... 627
16.1.18INT_PN—Interrupt Pin Register (Audio—D30:F2) ...................................... 628
16.1.19PCID—Programmable Codec Identification Register (Audio—D30:F2) ........... 628
16.1.20CFG—Configuration Register (Audio—D30:F2) .......................................... 628
16.1.21PID—PCI Power Management Capability Identification
Register (Audio—D30:F2) ...................................................................... 629
16.1.22PC—Power Management Capabilities Register (Audio—D30:F2) ................... 629
16.1.23PCS—Power Management Control and Status Register (Audio—D30:F2)....... 630
16.2 AC ’97 Audio I/O Space (D30:F2) ...................................................................... 631
16.2.1 x_BDBAR—Buffer Descriptor Base Address Register (Audio—D30:F2) .......... 635
16.2.2 x_CIV—Current Index Value Register (Audio—D30:F2) .............................. 635
16.2.3 x_LVI—Last Valid Index Register (Audio—D30:F2) .................................... 636
16.2.4 x_SR—Status Register (Audio—D30:F2) .................................................. 636
16.2.5 x_PICB—Position In Current Buffer Register (Audio—D30:F2) ..................... 638
16.2.6 x_PIV—Prefetched Index Value Register (Audio—D30:F2) .......................... 638
16.2.7 x_CR—Control Register (Audio—D30:F2) ................................................. 639
16.2.8 GLOB_CNT—Global Control Register (Audio—D30:F2)................................ 640
16.2.9 GLOB_STA—Global Status Register (Audio—D30:F2) ................................. 642
16.2.10CAS—Codec Access Semaphore Register (Audio—D30:F2) ......................... 644
16.2.11SDM—SDATA_IN Map Register (Audio—D30:F2) ....................................... 645
17
AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)............... 647
17.1 AC ’97 Modem PCI Configuration Space (D30:F3) ................................................ 647
17.1.1 VID—Vendor Identification Register (Modem—D30:F3) .............................. 648
17.1.2 DID—Device Identification Register (Modem—D30:F3) .............................. 648
17.1.3 PCICMD—PCI Command Register (Modem—D30:F3) ................................. 648
17.1.4 PCISTS—PCI Status Register (Modem—D30:F3) ....................................... 649
17.1.5 RID—Revision Identification Register (Modem—D30:F3) ............................ 650
17.1.6 PI—Programming Interface Register (Modem—D30:F3) ............................. 650
17.1.7 SCC—Sub Class Code Register (Modem—D30:F3) ..................................... 650
17.1.8 BCC—Base Class Code Register (Modem—D30:F3).................................... 650
17.1.9 HEADTYP—Header Type Register (Modem—D30:F3) .................................. 650
17.1.10MMBAR—Modem Mixer Base Address Register (Modem—D30:F3) ................ 651
17.1.11MBAR—Modem Base Address Register (Modem—D30:F3)........................... 651
17.1.12SVID—Subsystem Vendor Identification Register (Modem—D30:F3) ............ 652
17.1.13SID—Subsystem Identification Register (Modem—D30:F3) ........................ 652
Intel ® ICH7 Family Datasheet
21
17.2
18
22
17.1.14CAP_PTR—Capabilities Pointer Register (Modem—D30:F3).......................... 652
17.1.15INT_LN—Interrupt Line Register (Modem—D30:F3) ................................... 653
17.1.16INT_PIN—Interrupt Pin Register (Modem—D30:F3) ................................... 653
17.1.17PID—PCI Power Management Capability Identification
Register (Modem—D30:F3) .................................................................... 653
17.1.18PC—Power Management Capabilities Register (Modem—D30:F3) ................. 654
17.1.19PCS—Power Management Control and Status Register (Modem—D30:F3) ..... 654
AC ’97 Modem I/O Space (D30:F3) .................................................................... 655
17.2.1 x_BDBAR—Buffer Descriptor List Base Address Register (Modem—D30:F3)... 657
17.2.2 x_CIV—Current Index Value Register (Modem—D30:F3) ............................ 657
17.2.3 x_LVI—Last Valid Index Register (Modem—D30:F3)................................... 657
17.2.4 x_SR—Status Register (Modem—D30:F3)................................................. 658
17.2.5 x_PICB—Position in Current Buffer Register (Modem—D30:F3) ................... 659
17.2.6 x_PIV—Prefetch Index Value Register (Modem—D30:F3)............................ 659
17.2.7 x_CR—Control Register (Modem—D30:F3) ............................................... 660
17.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3) .............................. 661
17.2.9 GLOB_STA—Global Status Register (Modem—D30:F3) ............................... 662
17.2.10CAS—Codec Access Semaphore Register (Modem—D30:F3) ....................... 664
PCI Express* Configuration Registers (Desktop and Mobile Only) .......................... 665
18.1 PCI Express* Configuration Registers
(PCI Express—D28:F0/F1/F2/F3/F4/F5) .............................................................. 665
18.1.1 VID—Vendor Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 667
18.1.2 DID—Device Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 667
18.1.3 PCICMD—PCI Command Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 667
18.1.4 PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 668
18.1.5 RID—Revision Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 669
18.1.6 PI—Programming Interface Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 669
18.1.7 SCC—Sub Class Code Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 669
18.1.8 BCC—Base Class Code Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 670
18.1.9 CLS—Cache Line Size Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 670
18.1.10PLT—Primary Latency Timer Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 670
18.1.11HEADTYP—Header Type Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 670
18.1.12BNUM—Bus Number Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 671
18.1.13IOBL—I/O Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 671
18.1.14SSTS—Secondary Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 672
18.1.15MBL—Memory Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 673
18.1.16PMBL—Prefetchable Memory Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 673
18.1.17PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)....................................... 674
Intel ® ICH7 Family Datasheet
18.1.18PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................... 674
18.1.19CAPP—Capabilities List Pointer Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 674
18.1.20INTR—Interrupt Information Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 675
18.1.21BCTRL—Bridge Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 676
18.1.22CLIST—Capabilities List Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677
18.1.23XCAP—PCI Express* Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677
18.1.24DCAP—Device Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 678
18.1.25DCTL—Device Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 679
18.1.26DSTS—Device Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 680
18.1.27LCAP—Link Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 681
18.1.28LCTL—Link Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 682
18.1.29LSTS—Link Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ............ 683
18.1.30SLCAP—Slot Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 684
18.1.31SLCTL—Slot Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) .......... 685
18.1.32SLSTS—Slot Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)........... 686
18.1.33RCTL—Root Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)........... 687
18.1.34RSTS—Root Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ........... 687
18.1.35MID—Message Signaled Interrupt Identifiers Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 688
18.1.36MC—Message Signaled Interrupt Message Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 688
18.1.37MA—Message Signaled Interrupt Message Address
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................... 688
18.1.38MD—Message Signaled Interrupt Message Data Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689
18.1.39SVCAP—Subsystem Vendor Capability Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689
18.1.40SVID—Subsystem Vendor Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689
18.1.41PMCAP—Power Management Capability Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689
18.1.42PMC—PCI Power Management Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 690
18.1.43PMCS—PCI Power Management Control and Status
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ...................................... 690
18.1.44MPC—Miscellaneous Port Configuration Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 691
18.1.45SMSCS—SMI/SCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ... 693
18.1.46RPDCGEN - Root Port Dynamic Clock Gating Enable
(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)................................. 694
18.1.47IPWS—Intel® PRO/Wireless 3945ABG Status
(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Mobile Only) ............................... 694
18.1.48VCH—Virtual Channel Capability Header Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 695
Intel ® ICH7 Family Datasheet
23
18.1.49VCAP2—Virtual Channel Capability 2 Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 695
18.1.50PVC—Port Virtual Channel Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 695
18.1.51PVS — Port Virtual Channel Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 696
18.1.52V0CAP — Virtual Channel 0 Resource Capability Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 696
18.1.53V0CTL — Virtual Channel 0 Resource Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 697
18.1.54V0STS — Virtual Channel 0 Resource Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 697
18.1.55UES — Uncorrectable Error Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 698
18.1.56UEM — Uncorrectable Error Mask
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 699
18.1.57UEV — Uncorrectable Error Severity
Q(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................. 700
18.1.58CES — Correctable Error Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 701
18.1.59CEM — Correctable Error Mask Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 701
18.1.60AECC — Advanced Error Capabilities and Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 702
18.1.61RES — Root Error Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 702
18.1.62RCTCL — Root Complex Topology Capability List Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 703
18.1.63ESD — Element Self Description Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 703
18.1.64ULD — Upstream Link Description Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 704
18.1.65ULBA — Upstream Link Base Address Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 704
18.1.66PEETM — PCI Express Extended Test Mode Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5) ................................................... 704
19
24
Intel® High Definition Audio Controller Registers (D27:F0).................................... 705
19.1 Intel® High Definition Audio PCI Configuration Space (Intel® High Definition
Audio— D27:F0) .............................................................................................. 705
19.1.1 VID—Vendor Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 707
19.1.2 DID—Device Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 707
19.1.3 PCICMD—PCI Command Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 708
19.1.4 PCISTS—PCI Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 709
19.1.5 RID—Revision Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 709
19.1.6 PI—Programming Interface Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 710
19.1.7 SCC—Sub Class Code Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 710
19.1.8 BCC—Base Class Code Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 710
19.1.9 CLS—Cache Line Size Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 710
Intel ® ICH7 Family Datasheet
19.1.10LT—Latency Timer Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 710
19.1.11HEADTYP—Header Type Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 711
19.1.12HDBARL—Intel® High Definition Audio Lower Base Address Register
(Intel® High Definition Audio—D27:F0) ................................................... 711
19.1.13HDBARU—Intel® High Definition Audio Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 711
19.1.14SVID—Subsystem Vendor Identification Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 712
19.1.15SID—Subsystem Identification Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 712
19.1.16CAPPTR—Capabilities Pointer Register (Audio—D30:F2) ............................. 713
19.1.17INTLN—Interrupt Line Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 713
19.1.18INTPN—Interrupt Pin Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 713
19.1.19HDCTL—Intel® High Definition Audio Control Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 714
19.1.20TCSEL—Traffic Class Select Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 715
19.1.21DCKCTL—Docking Control Register (Mobile Only)
(Intel® High Definition Audio Controller—D27:F0)..................................... 715
19.1.22DCKSTS—Docking Status Register
(Intel® High Definition Audio Controller—D27:F0) (Mobile Only) ................. 716
19.1.23PID—PCI Power Management Capability ID Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 716
19.1.24PC—Power Management Capabilities Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 716
19.1.25PCS—Power Management Control and Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 717
19.1.26MID—MSI Capability ID Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 718
19.1.27MMC—MSI Message Control Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 718
19.1.28MMLA—MSI Message Lower Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 718
19.1.29MMUA—MSI Message Upper Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 718
19.1.30MMD—MSI Message Data Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 719
19.1.31PXID—PCI Express* Capability ID Register
(Intel® High Definition Audio Controller—D27:F0) (Desktop and Mobile Only)719
19.1.32PXC—PCI Express* Capabilities Register (Desktop and Mobile Only)
(Intel® High Definition Audio Controller—D27:F0)..................................... 719
19.1.33DEVCAP—Device Capabilities Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 720
19.1.34DEVC—Device Control Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 721
19.1.35DEVS—Device Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 721
19.1.36VCCAP—Virtual Channel Enhanced Capability Header
(Intel® High Definition Audio Controller—D27:F0)
(Desktop and Mobile Only) .................................................................... 722
19.1.37PVCCAP1—Port VC Capability Register 1
(Intel® High Definition Audio Controller—D27:F0)
(Desktop and Mobile Only) .................................................................... 722
Intel ® ICH7 Family Datasheet
25
19.2
26
19.1.38PVCCAP2 — Port VC Capability Register 2
(Intel® High Definition Audio Controller—D27:F0) ..................................... 722
19.1.39PVCCTL — Port VC Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 723
19.1.40PVCSTS—Port VC Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 723
19.1.41VC0CAP—VC0 Resource Capability Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 723
19.1.42VC0CTL—VC0 Resource Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 724
19.1.43VC0STS—VC0 Resource Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 724
19.1.44VCiCAP—VCi Resource Capability Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 725
19.1.45VCiCTL—VCi Resource Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 725
19.1.46VCiSTS—VCi Resource Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 726
19.1.47RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register (Intel® High Definition Audio
Controller—D27:F0) (Desktop and Mobile Only) ........................................ 726
19.1.48ESD—Element Self Description Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 726
19.1.49L1DESC—Link 1 Description Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 727
19.1.50L1ADDL—Link 1 Lower Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 727
19.1.51L1ADDU—Link 1 Upper Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 727
® High Definition Audio Memory-Mapped Configuration Registers
Intel
(Intel® High Definition Audio— D27:F0).............................................................. 728
19.2.1 GCAP—Global Capabilities Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 732
19.2.2 VMIN—Minor Version Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 732
19.2.3 VMAJ—Major Version Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 732
19.2.4 OUTPAY—Output Payload Capability Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 733
19.2.5 INPAY—Input Payload Capability Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 733
19.2.6 GCTL—Global Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 734
19.2.7 WAKEEN—Wake Enable Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 735
19.2.8 STATESTS—State Change Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 735
19.2.9 GSTS—Global Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 736
19.2.10ECAP—Extended Capabilities
(Intel® High Definition Audio Controller—D27:F0) ..................................... 737
19.2.11OUTSTRMPAY—Output Stream Payload Capability
(Intel® High Definition Audio Controller—D27:F0) ..................................... 737
19.2.12INSTRMPAY—Input Stream Payload Capability
(Intel® High Definition Audio Controller—D27:F0) ..................................... 738
19.2.13INTCTL—Interrupt Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 739
Intel ® ICH7 Family Datasheet
19.2.14INTSTS—Interrupt Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 740
19.2.15WALCLK—Wall Clock Counter Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 741
19.2.16SSYNC—Stream Synchronization Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 741
19.2.17CORBLBASE—CORB Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 742
19.2.18CORBUBASE—CORB Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 742
19.2.19CORBWP—CORB Write Pointer Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 742
19.2.20CORBRP—CORB Read Pointer Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 743
19.2.21CORBCTL—CORB Control Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 743
19.2.22CORBST—CORB Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 744
19.2.23CORBSIZE—CORB Size Register
Intel® High Definition Audio Controller—D27:F0) ...................................... 744
19.2.24RIRBLBASE—RIRB Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 744
19.2.25RIRBUBASE—RIRB Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 745
19.2.26RIRBWP—RIRB Write Pointer Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 745
19.2.27RINTCNT—Response Interrupt Count Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 746
19.2.28RIRBCTL—RIRB Control Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 746
19.2.29RIRBSTS—RIRB Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 747
19.2.30RIRBSIZE—RIRB Size Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 747
19.2.31IC—Immediate Command Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 747
19.2.32IR—Immediate Response Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 748
19.2.33IRS—Immediate Command Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 748
19.2.34DPLBASE—DMA Position Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 749
19.2.35DPUBASE—DMA Position Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 749
19.2.36SDCTL—Stream Descriptor Control Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 750
19.2.37SDSTS—Stream Descriptor Status Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 752
19.2.38SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel® High Definition Audio Controller—D27:F0) ........................ 753
19.2.39SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 753
19.2.40SDLVI—Stream Descriptor Last Valid Index Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 754
19.2.41SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel® High Definition Audio Controller—D27:F0)..................................... 754
Intel ® ICH7 Family Datasheet
27
19.2.42SDFIFOS—Stream Descriptor FIFO Size Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 755
19.2.43SDFMT—Stream Descriptor Format Register
(Intel® High Definition Audio Controller—D27:F0) ..................................... 756
19.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base
Address Register (Intel® High Definition Audio Controller—D27:F0) ............. 757
19.2.45SDBDPU—Stream Descriptor Buffer Descriptor List PointerUpper Base
Address Register (Intel® High Definition Audio Controller—D27:F0) ............. 757
20
High Precision Event Timer Registers..................................................................... 759
20.1 Memory Mapped Registers ................................................................................ 759
20.1.1 GCAP_ID—General Capabilities and Identification Register.......................... 760
20.1.2 GEN_CONF—General Configuration Register ............................................. 761
20.1.3 GINTR_STA—General Interrupt Status Register ......................................... 761
20.1.4 MAIN_CNT—Main Counter Value Register ................................................. 762
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register...................... 762
20.1.6 TIMn_COMP—Timer n Comparator Value Register ...................................... 764
21
Serial Peripheral Interface (SPI) (Desktop and Mobile Only) ................................. 765
21.1 Serial Peripheral Interface Memory Mapped Configuration Registers ........................ 765
21.1.1 SPIS—SPI Status Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 767
21.1.2 SPIC—SPI Control Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 768
21.1.3 SPIA—SPI Address Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 769
21.1.4 SPID[N] —SPI Data N Register (SPI Memory Mapped Configuration
Registers) ............................................................................................ 769
21.1.5 BBAR—BIOS Base Address Register
(SPI Memory Mapped Configuration Registers).......................................... 770
21.1.6 PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 770
21.1.7 OPTYPE—Opcode Type Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 771
21.1.8 OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers).......................................... 772
21.1.9 PBR[N]—Protected BIOS Range [N]
(SPI Memory Mapped Configuration Registers).......................................... 772
22
Ballout Definition ................................................................................................... 773
22.1 Desktop, Mobile, and Digital Home Component Ballout.......................................... 773
22.2 Ultra Mobile Component Ballout ......................................................................... 782
23
Electrical Characteristics........................................................................................ 789
23.1 Thermal Specifications...................................................................................... 789
23.2 Absolute Maximum Ratings ............................................................................... 789
23.3 DC Characteristics ........................................................................................... 790
23.4 AC Characteristics............................................................................................ 801
23.5 Timing Diagrams ............................................................................................. 817
24
Package Information ............................................................................................. 835
24.1 Desktop and Mobile Package Information ............................................................ 835
24.2 Ultra Mobile Package Information ....................................................................... 837
25
Testability (Desktop and Mobile Only).................................................................... 839
25.1 XOR Chain Tables............................................................................................. 841
28
Intel ® ICH7 Family Datasheet
Figures
2-1 Interface Signals Block Diagram (Desktop Only)........................................................... 52
2-2 Interface Signals Block Diagram (Mobile Only) ............................................................ 53
2-3 Interface Signals Block Diagram (Ultra Mobile Only) ..................................................... 54
2-4 Example External RTC Circuit..................................................................................... 78
4-1 Desktop Only Conceptual System Clock Diagram .......................................................... 96
4-2 Mobile Only Conceptual Clock Diagram........................................................................ 96
4-3 Ultra Mobile Only Conceptual Clock Diagram ................................................................ 97
5-1 Generation of SERR# to Platform ............................................................................. 105
5-2 64-Word EEPROM Read Instruction Waveform............................................................ 112
5-3 LPC Interface Diagram ............................................................................................ 118
5-4 LPC Bridge SERR# Generation ................................................................................. 123
5-5 Intel® ICH7 DMA Controller ..................................................................................... 124
5-6 DMA Request Assertion through LDRQ# .................................................................... 127
5-7 Coprocessor Error Timing Diagram ........................................................................... 151
5-8 Physical Region Descriptor Table Entry...................................................................... 186
5-9 SATA Power States................................................................................................. 195
5-10USB Legacy Keyboard Flow Diagram......................................................................... 205
5-11 Intel® ICH7-USB Port Connections .......................................................................... 212
5-12Intel® ICH7-Based Audio Codec ’97 Specification, Version 2.3...................................... 233
5-13AC ’97 2.3 Controller-Codec Connection .................................................................... 235
5-14AC-Link Protocol .................................................................................................... 236
5-15AC-Link Powerdown Timing ..................................................................................... 237
5-16SDIN Wake Signaling.............................................................................................. 238
22-1 Desktop and Mobile Component Ballout (Topview–Left Side) ....................................... 774
22-2Desktop and Mobile Component Ballout (Topview–Right Side) ...................................... 775
22-3Intel® ICH7-U Ballout (top view, left side)................................................................. 782
22-4Intel® ICH7-U Ballout (top view, right side)............................................................... 783
23-1Clock Timing ......................................................................................................... 817
23-2Valid Delay from Rising Clock Edge........................................................................... 817
23-3Setup and Hold Times............................................................................................. 817
23-4Float Delay ........................................................................................................... 818
23-5Pulse Width ........................................................................................................... 818
23-6Output Enable Delay............................................................................................... 818
23-7IDE PIO Mode........................................................................................................ 819
23-8IDE Multiword DMA ................................................................................................ 819
23-9Ultra ATA Mode (Drive Initiating a Burst Read)........................................................... 820
23-10Ultra ATA Mode (Sustained Burst) .......................................................................... 820
23-11Ultra ATA Mode (Pausing a DMA Burst).................................................................... 821
23-12Ultra ATA Mode (Terminating a DMA Burst).............................................................. 821
23-13USB Rise and Fall Times ........................................................................................ 822
23-14USB Jitter............................................................................................................ 822
23-15USB EOP Width .................................................................................................... 822
23-16SMBus Transaction ............................................................................................... 823
23-17SMBus Timeout.................................................................................................... 823
23-18Power Sequencing and Reset Signal Timings (Desktop Only) ...................................... 824
23-19Power Sequencing and Reset Signal Timings (Mobile/Ultra Mobile Only)....................... 825
23-20G3 (Mechanical Off) to S0 Timings (Desktop Only).................................................... 826
23-21G3 (Mechanical Off) to S0 Timings (Mobile/Ultra Mobile Only) .................................... 827
23-22S0 to S1 to S0 Timing (Desktop Only)..................................................................... 827
23-23S0 to S5 to S0 Timings, S3COLD (Desktop Only)........................................................ 828
23-24S0 to S5 to S0 Timings, S3HOT (Desktop Only) ......................................................... 829
23-25S0 to S5 to S0 Timings, S3COLD (Mobile/Ultra Mobile Only) ........................................ 830
23-26S0 to S5 to S0 Timings, S3HOT (Mobile/Ultra Mobile Only).......................................... 831
Intel ® ICH7 Family Datasheet
29
23-27C0 to C2 to C0 Timings (Mobile/Ultra Mobile Only) .................................................... 831
23-28C0 to C3 to C0 Timings (Mobile/Ultra Mobile Only) .................................................... 832
23-29C0 to C4 to C0 Timings (Mobile/Ultra Mobile Only) .................................................... 832
23-30AC ’97 Data Input and Output Timings (Desktop and Mobile Only)............................... 833
23-31Intel® High Definition Audio Input and Output Timings .............................................. 833
23-32SPI Timings (Desktop and Mobile Only) ................................................................... 834
24-1Intel® ICH7 Package (Top View)............................................................................... 835
24-2Intel® ICH7 Package (Bottom View).......................................................................... 836
24-3Intel® ICH7 Package (Side View).............................................................................. 836
24-4Intel ICH7-U Package Drawing ................................................................................. 837
25-1XOR Chain Test Mode Selection, Entry and Testing...................................................... 839
25-2Example XOR Chain Circuitry ................................................................................... 840
Tables
1-1 Industry Specifications ..............................................................................................39
1-2 PCI Devices and Functions .........................................................................................43
1-3 Intel® ICH7 Desktop/Server Family ............................................................................50
1-4 Intel® ICH7-M Mobile and ICH7-U Ultra Mobile Components ...........................................50
2-1 Direct Media Interface Signals ....................................................................................55
2-2 PCI Express* Signals ................................................................................................55
2-3 Platform LAN Connect Interface Signals .......................................................................56
2-4 EEPROM Interface Signals..........................................................................................56
2-5 Firmware Hub Interface Signals ..................................................................................56
2-6 PCI Interface Signals ................................................................................................57
2-7 Serial ATA Interface Signals .......................................................................................59
2-8 IDE Interface Signals ................................................................................................60
2-9 LPC Interface Signals ................................................................................................62
2-10Interrupt Signals ......................................................................................................62
2-11USB Interface Signals ...............................................................................................63
2-12Power Management Interface Signals ..........................................................................64
2-13Processor Interface Signals ........................................................................................66
2-14SM Bus Interface Signals ...........................................................................................68
2-15System Management Interface Signals ........................................................................68
2-16Real Time Clock Interface ..........................................................................................69
2-17Other Clocks ............................................................................................................69
2-18Miscellaneous Signals................................................................................................70
2-19AC ’97/Intel® High Definition Audio Link Signals ...........................................................71
2-20Serial Peripheral Interface (SPI) Signals ......................................................................72
2-21General Purpose I/O Signals ......................................................................................72
2-22Power and Ground Signals .........................................................................................74
2-23Functional Strap Definitions .......................................................................................76
3-1 Integrated Pull-Up and Pull-Down Resistors..................................................................79
3-2 IDE Series Termination Resistors ................................................................................80
3-3 Power Plane and States for Output and I/O Signals for Desktop Only Configurations ..........81
3-4 Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only
Configurations .........................................................................................................86
3-5 Power Plane for Input Signals for Desktop Only Configurations .......................................90
3-6 Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations ........................92
4-1 Intel® ICH7 and System Clock Domains ......................................................................95
5-1 PCI Bridge Initiator Cycle Types .................................................................................99
5-2 Type 1 Address Format ........................................................................................... 102
5-3 MSI vs. PCI IRQ Actions .......................................................................................... 104
5-4 Advanced TCO Functionality ..................................................................................... 114
5-5 LPC Cycle Types Supported...................................................................................... 119
30
Intel ® ICH7 Family Datasheet
5-6 Start Field Bit Definitions ........................................................................................ 119
5-7 Cycle Type Bit Definitions........................................................................................ 120
5-8 Transfer Size Bit Definition ...................................................................................... 120
5-9 SYNC Bit Definition................................................................................................. 121
5-10DMA Transfer Size.................................................................................................. 126
5-11Address Shifting in 16-Bit I/O DMA Transfers ............................................................. 126
5-12Counter Operating Modes........................................................................................ 131
5-13Interrupt Controller Core Connections ....................................................................... 133
5-14Interrupt Status Registers ....................................................................................... 134
5-15Content of Interrupt Vector Byte .............................................................................. 134
5-16APIC Interrupt Mapping .......................................................................................... 140
5-17Interrupt Message Address Format ........................................................................... 142
5-18Interrupt Message Data Format ............................................................................... 143
5-19Stop Frame Explanation .......................................................................................... 144
5-20Data Frame Format ................................................................................................ 145
5-21Configuration Bits Reset by RTCRST# Assertion ......................................................... 148
5-22INIT# Going Active ................................................................................................ 150
5-23NMI Sources.......................................................................................................... 151
5-24DP Signal Differences ............................................................................................. 152
5-25General Power States for Systems Using Intel® ICH7.................................................. 153
5-26State Transition Rules for Intel® ICH7 ...................................................................... 155
5-27System Power Plane ............................................................................................... 156
5-28Causes of SMI# and SCI ......................................................................................... 157
5-29Break Events (Mobile/Ultra Mobile Only).................................................................... 160
5-30Sleep Types .......................................................................................................... 163
5-31Causes of Wake Events........................................................................................... 164
5-32GPI Wake Events ................................................................................................... 165
5-33Transitions Due to Power Failure .............................................................................. 166
5-34Transitions Due to Power Button .............................................................................. 167
5-35Transitions Due to RI# Signal .................................................................................. 168
5-36Write Only Registers with Read Paths in ALT Access Mode ........................................... 171
5-37PIC Reserved Bits Return Values .............................................................................. 173
5-38Register Write Accesses in ALT Access Mode .............................................................. 173
5-39Intel® ICH7 Clock Inputs ........................................................................................ 176
5-40Heartbeat Message Data ......................................................................................... 182
5-41 IDE Transaction Timings (PCI Clocks) ...................................................................... 184
5-42Interrupt/Active Bit Interaction Definition .................................................................. 188
5-43SATA Features Support in Intel® ICH7 ...................................................................... 191
5-44SATA Feature Description........................................................................................ 192
5-45Legacy Replacement Routing ................................................................................... 198
5-46Bits Maintained in Low Power States ......................................................................... 204
5-47USB Legacy Keyboard State Transitions .................................................................... 205
5-48UHCI vs. EHCI ....................................................................................................... 207
5-49Debug Port Behavior .............................................................................................. 215
5-50I2C Block Read ...................................................................................................... 223
5-51Enable for SMBALERT# ........................................................................................... 225
5-52Enables for SMBus Slave Write and SMBus Host Events............................................... 225
5-53Enables for the Host Notify Command ....................................................................... 226
5-54Slave Write Registers ............................................................................................. 227
5-55Command Types .................................................................................................... 228
5-56Read Cycle Format ................................................................................................. 229
5-57Data Values for Slave Read Registers........................................................................ 229
5-58Host Notify Format ................................................................................................. 231
5-59Features Supported by Intel® ICH7 .......................................................................... 232
5-60Output Tag Slot 0 .................................................................................................. 237
Intel ® ICH7 Family Datasheet
31
5-61SPI Implementation Options .................................................................................... 245
5-62Required Commands and Opcodes ............................................................................ 247
5-63Intel® ICH7 Standard SPI Commands ....................................................................... 247
5-64Flash Protection Mechanism Summary....................................................................... 248
6-1 PCI Devices and Functions ....................................................................................... 254
6-2 Fixed I/O Ranges Decoded by Intel® ICH7 ................................................................. 256
6-3 Variable I/O Decode Ranges..................................................................................... 258
6-4 Memory Decode Ranges from Processor Perspective.................................................... 259
7-1 Chipset Configuration Register Memory Map (Memory Space) ....................................... 263
8-1 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) ........................... 303
8-2 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM .......................... 310
8-3 Data Register Structure ........................................................................................... 314
8-4 Intel® ICH7 Integrated LAN Controller CSR Space Register Address Map........................ 315
8-5 Self-Test Results Format ......................................................................................... 320
8-6 Statistical Counters................................................................................................. 327
8-7 ASF Register Address Map ....................................................................................... 329
9-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0) ................................................... 345
10-1LPC Interface PCI Register Address Map (LPC I/F—D31:F0) .......................................... 363
10-2DMA Registers ....................................................................................................... 385
10-3PIC Registers (LPC I/F—D31:F0)............................................................................... 396
10-4APIC Direct Registers (LPC I/F—D31:F0) ................................................................... 404
10-5APIC Indirect Registers (LPC I/F—D31:F0) ................................................................. 404
10-6RTC I/O Registers (LPC I/F—D31:F0) ........................................................................ 409
10-7RTC (Standard) RAM Bank (LPC I/F—D31:F0) ............................................................ 410
10-8Processor Interface PCI Register Address Map (LPC I/F—D31:F0).................................. 415
10-9Power Management PCI Register Address Map (PM—D31:F0) ....................................... 418
10-10APM Register Map ................................................................................................. 430
10-11ACPI and Legacy I/O Register Map .......................................................................... 431
10-12TCO I/O Register Address Map ............................................................................... 456
10-13Registers to Control GPIO Address Map.................................................................... 463
11-1UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3) ............................. 469
11-2USB I/O Registers .................................................................................................. 479
11-3Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation .................. 482
12-1SATA Controller PCI Register Address Map (SATA–D31:F2) .......................................... 489
12-2Bus Master IDE I/O Register Address Map.................................................................. 519
12-3AHCI Register Address Map...................................................................................... 523
12-4Generic Host Controller Register Address Map ............................................................ 524
12-5Port [3:0] DMA Register Address Map ....................................................................... 529
13-1USB EHCI PCI Register Address Map (USB EHCI—D29:F7) ........................................... 545
13-2Enhanced Host Controller Capability Registers ............................................................ 561
13-3Enhanced Host Controller Operational Register Address Map ........................................ 564
13-4Debug Port Register Address Map ............................................................................. 577
14-1SMBus Controller PCI Register Address Map (SMBUS—D31:F3)..................................... 583
14-2SMBus I/O Register Address Map.............................................................................. 588
15-1IDE Controller PCI Register Address Map (IDE-D31:F1) ............................................... 601
15-2Bus Master IDE I/O Registers ................................................................................... 615
16-1AC ‘97 Audio PCI Register Address Map (Audio—D30:F2) ............................................. 619
16-2Intel® ICH7 Audio Mixer Register Configuration .......................................................... 631
16-3Native Audio Bus Master Control Registers ................................................................. 633
17-1AC ‘97 Modem PCI Register Address Map (Modem—D30:F3) ........................................ 647
17-2Intel® ICH7 Modem Mixer Register Configuration........................................................ 655
17-3Modem Registers.................................................................................................... 656
18-1PCI Express* Configuration Registers Address Map
(PCI Express—D28:F0/F1/F2/F3/F4/F5)..................................................................... 665
32
Intel ® ICH7 Family Datasheet
19-1Intel® High Definition Audio PCI Register Address Map
(Intel® High Definition Audio D27:F0)....................................................................... 705
19-2Intel® High Definition Audio PCI Register Address Map
(Intel® High Definition Audio D27:F0)....................................................................... 728
20-1Memory-Mapped Registers ...................................................................................... 759
21-1Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) ........................................................... 765
22-1 Desktop and Mobile Component Ballout by Signal Name ............................................. 776
22-2Intel® ICH7-U Ballout by Signal Name ...................................................................... 784
23-1Intel® ICH7 Absolute Maximum Ratings .................................................................... 789
23-2DC Current Characteristics ...................................................................................... 790
23-3DC Current Characteristics (Mobile/Ultra Mobile Only) ................................................. 791
23-4DC Characteristic Input Signal Association................................................................. 792
23-5DC Input Characteristics ......................................................................................... 794
23-6DC Characteristic Output Signal Association............................................................... 796
23-7DC Output Characteristics ....................................................................................... 798
23-8Other DC Characteristics ......................................................................................... 799
23-9Clock Timings ........................................................................................................ 801
23-10PCI Interface Timing............................................................................................. 803
23-11IDE PIO Mode Timings .......................................................................................... 804
23-12IDE Multiword DMA Timings ................................................................................... 804
23-13Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ............................................................ 805
23-14Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ............................................................ 807
23-15Universal Serial Bus Timing ................................................................................... 809
23-16SATA Interface Timings (Desktop and Mobile Only) ................................................... 810
23-17SMBus Timing...................................................................................................... 810
23-19LPC Timing .......................................................................................................... 811
23-20Miscellaneous Timings........................................................................................... 811
23-18AC ’97 / Intel® High Definition Audio Timing ............................................................ 811
23-21SPI Timings (Desktop and Mobile Only) ................................................................... 812
23-22(Power Sequencing and Reset Signal Timings........................................................... 812
23-23Power Management Timings .................................................................................. 814
25-1XOR Test Pattern Example ...................................................................................... 840
25-2XOR Chain 1 (REQ[4:1]# = 0000)............................................................................ 841
25-3XOR Chain 2 (REQ[4:1]# = 0001)............................................................................ 842
25-4XOR Chain 3 (REQ[4:1]# = 0010)............................................................................ 843
25-5XOR Chain 4-1 (REQ[4:1]# = 0011)......................................................................... 844
25-6XOR Chain 4-2 (REQ[4:1]# = 0011)......................................................................... 845
25-7XOR Chain 5 (REQ[4:1]# = 0100)............................................................................ 846
Intel ® ICH7 Family Datasheet
33
Revision History
Revision
-001
Description
•
Date
Initial release
April 2005
-002
•
Added specificaitons for ICH7DH, ICH7-M, and ICH7-M DH
-003
•
•
Added specifications for the ICH7-U
Added Documentation Changes/Specification Changes from Spec Update Revision -020.
January 2006
April 2007
§
34
Intel ® ICH7 Family Datasheet
Intel® ICH7 Family Features
„ Direct Media Interface
„
„
„
„
„
„
— 10 Gb/s each direction, full duplex
— Transparent to software
PCI Express* (Desktop and Mobile Only)
— 4 PCI Express root ports
— NEW: 2 Additional PCI Express root ports (ICH7R/
Digital Home only) configurable as x1 only
— Supports PCI Express 1.0a
— Ports 1-4 can be statically configured as 4x1, or 1x4.
— Support for full 2.5 Gb/s bandwidth in each direction
per x1 lane
— Module based Hot-Plug supported
(e.g., ExpressCard*) (Desktop and Mobile Only)
PCI Bus Interface
— Supports PCI Rev 2.3 Specification at 33 MHz
— New: Six available PCI REQ/GNT pairs (3 pairs on
Ultra Mobile)
— Support for 64-bit addressing on PCI using DAC
protocol
Integrated Serial ATA Host Controller (Desktop and Mobile
Only)
— Four ports (desktop only) or two ports (Mobile only)
— NEW: Data transfer rates up to 3.0 Gb/s
(300 MB/s) (Desktop Only)
— Integrated AHCI controller
(RAID, Digital Home and Mobile only)
Intel® Matrix Storage Technology
(RAID and Digital Home only)
— Configures the ICH7 SATA controller as a RAID
controller supporting RAID 0/1/10 (RAID and ICH7
DH only)
— Configures the ICH7 SATA controller as a RAID
controller supporting RAID 0/1 (ICH7-M DH)
— NEW: Support for RAID 5 (RAID and ICH7 DH only)
Integrated IDE Controller
— Independent timing of up to two drives (one drive on
Ultra Mobile)
— Ultra ATA/100/66/33, BMIDE and PIO modes
— Tri-state modes to enable swap bay
— Supports ATA/ATAPI-7
Intel® High Definition Audio Interface
— PCI Express endpoint
— Independent Bus Master logic for eight general purpose
streams: four input and four output
— Support three external Codecs
— Supports variable length stream slots
— Supports multichannel, 32-bit sample depth and 192
kHz sample rate output
— Provides mic array support
— Allows for non-48 kHz sampling output
— Support for ACPI Device States
— NEW: Docking Support (Mobile Only)
— NEW: Low Voltage Mode (Mobile/Ultra Mobile Only)
Intel ® ICH7 Family Datasheet
„ AC-Link for Audio and Telephony CODECs (Desktop and
„
„
„
„
„
„
„
Mobile Only)
— Support for three AC ‘97 2.3 codecs.
— Independent bus master logic for 8 channels (PCM In/
Out, PCM 2 In, Mic 1 Input, Mic 2 Input, Modem In/
Out, S/PDIF Out)
— Support for up to six channels of PCM audio output
(full AC3 decode)
— Supports wake-up events
USB 2.0
— Includes four UHCI Host Controllers, supporting eight
external ports
— Includes one EHCI Host Controller that supports all
eight ports
— Includes one USB 2.0 High-speed Debug Port
— Supports wake-up from sleeping states S1–S5
— Supports legacy Keyboard/Mouse software
Integrated LAN Controller (Desktop and Mobile Only)
— Integrated ASF Management Controller
— Supports IEEE 802.3
— LAN Connect Interface (LCI)
— 10/100 Mb/s Ethernet Support
NEW: Intel Active Management Technology (Desktop and
Mobile Only)
NEW: Intel® Quick Resume Technology Support (Digital
Home Only)
Power Management Logic
— Supports ACPI 3.0
— ACPI-defined power states (C1, S1, S3–S5 for Desktop
and C1–C4, S1, S3–S5 for Mobile/Ultra Mobile)
— ACPI Power Management Timer
— (Mobile/Ultra Mobile Only) Support for “Intel
SpeedStep® Technology” processor power control and
“Deeper Sleep” power state
— PCI CLKRUN# and PME# support
— SMI# generation
— All registers readable/restorable for proper resume
from 0 V suspend states
— Support for APM-based legacy power management for
non-ACPI Desktop and Mobile implementations
External Glue Integration
— Integrated Pull-up, Pull-down and Series Termination
resistors on IDE, processor interface
— Integrated Pull-down and Series resistors on USB
Enhanced DMA Controller
— Two cascaded 8237 DMA controllers
— Supports LPC DMA (Desktop and Mobile Only)
35
„
„
„
„
„
SMBus
— Flexible SMBus/SMLink architecture to optimize
for ASF
— Provides independent manageability bus through
SMLink interface
— Supports SMBus 2.0 Specification
— Host interface allows processor to communicate
via SMBus
— Slave interface allows an internal or external
Microcontroller to access system resources
— Compatible with most two-wire components that
are also I2C compatible
High Precision Event Timers
— Advanced operating system interrupt scheduling
Timers Based on 82C54
— System timer, Refresh request, Speaker tone
output
Real-Time Clock
— 256-byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter implementation
System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon
detection of system hang
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
— Supports ability to disable external devices
„
„
„
„
Interrupt Controller
— Supports up to eight PCI interrupt pins
— Supports PCI 2.3 Message Signaled Interrupts
— Two cascaded 82C59 with 15 interrupts
— Integrated I/O APIC capability with 24 interrupts
— Supports Processor System Bus interrupt
delivery
1.05 V operation with 1.5 V and 3.3 V I/O
— 5 V tolerant buffers on IDE, PCI, USB and
Legacy signals
NEW: 1.05 V Core Voltage
Integrated 1.05 V Voltage Regulator (INTVR) for
the Suspend and LAN wells (Desktop and Mobile
Only)
„
„
„
„
„
„
Firmware Hub I/F supports BIOS Memory size up
to 8 MBytes (Desktop and Mobile Only)
NEW: Serial Peripheral Interface (SPI) for Serial
and Shared Flash (Desktop and Mobile Only)
Low Pin Count (LPC) I/F
— Supports two Master/DMA devices.
— Support for Security Device (Trusted Platform
Module) connected to LPC.
GPIO
— TTL, Open-Drain, Inversion
NEW: Package 31 mm x 31 mm 652 mBGA
(Desktop and Mobile Only)
New: Package 15 mm x 15 mm, 452 balls (Ultra
Mobile only)
Desktop Configuration
DMI
(To (G)MCH)
USB 2.0
Power Management
(Supports 8 USB ports)
IDE
Clock Generators
SATA (4 ports)
Intel® PCI Express
Gigabit Ethernet
System Management
(TCO)
Intel®
ICH7
AC ’97/Intel® High
Definition Audio
Codec(s)
SMBus 2.0/I2C
PCI Express* x1
SPI BIOS
PCI Bus
LAN Connect
GPIO
LPC I/F
S
L
O
T
...
S
L
O
T
Other ASICs
(Optional)
Super I/O
TPM
(Optional)
36
Firmware Hub
Intel ® ICH7 Family Datasheet
Mobile Configuration
DMI
(To (G)MCH)
USB 2.0
Power Management
(Supports 8 USB ports)
IDE
Clock Generators
SATA (2 ports)
System Management
(TCO)
Intel®
ICH7-M
AC’97/Intel® High
Definition Audio
Codec(s)
SMBus 2.0/I2C
PCI Bus
Docking
Bridge
PCI Express x1
Cardbus
Controller (&
attached slots)
LAN Connect
GPIO
Other ASICs
(Optional)
SPI BIOS
LPC I/F
Super I/O
TPM
(Optional)
Flash BIOS
Ultra Mobile Configuration
DMI
(To GMCH)
USB 2.0
Power Management
(Supports 8 USB ports)
Clock Generators
IDE
System Management
(TCO)
Intel®
ICH7-U
Intel® High Definition
Audio Codec(s)
SMBus 2.0/I2C
PCI Bus
GPIO
3 PCI
Other ASICs
(Optional)
LPC I/F
Super I/O
TPM
(Optional)
Flash BIOS
§
Intel ® ICH7 Family Datasheet
37
38
Intel ® ICH7 Family Datasheet
Introduction
1
Introduction
This document is intended for Original Equipment Manufacturers and BIOS vendors
creating Intel® I/O Controller Hub 7 (ICH7) Family based products. This document is
the datasheet for the following:
• Intel® 82801GB ICH7 (ICH7)
• Intel® 82801GR ICH7 RAID (ICH7R)
• Intel® 82801GDH ICH7 Digital Home (ICH7DH)
• Intel® 82801GBM ICH7 Mobile (ICH7-M)
• Intel® 82801GHM ICH7 Mobile Digital Home (ICH7-M DH)
• Intel® 82801GU ICH7-U Ultra Mobile (ICH7-U)
Section 1.2 provides high-level feature differences for the ICH7 Family components.
Note:
Throughout this datasheet, ICH7 is used as a general ICH7 term and refers to the
82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 82801GBM ICH7-M, 82801GHM
ICH7-M DH, and 82801GU ICH7-U components, unless specifically noted otherwise.
Note:
Throughout this datasheet, the term “Desktop” refers to any implementation, be it in a
desktop, server, workstation, etc., unless specifically noted otherwise.
Note:
Throughout this datasheet, the terms “Desktop”, “Digital Home” “Mobile”, and “Ultra
Mobile” refer to the following components, unless specifically noted otherwise:
• Desktop refers to the 82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH.
• Digital Home refers to the 82801GDH ICH7DH and 82801GHM ICH7-M DH.
• Mobile refers to the 82801GBM ICH7-M, and 82801GHM ICH7-M DH.
• Ultra Mobile refers to the 82801GU ICH7-U.
Note:
“Desktop and Mobile Only” refers to all components in this document except the
82801GU ICH7-U Ultra Mobile component.
This datasheet assumes a working knowledge of the vocabulary and principles of PCI
Express*, USB, IDE, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio),
AC ’97, SMBus, PCI, ACPI and LPC. Although some details of these features are
described within this manual, refer to the individual industry specifications listed in
Table 1-1 for the complete details.
Table 1-1.
Industry Specifications
Specification
Location
Intel® I/O Controller Hub ICH7 Family Specification
Update
http://developer.intel.com//design/
chipsets/specupdt/307014.htm
Intel® I/O Controller Hub ICH7 Family Thermal
Mechanical Guidelines
http://developer.intel.com//design/
chipsets/designex/307015.htm
PCI Express* Base Specification, Revision 1.0a
http://www.pcisig.com/specifications
Low Pin Count Interface Specification, Revision 1.1
(LPC)
http://developer.intel.com/design/
chipsets/industry/lpc.htm
Audio Codec ‘97 Component Specification, Version 2.3
(AC ’97)
http://www.intel.com/design/
chipsets/audio/
Intel ® ICH7 Family Datasheet
39
Introduction
Table 1-1.
Industry Specifications
Specification
Location
System Management Bus Specification, Version 2.0
(SMBus)
http://www.smbus.org/specs/
PCI Local Bus Specification, Revision 2.3 (PCI)
http://www.pcisig.com/specifications
PCI Mobile Design Guide, Revision 1.1
http://www.pcisig.com/specifications
PCI Power Management Specification, Revision 1.1
http://www.pcisig.com/specifications
Universal Serial Bus Specification (USB), Revision 2.0
http://www.usb.org/developers/docs
Advanced Configuration and Power Interface, Version
2.0 (ACPI)
http://www.acpi.info/spec.htm
Universal Host Controller Interface, Revision 1.1 (UHCI)
http://developer.intel.com/design/
USB/UHCI11D.htm
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/
technology/usb/ehcispec.htm
Serial ATA Specification, Revision 1.0a
http://www.serialata.org/
specifications.asp
Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0
http://www.serialata.org/
specifications.asp
Alert Standard Format Specification, Version 1.03
http://www.dmtf.org/standards/asf
IEEE 802.3 Fast Ethernet
http://standards.ieee.org/
getieee802/
AT Attachment - 6 with Packet Interface (ATA/ATAPI 6)
http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers) Specification,
Revision 1.0
http://www.intel.com/
hardwaredesign/hpetspec.htm
Chapter 1. Introduction
Chapter 1 introduces the ICH7 and provides information on manual organization and
gives a general overview of the ICH7.
Chapter 2. Signal Description
Chapter 2 provides a block diagram of the ICH7 interface signals and a detailed
description of each signal. Signals are arranged according to interface and details are
provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals.
Chapter 3. Intel® ICH7 Pin States
Chapter 3 provides a complete list of signals, their associated power well, their logic
level in each suspend state, and their logic level before and after reset.
Chapter 4. Intel® ICH7 and System Clock Domains
Chapter 4 provides a list of each clock domain associated with the ICH7 in an ICH7
based system.
Chapter 5. Functional Description
Chapter 5 provides a detailed description of the functions in the ICH7. All PCI buses,
devices and functions in this manual are abbreviated using the following nomenclature;
Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8,
D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For
example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is
abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be
considered to be Bus 0. Note that the ICH7’s external PCI bus is typically Bus 1, but
may be assigned a different number depending upon system configuration.
40
Intel ® ICH7 Family Datasheet
Introduction
Chapter 6. Register and Memory Mappings
Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges
and memory ranges decoded by the ICH7.
Chapter 7. Chipset Configuration Registers
Chapter 7 provides a detailed description of all registers and base functionality that is
related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI
Express). It contains the root complex register block, which describes the behavior of
the upstream internal link.
Chapter 8. LAN Controller Registers
Chapter 8 provides a detailed description of all registers that reside in the ICH7’s
integrated LAN controller. The integrated LAN controller resides on the ICH7’s external
PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0).
Chapter 9. PCI-to-PCI Bridge Registers
Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI
bridge. This bridge resides at Device 30, Function 0 (D30:F0).
Chapter 10. LPC Bridge Registers
Chapter 10 provides a detailed description of all registers that reside in the LPC bridge.
This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers
for many different units within the ICH7 including DMA, Timers, Interrupts, Processor
Interface, GPIO, Power Management, System Management and RTC.
Chapter 11. SATA Controller Registers
Chapter 12 provides a detailed description of all registers that reside in the SATA
controller. This controller resides at Device 31, Function 2 (D31:F2).
Chapter 12. UHCI Controller Registers
Chapter 11 provides a detailed description of all registers that reside in the four UHCI
host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3
(D29:F0/F1/F2/F3).
Chapter 13. EHCI Controller Registers
Chapter 13 provides a detailed description of all registers that reside in the EHCI host
controller. This controller resides at Device 29, Function 7 (D29:F7).
Chapter 14. SMBus Controller Registers
Chapter 14 provides a detailed description of all registers that reside in the SMBus
controller. This controller resides at Device 31, Function 3 (D31:F3).
Chapter 15. IDE Controller Registers
Chapter 15 provides a detailed description of all registers that reside in the IDE
controller. This controller resides at Device 31, Function 1 (D31:F1).
Chapter 16. AC ’97 Audio Controller Registers
Chapter 16 provides a detailed description of all registers that reside in the audio
controller. This controller resides at Device 30, Function 2 (D30:F2). Note that this
section of the datasheet does not include the native audio mixer registers. Accesses to
the mixer registers are forwarded over the AC-link to the codec where the registers
reside.
Chapter 17. AC ’97 Modem Controller Registers
Chapter 17 provides a detailed description of all registers that reside in the modem
controller. This controller resides at Device 30, Function 3 (D30:F3). Note that this
section of the datasheet does not include the modem mixer registers. Accesses to the
mixer registers are forwarded over the AC-link to the codec where the registers reside.
Chapter 18. Intel® High Definition Audio Controller Registers
Chapter 18 provides a detailed description of all registers that reside in the Intel® High
Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).
Chapter 19. PCI Express* Port Controller Registers
Chapter 19 provides a detailed description of all registers that reside in the PCI Express
controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5).
Intel ® ICH7 Family Datasheet
41
Introduction
Chapter 20. High Precision Event Timers Registers
Chapter 20 provides a detailed description of all registers that reside in the multimedia
timer memory mapped register space.
Chapter 21. Serial Peripheral Interface Registers
Chapter 21 provides a detailed description of all registers that reside in the SPI
memory mapped register space.
Chapter 22. Ballout Definition
Chapter 22 provides a table of each signal and its ball assignment in the 652-mBGA
package.
Chapter 23. Electrical Characteristics
Chapter 23 provides all AC and DC characteristics including detailed timing diagrams.
Chapter 24. Package Information
Chapter 24 provides drawings of the physical dimensions and characteristics of the
652-mBGA package.
Chapter 25. Testability
Chapter 25 provides detail about the implementation of test modes provided in the
ICH7.
1.1
Overview
The ICH7 provides extensive I/O support. Functions and capabilities include:
• PCI Express* Base Specification, Revision 1.0a support (Desktop and Mobile Only)
• PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations
(supports up to six Req/Gnt pairs; three pairs on Ultra Mobile).
• ACPI Power Management Logic Support
• Enhanced DMA controller, interrupt controller, and timer functions (Desktop and
Mobile Only)
• Integrated Serial ATA host controller with independent DMA operation on four ports
(Desktop only) or two ports (Mobile Only) and AHCI (ICH7R, ICH7DH, ICH7-M, and
ICH7-M DH Only) support. (SATA not supported on Ultra Mobile)
• Integrated IDE controller supports Ultra ATA100/66/33
• USB host interface with support for eight USB ports; four UHCI host controllers;
one EHCI high-speed USB 2.0 Host controller
• Integrated LAN controller (Desktop and Mobile Only)
• System Management Bus (SMBus) Specification, Version 2.0 with additional
support for I2C devices (Desktop and Mobile Only)
• Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a., AC ’97 Component
Specification, Revision 2.3) which provides a link for Audio and Telephony codecs
(up to 7 channels) (Desktop and Mobile Only)
• Supports Intel High Definition Audio
• Supports Intel® Matrix Storage Technology (ICH7R, ICH7DH, and Mobile Only)
• Supports Intel® Active Management Technology (Desktop and Mobile Only)
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
• Serial Peripheral Interface (SPI) support (Desktop and Mobile Only)
42
Intel ® ICH7 Family Datasheet
Introduction
The ICH7 incorporates a variety of PCI functions that are divided into six logical devices
(B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8) as listed in Table 1-2. D30 is
the DMI-to-PCI bridge and the AC ’97 Audio and Modem controller functions, D31
contains the PCI-to-LPC bridge, IDE controller, SATA controller, and SMBus controller,
D29 contains the four USB UHCI controllers and one USB EHCI controller, and D27
contains the PCI Express root ports. B1:D8 is the integrated LAN controller.
Table 1-2.
PCI Devices and Functions
Bus:Device:Function
Function Description
Bus 0:Device 30:Function 0
PCI-to-PCI Bridge
Bus 0:Device 30:Function 2
AC ’97 Audio Controller (Desktop and Mobile Only)
Bus 0:Device 30:Function 3
AC ’97 Modem Controller (Desktop and Mobile Only)
Bus 0:Device 31:Function 0
LPC Controller1
Bus 0:Device 31:Function 1
IDE Controller
Bus 0:Device 31:Function 2
SATA Controller (Desktop and Mobile Only)
Bus 0:Device 31:Function 3
SMBus Controller
Bus 0:Device 29:Function 0
USB UHCI Controller #1
Bus 0:Device 29:Function 1
USB UHCI Controller #2
Bus 0:Device 29:Function 2
USB UHCI Controller #3
Bus 0:Device 29:Function 3
USB UHCI Controller #4
Bus 0:Device 29:Function 7
USB 2.0 EHCI Controller
Bus 0:Device 28:Function 0
PCI Express* Port 1 (Desktop and Mobile Only)
Bus 0:Device 28:Function 1
PCI Express Port 2 (Desktop and Mobile Only)
Bus 0:Device 28:Function 2
PCI Express Port 3 (Desktop and Mobile Only)
Bus 0:Device 28:Function 3
PCI Express Port 4 (Desktop and Mobile Only)
Bus 0:Device 28:Function 4
PCI Express Port 5 (Intel® ICH7R, ICH7DH, and ICH7-M DH
Only)
Bus 0:Device 28:Function 5
PCI Express Port 6 (Intel ICH7R, ICH7DH, and ICH7-M DH Only)
Bus 0:Device 27:Function 0
Intel® High Definition Audio Controller
Bus n:Device 8:Function 0
LAN Controller (Desktop and Mobile Only)
NOTES:
1.
The PCI-to-LPC bridge contains registers that control LPC, Power Management, System
Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.
The following sub-sections provide an overview of the ICH7 capabilities.
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the Memory
Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 7
(ICH7). This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software-transparent, permitting current and legacy software to operate
normally.
Intel ® ICH7 Family Datasheet
43
Introduction
PCI Express* Interface (Desktop and Mobile Only)
The ICH7R, ICH7DH, ICH7-M DH have six PCI Express root ports and the ICH7 and
ICH7-M have four PCI Express root ports (ports 1-4), supporting the PCI Express Base
Specification, Revision 1.0a. PCI Express root ports 1–4 can be statically configured as
four x1 ports or ganged together to form one x4 port. Ports 5 and 6 on the ICH7R,
ICH7DH, and ICH7-M DH can only be used as two x1 ports. Each Root Port supports
2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent).
Serial ATA (SATA) Controller (Desktop and Mobile Only)
The ICH7 has an integrated SATA host controller that supports independent DMA
operation on four ports (desktop only) or two ports (mobile only) and supports data
transfer rates of up to 3.0 Gb/s (300 MB/s). The SATA controller contains two modes of
operation – a legacy mode using I/O space, and an AHCI mode using memory space.
SATA and PATA can also be used in a combined function mode (where the SATA function
is used with PATA). In this combined function mode, AHCI mode is not used. Software
that uses legacy mode will not have AHCI capabilities.
The ICH7 supports the Serial ATA Specification, Revision 1.0a. The ICH7 also supports
several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0
Specification, Revision 1.0 (AHCI support is required for some elements).
AHCI (Intel® ICH7R, ICH7DH, and Mobile Only)
The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a
new programming interface for SATA host controllers. Platforms supporting AHCI may
take advantage of performance features such as no master/slave designation for SATA
devices—each device is treated as a master—and hardware-assisted native command
queuing. AHCI also provides usability enhancements such as Hot-Plug (Desktop and
Mobile Only). AHCI requires appropriate software support (e.g., an AHCI driver) and for
some features, hardware support in the SATA device or additional platform hardware.
Intel® Matrix Storage Technology (Intel® ICH7R, ICH7DH, and ICH7-M
DH Only)
The ICH7 provides support for Intel Matrix Storage Technology, providing both AHCI
(see above for details on AHCI) and integrated RAID functionality. The industry-leading
RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality
(RAID 0/1 functionality for ICH7-M DH) on up to 4 SATA ports of ICH7. Matrix RAID
support is provided to allow multiple RAID levels to be combined on a single set of hard
drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare
support, SMART alerting, and RAID 0 auto replace. Software components include an
Option ROM for pre-boot configuration and boot functionality, a Microsoft* Windows*
compatible driver, and a user interface for configuration and management of the RAID
capability of ICH7.
PCI Interface
The ICH7 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH7
integrates a PCI arbiter that supports up to six external PCI bus masters (three on Ultra
Mobile) in addition to the internal ICH7 requests. This allows for combinations of up to
six PCI down devices (three on Ultra Mobile) and PCI slots.
44
Intel ® ICH7 Family Datasheet
Introduction
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile)
providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have
independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and
Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources.
The IDE interface integrates 16x32-bit buffers for optimal transfers.
The ICH7’s IDE system contains a single, independent IDE signal channel that can be
electrically isolated. There are integrated series resistors on the data and control lines
(see Section 5.16 for details).
Low Pin Count (LPC) Interface
The ICH7 implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the ICH7 resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.
Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
The ICH7 implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-bybyte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
The ICH7 supports LPC DMA (Desktop and Mobile Only), which is similar to ISA DMA,
through the ICH7’s DMA controller. LPC DMA is handled through the use of the LDRQ#
lines from peripherals and special encoding on LAD[3:0] from the host. Single,
Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–
3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a
generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those
found in one 82C54 programmable interval timer. These three counters are combined
to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator
input provides the clock source for these three counters.
The ICH7 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the ICH7 supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt controller (PIC)
described in the previous section, the ICH7 incorporates the Advanced Programmable
Interrupt Controller (APIC).
Intel ® ICH7 Family Datasheet
45
Introduction
Universal Serial Bus (USB) Controller
The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller that
supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to
480 Mb/s which is 40 times faster than full-speed USB. The ICH7 also contains four
Universal Host Controller Interface (UHCI) controllers that support USB full-speed and
low-speed signaling.
The ICH7 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and
low-speed capable. ICH7’s port-routing logic determines whether a USB port is
controlled by one of the UHCI controllers or by the EHCI controller. See Section 5.19
and Section 5.20 for details.
LAN Controller (Desktop and Mobile Only)
The ICH7’s integrated LAN controller includes a 32-bit PCI controller that provides
enhanced scatter-gather bus mastering capabilities and enables the LAN controller to
perform high speed data transfers over the PCI bus. Its bus master capabilities enable
the component to process high-level commands and perform multiple operations; this
lowers processor utilization by off-loading communication tasks from the processor.
Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and
overruns while waiting for bus accesses. This enables the integrated LAN controller to
transmit data with minimum interframe spacing (IFS).
The LAN controller can operate in either full duplex or half duplex mode. In full duplex
mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism. See
Section 5.3 for details.
Alert Standard Format (ASF) Management Controller (Desktop and
Mobile Only)
ICH7 integrates an Alert Standard Format controller in addition to the integrated LAN
controller, allowing interface system-monitoring devices to communicate through the
integrated LAN controller to the network. This makes remote manageability and system
hardware monitoring possible using ASF.
The ASF controller can collect and send various information from system components
such as the processor, chipset, BIOS and sensors on the motherboard to a remote
server running a management console. The controller can also be programmed to
accept commands back from the management console and execute those commands
on the local system.
46
Intel ® ICH7 Family Datasheet
Introduction
RTC
The ICH7 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes
of battery-backed RAM. The real-time clock performs two key functions: keeping track
of the time of day and storing system data, even when the system is powered down.
The RTC operates on a 32.768 KHz crystal and a 3 V battery.
The RTC also supports two lockable memory ranges. By setting bits in the configuration
space, two 8-byte ranges can be locked to read and write accesses. This prevents
unauthorized reading of passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to
30 days in advance, rather than just 24 hours in advance.
GPIO
Various general purpose inputs and outputs are provided for custom system design.
The number of inputs and outputs varies depending on ICH7 configuration.
Enhanced Power Management
The ICH7’s power management functions include enhanced clock control and various
low-power (suspend) states (e.g., Suspend-to-RAM and Suspend-to-Disk). A hardwarebased thermal management circuit permits software-independent entrance to lowpower states. The ICH7 contains full support for the Advanced Configuration and Power
Interface (ACPI) Specification, Revision 3.0.
Intel® Quick Resume Technology (Digital Home Only)
ICH7 implements Intel Quick Resume Technology that provides the capability to design
a PC with a single power button that reliably and instantly (user's perception) turns the
PC On and Off. When the system is On and the user presses the power button, the
display instantly goes dark, sound is muted, and there is no response to keyboard/
mouse commands (except for keyboard power button). When the system is Off and the
user presses the power button, picture and sound quickly return, and the keyboard/
mouse return to normal functionality, allowing user input.
Intel® Active Management Technology (Intel® AMT) (Desktop and
Mobile Only)
Intel Active Management Technology is the next generation of client manageability via
the wired network. Intel AMT is a set of advanced manageability features developed as
a direct result of IT customer feedback gained through Intel market research.
Intel ® ICH7 Family Datasheet
47
Introduction
Manageability
In addition to Intel AMT the ICH7 integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.
• TCO Timer. The ICH7’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.
• Processor Present Indicator. The ICH7 looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the ICH7
will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to the ICH7. The host controller can
instruct the ICH7 to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The ICH7 provides the ability to disable the following integrated
functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel HD Audio, SATA,
or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI
configuration space. Also, no interrupts or power management events are
generated from the disable functions.
• Intruder Detect. The ICH7 provides an input signal (INTRUDER#) that can be
attached to a switch that is activated by the system case being opened. The ICH7
can be programmed to generate an SMI# or TCO interrupt due to an active
INTRUDER# signal.
System Management Bus (SMBus 2.0) (Desktop and Mobile Only)
The ICH7 contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I2C devices. Special I2C
commands are implemented.
The ICH7’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the ICH7 supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
ICH7’s SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address
to all SMBus devices.
48
Intel ® ICH7 Family Datasheet
Introduction
Intel® High Definition Audio Controller
The Intel® High Definition Audio Specification defines a digital interface that can be
used to attach different types of codecs, such as audio and modem codecs. The ICH7
Intel HD Audio digital link shares pins with the AC-link. Concurrent operation of Intel
HD Audio and AC ’97 functionality is not supported. The ICH7 Intel HD Audio controller
supports up to 3 codecs.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel® HD Audio controller provides audio quality that can deliver CE
levels of audio experience. On the input side, the ICH7 adds support for an arrays of
microphones.
The Intel HD Audio controller uses multi-purpose DMA engines, as opposed to
dedicated DMA engines in AC ’97 (Desktop and Mobile Only), to effectively manage the
link bandwidth and support simultaneous independent streams on the link. The
capability enables new exciting usage models with Intel HD Audio (e.g., listening to
music while playing multi-player game on the internet.) The Intel HD Audio controller
also supports isochronous data transfers allowing glitch-free audio to the system.
Note:
Users interested in providing feedback on the Intel High Definition Audio Specification
or planning to implement the Intel High Definition Audio Specification into a future
product will need to execute the Intel High Definition Audio Specification Developer’s
Agreement. For more information, contact [email protected].
AC ’97 2.3 Controller (Desktop and Mobile Only)
The ICH7 integrates an Audio Codec '97 Component Specification, Version 2.3
controller that can be used to attach an audio codec (AC), a modem codec (MC), an
audio/modem codec (AMC) or a combination of ACs and a single MC. The ICH7
supports up to six channels of PCM audio output (full AC3 decode). For a complete
surround-sound experience, six-channel audio consists of: front left, front right, back
left, back right, center, and subwoofer. ICH7 has expanded support for up to three
audio codecs on the AC-link.
In addition, an AC '97 soft modem can be implemented with the use of a modem codec.
Several system options exist when implementing AC '97. The ICH7-integrated AC '97
controller allows up to three external codecs to be connected to the ICH7. The system
designer can provide AC '97 modem with a modem codec, or both audio and modem
with up to two audio codecs with a modem codec.
Intel ® ICH7 Family Datasheet
49
Introduction
1.2
Intel® ICH7 Family High-Level Component
Differences
Table 1-3.
Intel® ICH7 Desktop/Server Family1
Product Name
Base
Features
Intel® Matrix
Storage
Technology RAID
0/1/5/10 /
AHCI
Intel® ICH7 Base
(ICH7)
Yes
No/No
No2
Yes
No
ICH7 Digital
Home (ICH7DH)
Yes
Yes / Yes
Yes2
Yes
Yes
ICH7 RAID
(ICH7R)
Yes
Yes / Yes
Yes2
Yes
No
6 PCI
Express
Ports
Intel®
AMT
Support
Intel®
Quick
Resume
Technology
NOTES:
1.
Feature capability can be read in D31:F0:Offset E4h.
2.
The ICH7 Base (ICH7) supports Ports 1:4; ICH7 RAID (ICH7R) and ICH7 Digital Home
(ICH7DH) supports Ports 1:6.
Table 1-4.
Intel® ICH7-M Mobile and ICH7-U Ultra Mobile Components1
Product Name
Short
Name
Base
Features
AHCI
Intel® Matrix
Storage
Technology
RAID 0/1
ICH7 Mobile
ICH7-M
Yes
Yes
No
No
Yes
ICH7 Mobile
Digital Home
ICH7-M DH
Yes
Yes
Yes
Yes
Yes
ICH7-U
Not all
features
No
No
No
No
ICH7 Ultra
Mobile
6 PCI
Express*
Ports
Intel®
AMT
Ready
NOTES:
1.
Feature capability can be read in D31:F0:Offset E4h.
§
50
Intel ® ICH7 Family Datasheet
Signal Description
2
Signal Description
This chapter provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface. Figure 2-1 shows the
interface signals for the Intel® 82801GB ICH7, 82801GR ICH7R, and 82801GDH
ICH7DH. Figure 2-2 shows the interface signals for the 82801GBM ICH7-M and
82801GHM ICH7-M DH. Figure 2-3 shows the interface signals for the 82801GU ICH7U.
The “#” symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When “#” is not present, the
signal is asserted when at the high voltage level.
The “Type” for each signal is indicative of the functional operating mode of the signal.
Unless otherwise noted in Section 3.3 or Section 3.4, a signal is considered to be in the
functional operating mode after RTCRST# for signals in the RTC well, RSMRST# for
signals in the suspend well, after PWROK for signals in the core well, and after
LAN_RST# for signals in the LAN well.
The following notations are used to describe the signal type:
I
Input Pin
O
Output Pin
OD O
Open Drain Output Pin.
I/OD
Bi-directional Input/Open Drain Output Pin.
I/O
Bi-directional Input / Output Pin.
OC
Open Collector Output Pin.
Intel ® ICH7 Family Datasheet
51
Signal Description
Figure 2-1.
Interface Signals Block Diagram (Desktop Only)
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
REQ[3:0]#
REQ[4]# / GPIO[22]
REQ[5]# / GPIO[1]
GNT[3:0]#
GNT[4]# / GPIO[48]
GNT[5]# / GPIO[17]
PCICLK
PCIRST#
PLOCK#
SERR#
PME#
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INIT3_3V#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD / GPIO[49]
SPI_CS#
SPI_MISO
SPI_MOSI
SPI_ARB
SPI_CLK
SERIRQ
PIRQ[D:A]#
PIRQ[H:E]# / GPIO[5:2]
IDEIRQ
PCI
Interface
Processor
Interface
Interrupt
Interface
USB
RTCX1
RTCX2
RTC
INTVRMEN
SPKR
RTCRST#
TP0
TP[2:1]
TP3
GPIO[39:38, 34:32, 28:26,
25:24, 20, 18, 16:12, 10:6]
EE_SHCLK
EE_DIN
EE_DOUT
EE_CS
PCI
Express*
Interface
PETp[6:1], PETn[6:1]
PERp[6:1], PERn[6:1]
Serial ATA
Interface
SATA[3:0]TXP, SATA[3:0]TXN
SATA[3:0]RXP, SATA[3:0]RXN
SATARBIAS
SATARBIAS#
SATA[3:0]GP/GPIO[37,36,21,19]
SATALED#
SATACLKREQ#/GPIO[35]
Power
Mgnt.
SPI
USBP[7:0]P
USBP[7:0]N
OC[4:0]#
OC[5]# / GPIO[29]
OC[6]# / GPIO[30]
OC[7]# / GPIO[31]
USBRBIAS#
USBRBIAS
CLK14
CLK48
SATA_CLKP, SATA_CLKN
DMI_CLKP, DMI_CLKN
52
IDE
Interface
AC '97/
®
Intel
High
Definition
Audio
General
Purpose
I/O
EEPROM
Interface
THRM#
THRMTRIP#
SYS_RESET#
RSMRST#
MCH_SYNC#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
RI#
WAKE#
SUS_STAT# / LPCPD#
SUSCLK
LAN_RST#
VRMPWRGD
PLTRST#
ACZ_RST#
ACZ_SYNC
ACZ_BIT_CLK
ACZ_SDOUT
ACZ_SDIN[2:0]
Direct
Media
Interface
DMI[3:0]TXP, DMI[3:0]TXN
DMI[3:0]RXP, DMI[3:0]RXN
DMI_ZCOMP
DMI_IRCOMP
Firmware
Hub
FWH[3:0] / LAD[3:0]
FWH[4] / LFRAME#
LPC
Interface
LAD[3:0] / FWH[3:0]
LFRAME# / FWH[4]
LDRQ[0]#
LDRQ[1]# / GPIO[23]
SMBus
Interface
SMBDATA
SMBCLK
SMBALERT# / GPIO[11]
System
Mgnt.
INTRUDER#
SMLINK[1:0]
LINKALERT#
Platform
LAN
Connect
LAN_CLK
LAN_RXD[2:0]
LAN_TXD[2:0]
LAN_RSTSYNC
Clocks
Misc.
Signals
DCS1#
DCS3#
DA[2:0]
DD[15:0]
DDREQ
DDACK#
DIOR# (DWSTB / RDMARDY#)
DIOW# (DSTOP)
IORDY (DRSTB / WDMARDY#)
Intel® Quick
Resume
Technology
EL_RSVD / GPIO26
EL_STATE[1:0] /
GPIO[28:27]
Digital
Home
Only
Intel ® ICH7 Family Datasheet
Signal Description
Figure 2-2.
Interface Signals Block Diagram (Mobile Only)
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
REQ[3:0]#
REQ[4]# / GPIO[22]
REQ[5]# / GPIO[1]
GNT[3:0]#
GNT[4]# / GPIO[48]
GNT[5]# / GPIO[17]
PME#
CLKRUN#
PCICLK
PCIRST#
PLOCK#
SERR#
SPI_CS#
SPI_MISO
SPI_MOSI
SPI_ARB
SPI_CLK
A20M#
FERR#
IGNNE#
INIT#
INIT3_3#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD / GPIO[49]
DPSLP#
SERIRQ
PIRQ[D:A]#
PIRQ[H:E]# / GPIO[5:2]
IDEIRQ
PCI
Interface
PCI
Express*
Interface
PETp[6:1], PETn[6:1]
PERp[6:1], PERn[6:1]
Serial ATA
Interface
SPI
Processor
Interface
Power
Mgnt.
Interrupt
Interface
AC '97/
®
Intel High
Definition
Audio
USBP[7:0]P
USBP[7:0]N
OC[4:0]#
OC[5]# / GPIO[29]
OC[6]# / GPIO[30]
OC[7]# / GPIO[31]
USBRBIAS
USBRBIAS#
USB
RTCX1
RTCX2
RTC
CLK14
CLK48
SATA_CLKP, SATA_CLKN
DMI_CLKP, DMI_CLKN
Clocks
INTVRMEN
SPKR
RTCRST#
TP[3]
Misc.
Signals
GPIO[39:37,25:24,19,1
5:12,10:6]
General
Purpose
I/O
EE_SHCLK
EE_DIN
EE_DOUT
EE_CS
EEPROM
Interface
Intel ® ICH7 Family Datasheet
IDE
Interface
DCS1#
DCS3#
DA[2:0]
DD[15:0]
DDREQ
DDACK#
DIOR# (DWSTB / RDMARDY#)
DIOW# (DSTOP)
IORDY (DRSTB / WDMARDY#)
SATA[2,0]TXP, SATA[2,0]TXN
SATA[2,0]RXP, SATA[2,0]RXN
SATARBIAS
SATARBIAS#
SATA[2,0]GP/GPIO[36,21]
SATALED#
SATACLKREQ#
THRM#
THRMTRIP#
SYS_RESET#
RSMRST#
MCH_SYNC#
DPRSTP#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
RI#
WAKE#
SUS_STAT# / LPCPD#
SUSCLK
LAN_RST#
VRMPWRGD
BMBUSY# / GPIO[0]
STP_PCI#
STP_CPU#
BATLOW#
DPRSLPVR
PLTRST#
ACZ_RST#, ACZ_SYNC, ACZ_SDOUT
ACZ_SDIN[2:0]
ACZ_BIT_CLK
AZ_DOCK_EN# / GPIO[33]
AZ_DOCK_RST# / GPIO[34]
Direct
Media
Interface
DMI[3:0]TXP, DMI[3:0]TXN
DMI[3:0]RXP, DMI[3:0]RXN
DMI_ZCOMP
DMI_IRCOMP
Firmware
Hub
FWH[3:0] / LAD[3:0]
FWH[4] / LFRAME#
LPC
Interface
LAD[3:0] / FWH[3:0]
LFRAME# / FWH[4]
LDRQ[0]#
LDRQ[1]# / GPIO[23]
SMBus
Interface
SMBDATA
SMBCLK
SMBALERT# / GPIO[11]
System
Mgnt.
INTRUDER#
SMLINK[1:0]
LINKALERT#
Platform
LAN
Connect
LAN_CLK
LAN_RXD[2:0]
LAN_TXD[2:0]
LAN_RSTSYNC
Digital
Home
El_RSVD / GPIO26
El_STATE[1:0] /
GPIO[28:27
Digital
Home
Only
ICH7_Signals_Mobile
53
Signal Description
Figure 2-3.
Interface Signals Block Diagram (Ultra Mobile Only)
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
REQ3#
REQ4# / GPIO[22]
REQ5# / GPIO[1]
GNT3]#
GNT4# / GPIO[48]
GNT5# / GPIO[17]
PME#
CLKRUN#
PCICLK
PCIRST#
PLOCK#
SERR#
A20M#
FERR#
IGNNE#
INIT#
INIT3_3#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD / GPIO[49]
DPSLP#
SERIRQ
PIRQ[H:E]# / GPIO[5:2]
IDEIRQ
IDE
Interface
PCI
Interface
Power
Mgnt.
®
USBP[7:0]P
USBP[7:0]N
OC[4:0]#
OC[5]# / GPIO[29]
OC[6]# / GPIO[30]
OC[7]# / GPIO[31]
USBRBIAS
USBRBIAS#
USB
RTCX1
RTCX2
RTC
CLK14
CLK48
Clocks
DMI_CLKP, DMI_CLKN
SPKR
RTCRST#
TP3
GPIO[39:37,25:24,19,1
5:12,10:6]
THRM#
THRMTRIP#
SYS_RESET#
RSMRST#
MCH_SYNC#
DPRSTP#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
RI#
WAKE#
SUS_STAT# / LPCPD#
SUSCLK
VRMPWRGD
BMBUSY# / GPIO[0]
STP_PCI#
STP_CPU#
BATLOW#
DPRSLPVR
PLTRST#
Processor
Interface
Interrupt
Interface
DCS1#
DCS3#
DA[2:0]
DD[15:0]
DDREQ
DDACK#
DIOR# (DWSTB / RDMARDY#)
DIOW# (DSTOP)
IORDY (DRSTB / WDMARDY#)
Intel High
Definition
Audio
ACZ_RST#, ACZ_SYNC,
ACZ_SDOUT
ACZ_SDIN[2:0]
ACZ_BIT_CLK
Direct
Media
Interface
DMI[1:0]TXP, DMI[1:0]TXN
DMI[1:0]RXP, DMI[1:0]RXN
DMI_ZCOMP
DMI_IRCOMP
Firmware
Hub
FWH[3:0] / LAD[3:0]
FWH[4] / LFRAME#
LPC
Interface
LAD[3:0] / FWH[3:0]
LFRAME# / FWH[4]
LDRQ0#
LDRQ1# / GPIO[23]
SMBus
Interface
SMBDATA
SMBCLK
SMBALERT# / GPIO[11]
System
Mgnt.
INTRUDER#
LINKALERT#
Misc.
Signals
General
Purpose
I/O
ICH7 Signals Ultra Mobile
54
Intel ® ICH7 Family Datasheet
Signal Description
2.1
Direct Media Interface (DMI) to Host Controller
Table 2-1.
Direct Media Interface Signals
Name
Type
Description
DMI[0:1]TXP,
DMI[0:1]TXN
O
Direct Media Interface Differential Transmit Pair 0:3
DMI[2:3]RXP,
DMI[2:3]RXN
(Desktop and
Mobile Only)
I
Direct Media Interface Differential Receive Pair 0:3
DMI_ZCOMP
I
Impedance Compensation Input: Determines DMI input impedance.
DMI_IRCOMP
O
Impedance/Current Compensation Output: Determines DMI
output impedance and bias current.
DMI[2:3]TXP,
DMI[2:3]TXN
(Desktop and
Mobile Only)
DMI[0:1]RXP,
DMI[0:1]RXN
2.2
PCI Express* (Desktop and Mobile Only)
Table 2-2.
PCI Express* Signals
Name
Type
Description
PETp[1:4],
PETn[1:4]
O
PCI Express* Differential Transmit Pair 1:4
PERp[1:4],
PERn[1:4]
I
PCI Express Differential Receive Pair 1:4
PETp[5:6],
PETn[5:6]
(Intel® ICH7R/
ICH7DH/ICH7-M DH
Only)
PERp[1:4],
PERn[5:6]
(ICH7R/ICH7DH/
ICH7-M DH Only)
Intel ® ICH7 Family Datasheet
O
I
PCI Express* Differential Transmit Pair 5:6
Reserved: ICH7/ICH7-M
PCI Express Differential Receive Pair 5:6
Reserved: ICH7/ICH7-M
55
Signal Description
2.3
Platform LAN Connect Interface (Desktop and
Mobile Only)
Table 2-3.
Platform LAN Connect Interface Signals
Name
Type
Description
LAN_CLK
I
LAN I/F Clock: This signal is driven by the Platform LAN Connect
component. The frequency range is 5 MHz to 50 MHz.
LAN_RXD[2:0]
I
Received Data: The Platform LAN Connect component uses these
signals to transfer data and control information to the integrated LAN
controller. These signals have integrated weak pull-up resistors.
LAN_TXD[2:0]
O
Transmit Data: The integrated LAN controller uses these signals to
transfer data and control information to the Platform LAN Connect
component.
LAN_RSTSYNC
O
LAN Reset/Sync: The Platform LAN Connect component’s Reset and
Sync signals are multiplexed onto this pin.
2.4
EEPROM Interface (Desktop and Mobile Only)
Table 2-4.
EEPROM Interface Signals
Name
Type
Description
EE_SHCLK
O
EEPROM Shift Clock: This signal is the serial shift clock output to the
EEPROM.
EE_DIN
I
EEPROM Data In: This signal transfers data from the EEPROM to the
Intel® ICH7. This signal has an integrated pull-up resistor.
EE_DOUT
O
EEPROM Data Out: This signal transfers data from the ICH7 to the
EEPROM.
EE_CS
O
EEPROM Chip Select: This is the chip select signal to the EEPROM.
2.5
Firmware Hub Interface (Desktop and Mobile
Only)
Table 2-5.
Firmware Hub Interface Signals
56
Name
Type
FWH[3:0] /
LAD[3:0]
I/O
FWH4 /
LFRAME#
O
Description
Firmware Hub Signals: These signals are multiplexed with the LPC
address signals.
Firmware Hub Signals: This signal is multiplexed with the LPC LFRAME#
signal.
Intel ® ICH7 Family Datasheet
Signal Description
2.6
PCI Interface
Table 2-6.
PCI Interface Signals (Sheet 1 of 3)
Name
AD[31:0]
Type
Description
I/O
PCI Address/Data: AD[31:0] is a multiplexed address and data bus.
During the first clock of a transaction, AD[31:0] contain a physical
address (32 bits). During subsequent clocks, AD[31:0] contain data. The
Intel® ICH7 will drive all 0s on AD[31:0] during the address phase of all
PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address phase
of a transaction, C/BE[3:0]# define the bus command. During the data
phase, C/BE[3:0]# define the Byte Enables.
C/BE[3:0]#
0000b
C/BE[3:0]#
I/O
Command Type
Interrupt Acknowledge
0001b
Special Cycle
0010b
I/O Read
0011b
I/O Write
0110b
Memory Read
0111b
Memory Write
1010b
Configuration Read
1011b
Configuration Write
1100b
Memory Read Multiple
1110b
Memory Read Line
1111b
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH7 does not
decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
DEVSEL#
FRAME#
IRDY#
Intel ® ICH7 Family Datasheet
I/O
Device Select: The ICH7 asserts DEVSEL# to claim a PCI transaction.
As an output, the ICH7 asserts DEVSEL# when a PCI master peripheral
attempts an access to an internal ICH7 address or an address destined
DMI (main memory or graphics). As an input, DEVSEL# indicates the
response to an ICH7-initiated transaction on the PCI bus. DEVSEL# is
tri-stated from the leading edge of PLTRST#. DEVSEL# remains tristated by the ICH7 until driven by a target device.
I/O
Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator asserts
FRAME#, data transfers continue. When the initiator negates FRAME#,
the transaction is in the final data phase. FRAME# is an input to the
ICH7 when the ICH7 is the target, and FRAME# is an output from the
ICH7 when the ICH7 is the initiator. FRAME# remains tri-stated by the
ICH7 until driven by an initiator.
I/O
Initiator Ready: IRDY# indicates the ICH7's ability, as an initiator, to
complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY#
indicates the ICH7 has valid data present on AD[31:0]. During a read, it
indicates the ICH7 is prepared to latch data. IRDY# is an input to the
ICH7 when the ICH7 is the target and an output from the ICH7 when the
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until driven by
an initiator.
57
Signal Description
Table 2-6.
PCI Interface Signals (Sheet 2 of 3)
Name
TRDY#
STOP#
PAR
PERR#
Type
Description
I/O
Target Ready: TRDY# indicates the Intel® ICH7's ability as a target to
complete the current data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is completed when both TRDY#
and IRDY# are sampled asserted. During a read, TRDY# indicates that
the ICH7, as a target, has placed valid data on AD[31:0]. During a write,
TRDY# indicates the ICH7, as a target is prepared to latch data. TRDY#
is an input to the ICH7 when the ICH7 is the initiator and an output from
the ICH7 when the ICH7 is a target. TRDY# is tri-stated from the leading
edge of PLTRST#. TRDY# remains tri-stated by the ICH7 until driven by
a target.
I/O
Stop: STOP# indicates that the ICH7, as a target, is requesting the
initiator to stop the current transaction. STOP# causes the ICH7, as an
initiator, to stop the current transaction. STOP# is an output when the
ICH7 is a target and an input when the ICH7 is an initiator.
I/O
Calculated/Checked Parity: PAR uses “even” parity calculated on 36
bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH7
counts the number of 1s within the 36 bits plus PAR and the sum is
always even. The ICH7 calculates PAR on 36 bits regardless of the valid
byte enables. The ICH7 generates PAR for address and data phases and
only ensures PAR to be valid one PCI clock after the corresponding
address or data phase. The ICH7 drives and tri-states PAR identically to
the AD[31:0] lines except that the ICH7 delays PAR by exactly one PCI
clock. PAR is an output during the address phase (delayed one clock) for
all ICH7 initiated transactions. PAR is an output during the data phase
(delayed one clock) when the ICH7 is the initiator of a PCI write
transaction, and when it is the target of a read transaction. ICH7 checks
parity when it is the target of a PCI write transaction. If a parity error is
detected, the ICH7 will set the appropriate internal status bits, and has
the option to generate an NMI# or SMI#.
I/O
Parity Error: An external PCI device drives PERR# when it receives
data that has a parity error. The ICH7 drives PERR# when it detects a
parity error. The ICH7 can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported via the
PERR# signal).
REQ[3:0]#
REQ4# /
GPIO22
I
REQ5# /
GPIO1
NOTE: REQ[2:0]# are not on Ultra Mobile.
PCI Grants: The ICH7 supports up to 6 masters on the PCI bus. The
GNT4# and GNT5# pins can instead be used as a GPIO.
GNT[3:0]#
GNT4# /
GPIO48
PCI Requests: The ICH7 supports up to 6 masters on the PCI bus. The
REQ4# and REQ5# pins can instead be used as a GPIO.
O
GNT5# /
GPIO17#
Pull-up resistors are not required on these signals. If pull-ups are used,
they should be tied to the Vcc3_3 power rail. GNT5#/GPIO17 has an
internal pull-up.
NOTE: GNT[2:0]# are not on Ultra Mobile.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
PCICLK
I
NOTE: (Mobile/Ultra Mobile Only) This clock does not stop based on
STP_PCI# signal. PCI Clock only stops based on SLP_S3#.
PCIRST#
58
O
PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR
of the primary interface PLTRST# signal and the state of the Secondary
Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6).
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-6.
PCI Interface Signals (Sheet 3 of 3)
Name
Type
Description
PLOCK#
I/O
PCI Lock: This signal indicates an exclusive bus operation and may
require multiple transactions to complete. The ICH7 asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus. PLOCK# is
ignored when PCI masters are granted the bus in desktop
configurations. Devices on the PCI bus (other than the ICH7) are not
permitted to assert the PLOCK# signal in mobile/Ultra Mobile
configurations.
SERR#
I/OD
System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
ICH7 has the ability to generate an NMI, SMI#, or interrupt.
I/OD
PCI Power Management Event: PCI peripherals drive PME# to wake
the system from low-power states S1–S5. PME# assertion can also be
enabled to generate an SCI from the S0 state. In some cases the ICH7
may drive PME# active due to an internal wake event. The ICH7 will not
drive PME# high, but it will be pulled up to VccSus3_3 by an internal
pull-up resistor.
PME#
2.7
Serial ATA Interface (Desktop and Mobile Only)
Table 2-7.
Serial ATA Interface Signals (Sheet 1 of 2)
Name
SATA0TXP
Type
Description
O
Serial ATA 0 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 0.
I
Serial ATA 0 Differential Receive Pair: These are inbound highspeed differential signals from Port 0.
O
Serial ATA 1 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 1. (Desktop Only)
I
Serial ATA 1 Differential Receive Pair: These are inbound highspeed differential signals from Port 1. (Desktop Only)
O
Serial ATA 2 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 2.
I
Serial ATA 2 Differential Receive Pair: These are inbound highspeed differential signals from Port 2.
O
Serial ATA 3 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 3. (Desktop Only)
SATA3RXN
(Desktop Only)
I
Serial ATA 3 Differential Receive Pair: These are inbound highspeed differential signals from Port 3. (Desktop Only)
SATARBIAS
O
Serial ATA Resistor Bias: These are analog connection points for
an external resistor to ground.
SATARBIAS#
I
Serial ATA Resistor Bias Complement: These are analog
connection points for an external resistor to ground.
SATA0TXN
SATA0RXP
SATA0RXN
SATA1TXP
SATA1TXN
(Desktop Only)
SATA1RXP
SATA1RXN
(Desktop Only)
SATA2TXP
SATA2TXN
SATA2RXP
SATA2RXN
SATA3TXP
SATA3TXN
(Desktop Only)
SATA3RXP
Intel ® ICH7 Family Datasheet
59
Signal Description
Table 2-7.
Serial ATA Interface Signals (Sheet 2 of 2)
Name
Type
SATA0GP /
GPIO21
Description
Serial ATA 0 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication, this signal should
be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to
indicate that the switch is open.
I
If interlock switches are not required, this pin can be configured as
GPIO21.
SATA1GP
(Desktop Only)
/ GPIO19
Serial ATA 1 General Purpose: Same function as SATA0GP, except
for SATA Port 1.
I
SATA2GP /
GPIO36
If interlock switches are not required, this pin can be configured as
GPIO19.
Serial ATA 2 General Purpose: Same function as SATA0GP, except
for SATA Port 2.
I
SATA3GP
(Desktop Only)
/ GPIO37
If interlock switches are not required, this pin can be configured as
GPIO36.
Serial ATA 3 General Purpose: Same function as SATA0GP, except
for SATA Port 3.
I
SATALED#
If interlock switches are not required, this pin can be configured as
GPIO37.
Serial ATA LED: This is an open-collector output pin driven during
SATA command activity. It is to be connected to external circuitry
that can provide the current to drive a platform LED. When active,
the LED is on. When tri-stated, the LED is off. An external pull-up
resistor to Vcc3_3 is required.
NOTE: An internal pull-up is enabled only during PLTRST# assertion.
OC
Serial ATA Clock Request: This is an open-drain output pin when
OD
configured as SATACLKREQ#. It is to connect to the system clock
SATACLKREQ#/ (Native)
chip. When active, request for SATA Clock running is asserted. When
/
GPIO35
tri-stated, it tells the Clock Chip that SATA Clock can be stopped. An
I/O (GP)
external pull-up resistor is required.
2.8
IDE Interface
Table 2-8.
IDE Interface Signals (Sheet 1 of 2)
60
Name
Type
Description
DCS1#
O
IDE Device Chip Selects for 100 Range: For ATA command register
block. This output signal is connected to the corresponding signal on the
IDE connector.
DCS3#
O
IDE Device Chip Select for 300 Range: For ATA control register
block. This output signal is connected to the corresponding signal on the
IDE connector.
DA[2:0]
O
IDE Device Address: These output signals are connected to the
corresponding signals on the IDE connector. They are used to indicate
which byte in either the ATA command block or control block is being
addressed.
DD[15:0]
I/O
IDE Device Data: These signals directly drive the corresponding
signals on the IDE connector. There is a weak internal pull-down resistor
on DD7.
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-8.
IDE Interface Signals (Sheet 2 of 2)
Name
DDREQ
DDACK#
DIOR# /
(DWSTB /
RDMARDY#)
Type
Description
I
IDE Device DMA Request: This input signal is directly driven from the
DRQ signal on the IDE connector. It is asserted by the IDE device to
request a data transfer, and used in conjunction with the PCI bus master
IDE function and are not associated with any AT compatible DMA
channel. There is a weak internal pull-down resistor on this signal.
O
IDE Device DMA Acknowledge: This signal directly drives the DAK#
signal on the IDE connector. DDACK# is asserted by the Intel® ICH7 to
indicate to IDE DMA slave devices that a given data transfer cycle
(assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal
is used in conjunction with the PCI bus master IDE function and are not
associated with any AT-compatible DMA channel.
Disk I/O Read (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may drive data onto the DD lines. Data is latched
by the ICH7 on the deassertion edge of DIOR#. The IDE device is
selected either by the ATA register file chip selects (DCS1# or DCS3#)
and the DA lines, or the IDE DMA acknowledge (DDAK#).
O
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write
strobe for writes to disk. When writing to disk, ICH7 drives valid data on
rising and falling edges of DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for
reads from disk. When reading from disk, ICH7 deasserts RDMARDY# to
pause burst data transfers.
DIOW# /
(DSTOP)
O
Disk I/O Write (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may latch data from the DD lines. Data is latched
by the IDE device on the deassertion edge of DIOW#. The IDE device is
selected either by the ATA register file chip selects (DCS1# or DCS3#)
and the DA lines, or the IDE DMA acknowledge (DDAK#).
Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst.
IORDY /
(DRSTB /
WDMARDY#)
I/O Channel Ready (PIO): This signal will keep the strobe active
(DIOR# on reads, DIOW# on writes) longer than the minimum width. It
adds wait-states to PIO transfers.
I
Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
disk, ICH7 latches data on rising and falling edges of this signal from
the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this
is de-asserted by the disk to pause burst data transfers.
Intel ® ICH7 Family Datasheet
61
Signal Description
2.9
LPC Interface
Table 2-9.
LPC Interface Signals
Name
Type
Description
LAD[3:0] /
FWH[3:0]
I/O
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pullups are provided.
LFRAME# /
FWH4
O
LDRQ0#
LDRQ1# /
GPIO23
(Desktop
and Mobile
only)
2.10
I
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically connected
to external Super I/O device. An internal pull-up resistor is provided on
these signals.
LDRQ1# may optionally be used as GPIO.
Interrupt Interface
Table 2-10. Interrupt Signals
Name
Type
SERIRQ
I/O
PIRQ[D:A]#
(Desktop
and Mobile
only)
62
I/OD
Description
Serial Interrupt Request: This pin implements the serial interrupt
protocol.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in
the Interrupt Steering section. Each PIRQx# line has a separate Route
Control register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17,
PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy
interrupts.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be
routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in
the Interrupt Steering section. Each PIRQx# line has a separate Route
Control register.
PIRQ[H:E]#
/ GPIO[5:2]
I/OD
IDEIRQ
I
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21,
PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy
interrupts. If not needed for interrupts, these signals can be used as
GPIO.
IDE Interrupt Request: This interrupt input is connected to the IDE
drive.
Intel ® ICH7 Family Datasheet
Signal Description
2.11
USB Interface
Table 2-11. USB Interface Signals
Name
USBP0P,
USBP0N,
USBP1P,
USBP1N
USBP2P,
USBP2N,
USBP3P,
USBP3N
USBP4P,
USBP4N,
USBP5P,
USBP5N
USBP6P,
USBP6N,
USBP7P,
USBP7N
Type
Universal Serial Bus Port [1:0] Differential: These differential
pairs are used to transmit Data/Address/Command signals for ports
0 and 1. These ports can be routed to UHCI controller #1 or the EHCI
controller.
I/O
NOTE: No external resistors are required on these signals. The
Intel® ICH7 integrates 15 kΩ pull-downs and provides an
output driver impedance of 45 Ω which requires no external
series resistor
I/O
OC6# / GPIO30
Universal Serial Bus Port [3:2] Differential: These differential
pairs are used to transmit data/address/command signals for ports 2
and 3. These ports can be routed to UHCI controller #2 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH7
integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
I/O
Universal Serial Bus Port [5:4] Differential: These differential
pairs are used to transmit Data/Address/Command signals for ports
4 and 5. These ports can be routed to UHCI controller #3 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH7
integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
I/O
Universal Serial Bus Port [7:6] Differential: These differential
pairs are used to transmit Data/Address/Command signals for ports
6 and 7. These ports can be routed to UHCI controller #4 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH7
integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor
OC[4:0]#
OC5# / GPIO29
Description
I
OC7# / GPIO31
Overcurrent Indicators: These signals set corresponding bits in
the USB controllers to indicate that an overcurrent condition has
occurred.
OC[7:5]# may optionally be used as GPIOs.
NOTE: OC[7:0]# are not 5 V tolerant.
USBRBIAS
O
USB Resistor Bias: Analog connection point for an external resistor.
Used to set transmit currents and internal load resistors.
USBRBIAS#
I
USB Resistor Bias Complement: Analog connection point for an
external resistor. Used to set transmit currents and internal load
resistors.
Intel ® ICH7 Family Datasheet
63
Signal Description
2.12
Power Management Interface
Table 2-12. Power Management Interface Signals (Sheet 1 of 3)
Name
PLTRST#
Type
O
Description
Platform Reset: The Intel® ICH7 asserts PLTRST# to reset devices
on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The
ICH7 asserts PLTRST# during power-up and when S/W initiates a hard
reset sequence through the Reset Control register (I/O Register
CF9h). The ICH7 drives PLTRST# inactive a minimum of 1 ms after
both PWROK and VRMPWRGD are driven high. The ICH7 drives
PLTRST# active a minimum of 1 ms when initiated through the Reset
Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.
I
Thermal Alarm: THRM# is an active low signal generated by external
hardware to generate an SMI# or SCI.
THRMTRIP#
I
Thermal Trip: When low, this signal indicates that a thermal trip from
the processor occurred, and the ICH7 will immediately transition to a
S5 state. The ICH7 will not wait for the processor stop grant cycle
since the processor has overheated.
SLP_S3#
O
S3 Sleep Control: SLP_S3# is for power plane control. This signal
shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.
THRM#
S4 Sleep Control: SLP_S4# is for power plane control. This signal
shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.
SLP_S4#
O
NOTE: This pin must be used to control the DRAM power to use the
ICH7’s DRAM power-cycling feature. Refer to
Chapter 5.14.11.2 for details.
SLP_S5#
PWROK
O
I
S5 Sleep Control: SLP_S5# is for power plane control. This signal is
used to shut power off to all non-critical systems when in the S5 (Soft
Off) states.
Power OK: When asserted, PWROK is an indication to the ICH7 that
core power has been stable for 99 ms and that PCICLK has been
stable for 1 ms. An exception to this rule is if the system is in S3HOT, in
which PWROK may or may not stay asserted even though PCICLK may
be inactive. PWROK can be driven asynchronously. When PWROK is
negated, the ICH7 asserts PLTRST#.
NOTE: PWROK must deassert for a minimum of three RTC clock
periods for the ICH7 to fully reset the power and properly
generate the PLTRST# output.
64
PWRBTN#
I
Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is
pressed for more than 4 seconds, this will cause an unconditional
transition (power button override) to the S5 state. Override will occur
even if the system is in the S1-S4 states. This signal has an internal
pull-up resistor and has an internal 16 ms de-bounce on the input.
RI#
(Desktop and
Mobile Only)
I
Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-12. Power Management Interface Signals (Sheet 2 of 3)
Name
Type
Description
SYS_RESET#
I
System Reset: This pin forces an internal reset after being
debounced. The ICH7 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before
forcing a reset on the system.
RSMRST#
I
Resume Well Reset: This signal is used for resetting the resume
power plane logic.
LAN_RST#
(Desktop and
Mobile Only)
I
LAN Reset: When asserted, the internal LAN controller will be put into
reset. This signal must be asserted for at least 10 ms after the resume
well power (VccSus3_3 in desktop and VccLAN3_3 and VccLAN1_05 in
mobile) is valid. When deasserted, this signal is an indication that the
resume (LAN for mobile) well power is stable.
NOTE: LAN_RST# should be tied to RSMRST#.
WAKE#
I
MCH_SYNC#
I
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.
MCH SYNC: This input is internally ANDed with the PWROK input.
Connect to the ICH_SYNC# output of (G)MCH.
SUS_STAT# /
LPCPD#
O
Suspend Status: This signal is asserted by the ICH7 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC interface.
SUSCLK
O
Suspend Clock: This clock is an output of the RTC generator circuit to
use by other chips for refresh clock.
VRMPWRGD
I
VRM Power Good: This should be connected to be the processor’s
VRM Power Good signifying the VRM is stable. This signal is internally
ANDed with the PWROK input.
Bus Master Busy: This signal supports the C3 state. It provides an
indication that a bus master device is busy. When this signal is
asserted, the BM_STS bit will be set. If this signal goes active in a C3
state, it is treated as a break event.
BM_BUSY#
(Mobile/Ultra
Mobile Only) /
GPIO0
(Desktop Only)
I
CLKRUN#
(Mobile/Ultra
Mobile Only)/
GPIO32
(Desktop Only)
I/O
STP_PCI#
(Mobile/Ultra
Mobile Only) /
GPIO18
(Desktop Only)
Intel ® ICH7 Family Datasheet
NOTE: This signal is internally synchronized using the PCICLK and a
two-stage synchronizer. It does not need to meet any
particular setup or hold time.
NOTE: In desktop configurations, this signal pin is a GPIO.
O
PCI Clock Run: This clock supports the PCI CLKRUN protocol. It
connects to peripherals that need to request clock restart or
prevention of clock stopping.
Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock. It is used to support PCI
CLKRUN# protocol. If this functionality is not needed, this signal can
be configured as a GPIO.
NOTE: Refered to as STPPCI# on Ultra Mobile.
65
Signal Description
Table 2-12. Power Management Interface Signals (Sheet 3 of 3)
Name
Type
STP_CPU#
(Mobile/Ultra
Mobile Only) /
GPIO20
(Desktop Only)
2.13
O
Description
Stop CPU Clock: This signal is an output to the external clock
generator for it to turn off the processor clock. It is used to support
the C3 state. If this functionality is not needed, this signal can be
configured as a GPIO.
NOTE: Refered to as STPCPU# on Ultra Mobile.
BATLOW#
(Mobile/Ultra
Mobile Only) /
TP0
(Desktop Only)
I
Battery Low: This signal is an input from battery to indicate that
there is insufficient power to boot the system. Assertion will prevent
wake from S3–S5 state. This signal can also be enabled to cause an
SMI# when asserted.
DPRSLPVR
(Mobile/Ultra
Mobile Only) /
GPIO16
(Desktop Only)
O
Deeper Sleep - Voltage Regulator: This signal is used to lower the
voltage of VRM during the C4 state. When the signal is high, the
voltage regulator outputs the lower “Deeper Sleep” voltage. When low
(default), the voltage regulator outputs the higher “Normal” voltage.
DPRSTP#
(Mobile/Ultra
Mobile Only) /
TP1
(Desktop Only)
O
Deeper Stop: This is a copy of the DPRSLPVR and it is active low.
Processor Interface
Table 2-13. Processor Interface Signals (Sheet 1 of 3)
Name
Type
Description
A20M#
O
Mask A20: A20M# will go active based on either setting the appropriate
bit in the Port 92h register, or based on the A20GATE input being active.
CPUSLP#
O
CPU Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that
time, no snoops occur. The Intel® ICH7 can optionally assert the CPUSLP#
signal when going to the S1 state. (Desktop Only)
Reserved. (Mobile/Ultra Mobile Only)
FERR#
I
Numeric Coprocessor Error: This signal is tied to the coprocessor error
signal on the processor. FERR# is only used if the ICH7 coprocessor error
reporting function is enabled in the OIC.CEN register (Chipset Config
Registers:Offset 31FFh: bit 1). If FERR# is asserted, the ICH7 generates
an internal IRQ13 to its interrupt controller unit. It is also used to gate the
IGNNE# signal to ensure that IGNNE# is not asserted to the processor
unless FERR# is active. FERR# requires an external weak pull-up to
ensure a high level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the processor
of pending interrupt events. This functionality is independent of
the OIC register bit setting.
66
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-13. Processor Interface Signals (Sheet 2 of 3)
Name
Type
Description
IGNNE#
O
Ignore Numeric Error: This signal is connected to the ignore error pin
on the processor. IGNNE# is only used if the ICH7 coprocessor error
reporting function is enabled in the OIC.CEN register (Chipset Config
Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a coprocessor
error, a write to the Coprocessor Error register (I/O register F0h) causes
the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is
negated. If FERR# is not asserted when the Coprocessor Error register is
written, the IGNNE# signal is not asserted.
INIT#
O
Initialization: INIT# is asserted by the ICH7 for 16 PCI clocks to reset
the processor. ICH7 can be configured to support processor Built In Self
Test (BIST).
INIT3_3V#
(Desktop
and Mobile
Only)
O
Initialization 3.3 V: This is the identical 3.3 V copy of INIT# intended
for Firmware Hub.
INTR
O
CPU Interrupt: INTR is asserted by the ICH7 to signal the processor that
an interrupt request is pending and needs to be serviced. It is an
asynchronous output and normally driven low.
NMI
O
Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt
to the processor. The ICH7 can generate an NMI when either SERR# is
asserted or IOCHK# goes active via the SERIRQ# stream. The processor
detects an NMI when it detects a rising edge on NMI. NMI is reset by
setting the corresponding NMI source enable/disable bit in the NMI Status
and Control register (I/O Register 61h).
SMI#
O
System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH7 in response to one of
many enabled hardware or software events.
O
Stop Clock Request: STPCLK# is an active low output synchronous to
PCICLK. It is asserted by the ICH7 in response to one of many hardware
or software events. When the processor samples STPCLK# asserted, it
responds by stopping its internal clock.
STPCLK#
RCIN#
I
Keyboard Controller Reset CPU: The keyboard controller can generate
INIT# to the processor. This saves the external OR gate with the ICH7’s
other sources of INIT#. When the ICH7 detects the assertion of this
signal, INIT# is generated for 16 PCI clocks.
NOTE: The ICH7 will ignore RCIN# assertion during transitions to the S1,
S3, S4, and S5 states.
Intel ® ICH7 Family Datasheet
67
Signal Description
Table 2-13. Processor Interface Signals (Sheet 3 of 3)
Name
Type
Description
A20GATE
I
A20 Gate: A20GATE is from the keyboard controller. The signal acts as an
alternative method to force the A20M# signal active. It saves the external
OR gate needed with various other chipsets.
CPUPWRGD
/ GPIO49
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input to indicate when the CPU power is valid. This is an output
signal that represents a logical AND of the ICH7’s PWROK and VRMPWRGD
signals.
O
This signal may optionally be configured as a GPIO.
DPSLP#
(Mobile/Ultra
Mobile Only)
/ TP2
(Desktop
Only)
2.14
Deeper Sleep: DPSLP# is asserted by the ICH7 to the processor. When
the signal is low, the processor enters the deep sleep state by gating off
the processor core clock inside the processor. When the signal is high
(default), the processor is not in the deep sleep state.
O
SMBus Interface
Table 2-14. SM Bus Interface Signals
2.15
Name
Type
Description
SMBDATA
I/OD
SMBus Data: External pull-up resistor is required.
SMBCLK
I/OD
SMBus Clock: External pull-up resistor is required.
SMBALERT# /
GPIO11
I
SMBus Alert: This signal is used to wake the system or generate
SMI#. If not used for SMBALERT#, it can be used as a GPIO.
System Management Interface
Table 2-15. System Management Interface Signals
68
Name
Type
Description
INTRUDER#
I
SMLINK[1:0]
(Desktop
and Mobile
Only)
I/OD
System Management Link: These signals provide a SMBus link to
optional external system management ASIC or LAN controller. External
pull-ups are required. Note that SMLINK0 corresponds to an SMBus
clock signal, and SMLINK1 corresponds to an SMBus Data signal.
LINKALERT#
(Desktop
and Mobile
Only)
I/OD
SMLink Alert: This signal is an output of the integrated LAN and input
to either the integrated ASF or an external management controller in
order for the LAN’s SMLINK slave to be serviced.
Intruder Detect: This signal can be set to disable the system if the
chasis is detected open. This signal’s status is readable, so it can be
used like a GPIO if the Intruder Detection is not needed.
Intel ® ICH7 Family Datasheet
Signal Description
2.16
Real Time Clock Interface
Table 2-16. Real Time Clock Interface
2.17
Name
Type
Description
RTCX1
Special
Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, RTCX1 can be driven with the desired clock
rate.
RTCX2
Special
Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, RTCX2 should be left floating.
Other Clocks
Table 2-17. Other Clocks
Name
Type
Description
CLK14
I
Oscillator Clock: This clock signal is used for the 8254 timers. It runs at
14.31818 MHz. This clock is permitted to stop during S3 (or lower)
states.
CLK48
I
48 MHz Clock: This clock signal is used to run the USB controller. It runs
at 48.000 MHz. This clock is permitted to stop during S3 (or lower)
states.
I
100 MHz Differential Clock: These signals are used to run the SATA
controller at 100 MHz. This clock is permitted to stop during S3/S4/S5
states.
I
100 MHz Differential Clock: These signals are used to run the Direct
Media Interface. They run at 100 MHz.
SATA_CLKP
SATA_CLKN
(Desktop
and Mobile
Only)
DMI_CLKP,
DMI_CLKN
Intel ® ICH7 Family Datasheet
69
Signal Description
2.18
Miscellaneous Signals
Table 2-18. Miscellaneous Signals
Name
Type
Description
INTVRMEN
(Desktop and
Mobile Only)
I
Internal Voltage Regulator Enable: This signal enables the internal
1.05 V Suspend regulator when connected to VccRTC. When connected
to Vss, the internal regulator is disabled
SPKR
O
Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal
drives an external speaker driver device, which in turn drives the
system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a functional
strap. See Section 2.24.1 for more details. There is a weak
integrated pull-down resistor on SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC
well.
70
RTCRST#
(Desktop and
Mobile Only)
I
NOTES:
1.
Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must be high when all other RTC
power planes are on.
2.
In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST# pin.
TP0
(Desktop
Only) /
BATLOW#
(Mobile/Ultra
Mobile Only)
I
Test Point 0: This signal must have an external pull-up to VccSus3_3.
TP1
(Desktop
Only) /
DPRSTP#
(Mobile/Ultra
Mobile Only)
O
Test Point 1: Route signal to a test point.
TP2
(Desktop
Only) /
DPSLP#
(Mobile/Ultra
Mobile Only)
O
Test Point 2: Route signal to a test point.
TP3
I/O
Test Point 3: Route signal to a test point.
Intel ® ICH7 Family Datasheet
Signal Description
2.19
AC ’97/Intel® High Definition Audio Link
Note:
AC ‘97 is not supported on Ultra Mobile.
Table 2-19. AC ’97/Intel® High Definition Audio Link Signals
Name1,2
Type
Description
®
ACZ_RST#
O
AC ’97/Intel High Definition Audio Reset: This signal is the
master hardware reset to external codec(s).
ACZ_SYNC
O
AC ’97/Intel High Definition Audio Sync: This signal is a 48 kHz
fixed rate sample sync to the codec(s). It is also used to encode the
stream number.
AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data
clock generated by the external codec(s). This signal has an
integrated pull-down resistor (see Note below).
ACZ_BIT_CLK
ACZ_SDOUT
I/O
O
Intel High Definition Audio Bit Clock Output: This signal is a
24.000 MHz serial data clock generated by the Intel High Definition
Audio controller (the Intel® ICH7). This signal has an integrated pulldown resistor so that ACZ_BIT_CLK doesn’t float when an Intel High
Definition Audio codec (or no codec) is connected but the signals are
temporarily configured as AC ’97.
AC ’97/Intel High Definition Audio Serial Data Out: This signal
is the serial TDM data output to the codec(s). This serial output is
double-pumped for a bit rate of 48 Mb/s for Intel High Definition
Audio.
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a
functional strap. See Section 2.24.1 for more details. There is
a weak integrated pull-down resistor on the ACZ_SDOUT pin.
ACZ_SDIN[2:0]
AZ_DOCK_EN#
(Mobile Only) /
GPIO33
AZ_DOCK_RST#
(Mobile Only) /
GPIO34
I
I/O
AC ’97/Intel High Definition Audio Serial Data In [2:0]: These
signals are serial TDM data inputs from the three codecs. The serial
input is single-pumped for a bit rate of 24 Mb/s for Intel® High
Definition Audio. These signals have integrated pull-down resistors
that are always enabled.
High Definition Audio Dock Enable: This signal controls the
external Intel HD Audio docking isolation logic. This is an active low
signal. When deasserted, the external docking switch is in isolate
mode. When asserted, the external docking switch electrically
connects the Intel HD Audio dock signals to the corresponding Intel®
ICH7 signals.
This signal is shared with GPIO33. This signal defaults to GPIO33
mode after PLTRST# reset and will be in the high state after
PLTRST# reset. BIOS is responsible for configuring GPIO33 to
AZ_DOCK_EN# mode.
I/O
High Definition Audio Dock Reset: This signal is a dedicated
AZ_RST# signal for the codec(s) in the docking station. Aside from
operating independently from the normal ACZ_RST# signal, it
otherwise works similarly to the ACZ_RST# signal.
This signal is shared with GPIO34. This signal defaults to GPIO34
mode after PLTRST# reset and will be in the low state after PLTRST#
reset. BIOS is responsible for configuring GPIO34 to
AZ_DOCK_RST# mode.
NOTES:
1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details.
2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode
of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0 AC ‘97 mode is selected. When set to
1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode).
Intel ® ICH7 Family Datasheet
71
Signal Description
2.20
Serial Peripheral Interface (SPI) (Desktop and
Mobile Only)
Table 2-20. Serial Peripheral Interface (SPI) Signals
2.21
Name
Type
Description
SPI_CS#
I/O
SPI_MISO
I
SPI Master IN Slave OUT: This signal is the data input pin for
Intel® ICH7.
SPI_MOSI
O
SPI Master OUT Slave IN: This signal is the data output pin for
ICH7.
SPI_ARB
I
SPI Arbitration: SPI_ARB is the SPI arbitration signal used to
arbitrate the SPI bus with Intel PRO 82573E Gigabit Ethernet
Controller when Shared Flash is implemented.
SPI_CLK
O
SPI Clock: This signal is the SPI clock signal. During idle, the bus
owner will drive the clock signal low. 17.86 MHz.
SPI Chip Select: This chip select signal is also used as the SPI bus
request signal.
Intel® Quick Resume Technology (Intel® ICH7DH
Only)
Signal Name
Type
EL_RSVD /
GPIO26
I/O
Description
Intel® Quick Resume Technology Reserved: This signal is
reserved and should be left as a no connect when Intel Quick
Resume Technology is enabled.
NOTE: This signal cannot be reused as a GPIO when Intel Quick
Resume Technology is enabled.
EL_STATE[1:0] /
GPIO[28:27]
2.22
I/O
Intel Quick Resume Technology State: Intel Quick Resume
Technology status signals that may optionally be used to drive front
chassis indicators. See Section 5.26.3 for details.
General Purpose I/O Signals
Table 2-21. General Purpose I/O Signals (Sheet 1 of 3)
72
Name1,2
Type
Tolerance
Power
Well
Default
GPIO49
I/O
V_CPU_IO
V_CPU_IO
Native
Description
Multiplexed with CPUPWRGD
GPIO48
I/O
3.3 V
Core
Native
GPIO[47:40]
N/A
N/A
N/A
N/A
Not implemented.
Multiplexed with GNT4#
GPIO[39:38]
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPI
Unmultiplexed.
GPIO37
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPI
Multiplexed with SATA3GP.
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-21. General Purpose I/O Signals (Sheet 2 of 3)
Name1,2
Type
Tolerance
Power
Well
Default
GPIO36
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPI
Multiplexed with SATA2GP.
GPIO35
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPO
Multiplexed with SATACLKREQ#.
GPIO34
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPO
Mobile Only: Multiplexed with
AZ_DOCK_RST#.
GPIO33
(Desktop and
Mobile Only)
I/O
GPIO32
Description
Desktop Only: Unmultiplexed.
3.3 V
Core
GPO
Mobile Only: Multiplexed with
AZ_DOCK_EN#.
Desktop Only: Unmultiplexed.
Mobile/Ultra Mobile Only: this
GPIO is not implemented and is
used instead as CLKRUN#.
I/O
3.3 V
Core
GPO
GPIO31
I/O
3.3 V
Resume
Native
Multiplexed with OC7#
GPIO30
I/O
3.3 V
Resume
Native
Multiplexed with OC6#
GPIO29
I/O
3.3 V
Resume
Native
(Desktop Only)
Desktop Only: Unmultiplexed.
GPIO28
(Desktop and
Mobile Only)
GPIO27
(Desktop and
Mobile Only)
I/O
I/O
3.3 V
3.3 V
Resume
Resume
GPO
GPO
Multiplexed with OC5#
Intel® ICH7, ICH7R, and Mobile
Only: Unmultiplexed.
ICH7DH Only: Multiplexed with
EL_STATE1
Intel® ICH7, ICH7R, and Mobile
Only: Unmultiplexed.
ICH7DH Only: Multiplexed with
EL_STATE0
Intel® ICH7, ICH7R, and Mobile
Only: Unmultiplexed.
GPIO26
(Desktop and
Mobile Only)
I/O
3.3 V
Resume
GPO
GPIO25
(Desktop and
Mobile Only)
I/O
3.3 V
Resume
GPO
Unmultiplexed.
GPIO24
(Desktop and
Mobile Only)
I/O
3.3 V
Resume
GPO
Unmultiplexed. Not cleared by
CF9h reset event.
GPIO23
(Desktop and
Mobile Only)
I/O
3.3 V
Core
Native
Multiplexed with LDRQ1#
GPIO22
I/O
3.3 V
Core
Native
Multiplexed with REQ4#
GPIO21
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPI
GPIO20
(Desktop Only)
I/O
3.3 V
Core
GPO
ICH7DH Only: Multiplexed with
EL_RSVD
Multiplexed with SATA0GP.
Mobile/Ultra Mobile Only: GPIO is
not implemented and is used
instead as STP_CPU#.
Desktop Only: Unmultiplexed.
Intel ® ICH7 Family Datasheet
73
Signal Description
Table 2-21. General Purpose I/O Signals (Sheet 3 of 3)
Name1,2
Type
Tolerance
Power
Well
Default
GPIO19
(Desktop and
Mobile Only)
I/O
3.3 V
Core
GPI
GPIO18
(Desktop Only)
I/O
3.3 V
Core
GPO
Description
Multiplexed with SATA1GP.
Mobile/Ultra Mobile Only: GPIO is
not implemented and is used
instead as STP_PCI#.
Desktop Only: Unmultiplexed.
GPIO17
GPIO16
I/O
I/O
3.3 V
3.3 V
Core
GPO
Core
Native
(Mobile/
Ultra
Mobile) /
GPO
(Desktop)
Multiplexed with GNT5#.
Mobile/Ultra Mobile Only:
Natively used as DPRSLPVR.
Desktop Only: Unmultiplexed.
GPIO[15:12]
I/O
3.3 V
Resume
GPI
GPIO11
I/O
3.3 V
Resume
Native
GPIO[10:8]
I/O
3.3 V
Resume
GPI
Unmultiplexed.
GPIO[7:6]
I/O
3.3 V
Core
GPI
Unmultiplexed.
GPIO[5:2]
I/OD
5V
Core
GPI
Multiplexed with PIRQ[H:E]#.
GPIO1
I/O
5V
Core
GPI
Multiplexed with REQ5#.
I/O
3.3 V
Core
GPI
Mobile/Ultra Mobile Only:
Multiplexed with BM_BUSY#.
GPIO0
(Desktop Only)
Unmultiplexed.
Multiplexed with SMBALERT#
Desktop Only: Unmultiplexed
NOTES:
1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI,
but not both.
2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven
high into powered-down planes. Some ICH7 GPIOs may be connected to pins on devices that exist in the core
well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button
Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down.
2.23
Power and Ground
Table 2-22. Power and Ground Signals (Sheet 1 of 3)
Name
Vcc3_3
Vcc1_05
These pins provide the 3.3 V supply for core well I/O buffers (22pins). This
power may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.05 V supply for core well logic (20 pins). This power
may be shut off in S3, S4, S5 or G3 states.
Vcc1_5_A
These pins provide the 1.5 V supply for Logic and I/O (30 pins). This power may
be shut off in S3, S4, S5 or G3 states.
Vcc1_5_B
These pins provide the 1.5 V supply for Logic and I/O (53 pins). This power may
be shut off in S3, S4, S5 or G3 states.
V5REF
(Desktop and
Mobile Only)
74
Description
These pins provide the reference for 5 V tolerance on core well inputs (2 pins).
This power may be shut off in S3, S4, S5 or G3 states.
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-22. Power and Ground Signals (Sheet 2 of 3)
Name
V5REF1
(Ultra Mobile
Only)
V5REF2
(Ultra Mobile
Only)
VccSus3_3
VccSus1_05
Description
These pins provide the reference for 5 V tolerance on core well inputs (1 pin).
This power may be shut off in S3, S4, S5 or G3 states.
These pins provide the reference for 5 V tolerance on core well inputs (1 pin).
This power may be shut off in S3, S4, S5 or G3 states.
These pins provide the 3.3 V supply for resume well I/O buffers (24 pins). This
power is not expected to be shut off unless the system is unplugged in desktop
configurations or the main battery is removed or completely drained and AC
power is not available in mobile/Ultra Mobile configurations.
These pins provide the 1.05 V supply for resume well logic (5 pins). This power
is not expected to be shut off unless the system is unplugged in desktop
configurations or the main battery is removed or completely drained and AC
power is not available in mobile/Ultra Mobile configurations.
This voltage may be generated internally (see Section 2.24.1 for strapping
option). If generated internally, these pins should not be connected to an
external supply.
V5REF_Sus
VccLAN3_3
(Mobile Only)
This pin provides the reference for 5 V tolerance on resume well inputs (1 pin).
This power is not expected to be shut off unless the system is unplugged in
desktop configurations or the main battery is removed or completely drained
and AC power is not available in mobile/Ultra Mobile configurations.
These pins provide the 3.3 V supply for LAN Connect interface buffers (4 pins).
This is a separate power plane that may or may not be powered in S3–S5 states
depending upon the presence or absence of AC power and network connectivity.
This plane must be on in S0 and S1.
NOTE: In Desktop mode these signals are added to the VccSus3_3 group.
VccLAN1_05
(Mobile Only)
VccSusHDA
(Mobile/Ultra
Mobile Only)
These pins provide the 1.05 V supply for LAN controller logic (2 pins). This is a
separate power plane that may or may not be powered in S3–S5 states
depending upon the presence or absence of AC power and network connectivity.
This plane must be on in S0 and S1.
NOTE: This voltage will be generated internally if VccSus1_05 is generated
internally (see Section 2.24.1 for strapping option). If generated
internally, these pins should not be connected to an external supply.
NOTE: In Desktop mode these signals are added to the VccSus1_05 group.
This pin provides the suspend supply for Intel High Definition Audio (1 pins).
This pin can be either 1.5 V or 3.3 V. This power is not expected to be shut off
unless the main battery is removed or completely drained and AC power is not
available in mobile/Ultra Mobile configurations.
NOTE: In Desktop mode this signal is added to the VccSus3_3 group.
VccHDA
(Mobile/Ultra
Mobile Only)
This pin provides the core supply for Intel High Definition Audio (1 pin). This pin
can be either 1.5 V or 3.3 V. This power may be shut off in S3, S4, S5 or G3
states. This plane must be on in S0 and S1.
NOTE: In Desktop mode these signals are added to the Vcc3_3 group.
Intel ® ICH7 Family Datasheet
75
Signal Description
Table 2-22. Power and Ground Signals (Sheet 3 of 3)
Name
Description
This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the
RTC well (1 pin). This power is not expected to be shut off unless the RTC
battery is removed or completely drained.
VccRTC
NOTE: Implementations should not attempt to clear CMOS by using a jumper to
pull VccRTC low. Clearing CMOS in an Intel® ICH7-based platform can be
done by using a jumper on RTCRST# or GPI.
VccUSBPLL
(Desktop and
Mobile Only)
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be
powered even if USB not used.
VccDMIPLL
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL
(Desktop and
Mobile Only)
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must
be powered even if SATA not used.
V_CPU_IO
Vss
These pins are powered by the same supply as the processor I/O voltage (3
pins). This supply is used to drive the processor interface signals listed in
Table 2-13.
Grounds (194 pins).
2.24
Pin Straps
2.24.1
Functional Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
Table 2-23. Functional Strap Definitions (Sheet 1 of 3)
Signal
Usage
ACZ_SDOUT
XOR Chain
Entrance /
PCI
Express*
Port Config
bit 1
When
Sampled
Comment
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK. See Chapter 25
for XOR Chain functionality information.
Rising Edge of
PWROK
When TP3 not pulled low at rising edge of PWROK,
sets bit 1 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See Section 7.1.34 for
details.
This signal has a weak internal pull-down.
76
ACZ_SYNC
PCI Express
Port Config
bit 0
EE_CS
(Desktop
and Mobile
Only)
Reserved
This signal has a weak internal pull-down.
Rising Edge of
PWROK
Sets bit 0 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See Section 7.1.34 for
details.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
Intel ® ICH7 Family Datasheet
Signal Description
Table 2-23. Functional Strap Definitions (Sheet 2 of 3)
When
Sampled
Comment
Signal
Usage
EE_DOUT
(Desktop
and Mobile
Only)
Reserved
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
GNT2#
Reserved
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
Top-Block
Swap
Override
The signal has a weak internal pull-up. If the signal
is sampled low, this indicates that the system is
strapped to the “top-block swap” mode (Intel®
ICH7 inverts A16 for all cycles targeting FWH BIOS
space). The status of this strap is readable via the
Top Swap bit (Chipset Configuration
Registers:Offset 3414h:bit 0). Note that software
will not be able to clear the Top-Swap bit until the
system is rebooted without GNT3# being pulled
down.
GNT3#
GNT5# /
GPIO17#,
GNT4# /
GPIO48
Boot BIOS
Destination
Selection
Rising Edge of
PWROK
Rising Edge of
PWROK
This field determines the destination of accesses to
the BIOS memory range. Signals have weak
internal pull-ups. Also controllable via Boot BIOS
Destination bit (Chipset Configuration
Registers:Offset 3410h:bit 11:10)
(GNT5# is MSB)
01 = SPI (Desktop and Mobile Only)
10 = PCI
11 = LPC
GPIO16
(Desktop
Only) /
DPRSLPVR
(Mobile/Ultra
Mobile Only)
This signal has a weak internal pull-down.
Reserved
NOTE: This signal should not be pulled high.
This signal has a weak internal pull-up.The internal
pull-up is disabled within 100 ms after RSMRST#
deasserts.
GPIO25
DMI AC/DC
Coupling
Selection
(Desktop
Only)
INTVRMEN
(Desktop
and Mobile
Only)
Intel ® ICH7 Family Datasheet
Integrated
VccSus1_05
VRM
Enable/
Disable
If the signal is sampled high, the DMI interface is strapped
to operate in DC coupled mode (No coupling capacitors
are required on DMI differential pairs).
Rising Edge of
RSMRST#
If the signal is sampled low, the DMI interface is strapped
to operate in AC coupled mode (Coupling capacitors are
required on DMI differential pairs).
NOTE: Board designer must ensure that DMI
implementation matches the strap selection.
NOTE: The signal must be held low at least 2 us after
RSMRST# deassertion to enable AC coupled
mode.
Always
Enables integrated VccSus1_05 VRM when sampled
high.
77
Signal Description
Table 2-23. Functional Strap Definitions (Sheet 3 of 3)
Signal
When
Sampled
Usage
Comment
LINKALERT#
(Desktop
and Mobile
Only)
Reserved
This signal requires an external pull-up resistor.
REQ[4:1]#
XOR Chain
Selection
Rising Edge of
PWROK
SATALED#
(Desktop
and Mobile
Only)
Reserved
This signal has a weak internal pull-up enabled only
when PLTRST# is asserted.
NOTE: This signal should not be pulled low.
SPKR
No Reboot
Rising Edge of
PWROK
The signal has a weak internal pull-down. If the
signal is sampled high, this indicates that the
system is strapped to the “No Reboot” mode (ICH7
will disable the TCO Timer system reboot feature).
The status of this strap is readable via the NO
REBOOT bit (Chipset Config Registers:Offset
3410h:bit 5).
TP3
XOR Chain
Entrance
Rising Edge of
PWROK
See Chapter 25 for functionality information. This
signal has a weak internal pull-up.
NOTE: This signal should not be pulled low unless
using XOR Chain testing.
See Chapter 25 for functionality information.
NOTE: See Section 3.1for full details on pull-up/pull-down resistors.
2.24.2
External RTC Circuitry
To reduce RTC well power consumption, the ICH7 implements an internal oscillator
circuit that is sensitive to step voltage changes in VccRTC. Figure 2-4 shows an
example schematic recommended to ensure correct operation of the ICH7 RTC.
Figure 2-4.
Example External RTC Circuit
VccSus3_3
VCCRTC
Schottky
Diodes
(20% tolerance)
RTCX2
1 KΩ
Vbatt
1 µF
20 KΩ
+
–
R1
10 MΩ
32.768 kHz
Xtal
RTCX1
1 µF
(20% tolerance)
C1
15 pF
C2
15 pF
(5% tolerance)
(5% tolerance)
RTCRST#
NOTE: C1 and C2 depend on crystal load.
§
78
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
3
Intel® ICH7 Pin States
3.1
Integrated Pull-Ups and Pull-Downs
Table 3-1.
Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)
Resistor
Nominal
Notes
ACZ_BIT_CLK, AC ‘97 (Desktop and
Mobile Only)
Signal
Pull-down
20 kΩ
1, 2, 3
ACZ_RST#, AC ‘97 (Desktop and
Mobile Only)
Pull-down
20 kΩ
1, 2, 4
ACZ_SDIN[2:0], AC ‘97 (Desktop and
Mobile Only)
Pull-down
20 kΩ
2, 4
ACZ_SDOUT, AC ‘97 (Desktop and
Mobile Only)
Pull-down
20 kΩ
2, 4, 5
ACZ_SYNC, AC ‘97 (Desktop and Mobile
Only)
Pull-down
20 kΩ
2, 4, 5
ACZ_BIT_CLK, Intel® High Definition
Audio
Pull-Down
20 kΩ
2, 6, 7
None
N/A
2
ACZ_SDIN[2:0], Intel High Definition
Audio
Pull-down
20 kΩ
2, 4
ACZ_SDOUT, Intel High Definition Audio
Pull-down
20 kΩ
1, 2
ACZ_SYNC, Intel High Definition Audio
Pull-down
20 kΩ
2, 4
ACZ_RST#, Intel High Definition Audio
DD7
Pull-down
11.5 kΩ
8
DDREQ
Pull-down
11.5 kΩ
8
DPRSLPVR / GPIO16
Pull-down
20 kΩ
4, 9
EE_CS (Desktop and Mobile Only)
Pull-down
20 kΩ
10, 11
EE_DIN (Desktop and Mobile Only)
Pull-up
20 kΩ
10
EE_DOUT (Desktop and Mobile Only)
Pull-up
20 kΩ
10
GNT[1:0]
Pull-up
20 kΩ
10, 12
GNT[3:2],
GNT4# / GPIO48
GNT5# / GPIO17
Pull-up
20 kΩ
10, 19
GPIO25
Pull-up
20 kΩ
10, 13
LAD[3:0]# / FHW[3:0]#
Pull-up
20 kΩ
10
LAN_CLK (Desktop and Mobile Only)
Pull-down
100 kΩ
14
LAN_RXD[2:0] (Desktop and Mobile
Only)
Pull-up
20 kΩ
15
LDRQ[0]
Pull-up
20 kΩ
10
LDRQ1 / GPIO23
Pull-up
20 kΩ
10
PME#
Pull-up
20 kΩ
10
PWRBTN#
Pull-up
20 kΩ
10
SATALED#
Pull-up
15 kΩ
16
Intel ® ICH7 Family Datasheet
79
Intel® ICH7 Pin States
Table 3-1.
Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)
Resistor
Nominal
SPI_ARB (Desktop and Mobile Only)
Signal
Pull-down
20 kΩ
10
SPI_CLK (Desktop and Mobile Only)
Pull-down
20 kΩ
10
SPKR
Pull-down
20 kΩ
4
Pull-up
20 kΩ
17
Pull-down
15 kΩ
18
TP3
USB[7:0] [P,N]
Notes
NOTES:
1.
The pull-down resistors on ACZ_BIT_CLK (AC ‘97) and ACZ_RST# are enabled when
either:
- The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or
- Both Function 2 and Function 3 of Device 30 are disabled.
Otherwise, the integrated Pull-down resistor is disabled.
2.
The AC ‘97/Intel High Definition Audio Link signals may either all be configured to be an
AC-Link or an Intel High Definition Audio Link.
3.
Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ.
4.
Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.
5.
The pull-down resistors on ACZ_SYNC (AC ‘97) and ACZ_SDOUT (AC ‘97) are enabled
during reset and also enabled when either:
- The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or
- Both Function 2 and Function 3 of Device 30 are disabled.
Otherwise, the integrated Pull-down resistor is disabled.
6.
Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.
7.
The pull-down on this signal (in Intel High Definition Audio mode) is only enabled when in
S3COLD.
8.
Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ.
9.
The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.
10.
Simulation data shows that these resistor values can range from 15 kΩ to 35 kΩ.
11.
The pull-down on this signal is only enabled when LAN_RST# is asserted.
12.
The internal pull-up is enabled only when the PCIRST# pin is driven low and the PWROK
indication is high.
13.
Internal pull-up is enabled during RSMRST# and is disabled within 100 ms after RSMRST#
de-asserts.
14.
Simulation data shows that these resistor values can range from 45 kΩ to 170 kΩ.
15.
Simulation data shows that these resistor values can range from 15 kΩ to 30 kΩ.
16.
Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The
internal pull-up is only enabled only during PLTRST# assertion.
17.
Simulation data shows that these resistor values can range from 10 kW to 30 kW.
18.
Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ
19.
The internal pull-up is enabled only when PCIRST# is low.
3.2
IDE Integrated Series Termination Resistors
Table 3-2 shows the ICH7 IDE signals that have integrated series termination resistors.
Table 3-2.
IDE Series Termination Resistors
Signal
Integrated Series Termination Resistor Value
DD[15:0], DIOW#, DIOR#, DREQ,
DDACK#, IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ
approximately 33 Ω (See Note)
NOTE: Simulation data indicates that the integrated series termination resistors are a nominal
33 Ω but can range from 21 Ω to 75 Ω.
80
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
3.3
Output and I/O Signals Planes and States
Table 3-3 and Table 3-4 show the power plane associated with the output and I/O
signals, as well as the state at various times. Within the table, the following terms are
used:
“High-Z”
Tri-state. ICH7 not driving the signal high or low.
“High”
ICH7 is driving the signal to a logic 1
“Low”
ICH7 is driving the signal to a logic 0
“Defined”
Driven to a level that is defined by the function (will be high or
low)
“Undefined”
ICH7 is driving the signal, but the value is indeterminate.
“Running”
Clock is toggling or signal is transitioning because function not
stopping
“Off”
The power plane is off, so ICH7 is not driving
Note that the signal levels are the same in S4 and S5, except as noted.
ICH7 suspend well signal states are indeterminate and undefined and may glitch,
including input signals acting as outputs, prior to RSMRST# deassertion. This does not
apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate
and defined prior to RSMRST# deassertion.
ICH7 core well signal states are indeterminate and undefined and may glitch, including
input signals acting as outputs, prior to PWROK assertion. This does not apply to
FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK
assertion.
Table 3-3.
Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 1 of 5)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
S1
S3COLD3
S4/S5
High4
Defined
Off
Off
High4
Defined
Off
Off
PCI Express*
PETp[4:1],
PETn[4:1]
PETp[6:5],
PETn[6:5]
(Intel® ICH7R and
ICH7DH Only)
Core
High
DMI
DMI[3:0]TXP,
DMI[3:0]TXN
Intel ® ICH7 Family Datasheet
Core
High
81
Intel® ICH7 Pin States
Table 3-3.
Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 2 of 5)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
S1
S3COLD3
S4/S5
PCI Bus
AD[31:0]
Core
Low
Undefined
Defined
Off
Off
C/BE[3:0]#
Core
Low
Undefined
Defined
Off
Off
DEVSEL#
Core
High-Z
High-Z
High-Z
Off
Off
FRAME#
Core
High-Z
High-Z
High-Z
Off
Off
Core
High-Z with
Internal Pullup
High
High
Off
Off
Core
High-Z
High-Z
High-Z
Off
Off
GNT[3:0]#
GNT4# / GPIO48
GNT5# / GPIO17
IRDY#, TRDY#
PAR
Core
Low
Undefined
Defined
Off
Off
PCIRST#
Suspend
Low
High
High
Low
Low
PERR#
Core
High-Z
High-Z
High-Z
Off
Off
PLOCK#
Core
High-Z
High-Z
High-Z
Off
Off
STOP#
Core
High-Z
High-Z
High-Z
Off
Off
LPC Interface
LAD[3:0] /
FWH[3:0]
Core
High
High
High
Off
Off
LFRAME# / FWH[4]
Core
High
High
High
Off
Off
Defined
Defined
Defined
LAN Connect and EEPROM Interface
EE_CS
Suspend
Low
Running
EE_DOUT
Suspend
High
High
Defined
Defined
Defined
EE_SHCLK
Suspend
High-Z
Running
Defined
Defined
Defined
LAN_RSTSYNC
Suspend
High
Low
Defined
Defined
Defined
LAN_TXD[2:0]
Suspend
Low
Low
Defined
Defined
Defined
IDE Interface
DA[2:0]
Core
Undefined
Undefined
Undefined
Off
Off
DCS1#, DCS3#
Core
High
High
High
Off
Off
DD[15:8], DD[6:0]
Core
High-Z
High-Z
High-Z
Off
Off
DD[7]
Core
Low
Low
Low
Off
Off
DDACK#
Core
High
High
High
Off
Off
DIOR#, DIOW#
Core
High
High
High
Off
Off
SATA Interface
82
SATA[3:0]TXP,
SATA[3:0]TXN
Core
High-Z
High-Z
Defined
Off
Off
SATALED#
Core
High-Z
High-Z
Defined
Off
Off
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
Table 3-3.
Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 3 of 5)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
S1
S3COLD3
S4/S5
SATARBIAS
Core
High-Z
High-Z
High-Z
Off
Off
Core
Input
Input
Driven
Driven
Driven
Core
Low
Low
Defined
Off
Off
SATA3GP / GPIO37
SATA2GP / GPIO36
SATA1GP / GPIO19
SATA0GP / GPIO21
SATACLKREQ# /
GPIO35
Interrupts
PIRQ[A:D]#,
PIRQ[H:E]# /
GPIO[5:2]
Core
High-Z
High-Z
High-Z
Off
Off
SERIRQ
Core
High-Z
High-Z
High-Z
Off
Off
USB Interface
USBP[7:0][P,N]
Suspend
Low
Low
Low
Low
Low
USBRBIAS
Suspend
High-Z
High-Z
Defined
Defined
Defined
OC[7:5]# /
GPIO[31:29]
Suspend
Input
Input
Driven
Driven
Driven
Power Management
PLTRST#
Suspend
Low
High
High
Low
Low
SLP_S3#
Suspend
Low
High
High
Low
Low
SLP_S4#
Suspend
Low
High
High
High
Low
SLP_S5#
Suspend
Low
High
High
High
Low5
SUS_STAT#
Suspend
Low
High
High
Low
Low
SUSCLK
Suspend
Low
Running
Processor Interface
A20M#
Core
Dependant
on A20GATE
Signal
See Note 6
High
Off
Off
CPUPWRGD /
GPIO49
Core
Defined
High7
High
Off
Off
CPUSLP#
Core
High
High
Defined
Off
Off
IGNNE#
Core
High
See Note 6
High
Off
Off
INIT#
Core
High
High
High
Off
Off
INIT3_3V#
Core
High
High
High
Off
Off
INTR
Core
See Note 6
See Note 8
Low
Off
Off
NMI
Core
See Note 6
See Note 8
Low
Off
Off
SMI#
Core
High
High
High
Off
Off
Intel ® ICH7 Family Datasheet
83
Intel® ICH7 Pin States
Table 3-3.
Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 4 of 5)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
S1
S3COLD3
S4/S5
STPCLK#
Core
High
High
Low
Off
Off
Defined
Defined
Defined
SMBus Interface
SMBCLK, SMBDATA
Suspend
High-Z
High-Z
System Management Interface
SMLINK[1:0]
Suspend
High-Z
High-Z
Defined
Defined
Defined
LINKALERT#
Suspend
High-Z
High-Z
Defined
Defined
Defined
Defined
Off
Off
Miscellaneous Signals
SPKR
Core
High-Z with
Internal Pulldown
Low
AC ’97 Interface
ACZ_RST#
Suspend
Low
Low
Low
Low
Low
ACZ_SDOUT
Core
Low
Running
Low
Off
Off
ACZ_SYNC
Core
Low
Running
Low
Off
Off
Intel® High Definition Audio Interface
ACZ_RST#
Suspend
Low
Low9
Running
Low
Low
ACZ_SDOUT
Core
High-Z with
Internal Pulldown
Running
Low
Off
Off
ACZ_SYNC
Core
High-Z with
Internal Pulldown
Running
Low
Off
Off
ACZ_BIT_CLK
Core
High-Z with
Internal Pulldown
Low9
Low
Off
Off
Driven
Off
Off
Unmultiplexed GPIO Signals
84
GPIO[7:6, 0]
Core
Input
Input
GPIO[15:12,10:8]
Suspend
Input
Input
Driven
Driven
Driven
GPIO16
Core
Low
Low
Defined
Off
Off
GPIO18
Core
High
See Note 10
Defined
Off
Off
GPIO20
Core
High
High
Defined
Off
Off
GPIO24
Suspend
No Change
No Change
Defined
Defined
Defined
GPIO25
Suspend
High
High11
Defined
Defined
Defined
GPIO[28:26]
Suspend
Low
Low
Defined
Defined
Defined
GPIO[33:32]
Core
High
High
Defined
Off
Off
GPIO34
Core
Low
Low
Defined
Off
Off
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
Table 3-3.
Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 5 of 5)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
S1
S3COLD3
S4/S5
GPIO[39:38]
Core
Input
Input
Driven
Off
Off
SPI Interface
SPI_CS#
Suspend
High
High
High
High
High
SPI_MOSI
Suspend
High
High
High
High
High
SPI_CLK
Suspend
Low
Low
Low
Low
Low
Intel® Quick Resume Technology Interface (ICH7DH Only)
EL_RSVD / GPIO26
Suspend
Low
Low
Defined
Defined
Defined
EL_STATE[1:0] /
GPIO[28:27]
Suspend
Low
Low
Defined
Defined
Defined
NOTES:
1.
The states of Vcc3_3 signals are taken at the times During PLTRST# and Immediately after
PLTRST#.
2.
The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately
after RSMRST#.
3.
In S3HOT, signal states are platform implementation specific, as some external components
and interfaces may be powered when the ICH7 is in the S3HOT state.
4.
On the ICH7, PETp/n[4:1] are high until port is enabled by software. On the ICH7R and
ICH7DH, PETp/n[6:1] are high until port is enabled by software.
5.
SLP_S5# signals will be high in the S4 state.
6.
ICH7 drives these signals High after the processor Reset.
7.
CPUPWRGD represents a logical AND of the ICH7’s VRMPWRGD and PWROK signals, and
thus will be driven low by the ICH7 when either VRMPWRGD or PWROK are inactive. During
boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition
from low to High-Z.
8.
ICH7 drives these signals Low before PWROK rising and Low after the processor Reset.
9.
Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be
Running.
10.
GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset
11.
GPIO25 transitions from pulled high internally to actively driven within 100 ms of the
deassertion of the RSMRST# pin.
Intel ® ICH7 Family Datasheet
85
Intel® ICH7 Pin States
Table 3-4.
Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 1 of 4)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
S1
S3COLD3
S4/
S5
Defined
Defined
Off
Off
Defined
Defined
Off
Off
Off
Off
C3/C4
PCI Express* (Mobile Only)
PETp[6:1],
PETn[6:1]
Core
High4
High
DMI
DMI[3:0]TXP,
DMI[3:0]TXN
Core
High4
High
PCI Bus
AD[31:0]
Core
Low
Undefined
Defined
Defined
C/BE[3:0]#
Core
Low
Undefined
Defined
Defined
CLKRUN#
Core
Low
Low
Defined
Off
Off
Off
Off
DEVSEL#
Core
High-Z
High-Z
High-Z
High-Z
Off
Off
FRAME#
Core
High-Z
High-Z
High-Z
High-Z
Off
Off
Core
High with
Internal Pullups
High
High
High
Off
Off
Core
High-Z
High-Z
High-Z
High-Z
Off
Off
GNT[3:0]#
GNT4# / GPIO48
GNT5# / GPIO17
IRDY#, TRDY#
PAR
Core
Low
Undefined
Defined
Defined
Off
Off
PCIRST#
Suspend
Low
High
High
High
Low
Low
PERR#
Core
High-Z
High-Z
High-Z
High-Z
Off
Off
PLOCK#
Core
High-Z
High-Z
High-Z
High-Z
Off
Off
STOP#
Core
High-Z
High-Z
High-Z
High-Z
Off
Off
LPC Interface
LAD[3:0] /
FWH[3:0]
Core
High
High
High
High
Off
Off
LFRAME# /
FWH[4]
Core
High
High
High
High
Off
Off
Note 5
Note 5
LAN Connect and EEPROM Interface (Mobile Only)
EE_CS
LAN
Low
Running
Defined
Defined
EE_DOUT
LAN
High
High
Defined
Defined
Note 5
Note 5
EE_SHCLK
LAN
High-Z
Running
Defined
Defined
Note 5
Note 5
LAN_RSTSYNC
LAN
High
Low
Defined
Defined
Note 5
Note 5
LAN_TXD[2:0]
LAN
Low
Low
Defined
Defined
Note 5
Note 5
IDE Interface
86
DA[2:0]
Core
Undefined
Undefined
Undefine
d
Undefine
d
Off
Off
DCS1#, DCS3#
Core
High
High
High
High
Off
Off
DD[15:8],
DD[6:0]
Core
High-Z
High-Z
Defined
High-Z
Off
Off
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
Table 3-4.
Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 2 of 4)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
C3/C4
S1
S3COLD3
S4/
S5
DD[7]
Core
Low
Low
Defined
Low
Off
Off
DDACK#
Core
High
High
High
High
Off
Off
DIOR#, DIOW#
Core
High
High
High
High
Off
Off
SATA Interface (Mobile Only)
SATA[0]TXP,
SATA[0]TXN
Core
High-Z
High-Z
Defined
Defined
Off
Off
SATALED#
Core
High-Z
High-Z
Defined
Defined
Off
Off
SATARBIAS
Core
High-Z
High-Z
Defined
Defined
Off
Off
Core
Input
Input
Driven
Driven
Driven
Core
Low
Low
Defined
Defined
Off
Off
SATA[2]TXP,
SATA[2]TXN
SATA2GP / GPIO36
SATA0GP / GPIO21
SATACLKREQ# /
GPIO35
Interrupts
PIRQ[A:D]#,
PIRQ[H:E]# /
GPIO[5:2]
Core
High-Z
High-Z
Defined
High-Z
Off
Off
SERIRQ
Core
High-Z
High-Z
Running
High-Z
Off
Off
USB Interface
USBP[7:0][P,N]
Suspend
Low
Low
Low
Low
Low
Low
USBRBIAS
Suspend
High-Z
High-Z
Defined
Defined
Defined
Define
d
OC[7:5]# /
GPIO[31:29]
Suspend
Input
Input
Driven
Driven
Driven
Driven
High
High
Low
Low
Power Management
PLTRST#
Suspend
Low
High
SLP_S3#
Suspend
Low
High
High
High
Low
Low
SLP_S4#
Suspend
Low
High
High
High
High
Low
SLP_S5#
Suspend
Low
High
High
High
High
Low6
STP_PCI#
Core
High
High
Defined
High
Low
Low
STP_CPU#
Core
High
High
Low
High
Low
Low
SUS_STAT#
Suspend
Low
High
High
High
Low
Low
DPRSLPVR
Core
Low
Low
Low/
High7
High
Off
Off
DPRSTP#
Core
High
High
Low/
High7
High
Off
Off
SUSCLK
Suspend
Low
Intel ® ICH7 Family Datasheet
Running
87
Intel® ICH7 Pin States
Table 3-4.
Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 3 of 4)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
C3/C4
S1
S3COLD3
S4/
S5
Processor Interface
A20M#
Core
Dependant
on A20GATE
Signal
See Note 8
Defined
High
Off
Off
CPUPWRGD /
GPIO49
Core
See Note 9
High
High
High
Off
Off
IGNNE#
Core
High
See Note 8
High
High
Off
Off
INIT#
Core
High
High
High
High
Off
Off
INIT3_3V#
Core
High
High
High
High
Off
Off
INTR
Core
See Note 10
See Note 10
Defined
Low
Off
Off
NMI
Core
See Note 10
See Note 10
Defined
Low
Off
Off
SMI#
Core
High
High
Defined
High
Off
Off
STPCLK#
Core
High
High
Low
Low
Off
Off
DPSLP#
Core
High
High
High/Low
High
Off
Off
Defined
Defined
Defined
Define
d
SMBus Interface
SMBCLK,
SMBDATA
Suspend
High-Z
High-Z
System Management Interface
SMLINK[1:0]
Suspend
High-Z
High-Z
Defined
Defined
Defined
Define
d
LINKALERT#
Suspend
High-Z
High-Z
Defined
Defined
Defined
Define
d
Defined
Defined
Off
Off
Cold
Reset Bit
(High)
Low
Low
Miscellaneous Signals
SPKR
Core
High-Z with
Internal Pulldown
Low
AC ’97 Interface (Mobile Only)
ACZ_RST#
Suspend
Low
Low
High
ACZ_SDOUT
Core
Low
Running
Running
Low
Off
Off
ACZ_SYNC
Core
Low
Running
Running
Low
Off
Off
Intel® High Definition Audio Interface
88
ACZ_RST#
Suspend
Low
Low11
High
TBD
Low
Low
ACZ_SDOUT
Core
High-Z with
Internal Pulldown
Running
Running
Low
Off
Off
ACZ_SYNC
Core
High-Z with
Internal Pulldown
Running
Running
Low
Off
Off
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
Table 3-4.
Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 4 of 4)
Signal Name
Power
Plane
During
PLTRST#1 /
RSMRST#2
Immediately
after
PLTRST#1 /
RSMRST#2
C3/C4
S1
S3COLD3
S4/
S5
ACZ_BIT_CLK
Core
High-Z with
Internal Pulldown
Low11
Running
Low
Off
Off
AZ_DOCK_RST# /
GPIO34
Core
Low
Low11
Defined
Defined
Off
Off
AZ_DOCK_EN# /
GPIO33
Core
High
High
Defined
Defined
Off
Off
Unmultiplexed GPIO Signals
GPIO[7:6]
Core
Input
Input
Driven
Driven
Off
Off
GPIO[15:12,10:8]
Suspend
Input
Input
Driven
Driven
Driven
Driven
GPIO18
Core
High
See Note 12
Driven
Driven
Off
Off
GPIO19
Core
Input
Input
Driven
Driven
Off
Off
GPIO24
Suspend
No Change
No Change
Defined
Defined
Defined
Define
d
GPIO25
Suspend
High
High13
Defined
Defined
Defined
Define
d
GPIO[28:26]
Suspend
Low
Low
Defined
Defined
Defined
Define
d
GPIO[39:37]
Core
Input
Input
Driven
Driven
Off
Off
SPI Interface (Mobile Only)
SPI_CS#
Suspend
High
High
High
High
High
High
SPI_MOSI
Suspend
High
High
High
High
High
High
SPI_ARB
Suspend
Low
Low
Low
Low
Low
Low
SPI_CLK
Suspend
Low
Low
Low
Low
Low
Low
NOTES:
1.
The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after
PLTRST#.
2.
The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately
after RSMRST#.
3.
In S3HOT, signal states are platform implementation specific, as some external components
and interfaces may be powered when the Intel® ICH7 is in the S3HOT state.
4.
PETp/n[6:1] high until port is enabled by software.
5.
LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3–S5 states
depending upon whether or not the LAN power planes are active.
6.
SLP_S5# signals will be high in the S4 state.
7.
The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled
or low if it is disabled.
8.
ICH7 drives these signals High after the processor Reset.
9.
CPUPWRGD is an output that represents a logical AND of the Intel® ICH7’s VRMPWRGD
and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or
PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD
will be expected to transition from low to High.
10.
IICH7 drives these signals Low before PWROK rising and Low after the processor Reset.
Intel ® ICH7 Family Datasheet
89
Intel® ICH7 Pin States
11.
12.
13.
3.4
Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be
Running.
GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset
GPIO25 transitions from pulled high internally to actively driven within 100 ms of the
deassertion of the RSMRST# pin.
Power Planes for Input Signals
Table 3-5 and Table 3-6 show the power plane associated with each input signal, as
well as what device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
ICH7 suspend well signal states are indeterminate and undefined and may glitch prior
to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and
SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion.
ICH7 core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are
determinate and defined prior to PWROK assertion.
Table 3-5.
Power Plane for Input Signals for Desktop Only Configurations (Sheet 1 of 3)
Signal Name
Power Well
Driver During Reset
S1
S3COLD1
S4/S5
A20GATE
Core
External
Microcontroller
Static
Low
Low
ACZ_BIT_CLK
(AC ‘97 Mode)
Core
AC ’97 Codec
Low
Low
Low
ACZ_SDIN[2:0] (AC ‘97
Mode)
Suspend
AC ’97 Codec
Low
Low
Low
ACZ_SDIN[2:0] (Intel®
High Definition Audio
Mode)
Suspend
Intel® High Definition
Audio Codec
Low
Low
Low
CLK14
Core
Clock Generator
Running
Low
Low
CLK48
Core
Clock Generator
Running
Low
Low
DDREQ
Core
IDE Device
Static
Low
Low
DMI_CLKP, DMI_CLKN
Core
Clock Generator
Running
Low
Low
EE_DIN
Suspend
EEPROM Component
Driven
Driven
Driven
FERR#
Core
Processor
Static
Low
Low
Core
PCI Express* Device
Driven
Driven
Driven
DMI[3:0]RXP,
DMI[3:0]RXN
Core
(G)MCH
Driven
Low
Low
IDEIRQ
Core
IDE
Static
Low
Low
INTRUDER#
RTC
External Switch
Driven
Driven
Driven
PERp[4:1], PERn[4:1]
PERp[6:5], PERn[6:5]
(Intel® ICH7R and
ICH7DH Only)
90
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
Table 3-5.
Power Plane for Input Signals for Desktop Only Configurations (Sheet 2 of 3)
Signal Name
Power Well
Driver During Reset
S1
S3COLD1
S4/S5
INTVRMEN
RTC
External Pull-up or
Pull-down
Driven
Driven
Driven
IORDY
Core
IDE Device
Static
Low
Low
LAN_CLK
Suspend
LAN Connect
Component
Driven
Driven
Driven
LAN_RST#
Suspend
External RC Circuit
High
High
High
LAN_RXD[2:0]
Suspend
LAN Connect
Component
Driven
Driven
Driven
LDRQ0#
Core
LPC Devices
High
Low
Low
LDRQ1# / GPIO232
Core
LPC Devices
High
Low
Low
MCH_SYNC#
Core
(G)MCH
Driven
Low
Low
OC[7:0]#
Suspend
External Pull-ups
Driven
Driven
Driven
PCICLK
Core
Clock Generator
Running
Low
Low
PME#
Suspend
Internal Pull-up
Driven
Driven
Driven
PWRBTN#
Suspend
Internal Pull-up
Driven
Driven
Driven
PWROK
RTC
System Power Supply
Driven
Low
Low
RCIN#
Core
External
Microcontroller
High
Low
Low
REQ[3:0]#,
REQ4# / GPIO222
REQ5# / GPIO122
Core
PCI Master
Driven
Low
Low
RI#
Suspend
Serial Port Buffer
Driven
Driven
Driven
RSMRST#
RTC
External RC Circuit
High
High
High
RTCRST#
RTC
External RC Circuit
High
High
High
SATA_CLKP, SATA_CLKN
Core
Clock Generator
Running
Low
Low
SATA[3:0]RXP,
SATA[3:0]RXN
Core
SATA Drive
Driven
Driven
Driven
SATARBIAS#
Core
External Pull-down
Driven
Driven
Driven
SATA[3:0]GP /
GPIO[31:29,26]2
Core
External Device or
External Pull-up/Pulldown
Driven
Driven
Driven
Core
PCI Bus Peripherals
High
Low
Low
SERR#
SMBALERT# / GPIO11
2
Suspend
External Pull-up
Driven
Driven
Driven
SYS_RESET#
Suspend
External Circuit
Driven
Driven
Driven
THRM#
Core
Thermal Sensor
Driven
Low
Low
THRMTRIP#
Core
Thermal Sensor
Driven
Low
Low
TP0
Suspend
External Pull-up
High
High
High
TP3
Suspend
Internal Pull-up
High
High
High
USBRBIAS#
Suspend
External Pull-down
Driven
Driven
Driven
Core
Processor Voltage
Regulator
High
Low
Low
VRMPWRGD
Intel ® ICH7 Family Datasheet
91
Intel® ICH7 Pin States
Table 3-5.
Power Plane for Input Signals for Desktop Only Configurations (Sheet 3 of 3)
Signal Name
Power Well
Driver During Reset
S1
S3COLD1
S4/S5
WAKE#
Suspend
External Pull-up
Driven
Driven
Driven
SPI_MISO
Suspend
External Pull-up
Driven
Driven
Driven
SPI_ARB
Suspend
Internal Pull-down
Low
Low
Low
NOTES:
1.
In S3HOT, signal states are platform implementation specific, as some external components
and interfaces may be powered when the ICH7 is in the S3HOT state.
2.
These signals can be configured as outputs in GPIO mode.
Table 3-6.
Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations
(Sheet 1 of 3)
Signal Name
Power
Well
Driver During Reset
C3/C4
S1
S3COLD1
S4/S5
A20GATE
Core
External
Microcontroller
Static
Static
Low
Low
ACZ_BIT_CLK
(AC ‘97 mode)
(Mobile Only)
Core
AC ’97 Codec
Driven
Low
Low
Low
ACZ_SDIN[2:0]
(AC ‘97 mode)
(Mobile Only)
Suspend
AC ’97 Codec
Driven
Low
Low
Low
Suspend
Intel® High Definition
Audio Codec
Driven
Low
Low
Low
BM_BUSY# /
GPIO01
Core
Graphics Component
[(G)MCH]
Driven
High
Low
Low
BATLOW#
Suspend
Power Supply
High
High
High
High
CLK14
Core
Clock Generator
Running
Running
Low
Low
CLK48
Core
Clock Generator
Running
Running
Low
Low
DDREQ
Core
IDE Device
Driven
Static
Low
Low
Core
Clock Generator
Running
Running
Low
Low
EE_DIN
(Mobile Only)
LAN
EEPROM Component
Driven
Driven
Note 2
Note 2
FERR#
Core
Processor
Static
Static
Low
Low
PERp[6:1],
PERn[6:1]
(Mobile Only)
Core
PCI Express* Device
Driven
Driven
Driven
Driven
Core
(G)MCH
Driven
Driven
Low
Low
IDEIRQ
Core
IDE
Driven
Static
Low
Low
INTRUDER#
RTC
External Switch
Driven
Driven
Driven
Driven
INTVRMEN
(Mobile Only)
RTC
External Pull-up or Pulldown
Driven
Driven
Driven
Driven
ACZ_SDIN[2:0]
(Intel® High
Definition Audio
Mode)
DMI_CLKP
DMI_CLKN
DMI[3:0]RXP,
DMI[3:0]RXN
92
Intel ® ICH7 Family Datasheet
Intel® ICH7 Pin States
Table 3-6.
Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations
(Sheet 2 of 3)
Signal Name
Power
Well
Driver During Reset
C3/C4
S1
S3COLD1
S4/S5
IORDY
Core
IDE Device
Static
Static
Low
Low
LAN_CLK
(Mobile Only)
LAN
LAN Connect
Component
Driven
Driven
Note 2
Note 2
LAN_RST#
(Mobile Only)
Suspend
Power Supply
High
High
Static
Static
LAN_RXD[2:0]
(Mobile Only)
LAN
LAN Connect
Component
Driven
Driven
Note 2
Note 2
LDRQ0#
Core
LPC Devices
Driven
High
Low
Low
LDRQ1# /
GPIO233
Core
LPC Devices
Driven
High
Low
Low
MCH_SYNC#
Core
(G)MCH
Driven
Driven
Low
Low
OC[7:0]#
Suspend
External Pull-ups
Driven
Driven
Driven
Driven
PCICLK
Core
Clock Generator
Running
Running
Low
Low
PME#
Suspend
Internal Pull-up
Driven
Driven
Driven
Driven
PWRBTN#
Suspend
Internal Pull-up
Driven
Driven
Driven
Driven
PWROK
RTC
System Power Supply
Driven
Driven
Low
Low
Core
External
Microcontroller
High
High
Low
Low
Core
PCI Master
Driven
Driven
Low
Low
RI#
Suspend
Serial Port Buffer
Driven
Driven
Driven
Driven
RSMRST#
RTC
External RC Circuit
High
High
High
High
RTCRST#
RTC
External RC Circuit
High
High
High
High
SATA_CLKP,
SATA_CLKN
(Mobile Only)
Core
Clock Generator
Running
Running
Low
Low
Core
SATA Drive
Driven
Driven
Driven
Driven
SATARBIAS#
(Mobile Only)
Core
External Pull-Down
Driven
Driven
Driven
Driven
SATA[2,0]GP
(Mobile Only)
Core
External Device or
External Pull-up/Pulldown
Driven
Driven
Driven
Driven
RCIN#
REQ[3:0]#,
REQ4# / GPIO223
REQ5# / GPIO13
SATA[0]RXP,
SATA[0]RXN
SATA[2]RXP,
SATA[2]RXN
(Mobile Only)
SERR#
Core
PCI Bus Peripherals
Driven
High
Low
Low
SMBALERT# /
GPIO113
Suspend
External Pull-up
Driven
Driven
Driven
Driven
SYS_RESET#
Suspend
External Circuit
Driven
Driven
Driven
Driven
THRM#
Core
Thermal Sensor
Driven
Driven
Low
Low
Intel ® ICH7 Family Datasheet
93
Intel® ICH7 Pin States
Table 3-6.
Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations
(Sheet 3 of 3)
Signal Name
Power
Well
Driver During Reset
C3/C4
S1
S3COLD1
S4/S5
THRMTRIP#
Core
Thermal Sensor
Driven
Driven
Low
Low
TP3
Suspend
Internal Pull-up
High
High
High
High
USBRBIAS#
Suspend
External Pull-down
Driven
Driven
Driven
Driven
VRMPWRGD
Core
Processor Voltage
Regulator
Driven
Driven
Low
Low
WAKE#
Suspend
External Pull-up
Driven
Driven
Driven
Driven
SPI_MISO
(Mobile Only)
Suspend
External Pull-up
Driven
Driven
Driven
Driven
SPI_ARB
(Mobile Only)
Suspend
Internal Pull-down
Low
Low
Low
Low
NOTES:
1.
In S3HOT, signal states are platform implementation specific, as some external components
and interfaces may be powered when the Intel® ICH7 is in the S3HOT state.
2.
LAN Connect and EEPROM signals will either be “Driven” or “Low” in S3–S5 states
depending upon whether or not the LAN power planes are active.
3.
These signals can be configured as outputs in GPIO mode.
§
94
Intel ® ICH7 Family Datasheet
Intel® ICH7 and System Clock Domains
4
Intel® ICH7 and System Clock
Domains
Table 4-1 shows the system clock domains. Figure 4-1 and Figure 4-2 show the
assumed connection of the various system components, including the clock generator
in desktop and mobile/ultra mobile systems. For complete details of the system
clocking solution, refer to the system’s clock generator component specification.
Table 4-1.
Intel® ICH7 and System Clock Domains
Clock Domain
Frequency
Source
Usage
Intel® ICH7
SATA_CLKP,
SATA_CLKN
(Desktop and
Mobile only)
100 MHz
Main Clock
Generator
Differential clock pair used for SATA.
ICH7
DMI_CLKP,
DMI_CLKN
100 MHz
Main Clock
Generator
Differential clock pair used for DMI.
ICH7
PCICLK
33 MHz
Main Clock
Generator
Free-running PCI Clock to ICH7. This clock
remains on during S0 and S1 (in desktop) state,
and is expected to be shut off during S3 or
below in desktop configurations or S1 or below
in mobile/ultra mobile configurations.
System PCI
33 MHz
Main Clock
Generator
PCI Bus, LPC I/F. These only go to external PCI
and LPC devices. Will stop based on CLKRUN#
(and STP_PCI#) in mobile/ultra mobile
configurations.
ICH7
CLK48
48.000 MHz
Main Clock
Generator
Super I/O, USB controllers. Expected to be shut
off during S3 or below in desktop configurations
or S1 or below in mobile/ultra mobile
configurations.
ICH7
CLK14
14.31818
MHz
Main Clock
Generator
Used for ACPI timer and Multimedia Timers.
Expected to be shut off during S3 or below in
desktop configurations or S1 or below in mobile/
ultra mobile configurations.
12.288 MHz
AC ’97 Codec
AC-link. Generated by AC ’97 Codec. Can be
shut by codec in D3. Expected to be shut off
during S3 or below in desktop configurations or
S1 or below in mobile configurations.
NOTE: For use only in AC ‘97 mode.
5 to 50 MHz
LAN Connect
Component
Generated by the LAN Connect component.
Expected to be shut off during S3 or below in
desktop configurations or S1 or below in mobile
configurations.
ICH
Generated by the LAN Connect component.
Expected to be shut off during S3 or below in
desktop configurations or S1 or below in mobile
configurations.
ICH7
ACZ_BIT_CLK
(Desktop and
Mobile only)
LAN_CLK
(Desktop and
Mobile only)
SPI_CLK
(Desktop and
Mobile Only)
Intel ® ICH7 Family Datasheet
17.86 MHz
95
Intel® ICH7 and System Clock Domains
Figure 4-1.
Desktop Only Conceptual System Clock Diagram
PCI
Clocks
(33 MHz)
33 MHz
Clock
Gen.
14.31818 MHz
48.000 MHz
48.000 MHz
Intel ®
ICH7
100 MHz
Diff.Pair
SATA 100 MHzDiff. Pair
DMI 100 MHz Diff. Pair
50 MHz
24 MHz
Figure 4-2.
PCI Express
100 MHz
Diff. Pairs
1 to 6
Differential
ClockFan
OutDev ice
LAN Connect
12.288 MHz
32 kHz
XTAL
14.31818 MHz
AC ’97 Codec(s)
HighDefinitionAudioCodec(s)
SUSCLK# (32 kHz)
Mobile Only Conceptual Clock Diagram
33 MHz
14.31818 MHz
48.000 MHz
Intel®
PCI Clocks
(33 MHz)
Clock
Gen.
STP_CPU#
14.31818 MHz
STP_PCI#
48 MHz
ICH7-M
100 MHz Diff. Pair
SATA 100 MHz Diff. Pair
DMI 100 MHz Diff. Pair
50 MHz
12.288 MHz
32 kHz
XTAL
24 MHz
PCI Express
100 MHz
Diff. Pairs
1 to 6
Differential
Clock Fan
Out Device
LAN Connect
AC ’97 Codec(s)
High Definition Audio Codec(s)
SUSCLK# (32 kHz)
§
96
Intel ® ICH7 Family Datasheet
Intel® ICH7 and System Clock Domains
Figure 4-3.
Ultra Mobile Only Conceptual Clock Diagram
33 MHz
PCI Clocks
(33 MHz)
14.31818 MHz
Clock
Generator
48.000 MHz
STP_CPU#
Intel®
ICH7-U
14.31818 MHz
48 MHz
STP_PCI#
DMI 100 MHz Diff Pair
24 MHz
32 kHz
XTAL
High Definition Audio Codec(s)
SUSCLK# (32 kHz)
§
Intel ® ICH7 Family Datasheet
97
Intel® ICH7 and System Clock Domains
98
Intel ® ICH7 Family Datasheet
Functional Description
5
Functional Description
This chapter describes the functions and interfaces of the ICH7 family.
5.1
PCI-to-PCI Bridge (D30:F0)
The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of
the ICH7 implements the buffering and control logic between PCI and Direct Media
Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI
decoder in this device must decode the ranges for the DMI. All register contents are
lost when core well power is removed.
Direct Media Interface (DMI) is the chip-to-chip connection between the Memory
Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub
7 (ICH7). This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is the highest priority. VC0 is
the default conduit of traffic for DMI and is always enabled. VC1 must be specifically
enabled and configured at both ends of the DMI link (i.e., the ICH7 and (G)MCH).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the Chipset Config Registers
(Section 7).
5.1.1
PCI Bus Interface
The ICH7 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.
The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters in
addition to the internal ICH7 requests.
5.1.2
PCI Bridge As an Initiator
The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge
generates the following cycle types:
Table 5-1.
PCI Bridge Initiator Cycle Types
Command
5.1.2.1
C/BE#
Notes
I/O Read/Write
2h/3h
Non-posted
Memory Read/Write
6h/7h
Writes are posted
Configuration Read/Write
Ah/Bh
Non-posted
Special Cycles
1h
Posted
Memory Reads and Writes
The bridge bursts memory writes on PCI that are received as a single packet from DMI.
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Functional Description
5.1.2.2
I/O Reads and Writes
The bridge generates single DW I/O read and write cycles. When the cycle completes
on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is
retried, the cycle is kept in the down bound queue and may be passed by a postable
cycle.
5.1.2.3
Configuration Reads and Writes
The bridge generates single DW configuration read and write cycles. When the cycle
completes on the PCI bus, the bridge generates a corresponding completion. If the
cycle is retried, the cycle is kept in the down bound queue and may be passed by a
postable cycle.
5.1.2.4
Locked Cycles
The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI
bridge implements bus lock, which means the arbiter will not grant to any agent except
DMI while locked.
If a locked read results in a target or master abort, the lock is not established (as per
the PCI Local Bus Specification). Agents north of the ICH7 must not forward a
subsequent locked read to the bridge if they see the first one finish with a failed
completion.
5.1.2.5
Target / Master Aborts
When a cycle initiated by the bridge is master/target aborted, the bridge will not reattempt the same cycle. For multiple DW cycles, the bridge increments the address and
attempts the next DW of the transaction. For all non-postable cycles, a target abort
response packet is returned for each DW that was master or target aborted on PCI. The
bridge drops posted writes that abort.
5.1.2.6
Secondary Master Latency Timer
The bridge implements a Master Latency Timer via the SLT register which, upon
expiration, causes the de-assertion of FRAME# at the next legal clock edge when there
is another active request to use the PCI bus.
5.1.2.7
Dual Address Cycle (DAC)
The bridge will issue full 64-bit dual address cycles for device memory-mapped
registers above 4 GB.
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Functional Description
5.1.2.8
Memory and I/O Decode to PCI
The PCI bridge in the ICH7 is a subtractive decode agent, which follows the following
rules when forwarding a cycle from DMI to the PCI interface:
• The PCI bridge will positively decode any memory/IO address within its window
registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory
windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows.
• The PCI bridge will subtractively decode any 64-bit memory address not claimed
by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.
• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by
another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) set
• If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively
forward from primary to secondary called out ranges in the IO window per PCI
Local Bus Specification (I/O transactions addressing the last 768 bytes in each,
1-KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively
assuming the above rules.
• If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively
forward from primary to secondary I/O and memory ranges as called out in the PCI
Bridge Specification, assuming the above rules are met.
5.1.3
Parity Error Detection and Generation
PCI parity errors can be detected and reported. The following behavioral rules apply:
• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE
(D30:F0:Offset 1Eh:bit 15).
• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) and one of the
parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD
(D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#.
— During a write cycle, the PERR# signal is active, or
— A data parity error is detected while performing a read cycle
• If an address or command parity error is detected on PCI and PCICMD.SEE
(D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1)
are all set, the bridge will set the PSTS.SSE (D30:F0:Offset 06h:bit 14) and
generate an internal SERR#.
• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is
set, the bridge will generate an internal SERR#
• When bad parity is detected from DMI, bad parity will be driven on all data the
bridge.
• When an address parity error is detected on PCI, the PCI bridge will not claim the
cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle
should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept
of address parity error, so claiming the cycle could result in the rest of the system
seeing a bad transaction as a good transaction.
5.1.4
PCIRST#
The PCIRST# pin is generated under two conditions:
• PLTRST# active
• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1
The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but
not other agents in the system.
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Functional Description
5.1.5
Peer Cycles
The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and
configuration cycle types. Peer cycles are only allowed through VC0, and are enabled
with the following bits:
• BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and IO cycles
• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles
When enabled for peer for one of the above cycle types, the PCI bridge will perform a
peer decode to see if a peer agent can receive the cycle. When not enabled, memory
cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles
are not claimed.
Configuration cycles have special considerations. Under the PCI Local Bus Specification,
these cycles are not allowed to be forwarded upstream through a bridge. However, to
enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are
allowed into the part. The address format of the type 1 cycle is slightly different from a
standard PCI configuration cycle to allow addressing of extended PCI space. The format
is as follows:
Table 5-2.
Type 1 Address Format
Bits
Definition
31:27
Reserved (same as the PCI Local Bus Specification)
26:24
Extended Configuration Address – allows addressing of up to 4K. These
bits are combined with bits 7:2 to get the full register.
23:16
Bus Number (same as the PCI Local Bus Specification)
15:11
Device Number (same as the PCI Local Bus Specification)
10:8
Function Number (same as the PCI Local Bus Specification)
7:2
Register (same as the PCI Local Bus Specification)
1
0
0
Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.
Note:
The ICH7’s AC ’97, IDE and USB controllers cannot perform peer-to-peer traffic.
5.1.6
PCI-to-PCI Bridge Model
From a software perspective, the ICH7 contains a PCI-to-PCI bridge. This bridge
connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH7
can have its decode ranges programmed by existing plug-and-play software such that
PCI ranges do not conflict with graphics aperture ranges in the Host controller.
Note:
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All downstream devices should be disabled before reconfiguring the PCI Bridge. Failure
to do so may cause undefined results.
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Functional Description
5.1.7
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH7 asserts
one address signal as an IDSEL. When accessing device 0, the ICH7 asserts AD16.
When accessing Device 1, the ICH7 asserts AD17. This mapping continues all the way
up to device 15 where the ICH7 asserts AD31. Note that the ICH7’s internal functions
(AC ’97 on Desktop/Mobile, Intel High Definition Audio, IDE, USB, SATA on Desktop/
Mobile and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI)
from the external PCI bus. The integrated LAN controller (Desktop and Mobile Only) is
Device 8 on the ICH7’s PCI bus, and hence it uses AD24 for IDSEL.
5.1.8
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus
cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration
space is supported by a mapping mechanism implemented within the ICH7. The PCI
Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration
space, Mechanism 1 and Mechanism 2. The ICH7 only supports Mechanism 1.
Warning:
Configuration writes to internal devices, when the devices are disabled, are invalid and
may cause undefined results.
5.2
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)
(Desktop and Mobile Only)
There are four root ports available in ICH7, with select ICH7 components (ICH7R,
ICH7DH, and ICH7-M DH) having six root ports adding port 5 and port 6 (see
Section 1.2). These all reside in device 28, and take function 0 – 5. Port 1 is function 0,
port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, and
port 6 is function 5.
Optionally, PCI Express ports 1-4 can be configured as a single one x4 port identified as
port 1. This is accomplished by placing external pull-up resistors on ACZ_SDOUT and
ACZ_SYNC. When these signals are sampled high on PWROK assertion, this will be
registered in the Port Configuration field of the Root Port Configuration Register and the
corresponding ports will be configured as one x4 port.
5.2.1
Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated via the legacy pin, the pin is internally routed to the
ICH7 interrupt controllers. The pin that is driven is based upon the setting of the
chipset configuration registers. Specifically, the chipset configuration registers used are
the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
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Functional Description
Table 5-3.
MSI vs. PCI IRQ Actions
WireMode Action
MSI Action
Wire inactive
No action
One or more bits set to 1
Wire active
Send
message
One or more bits set to 1, new bit gets set to 1
Wire active
Send
message
One or more bits set to 1, software clears some (but not all)
bits
Wire active
Send
message
Wire inactive
No action
Wire active
Send
message
Interrupt Register
All bits 0
One or more bits set to 1, software clears all bits
Software clears one or more bits, and one or more bits are
set on the same clock
5.2.2
Power Management
5.2.2.1
S3/S4/S5 Support
Software initiates the transition to S3/S4/S5 by performing an IO write to the Power
Management Control register in the ICH7. After the IO write completion has been
returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction
Layer Packet) message on it's downstream link. The device attached to the link will
eventually respond with a PME_TO_Ack TLP message followed by sending a
PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.
When all of the ICH7 root ports links are in the L2/L3 Ready state, the ICH7 power
management control logic will proceed with the entry into S3/S4/S5.
Prior to entering S3, software is required to put each device into D3HOT. When a device
is put into D3HOT, it will initiate entry into a L1 link state by sending a PM_Enter_L1
DLLP. Thus, under normal operating conditions when the root ports sends the
PME_Turn_Off message, the link will be in state L1. However, when the root port is
instructed to send the PME_Turn_Off message, it will send it whether or not the link
was in L1. Endpoints attached to the ICH7 can make no assumptions about the state of
the link prior to receiving a PME_Turn_Off message.
5.2.2.2
Resuming from Suspended State
The root port contains enough circuitry in the resume well to detect a wake event thru
the WAKE# signal and to wake the system. When WAKE# is detected asserted, an
internal signal is sent to the power management controller of the ICH7 to cause the
system to wake up. This internal message is not logged in any register, nor is an
interrupt/GPE generated due to it.
5.2.2.3
Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a
device requesting service will send a PM_PME message continuously, until acknowledge
by the root port. The root port will take different actions depending upon whether this
is the first PM_PME has been received, or whether a previous message has been
received but not yet serviced by the operating system.
If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit
16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into
RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via
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Functional Description
RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated.
This interrupt can be either a pin or a MSI if MSI is enabled via MC.MSIE (D28:F0/F1/
F2/F3/F4/F5:Offset 82h:bit 0). See Section 5.2.2.4 for SMI/SCI generation.
If this is a subsequent message received (RSTS.PS is already set), the root port will set
RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID
from the message in a hidden register. No other action will be taken.
When the first PME event is cleared by software clearing RSTS.PS, the root port will set
RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into
RSTS.RID.
If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power
management controller so that a GPE can be set. If messages have been logged
(RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be
generated. This last condition handles the case where the message was received prior
to the operating system re-enabling interrupts after resuming from a low power state.
5.2.2.4
SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating
systems. To support power management on non-PCI Express aware operating systems,
PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.
When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/
F5:Offset DCh:bit 31) to be set.
Additionally, BIOS workarounds for power management can be supported by setting
MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power
management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0),
and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI
is enabled. The SMI# may occur concurrently with an interrupt or SCI.
5.2.3
SERR# Generation
SERR# may be generated via two paths – through PCI mechanisms involving bits in the
PCI header, or through PCI Express mechanisms involving bits in the PCI Express
capability structure.
Figure 5-1.
Generation of SERR# to Platform
Secondary Parity Error
PCI
PSTS.SSE
Primary Parity Error
Secondary SERR#
PCICMD.SEE
SERR#
Correctable SERR#
PCI Express
Fatal SERR#
Non-Fatal SERR#
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Functional Description
5.2.4
Hot-Plug
Each root port implements a Hot-Plug controller which performs the following:
• Messages to turn on / off / blink LEDs
• Presence and attention button detection
• Interrupt generation
The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Edge-connector
based Hot-Plug is not supported.
5.2.4.1
Presence Detection
When a module is plugged in and power is supplied, the physical layer will detect the
presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/
F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE
(D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3F4/
F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt.
When a module is removed (via the physical layer detection), the root port clears
SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root
port will also generate an interrupt.
5.2.4.2
Message Generation
When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits
7:6) or SLCTL.PIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 9:8), the root port will send
a message down the link to change the state of LEDs on the module.
Writes to these fields are non-postable cycles, and the resulting message is a postable
cycle. When receiving one of these writes, the root port performs the following:
• Changes the state in the register.
• Generates a completion into the upstream queue
• Formulates a message for the downstream port if the field is written to regardless
of if the field changed.
• Generates the message on the downstream port
• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/
F2/F3F4/F5:Offset 58h:bit 4) to indicate the command has completed. If
SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 5) are set, the
root port generates an interrupt.
The command completed register (SLSTS.CC) applies only to commands issued by
software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),
or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control
Register would invariably end up writing to the indicators, power controller fields;
Hence, any write to the Slot Control Register is considered a command and if enabled,
will result in a command complete interrupt. The only exception to this rule is a write to
disable the command complete interrupt which will not result in a command complete
interrupt.
A single write to the Slot Control register is considered to be a single command, and
hence receives a single command complete, even if the write affects more than one
field in the Slot Control Register.
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Functional Description
5.2.4.3
Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user.
This attention button press will result in a the PCI Express message
“Attention_Button_Pressed” from the device. Upon receiving this message, the root
port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/
F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an
interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is
already set, a new interrupt will not be generated.
5.2.4.4
SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To
support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be
routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset
D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS
(D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set.
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME
(D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can
cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their
corresponding SMSCS bit are:
• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3)
• Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
1)
• Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
2)
• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
4)
When any of these bits are set, SMI # will be generated. These bits are set regardless
of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur
concurrently with an interrupt or SCI.
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Functional Description
5.3
LAN Controller (B1:D8:F0) (Desktop and Mobile
Only)
The ICH7’s integrated LAN controller includes a 32-bit PCI controller that provides
enhanced scatter-gather bus mastering capabilities and enables the LAN controller to
perform high-speed data transfers over the PCI bus. Its bus master capabilities enable
the component to process high level commands and perform multiple operations; this
lowers processor utilization by off-loading communication tasks from the processor.
Two large transmit and receive FIFOs of 3 KB each, help prevent data underruns and
overruns while waiting for bus accesses. This enables the integrated LAN controller to
transmit data with minimum interframe spacing (IFS).
The ICH7 integrated LAN controller can operate in either full-duplex or half-duplex
mode. In full- duplex mode the LAN controller adheres with the IEEE 802.3x Flow
Control Specification. Half duplex performance is enhanced by a proprietary collision
reduction mechanism.
The integrated LAN controller also includes an interface to a serial (4-pin) EEPROM. The
EEPROM provides power-on initialization for hardware and software configuration
parameters.
From a software perspective, the integrated LAN controller appears to reside on the
secondary side of the ICH7’s virtual PCI-to-PCI bridge (see Section 5.1.6). This is
typically Bus 1, but may be assigned a different number, depending upon system
configuration.
The following summarizes the ICH7 LAN controller features:
• Compliance with Advanced Configuration and Power Interface and PCI Power
Management standards
• Support for wake-up on interesting packets and link status change
• Support for remote power-up using Wake on LAN* (WOL) technology
• Deep power-down mode support
• Backward compatible software with 82550, 82557, 82558 and 82559
• TCP/UDP checksum off load capabilities
• Support for Intel’s Adaptive Technology
5.3.1
LAN Controller PCI Bus Interface
As a Fast Ethernet controller, the role of the ICH7 integrated LAN controller is to access
transmitted data or deposit received data. The LAN controller, as a bus master device,
initiates memory cycles via the PCI bus to fetch or deposit the required data.
To perform these actions, the LAN controller is controlled and examined by the
processor via its control and status structures and registers. Some of these control and
status structures reside in the LAN controller and some reside in system memory. For
access to the LAN controller’s Control/Status Registers (CSR), the LAN controller acts
as a slave (in other words, a target device). The LAN controller serves as a slave also
while the processor accesses the EEPROM.
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Functional Description
5.3.1.1
Bus Slave Operation
The ICH7 integrated LAN controller serves as a target device in one of the following
cases:
• Processor accesses to the LAN controller System Control Block (SCB) Control/
Status Registers (CSR)
• Processor accesses to the EEPROM through its CSR
• Processor accesses to the LAN controller PORT address via the CSR
• Processor accesses to the MDI control register in the CSR
The size of the CSR memory space is 4 Kbyte in the memory space and 64 bytes in the
I/O space. The LAN controller treats accesses to these memory spaces differently.
Control/Status Register (CSR) Accesses
The integrated LAN controller supports zero wait-state single cycle memory or I/O
mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and
64 bytes of I/O space to accomplish this. Based on its needs, the software driver uses
either memory or I/O mapping to access these registers. The LAN controller provides
four valid KB of CSR space that include the following elements:
• System Control Block (SCB) registers
• PORT register
• EEPROM control register
• MDI control register
• Flow control registers
In the case of accessing the Control/Status Registers, the processor is the initiator and
the LAN controller is the target.
Retry Premature Accesses
The LAN controller responds with a Retry to any configuration cycle accessing the LAN
controller before the completion of the automatic read of the EEPROM. The LAN
controller may continue to Retry any configuration accesses until the EEPROM read is
complete. The LAN controller does not enforce the rule that the retried master must
attempt to access the same address again in order to complete any delayed
transaction. Any master access to the LAN controller after the completion of the
EEPROM read is honored.
Error Handling
Data Parity Errors: The LAN controller checks for data parity errors while it is the
target of the transaction. If an error was detected, the LAN controller sets the Detected
Parity Error bit in the PCI Configuration Status register, bit 15. The LAN controller also
asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command
register, bit 6). The LAN controller does not attempt to terminate a cycle in which a
parity error was detected. This gives the initiator the option of recovery.
Target-Disconnect: The LAN controller prematurely terminate a cycle in the following
cases:
• After accesses to its CSR
• After accesses to the configuration space
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Functional Description
System Error: The LAN controller reports parity error during the address phase using
the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or
the Parity Error Response bit are not set, the LAN controller only sets the Detected
Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity
Error Response bits are both set, the LAN controller sets the Signaled System Error bit
(PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and
asserts SERR# for one clock.
The LAN controller, when detecting system error, claims the cycle if it was the target of
the transaction and continues the transaction as if the address was correct.
Note:
The LAN controller reports a system error for any error during an address phase,
whether or not it is involved in the current transaction.
5.3.1.2
CLKRUN# Signal (Mobile Only)
The Intel® ICH7 receives a free-running 33 MHz clock. It does not stop based on the
CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the
ICH7 makes sure that the STP_PCI# signal is high indicating that the PCI clock will be
running. This is to make sure that any PCI tracker does not get confused by
transactions on the PCI bus with its PCI clock stopped.
5.3.1.3
PCI Power Management
Enhanced support for the power management standard, PCI Local Bus Specification,
Revision 2.3, is provided in the ICH7 integrated LAN controller. The LAN controller
supports a large set of wake-up packets and the capability to wake the system from a
low power state on a link status change. The LAN controller enables the host system to
be in a sleep state and remain virtually connected to the network.
After a power management event or link status change is detected, the LAN controller
wakes the host system. The following sections describe these events, the LAN
controller power states, and estimated power consumption at each power state.
The LAN controller contains power management registers for PCI, and implements four
power states, D0 through D3, which vary from maximum power consumption at D0 to
the minimum power consumption at D3. PCI transactions are only allowed in the D0
state, except for host accesses to the LAN controller’s PCI configuration registers. The
D1 and D2 power management states enable intermediate power savings while
providing the system wake-up capabilities. In the D3COLD state, the LAN controller can
provide wake-up capabilities. Wake-up indications from the LAN controller are provided
by the Power Management Event (PME#) signal.
5.3.1.4
PCI Reset Signal
The PCIRST# signal may be activated in one of the following cases:
• During S3–S5 states
• Due to a CF9h reset
If PME is enabled (in the PCI power management registers), PCIRST# assertion does
not affect any PME related circuits (in other words, PCI power management registers
and the wake-up packet would not be affected). While PCIRST# is active, the LAN
controller ignores other PCI signals. The configuration of the LAN controller registers
associated with ACPI wake events is not affected by PCIRST#.
The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication
to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN controller
PCI Configuration Space, MAC configuration, and memory structure are initialized while
preserving the PME# signal and its context.
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Functional Description
5.3.1.5
Wake-Up Events
There are two types of wake-up events: “Interesting” Packets and Link Status Change.
These two events are detailed below.
Note:
If the Wake on LAN bit in the EEPROM is not set, wake-up events are supported only if
the PME Enable bit in the Power Management Control/Status Register (PMCSR) is set.
However, if the Wake on LAN bit in the EEPROM is set, and Wake on Magic Packet* or
Wake on Link Status Change are enabled, the Power Management Enable bit is ignored
with respect to these events. In the latter case, PME# would be asserted by these
events.
“Interesting” Packet Event
In the power-down state, the LAN controller is capable of recognizing “interesting”
packets. The LAN controller supports predefined and programmable packets that can
be defined as any of the following:
• ARP Packets (with Multiple IP addresses)
• Direct Packets (with or without type qualification)
• Magic Packet
• Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)
• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
• Internetwork Package Exchange* (IPX) Diagnostic Packet
This allows the LAN controller to handle various packet types. In general, the LAN
controller supports programmable filtering of any packet in the first 128 bytes.
When the LAN controller is in one of the low power states, it searches for a predefined
pattern in the first 128 bytes of the incoming packets. The only exception is the Magic
Packet, which is scanned for the entire frame. The LAN controller classifies the
incoming packets as one of the following categories:
• No Match: The LAN controller discards the packet and continues to process the
incoming packets.
• TCO Packet: The LAN controller implements perfect filtering of TCO packets. After
a TCO packet is processed, the LAN controller is ready for the next incoming
packet. TCO packets are treated as any other wake-up packet and may assert the
PME# signal if configured to do so.
• Wake-up Packet: The LAN controller is capable of recognizing and storing the first
128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its
tail is discarded by the LAN controller. After the system is fully powered-up,
software has the ability to determine the cause of the wake-up event via the PMDR
and dump the stored data to the host memory.
Magic Packets are an exception. The Magic Packets may cause a power
management event and set an indication bit in the PMDR; however, it is not stored
by the LAN controller for use by the system when it is woken up.
Link Status Change Event
The LAN controller link status indication circuit is capable of issuing a PME on a link
status change from a valid link to an invalid link condition or vice versa. The LAN
controller reports a PME link status event in all power states. If the Wake on LAN bit in
the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR
and the CSMA Configure command.
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5.3.1.6
Wake on LAN* (Preboot Wake-Up)
The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the
EEPROM is set. At this point, the LAN controller is in the D0u state. When the LAN
controller is in Wake on LAN mode:
• The LAN controller scans incoming packets for a Magic Packet and asserts the
PME# signal for 52 ms when a 1 is detected in Wake on LAN mode.
• The Activity LED changes its functionality to indicates that the received frame
passed Individual Address (IA) filtering or broadcast filtering.
• The PCI Configuration registers are accessible to the host.
The LAN controller switches from Wake on LAN mode to the D0a power state following
a setup of the Memory or I/O Base Address Registers in the PCI configuration space.
5.3.2
Serial EEPROM Interface
The serial EEPROM stores configuration data for the ICH7 integrated LAN controller and
is a serial in/serial out device. The LAN controller supports a 64-register or 256-register
size EEPROM and automatically detects the EEPROM’s size. The EEPROM should operate
at a frequency of at least 1 MHz.
All accesses, either read or write, are preceded by a command instruction to the
device. The address field is six bits for a 64-register EEPROM or eight bits for a 256register EEPROM. The end of the address field is indicated by a dummy 0 bit from the
EEPROM that indicates the entire address field has been transferred to the device. An
EEPROM read instruction waveform is shown in Figure 5-2.
Figure 5-2.
64-Word EEPROM Read Instruction Waveform
EE_SHCLKK
EE_CS
A5
A4
A3
A2
AA10
A0
EE_DIN
READ OP code
D15
D0
EE_DOUT
The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch,
and Dh) of the EEPROM after the deassertion of Reset.
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Functional Description
5.3.3
CSMA/CD Unit
The ICH7 integrated LAN controller CSMA/CD unit implements both the IEEE 802.3
Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all
the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, etc.).
The LAN controller CSMA/CD unit interfaces to the 82562ET/EM/EZ/EX 10/100 Mbps
Ethernet through the ICH7’s LAN Connect interface signals.
5.3.3.1
Full Duplex
When operating in full-duplex mode, the LAN controller can transmit and receive
frames simultaneously. Transmission starts regardless of the state of the internal
receive path. Reception starts when the platform LAN Connect component detects a
valid frame on its receive differential pair. The ICH7 integrated LAN controller also
supports the IEEE 802.3x flow control standard, when in full-duplex mode.
The LAN controller operates in either half-duplex mode or full-duplex mode. For proper
operation, both the LAN controller CSMA/CD module and the discrete platform LAN
Connect component must be set to the same duplex mode. The CSMA duplex mode is
set by the LAN Controller Configure command or forced by automatically tracking the
mode in the platform LAN Connect component. Following reset, the CSMA defaults to
automatically track the platform LAN Connect component duplex mode.
The selection of duplex operation (full or half) and flow control is done in two levels:
MAC and LAN Connect.
5.3.3.2
Flow Control
The LAN controller supports IEEE 802.3x frame-based flow control frames only in both
full duplex and half duplex switched environments. The LAN controller flow control
feature is not intended to be used in shared media environments.
Flow control is optional in full-duplex mode and is selected through software
configuration. There are three modes of flow control that can be selected: frame-based
transmit flow control, frame-based receive flow control, and none.
5.3.3.3
VLAN Support
The LAN controller supports the IEEE 802.1 standard VLAN. All VLAN flows will be
implemented by software. The LAN controller supports the reception of long frames,
specifically frames longer than 1518 bytes, including the CRC, if software sets the Long
Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded.
5.3.4
Media Management Interface
The management interface allows the processor to control the platform LAN Connect
component via a control register in the ICH7 integrated LAN controller. This allows the
software driver to place the platform LAN Connect in specific modes (e.g., full duplex,
loopback, power down, etc.) without the need for specific hardware pins to select the
desired mode. This structure allows the LAN controller to query the platform LAN
Connect component for status of the link. This register is the MDI Control Register and
resides at offset 10h in the LAN controller CSR. The MDI registers reside within the
platform LAN Connect component, and are described in detail in the platform LAN
Connect component’s datasheet. The processor writes commands to this register and
the LAN controller reads or writes the control/status parameters to the platform LAN
Connect component through the MDI register.
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Functional Description
5.3.5
TCO Functionality
The ICH7 integrated LAN controller supports management communication to reduce
Total Cost of Ownership (TCO). The SMBus is used as an interface between the ASF
controller and the integrated TCO host controller. There are two different types of TCO
operation that are supported (only one supported at a time), they are 1) Integrated
ASF Control or 2) external TCO controller support. The SMLink is a dedicated bus
between the LAN controller and the integrated ASF controller (if enabled) or an external
management controller. An EEPROM of 256 words is required to support the heartbeat
command.
5.3.5.1
Advanced TCO Mode
The Advanced TCO functionalities through the SMLink are listed in Table 5-4.
Table 5-4.
Advanced TCO Functionality
Power State
TCO Controller Functionality
Transmit
Set Receive TCO Packets
D0 nominal
Receive TCO Packets
Read Intel® ICH7 status (PM & Link state)
Force TCO Mode
Dx (x>0)
D0 functionality plus:
Read PHY registers
Dx functionality plus:
Force TCO Mode
Configuration commands
Read/Write PHY registers
Note:
For a complete description on various commands, see the Total Cost of Ownership
(TCO) System Management Bus Interface Application Note (AP-430).
Transmit Command during Normal Operation
To serve a transmit request from the TCO controller, the ICH7 LAN controller first
completes the current transmit DMA, sets the TCO request bit in the PMDR register (see
Section 8.2), and then responds to the TCO controller’s transmit request. Following the
completion of the TCO transmit DMA, the LAN controller increments the Transmit TCO
statistic counter (described in Section 8.2.14). Following the completion of the transmit
operation, the ICH7 increments the nominal transmit statistic counters, clears the TCO
request bit in the PMDR register, and resumes its normal transmit flow. The receive flow
is not affected during this entire period of time.
Receive TCO
The ICH7 LAN controller supports receive flow towards the TCO controller. The ICH7
can transfer only TCO packets, or all packets that passed MAC address filtering
according to its configuration and mode of operation as detailed below. While
configured to transfer only TCO packets, it supports Ethernet type II packets with
optional VLAN tagging.
Force TCO Mode: While the ICH7 is in the force TCO mode, it may receive packets
(TCO or all) directly from the TCO controller. Receiving TCO packets and filtering level is
controlled by the set Receive enable command from the TCO controller. Following a
reception of a TCO packet, the ICH7 increments its nominal Receive statistic counters
as well as the Receive TCO counter.
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Functional Description
Dx>0 Power State: While the ICH7 is in a powerdown state, it may receive TCO
packets or all directly to the TCO controller. Receiving TCO packets is enabled by the set
Receive enable command from the TCO controller. Although TCO packet might match
one of the other wake up filters, once it is transferred to the TCO controller, no further
matching is searched for and PME is not issued. While receive to TCO is not enabled, a
TCO packet may cause a PME if configured to do so (setting TCO to 1 in the filter type).
D0 Power State: At D0 power state, the ICH7 may transfer TCO packets to the TCO
controller. At this state, TCO packets are posted first to the host memory, then read by
the ICH7, and then posted back to the TCO controller. After the packet is posted to
TCO, the receive memory structure (that is occupied by the TCO packet) is reclaimed.
Other than providing the necessary receive resources, there is no required device
driver intervention with this process. Eventually, the ICH7 increments the receive TCO
static counter, clears the TCO request bit, and resumes normal control.
Read Intel® ICH7 Status (PM and Link State)
The TCO controller is capable of reading the ICH7 power state and link status. Following
a status change, the ICH7 asserts LINKALERT# and then the TCO can read its new
power state.
Set Force TCO Mode
The TCO controller put the ICH7 into the Force TCO mode. The ICH7 is set back to the
nominal operation following a PCIRST#. Following the transition from nominal mode to
a TCO mode, the ICH7 aborts transmission and reception and loses its memory
structures. The TCO may configure the ICH7 before it starts transmission and reception
if required.
Warning:
The Force TCO is a destructive command. It causes the ICH7 to lose its memory
structures, and during the Force TCO mode the ICH7 ignores any PCI accesses.
Therefore, it is highly recommended to use this command by the TCO controller at
system emergency only.
5.4
Alert Standard Format (ASF) (Desktop and Mobile
Only)
The ASF controller collects information from various components in the system
(including the processor, chipset, BIOS, and sensors on the motherboard) and sends
this information via the LAN controller to a remote server running a management
console. The controller also accepts commands back from the management console
and drives the execution of those commands on the local system.
The ASF controller is responsible for monitoring sensor devices and sending packets
through the LAN controller SMBus (System Management Bus) interface. These ASF
controller alerting capabilities include system health information such as BIOS
messages, POST alerts, operating system failure notifications, and heartbeat signals to
indicate the system is accessible to the server. Also included are environmental
notification (e.g., thermal, voltage and fan alerts) that send proactive warnings that
something is wrong with the hardware. The packets are used as Alert (S.O.S.) packets
or as “heartbeat” status packets. In addition, asset security is provided by messages
(e.g., “cover tamper” and “CPU missing”) that notify of potential system break-ins and
processor or memory theft.
The ASF controller is also responsible for receiving and responding to RMCP (Remote
Management and Control Protocol) packets. RMCP packets are used to perform various
system APM commands (e.g., reset, power-up, power-cycle, and power-down). RMCP
can also be used to ping the system to ensure that it is on the network and running
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Functional Description
correctly and for capability reporting. A major advantage of ASF is that it provides
these services during the time that software is unable to do so (e.g., during a lowpower state, during boot-up, or during an operating system hang) but are not
precluded from running in the working state.
The ASF controller communicates to the system and the LAN controller logic through
the SMBus connections. The first SMBus connects to the host SMBus controller (within
the ICH7) and any SMBus platform sensors. The SMBus host is accessible by the
system software, including software running on the operating system and the BIOS.
Note that the host side bus may require isolation if there are non-auxiliary devices that
can pull down the bus when un-powered. The second SMBus connects to the LAN
controller. This second SMBus is used to provide a transmit/receive network interface.
The stimulus for causing the ASF controller to send packets can be either internal or
external to the ASF controller. External stimuli are link status changes or polling data
from SMBus sensor devices; internal events come from, among others, a set of timers
or an event caused by software.
The ASF controller provides three local configuration protocols via the host SMBus. The
first one is the SMBus ARP interface that is used to identify the SMBus device and allow
dynamic SMBus address assignment. The second protocol is the ASF controller
command set that allows software to manage an ASF controller compliant interface for
retrieving info, sending alerts, and controlling timers.
ICH7 provides an input and an output EEPROM interface. The EEPROM contains the LAN
controller configuration and the ASF controller configuration/packet information.
5.4.1
ASF Management Solution Features/Capabilities
• Alerting
— Transmit SOS packets from S0–S5 states
— System Health Heartbeats
— SOS Hardware Events
- System Boot Failure (Watchdog Expires on boot)
- LAN Link Loss
- Entity Presence (on ASF power-up)
- SMBus Hung
- Maximum of eight Legacy Sensors
- Maximum of 128 ASF Sensor events
— Watchdog Timer for operating system lockup/System Hang/Failure to Boot
— General Push support for BIOS (POST messages)
• Remote Control
— Presence Ping Response
— Configurable Boot Options
— Capabilities Reporting
— Auto-ARP Support
— System Remote Control
- Power-Down
- Power-Up
- Power Cycle
- System Reset
— State-Based Security – Conditional Action on WatchDog Expire
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Functional Description
• ASF Compliance
— Compliant with the Alert Standard Format (ASF) Specification, Version 1.03
- PET Compliant Packets
- RMCP
- Legacy Sensor Polling
- ASF Sensor Polling
- Remote Control Sensor Support
• Advanced Features / Miscellaneous
— SMBus 2.0 compliant
— Optional reset extension logic (for use with a power-on reset)
5.4.2
ASF Hardware Support
ASF requires additional hardware to make a complete solution.
Note:
If an ASF compatible device is externally connected and properly configured, the
internal ICH7 ASF controller will be disabled. The external ASF device will have access
to the SMBus controller.
5.4.2.1
Intel® 82562EM/EX
The 82562EM/EX Ethernet LAN controller is necessary. This LAN controller provides the
means of transmitting and receiving data on the network, as well as adding the
Ethernet CRC to the data from the ASF.
5.4.2.2
EEPROM (256x16, 1 MHz)
To support the ICH7 ASF solution, a larger, 256x16 1 MHz, EEPROM is necessary to
configure defaults on reset and on hard power losses (software un-initiated). The ASF
controller shares this EEPROM with the LAN controller and provides a pass through
interface to achieve this. The ASF controller expects to have exclusive access to words
40h through F7h. The LAN controller can use the other EEPROM words. The ASF
controller will default to safe defaults if the EEPROM is not present or not configured
properly (both cause an invalid CRC).
5.4.2.3
Legacy Sensor SMBus Devices
The ASF controller is capable of monitoring up to eight sensor devices on the main
SMBus. These sensors are expected to be compliant with the Legacy Sensor
Characteristics defined in the Alert Standard Format (ASF) Specification, Version 1.03.
5.4.2.4
Remote Control SMBus Devices
The ASF controller is capable of causing remote control actions to Remote Control
devices via SMBus. These remote control actions include Power-Up, Power-Down,
Power-Cycle, and Reset. The ASF controller supports devices that conform to the Alert
Standard Format (ASF) Specification, Version 1.03, Remote Control Devices.
5.4.2.5
ASF Sensor SMBus Devices
The ASF controller is capable of monitoring up to 128 ASF sensor devices on the main
SMBus. However, ASF is restricted by the number of total events which may reduce the
number of SMBus devices supported. The maximum number of events supported by
ASF is 128. The ASF sensors are expected to operate as defined in the Alert Standard
Format (ASF) Specification, Version 1.03.
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Functional Description
5.4.3
ASF Software Support
ASF requires software support to make a complete solution. The following software is
used as part of the complete solution.
• ASF Configuration driver / application
• Network Driver
• BIOS Support for SMBIOS, SMBus ARP, ACPI
• Sensor Configuration driver / application
Note:
Contact your Intel Field Representative for the Client ASF Software Development Kit
(SDK) that includes additional documentation and a copy of the client ASF software
drivers. Intel also provides an ASF Console SDK to add ASF support to a management
console.
5.5
LPC Bridge (w/ System and Management
Functions) (D31:F0)
Note:
LPC DMA is not supported on the Ultra Mobile component (ICH7-U).
The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. In addition to
the LPC bridge function, D31:F0 contains other functional units including DMA (Desktop
and Mobile only), Interrupt controllers, Timers, Power Management, System
Management, GPIO, and RTC. In this chapter, registers and functions associated with
other functional units (power management, GPIO, USB, IDE, etc.) are described in their
respective sections.
5.5.1
LPC Interface
The ICH7 implements an LPC interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The LPC interface to the ICH7 is shown in Figure 5-3. Note
that the ICH7 implements all of the signals that are shown as optional, but peripherals
are not required to do so.
Figure 5-3.
LPC Interface Diagram
PCI Bus
PCI
CLK
PCI
RST#
PCI
SERIRQ
PCI
PM
E#
LAD[3:0]
Intel®ICH7
LFRAM
E#
LDRQ#
(optional)
118
SUS_STAT#
LPCPD#
(optional)
GPI
LSM
I#
(optional)
LPCDevice
Intel ® ICH7 Family Datasheet
Functional Description
5.5.1.1
LPC Cycle Types
The ICH7 implements the following cycle types as described in Table 5-5
Table 5-5.
LPC Cycle Types Supported
Cycle Type
Comment
®
I/O Read
1 byte only. Intel ICH7 breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
I/O Write
1 byte only. ICH7 breaks up 16- and 32-bit processor cycles into multiple
8-bit transfers.
DMA Read
(Desktop and
Mobile Only)
Can be 1, or 2 bytes
DMA Write
(Desktop and
Mobile Only)
Can be 1, or 2 bytes
Bus Master Read
Can be 1, 2, or 4 bytes. (See Note 1 below)
Bus Master Write
Can be 1, 2, or 4 bytes. (See Note 1 below)
NOTES:
1.
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an
address where A0=0). A dword transfer must be dword-aligned (i.e., with an address
where A1 and A0 are both 0)
5.5.1.2
Start Field Definition
Table 5-6.
Start Field Bit Definitions
Bits[3:0]
Encoding
Definition
0000
Start of cycle for a generic target
0010
Grant for bus master 0
0011
Grant for bus master 1
1111
Stop/Abort: End of a cycle for a
target.
NOTE: All other encodings are RESERVED.
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Functional Description
5.5.1.3
Cycle Type / Direction (CYCTYPE + DIR)
The ICH7 drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0. Table 5-7 shows the valid bit encodings.
Table 5-7.
Cycle Type Bit Definitions
Bits[3:2]
Bit1
Definition
00
0
I/O Read
00
1
I/O Write
10
0
10
1
11
x
Desktop and Mobile: DMA Read
Ultra Mobile: Reserved
Desktop and Mobile: DMA Write
Ultra Mobile: Reserved
Reserved. If a peripheral performing a bus master cycle generates this
value, the Intel® ICH7 aborts the cycle.
NOTE: All other encodings are RESERVED.
5.5.1.4
SIZE
Bits[3:2] are reserved. The ICH7 drives them to 00. Peripherals running bus master
cycles are also supposed to drive 00 for bits 3:2; however, the ICH7 ignores those bits.
Bits[1:0] are encoded as listed in Table 5-8.
Table 5-8.
Transfer Size Bit Definition
Bits[1:0]
120
Size
00
8-bit transfer (1 byte)
01
16-bit transfer (2 bytes)
10
Reserved. The Intel® ICH7 does not drive this combination. If a peripheral
running a bus master cycle drives this combination, the ICH7 may abort the
transfer.
11
32-bit transfer (4 bytes)
Intel ® ICH7 Family Datasheet
Functional Description
5.5.1.5
SYNC
Valid values for the SYNC field are shown in Table 5-9.
Table 5-9.
SYNC Bit Definition
Bits[3:0]1,2
Indication
0000
Ready: SYNC achieved with no error. For DMA transfers on desktop and mobile
components, this also indicates DMA request deassertion and no more transfers
desired for that channel.
0101
Short Wait: Part indicating wait-states. For bus master cycles, the Intel® ICH7
does not use this encoding. Instead, the ICH7 uses the Long Wait encoding (see
next encoding below).
0110
Long Wait: Part indicating wait-states, and many wait-states will be added. This
encoding driven by the ICH7 for bus master cycles, rather than the Short Wait
(0101).
1001
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with
no error and more DMA transfers desired to continue after this transfer. This
value is valid only on DMA transfers and is not allowed for any other type of
cycle.
Ultra Mobile: Reserved
1010
Error: Sync achieved with error. This is generally used to replace the SERR# or
IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred,
but there is a serious error in this transfer. For DMA transfers on desktop and
mobile components, this not only indicates an error, but also indicates DMA
request deassertion and no more transfers desired for that channel.
NOTES:
1.
All other combinations are RESERVED.
2.
If the LPC controller receives any SYNC returned from the device other than short (0101),
long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may
occur. A FWH device is not allowed to assert an Error SYNC.
5.5.1.6
SYNC Time-Out
There are several error cases that can occur on the LPC interface. The ICH7 responds
as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1
to the stimuli described therein. There may be other peripheral failure conditions;
however, these are not handled by the ICH7.
5.5.1.7
SYNC Error Indication
The ICH7 responds as defined in section 4.2.1.10 of the Low Pin Count Interface
Specification, Revision 1.1.
Upon recognizing the SYNC field indicating an error, the ICH7 treats this as an SERR by
reporting this into the Device 31 Error Reporting Logic.
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Functional Description
5.5.1.8
LFRAME# Usage
The ICH7 follows the usage of LFRAME# as defined in the Low Pin Count Interface
Specification, Revision 1.1.
The ICH7 performs an abort for the following cases (possible failure cases):
• ICH7 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after
four consecutive clocks.
• ICH7 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC
pattern.
• A peripheral drives an invalid address when performing bus master cycles.
• A peripheral drives an invalid value.
5.5.1.9
I/O Cycles
For I/O cycles targeting registers specified in the ICH7’s decode ranges, the ICH7
performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision
1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the
ICH7 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.
Note:
If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH7
returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with
ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.
5.5.1.10
Bus Master Cycles
The ICH7 supports Bus Master cycles and requests (using LDRQ#) as defined in the
Low Pin Count Interface Specification, Revision 1.1. The ICH7 has two LDRQ# inputs,
and thus supports two separate bus master devices. It uses the associated START fields
for Bus Master 0 (0010b) or Bus Master 1 (0011b).
Note:
The ICH7 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters
should only perform memory read or memory write cycles.
5.5.1.11
LPC Power Management
CLKRUN# Protocol (Mobile/Ultra Mobile Only)
The CLKRUN# protocol is same as in the PCI Local Bus Specification. Stopping the PCI
clock stops the LPC clock.
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive
LDRQ# low or tri-state it. ICH7 shuts off the LDRQ# input buffers. After driving
SUS_STAT# active, the ICH7 drives LFRAME# low, and tri-states (or drive low)
LAD[3:0].
Note:
122
The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. The ICH7 asserts both
SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time
when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not
inconsistent with the LPC LPCPD# protocol.
Intel ® ICH7 Family Datasheet
Functional Description
5.5.1.12
Configuration and Intel® ICH7 Implications
LPC Interface Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH7
includes several decoders. During configuration, the ICH7 must be programmed with
the same decode ranges as the peripheral. The decoders are programmed via the
Device 31:Function 0 configuration space.
Note:
The ICH7 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with
similar characteristics (specifically those with a “Retry Read” feature which is enabled)
to an LPC device if there is an outstanding LPC read cycle towards the same PCI device
or bridge. These cycles are not part of normal system operation, but may be
encountered as part of platform validation testing using custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the ICH7 that supports two
LPC bus masters, it drives 0010 for the START field for grants to bus master #0
(requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via
LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular
bus master.
5.5.2
SERR# Generation
Several internal and external sources of the LPC Bridge can cause SERR#, as described
below.
The first class of errors is parity errors related to the backbone. The LPC Bridge
captures generic data parity errors (errors it finds on the backbone) as well as errors
returned on the backbone cycles where the bridge was the master and parity error
response is enabled. If either of these two conditions is met, and with SERR# enable
(PCICMD.SERR_EN) set, SERR# will be captured.
Additionally, if the LPC Bridge receives an error SYNC on LPC bus, an SERR# will also
be generated.
Figure 5-4.
LPC Bridge SERR# Generation
PCISTS.DPE
(D31:F0:06h, bit15)
PCISTS.DPED
(D31:F0:06h, bit 8)
PCISTS.SSE
(D31:F0:06h, bit 14)
LPC Error Sync
Received
SERR#
PCICMD.SERR_EN
(D31:F0:04h, bit 8)
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Functional Description
5.6
DMA Operation (D31:F0)
Note:
For ICH7-U Ultra Mobile, LPC DMA is not supported.
The ICH7 supports LPC DMA using the ICH7’s DMA controller. The DMA controller has
registers that are fixed in the lower 64 KB of I/O space. The DMA controller is
configured using registers in the PCI configuration space. These registers allow
configuration of the channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with
seven independently programmable channels (Figure 5-5). DMA controller 1 (DMA-1)
corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to
channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Figure 5-5.
Intel® ICH7 DMA Controller
Channel 4
Channel 0
Channel 1
Channel 5
DMA-1
Channel 2
Channel 6
Channel 3
Channel 7
DMA-2
Each DMA channel is hardwired to the compatible settings for DMA device size:
channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are
hardwired to 16-bit, count-by-words (address shifted) transfers.
ICH7 provides 24-bit addressing in compliance with the ISA-Compatible specification.
Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16
least-significant bits of the 24-bit address, an ISA-Compatible Page Register which
contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization
following a DMA termination.
5.6.1
Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3
and channels 4–7. Each group may be in either fixed or rotate mode, as determined by
the DMA Command Register.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,
a software request for DMA service can be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any
hardware request. See the detailed register description for Request Register
programming information in Section 10.2.
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Functional Description
5.6.1.1
Fixed Priority
The initial fixed priority structure is as follows:
High priority
Low priority
0, 1, 2, 3
5, 6, 7
The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the
highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume
the priority position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and
7.
5.6.1.2
Rotating Priority
Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the
last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).
Channels 0–3 rotate as a group of 4. They are placed between channel 5 and channel 7
in the priority list.
Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three
positions in the rotation, while channel group (0–3) comprises the fourth position in the
arbitration.
5.6.2
Address Compatibility Mode
When the DMA is operating, the addresses do not increment or decrement through the
High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments,
the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h
and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is
operating in 16-bit mode, the addresses still do not increment or decrement through
the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a
24-bit address is 01FFFEh and increments, the next address is 000000h, not
0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address
is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register
implementation used in the PC-AT. This mode is set after CPURST is valid.
5.6.3
Summary of DMA Transfer Sizes
Table 5-10 lists each of the DMA device transfer sizes. The column labeled “Current
Byte/Word Count Register” indicates that the register contents represents either the
number of bytes to transfer or the number of 16-bit words to transfer. The column
labeled “Current Address Increment/Decrement” indicates the number added to or
taken from the Current Address register after each DMA transfer cycle. The DMA
Channel Mode Register determines if the Current Address Register will be incremented
or decremented.
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Functional Description
5.6.3.1
Address Shifting When Programmed for 16-Bit I/O Count by Words
Table 5-10. DMA Transfer Size
Current Byte/Word
Count Register
Current Address
Increment/
Decrement
8-Bit I/O, Count By Bytes
Bytes
1
16-Bit I/O, Count By Words (Address
Shifted)
Words
1
DMA Device Date Size And Word Count
The ICH7 maintains compatibility with the implementation of the DMA in the PC AT that
used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device
count-by-words.
Note:
The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
When programming the Current Address Register (when the DMA channel is in this
mode), the Current Address must be programmed to an even address with the address
value shifted right by one bit.
The address shifting is shown in Table 5-11.
Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers
Output
Address
8-Bit I/O Programmed
Address (Ch 0–3)
16-Bit I/O Programmed
Address (Ch 5–7)
(Shifted)
A0
A[16:1]
A[23:17]
A0
A[16:1]
A[23:17]
0
A[15:0]
A[23:17]
NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
5.6.4
Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following TC. The Base Registers are loaded simultaneously
with the Current Registers by the microprocessor when the DMA channel is
programmed and remain unchanged throughout the DMA service. The mask bit is not
set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ
is detected.
5.6.5
Software Commands
There are three additional special software commands that the DMA controller can
execute. The three software commands are:
• Clear Byte Pointer Flip-Flop
• Master Clear
• Clear Mask Register
They do not depend on any specific bit pattern on the data bus.
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Functional Description
5.7
LPC DMA (Desktop and Mobile Only)
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and
special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment
modes are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels
5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.
5.7.1
Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the
LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own
dedicated LDRQ# signal (they may not be shared between two separate peripherals).
The ICH7 has two LDRQ# inputs, allowing at least two devices to support DMA or bus
mastering.
LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-6, the peripheral
uses the following serial encoding sequence:
• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high
during idle conditions.
• The next three bits contain the encoded DMA channel number (MSB first).
• The next bit (ACT) indicates whether the request for the indicated DMA channel is
active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is
inactive. The case where ACT is low is rare, and is only used to indicate that a
previous request for that channel is being abandoned.
• After the active/inactive indication, the LDRQ# signal must go high for at least
1 clock. After that one clock, LDRQ# signal can be brought low to the next
encoding sequence.
If another DMA channel also needs to request a transfer, another sequence can be sent
on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel
3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral
can send the encoded request for channel 3. This allows multiple DMA agents behind an
I/O device to request use of the LPC interface, and the I/O device does not need to selfarbitrate before sending the message.
Figure 5-6.
DMA Request Assertion through LDRQ#
LCLK
LDRQ#
5.7.2
Start
MSB
LSB
ACT
Start
Abandoning DMA Requests
DMA Requests can be deasserted in two fashions: on error conditions by sending an
LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the
DMA transfer. This section describes boundary conditions where the DMA request needs
to be removed prior to a data transfer.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
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127
Functional Description
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was
seen by the ICH7, there is no assurance that the cycle has not been granted and will
shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may
still occur. The peripheral can choose not to respond to this cycle, in which case the
host will abort it, or it can choose to complete the cycle normally with any random data.
This method of DMA deassertion should be prevented whenever possible, to limit
boundary conditions both on the ICH7 and the peripheral.
5.7.3
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA
transfer is as follows:
1. ICH7 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.
2. ICH7 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.
3. ICH7 asserts channel number and, if applicable, terminal count.
4. ICH7 indicates the size of the transfer: 8 or 16 bits.
5. If a DMA read…
— The ICH7 drives the first 8 bits of data and turns the bus around.
— The peripheral acknowledges the data with a valid SYNC.
— If a 16-bit transfer, the process is repeated for the next 8 bits.
6. If a DMA write…
— The ICH7 turns the bus around and waits for data.
— The peripheral indicates data ready through SYNC and transfers the first byte.
— If a 16-bit transfer, the peripheral indicates data ready and transfers the next
byte.
7. The peripheral turns around the bus.
5.7.4
Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates
the last byte of transfer, based upon the size of the transfer.
For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is
the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the
second byte is the last byte. The peripheral, therefore, must internalize the TC bit when
the CHANNEL field is communicated, and only signal TC when the last byte of that
transfer size has been transferred.
5.7.5
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral will be driving
data onto the LPC interface. However, the host will not transfer this data into main
memory.
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Intel ® ICH7 Family Datasheet
Functional Description
5.7.6
DMA Request Deassertion
An end of transfer is communicated to the ICH7 through a special SYNC field
transmitted by the peripheral. An LPC device must not attempt to signal the end of a
transfer by deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer
from a demand mode device) the ICH7 needs to know when to deassert the DMA
request based on the data currently being transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to the ICH7 whether this is the last byte of transfer or if more bytes are
requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of
0000b (ready with no error), or 1010b
(ready with error). These encodings tell the ICH7 that this is the last piece of data
transferred on a DMA read (ICH7 to peripheral), or the byte that follows is the last
piece of data transferred on a DMA write (peripheral to ICH7).
When the ICH7 sees one of these two encodings, it ends the DMA transfer after this
byte and deasserts the DMA request to the 8237. Therefore, if the ICH7 indicated a 16bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC
value of 0000b or 1010b. The ICH7 does not attempt to transfer the second byte, and
deasserts the DMA request internally.
If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the
indicated size, then the ICH7 only deasserts the DMA request to the 8237 since it does
not need to end the transfer.
If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of
1001b (ready plus more data). This tells the 8237 that more data bytes are requested
after the current byte has been transferred, so the ICH7 keeps the DMA request active
to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC
value of 1001b to the ICH7, the data will be transferred and the DMA request will
remain active to the 8237. At a later time, the ICH7 will then come back with another
START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the
peripheral.
The peripheral must not assume that the next START indication from the ICH7 is
another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single
mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode
DMA devices can be ensured that they will receive the next START indication from the
ICH7.
Note:
Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit
channel (first byte of a 16-bit transfer) is an error condition.
Note:
The host stops the transfer on the LPC bus as indicated, fills the upper byte with
random data on DMA writes (peripheral to memory), and indicates to the 8237 that the
DMA transfer occurred, incrementing the 8237’s address and decrementing its byte
count.
5.7.7
SYNC Field / LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
are ended through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a deassertion is
indicated through the SYNC field. This is needed to allow the 8237, that typically runs
off a much slower internal clock, to see a message deasserted before it is re-asserted
so that it can arbitrate to the next agent.
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Functional Description
Under default operation, the host only performs 8-bit transfers on 8-bit channels and
16-bit transfers on 16-bit channels.
The method by which this communication between host and peripheral through system
BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC
peripheral are motherboard devices, no “plug-n-play” registry is required.
The peripheral must not assume that the host is able to perform transfer sizes that are
larger than the size allowed for the DMA channel, and be willing to accept a SIZE field
that is smaller than what it may currently have buffered.
To that end, it is recommended that future devices that may appear on the LPC bus,
that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus
mastering interface and not rely on the 8237.
5.8
8254 Timers (D31:F0)
The ICH7 contains three counters that have fixed uses. All registers and functions
associated with the 8254 timers are in the core well. The 8254 unit is clocked by a
14.31818 MHz clock.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with
a period equal to the product of the counter period (838 ns) and the initial count value.
The counter loads the initial count value 1 counter period after software writes the
count value to the counter I/O address. The counter initially asserts IRQ0 and
decrements the count value by two each counter period. The counter negates IRQ0
when the count value reaches 0. It then reloads the initial count value and again
decrements the initial count value by two each counter period. The counter then
asserts IRQ0 when the count value reaches 0, reloads the initial count value, and
repeats the cycle, alternately asserting and negating IRQ0.
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for Mode
2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial
count value is loaded one counter period after being written to the counter I/O address.
The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and
will toggle at a rate based on the value in the counter. Programming the counter to
anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to port 061h (see NMI Status and Control ports).
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Functional Description
5.8.1
Timer Programming
The counter/timers are programmed in the following fashion:
1. Write a control word to select a counter.
2. Write an initial count for that counter.
3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4)
of the 16-bit counter.
4. Repeat with other counters.
Only two conventions need to be observed when programming the counters. First, for
each counter, the control word must be written before the initial count is written.
Second, the initial count must follow the count format specified in the control word
(least significant byte only, most significant byte only, or least significant byte and then
most significant byte).
A new initial count may be written to a counter at any time without affecting the
counter's programmed mode. Counting is affected as described in the mode definitions.
The new count must follow the programmed count format.
If a counter is programmed to read/write two-byte counts, the following precaution
applies: A program must not transfer control between writing the first and second byte
to another routine which also writes into that same counter. Otherwise, the counter will
be loaded with an incorrect count.
The Control Word Register at port 43h controls the operation of all three counters.
Several commands are available:
• Control Word Command. Specifies which counter to read or write, the operating
mode, and the count format (binary or BCD).
• Counter Latch Command. Latches the current count so that it can be read by the
system. The countdown process continues.
• Read Back Command. Reads the count value, programmed mode, the current
state of the OUT pins, and the state of the Null Count Flag of the selected counter.
Table 5-12 lists the six operating modes for the interval counters.
Table 5-12. Counter Operating Modes
Mode
Function
Description
0
Out signal on end of count (=0)
Output is 0. When count goes to 0, output goes to
1 and stays at 1 until counter is reprogrammed.
1
Hardware retriggerable one-shot
Output is 0. When count goes to 0, output goes to
1 for one clock time.
2
Rate generator (divide by n
counter)
Output is 1. Output goes to 0 for one clock time,
then back to 1 and counter is reloaded.
3
Square wave output
Output is 1. Output goes to 0 when counter rolls
over, and counter is reloaded. Output goes to 1
when counter rolls over, and counter is reloaded,
etc.
4
Software triggered strobe
Output is 1. Output goes to 0 when count expires
for one clock time.
5
Hardware triggered strobe
Output is 1. Output goes to 0 when count expires
for one clock time.
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Functional Description
5.8.2
Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in
progress. There are three methods for reading the counters: a simple read operation,
counter Latch command, and the Read-Back command. Each is explained below.
With the simple read and counter latch command methods, the count must be read
according to the programmed format; specifically, if the counter is programmed for two
byte counts, two bytes must be read. The two bytes do not have to be read one right
after the other. Read, write, or programming operations for other counters may be
inserted between them.
5.8.2.1
Simple Read
The first method is to perform a simple read operation. The counter is selected through
port 40h (counter 0), 41h (counter 1), or 42h (counter 2).
Note:
Performing a direct read from the counter does not return a determinate value,
because the counting process is asynchronous to read operations. However, in the case
of counter 2, the count can be stopped by writing to the GATE bit in port 61h.
5.8.2.2
Counter Latch Command
The Counter Latch command, written to port 43h, latches the count of a specific
counter at the time the command is received. This command is used to ensure that the
count read from the counter is accurate, particularly when reading a two-byte count.
The count value is then read from each counter’s Count register as was programmed by
the Control register.
The count is held in the latch until it is read or the counter is reprogrammed. The count
is then unlatched. This allows reading the contents of the counters on the fly without
affecting counting in progress. Multiple Counter Latch Commands may be used to latch
more than one counter. Counter Latch commands do not affect the programmed mode
of the counter in any way.
If a Counter is latched and then, some time later, latched again before the count is
read, the second Counter Latch command is ignored. The count read is the count at the
time the first Counter Latch command was issued.
5.8.2.3
Read Back Command
The Read Back command, written to port 43h, latches the count value, programmed
mode, and current states of the OUT pin and Null Count flag of the selected counter or
counters. The value of the counter and its status may then be read by I/O access to the
counter address.
The Read Back command may be used to latch multiple counter outputs at one time.
This single command is functionally equivalent to several counter latch commands, one
for each counter latched. Each counter's latched count is held until it is read or
reprogrammed. Once read, a counter is unlatched. The other counters remain latched
until they are read. If multiple count Read Back commands are issued to the same
counter without reading the count, all but the first are ignored.
The Read Back command may additionally be used to latch status information of
selected counters. The status of a counter is accessed by a read from that counter's
I/O port address. If multiple counter status latch operations are performed without
reading the status, all but the first are ignored.
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Functional Description
Both count and status of the selected counters may be latched simultaneously. This is
functionally the same as issuing two consecutive, separate Read Back commands. If
multiple count and/or status Read Back commands are issued to the same counters
without any intervening reads, all but the first are ignored.
If both count and status of a counter are latched, the first read operation from that
counter returns the latched status, regardless of which was latched first. The next one
or two reads, depending on whether the counter is programmed for one or two type
counts, returns the latched count. Subsequent reads return unlatched count.
5.9
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH7 incorporates the functionality of two 8259 interrupt controllers that provide
system interrupts for the ISA compatible interrupts. These interrupts are: system
timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, and
DMA channels. In addition, this interrupt controller can support the PCI based
interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each
8259 core supports eight interrupts, numbered 0–7. Table 5-13 shows how the cores
are connected.
.
Table 5-13. Interrupt Controller Core Connections
8259
8259
Input
Master
Slave
Typical Interrupt
Source
Connected Pin / Function
0
Internal
Internal Timer / Counter 0 output / HPET #0
1
Keyboard
IRQ1 via SERIRQ
2
Internal
Slave controller INTR output
3
Serial Port A
IRQ3 via SERIRQ, PIRQ#
4
Serial Port B
IRQ4 via SERIRQ, PIRQ#
5
Parallel Port / Generic
IRQ5 via SERIRQ, PIRQ#
6
Floppy Disk
IRQ6 via SERIRQ, PIRQ#
7
Parallel Port / Generic
IRQ7 via SERIRQ, PIRQ#
0
Internal Real Time
Clock
Internal RTC / HPET #1
1
Generic
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
2
Generic
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
3
Generic
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#
4
PS/2 Mouse
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#
5
Internal
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
6
IDE cable, SATA
IDEIRQ (legacy mode, non-combined or combined
mapped as primary), SATA Primary (legacy mode),
or via SERIRQ or PIRQ#
7
IDE cable, SATA
IDEIRQ (legacy mode — combined, mapped as
secondary), SATA Secondary (legacy mode) or via
SERIRQ or PIRQ#
The ICH7 cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
ICH7 PIC.
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133
Functional Description
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,
IRQ8#, and IRQ13.
Note:
Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH7. In the
following descriptions of the 8259s, the interrupt levels are in reference to the signals
at the internal interface of the 8259s, after the required inversions have occurred.
Therefore, the term “high” indicates “active,” which means “low” on an originating
PIRQ#.
5.9.1
Interrupt Handling
5.9.1.1
Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts. Table 5-14 defines the IRR, ISR, and IMR.
Table 5-14. Interrupt Status Registers
5.9.1.2
Bit
Description
IRR
Interrupt Request Register. This bit is set on a low to high transition of the interrupt
line in edge mode, and by an active high level in level mode. This bit is set whether or
not the interrupt is masked. However, a masked interrupt will not generate INTR.
ISR
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,
when an interrupt acknowledge cycle is seen, and the vector returned is for that
interrupt.
IMR
Interrupt Mask Register. This bit determines whether an interrupt is masked.
Masked interrupts will not generate INTR.
Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated by the host
bridge into a PCI Interrupt Acknowledge Cycle to the ICH7. The PIC translates this
command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the
first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On
the second INTA# pulse, the master or slave sends the interrupt vector to the
processor with the acknowledged interrupt code. This code is based upon bits [7:3] of
the corresponding ICW2 register, combined with three bits representing the interrupt
within that controller.
Table 5-15. Content of Interrupt Vector Byte
Master, Slave Interrupt
Bits [2:0]
IRQ7,15
111
IRQ6,14
110
IRQ5,13
101
IRQ4,12
IRQ3,11
134
Bits [7:3]
ICW2[7:3]
100
011
IRQ2,10
010
IRQ1,9
001
IRQ0,8
000
Intel ® ICH7 Family Datasheet
Functional Description
5.9.1.3
Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by the ICH7.
4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH7 converts it
into the two cycles that the internal 8259 pair can respond to. Each cycle appears
as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded
interrupt controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA#
pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. If no interrupt request is present because the request was too
short in duration, the PIC returns vector 7 from the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
5.9.2
Initialization Command Words (ICWx)
Before operation can begin, each 8259 must be initialized. In the ICH7, this is a four
byte sequence. The four initialization command words are referred to by their
acronyms: ICW1, ICW2, ICW3, and ICW4.
The base address for each 8259 initialization command word is a fixed location in the
I/O memory space: 20h for the master controller, and A0h for the slave controller.
5.9.2.1
ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, the ICH7 PIC expects three
more byte writes to 21h for the master controller, or A1h for the slave controller, to
complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
transition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
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Functional Description
5.9.2.2
ICW2
The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
5.9.2.3
ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
• For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the ICH7, IRQ2 is used. Therefore, bit 2 of
ICW3 on the master controller is set to a 1, and the other bits are set to 0s.
• For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller if the cascaded interrupt won
arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and if it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
5.9.2.4
ICW4
The final write in the sequence (ICW4) must be programmed for both controllers. At
the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in
an Intel Architecture-based system.
5.9.3
Operation Command Words (OCW)
These command words reprogram the Interrupt controller to operate in various
interrupt modes.
• OCW1 masks and unmasks interrupt lines.
• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
and controls the EOI function.
• OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM),
and enables/disables polled interrupt mode.
5.9.4
Modes of Operation
5.9.4.1
Fully Nested Mode
In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being
the highest. When an interrupt is acknowledged, the highest priority request is
determined and its vector placed on the bus. Additionally, the ISR for the interrupt is
set. This ISR bit remains set until: the processor issues an EOI command immediately
before returning from the service routine; or if in AEOI mode, on the trailing edge of
the second INTA#. While the ISR bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels generate another interrupt. Interrupt priorities
can be changed in the rotating priority mode.
136
Intel ® ICH7 Family Datasheet
Functional Description
5.9.4.2
Special Fully-Nested Mode
This mode is used in the case of a system where cascading is used, and the priority has
to be conserved within each slave. In this case, the special fully-nested mode is
programmed to the master controller. This mode is similar to the fully-nested mode
with the following exceptions:
• When an interrupt request from a certain slave is in service, this slave is not locked
out from the master's priority logic and further interrupt requests from higher
priority interrupts within the slave are recognized by the master and initiate
interrupts to the processor. In the normal-nested mode, a slave is masked out
when its request is in service.
• When exiting the Interrupt Service routine, software has to check whether the
interrupt serviced was the only one from that slave. This is done by sending a NonSpecific EOI command to the slave and then reading its ISR. If it is 0, a nonspecific EOI can also be sent to the master.
5.9.4.3
Automatic Rotation Mode (Equal Priority Devices)
In some applications, there are a number of interrupting devices of equal priority.
Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a
device receives the lowest priority after being serviced. In the worst case, a device
requesting an interrupt has to wait until each of seven other devices are serviced at
most once.
There are two ways to accomplish automatic rotation using OCW2; the Rotation on
Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode
which is set by (R=1, SL=0, EOI=0).
5.9.4.4
Specific Rotation Mode (Specific Priority)
Software can change interrupt priorities by programming the bottom priority. For
example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest
priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:
R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device.
In this mode, internal status is updated by software control during OCW2. However, it
is independent of the EOI command. Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1
and LO–L2=IRQ level to receive bottom priority.
5.9.4.5
Poll Mode
Poll mode can be used to conserve space in the interrupt vector table. Multiple
interrupts that can be serviced by one interrupt service routine do not need separate
vectors if the service routine uses the poll command. Poll mode can also be used to
expand the number of interrupts. The polling interrupt service routine can call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary
code of the highest priority level in bits 2:0.
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Functional Description
5.9.4.6
Cascade Mode
The PIC in the ICH7 has one master 8259 and one slave 8259 cascaded onto the
master through IRQ2. This configuration can handle up to 15 separate priority levels.
The master controls the slaves through a three bit internal bus. In the ICH7, when the
master drives 010b on this bus, the slave controller takes responsibility for returning
the interrupt vector. An EOI command must be issued twice: once for the master and
once for the slave.
5.9.4.7
Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge
for the entire controller. In the ICH7, this bit is disabled and a new register for edge and
level triggered mode selection, per interrupt input, is included. This is the Edge/Level
control Registers ELCR1 and ELCR2.
If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
5.9.4.8
End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to 1.
5.9.4.9
Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and
Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest
ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of
the PIC within the ICH7, as the interrupt being serviced currently is the interrupt
entered with the interrupt acknowledge. When the PIC is operated in modes that
preserve the fully nested structure, software can determine which ISR bit to clear by
issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if
the PIC is in the special mask mode. An EOI command must be issued for both the
master and slave controller.
5.9.4.10
Automatic End of Interrupt Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller and not
the slave controller.
138
Intel ® ICH7 Family Datasheet
Functional Description
5.9.5
Masking Interrupts
5.9.5.1
Masking on an Individual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller masks all requests for service
from the slave controller.
5.9.5.2
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The special mask mode enables all interrupts not masked by a bit set in the Mask
register. Normally, when an interrupt service routine acknowledges an interrupt without
issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority
requests. In the special mask mode, any interrupts may be selectively enabled by
loading the Mask Register with the appropriate pattern. The special mask mode is set
by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
5.9.6
Steering PCI Interrupts
The ICH7 can be programmed to allow PIRQA#-PIRQH# (PIRQE#–PIRQH# on Ultra
Mobile) to be internally routed to interrupts 3–7, 9–12, 14 or 15. The assignment is
programmable through the through the PIRQx Route Control registers, located at 60–
63h and 68–6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to
the same IRQx input. If interrupt steering is not required, the Route registers can be
programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a PCI board to share a single line across the connector. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
sensitive mode. The ICH7 internally inverts the PIRQx# line to send an active high level
to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer
be used by an active high device (through SERIRQ). However, active low interrupts can
share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external
PIRQ to be asserted. The ICH7 receives the PIRQ input, like all of the other external
sources, and routes it accordingly.
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Functional Description
5.10
Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous chapter, the
ICH7 incorporates the APIC. While the standard interrupt controller is intended for use
in a uni-processor system, APIC can be used in either a uni-processor or multiprocessor system.
5.10.1
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal datapath to the processor, and interrupts are handled
without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in the ICH7 supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.
5.10.2
Interrupt Mapping
The I/O APIC within the ICH7 supports 24 APIC interrupts. Each interrupt has its own
unique vector assigned by software. The interrupt vectors are mapped as follows, and
match “Config 6” of the Multi-Processor Specification.
Table 5-16. APIC Interrupt Mapping (Sheet 1 of 2)
Via
SERIRQ
Direct
from Pin
0
No
No
No
1
Yes
No
Yes
2
No
No
No
3
Yes
No
Yes
4
Yes
No
Yes
5
Yes
No
Yes
6
Yes
No
Yes
7
Yes
No
Yes
8
No
No
No
RTC, HPET #1 (legacy mode)
9
Yes
No
Yes
Option for SCI, TCO
IRQ #1
140
Via PCI
Message
Internal Modules
Cascade from 8259 #1
8254 Counter 0, HPET #0 (legacy mode)
10
Yes
No
Yes
Option for SCI, TCO
11
Yes
No
Yes
HPET #2, Option for SCI, TCO2
12
Yes
No
Yes
13
No
No
No
FERR# logic
14
Yes
Yes3
Yes
IDEIRQ (legacy mode, non-combined or
combined mapped as primary), SATA Primary
(legacy mode)
15
Yes
Yes
Yes
IDEIRQ (legacy mode — combined, mapped as
secondary), SATA Secondary (legacy mode)
Intel ® ICH7 Family Datasheet
Functional Description
Table 5-16. APIC Interrupt Mapping (Sheet 2 of 2)
IRQ #1
Via
SERIRQ
Direct
from Pin
16
PIRQA#
PIRQA#
17
PIRQB#
PIRQB#
18
PIRQC#
PIRQC#
19
PIRQD#
PIRQD#
20
N/A
PIRQE#
21
N/A
PIRQF#
22
N/A
PIRQG#
23
N/A
PIRQH#
Via PCI
Message
Internal Modules
Internal devices are routable; see
Section 7.1.41 though Section 7.1.50.
Yes
NOTE: PIRQA#–PIRQD# are not on Ultra
Mobile.
Yes
Option for SCI, TCO, HPET #0,1,2. Other
internal devices are routable; see
Section 7.1.41 through Section 7.1.50.
NOTES:
1.
When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources, while interrupts 16 through 23
receive active-low internal interrupt sources.
2.
If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of HPET #2. ICH7 hardware does not prevent
sharing of IRQ 11.
3.
IDEIRQ can only be driven directly from the pin when in legacy IDE mode.
5.10.3
PCI / PCI Express* Message-Based Interrupts
When external devices through PCI / PCI Express wish to generate an interrupt, they
will send the message defined in the PCI Express* Base Specification, Revision 1.0a for
generating INTA# – INTD#. These will be translated internal assertions/de-assertions
of INTA# – INTD#.
5.10.4
Front Side Bus Interrupt Delivery
For processors that support Front Side Bus (FSB) interrupt delivery, the ICH7 requires
that the I/O APIC deliver interrupt messages to the processor in a parallel manner,
rather than using the I/O APIC serial scheme.
This is done by the ICH7 writing (via DMI) to a memory location that is snooped by the
processor(s). The processor(s) snoop the cycle to know which interrupt goes active.
The following sequence is used:
1. When the ICH7 detects an interrupt event (active edge for edge-triggered mode or
a change for level-triggered mode), it sets or resets the internal IRR bit associated
with that interrupt.
2. Internally, the ICH7 requests to use the bus in a way that automatically flushes
upstream buffers. This can be internally implemented similar to a DMA device
request.
3. The ICH7 then delivers the message by performing a write cycle to the appropriate
address with the appropriate data. The address and data formats are described
below in Section 5.10.4.4.
Note:
FSB Interrupt Delivery compatibility with processor clock control depends on the
processor, not the ICH7.
Intel ® ICH7 Family Datasheet
141
Functional Description
5.10.4.1
Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt.
5.10.4.2
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on
the interrupt. If after the EOI the interrupt is still active, then another “Assert Message”
is sent to indicate that the interrupt is still active.
5.10.4.3
Registers Associated with Front Side Bus Interrupt Delivery
Capabilities Indication: The capability to support Front Side Bus interrupt delivery is
indicated via ACPI configuration techniques. This involves the BIOS creating a data
structure that gets reported to the ACPI configuration software.
5.10.4.4
Interrupt Message Format
The ICH7 writes the message to PCI (and to the Host controller) as a 32-bit memory
write cycle. It uses the formats shown in Table 5-17 and Table 5-18 for the address and
data.
The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus
messages as a SMI in which case the processor treats the incoming interrupt as a SMI
instead of as an interrupt. This does not mean that the ICH7 has any way to have a SMI
source from ICH7 power management logic cause the I/O APIC to send an SMI
message (there is no way to do this). The ICH7’s I/O APIC can only send interrupts due
to interrupts which do not include SMI, NMI or INIT. This means that in IA32/IA64
based platforms, Front Side Bus interrupt message format delivery modes 010
(SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used
and is not supported. Only the hardware pin connection is supported by ICH7.
:
Table 5-17. Interrupt Message Address Format
Bit
Description
31:20
Will allways be FEEh
19:12
Destination ID: This is the same as bits 63:56 of the I/O Redirection Table entry for
the interrupt associated with this message.
11:4
Extended Destination ID: This is the same as bits 55:48 of the I/O Redirection
Table entry for the interrupt associated with this message.
Redirection Hint: This bit is used by the processor host bridge to allow the interrupt
message to be redirected.
3
0 = The message will be delivered to the agent (processor) listed in bits 19:12.
1 = The message will be delivered to an agent with a lower interrupt priority This can
be derived from bits 10:8 in the Data Field (see below).
The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated
with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the
Redirection Hint bit will be 0
2
1:0
142
Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the
Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical
destination mode is used, and the redirection is limited only to those processors that
are part of the logical group as based on the logical ID.
Will always be 00.
Intel ® ICH7 Family Datasheet
Functional Description
Table 5-18. Interrupt Message Data Format
Bit
31:16
Description
Will always be 0000h.
15
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O
Redirection Table for that interrupt.
14
Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit
is always 1.
13:12
11
Will always be 00
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the
I/O Redirection Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection
Table for that interrupt.
10:8
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
7:0
5.11
Vector: This is the same as the corresponding bits in the I/O Redirection Table for
that interrupt.
Serial Interrupt (D31:F0)
The ICH7 supports a serial IRQ scheme. This allows a single signal to be used to report
interrupt requests. The signal used to transmit this information is shared between the
host, the ICH7, and all peripherals that support serial interrupts. The signal line,
SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is
used by all PCI signals. This means that if a device has driven SERIRQ low, it will first
drive it high synchronous to PCI clock and release it the following PCI clock. The serial
IRQ protocol defines this sustained tri-state signaling in the following fashion:
• S – Sample Phase. Signal driven low
• R – Recovery Phase. Signal driven high
• T – Turn-around Phase. Signal released
The ICH7 supports a message for 21 serial interrupts. These represent the 15 ISA
interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts
(20–23).
Note:
When the IDE controller is enabled or the SATA controller (Desktop and Mobile Only) is
configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA
legacy interrupts, which cannot be shared, i.e. through the Serial Interrupt pin. If
IRQ14 and IRQ15 are shared with Serial Interrupt pin then abnormal system behavior
may occur. For example, IRQ14/15 may not be detected by ICH7's interrupt controller.
5.11.1
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These
two modes are: Continuous, where the ICH7 is solely responsible for generating the
start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the
start frame.
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Functional Description
The mode that must first be entered when enabling the serial IRQ protocol is
continuous mode. In this mode, the ICH7 asserts the start frame. This start frame is 4,
6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in
Device 31:Function 0 configuration space. This is a polling mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the
SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a
peripheral drives the SERIRQ signal low. The ICH7 senses the line low and continues to
drive it low for the remainder of the Start Frame. Since the first PCI clock of the start
frame was driven by the peripheral in this mode, the ICH7 drives the SERIRQ line low
for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet,
and therefore lower power, operation.
5.11.2
Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start
counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has
exactly 3 phases of 1 clock each:
• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the
corresponding interrupt signal is low. If the corresponding interrupt is high, then
the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due
to pull-up resistors (there is no internal pull-up resistor on this signal, an external
pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames
indicates that an active-high ISA interrupt is not being requested, but a low level
during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low
interrupt is being requested.
• Recovery Phase. During this phase, the device drives the SERIRQ line high if in
the Sample Phase it was driven low. If it was not driven in the sample phase, it is
tri-stated in this phase.
• Turn-around Phase. The device tri-states the SERIRQ line
5.11.3
Stop Frame
After all data frames, a Stop Frame is driven by the ICH7. The SERIRQ signal is driven
low by the ICH7 for 2 or 3 PCI clocks. The number of clocks is determined by the
SERIRQ configuration register. The number of clocks determines the next mode:
Table 5-19. Stop Frame Explanation
Stop Frame Width
5.11.4
Next Mode
2 PCI clocks
Quiet Mode. Any SERIRQ device may initiate a Start Frame
3 PCI clocks
Continuous Mode. Only the host (Intel® ICH7) may initiate a Start
Frame
Specific Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream that are not supported by the
ICH7. These interrupts are generated internally, and are not sharable with other
devices within the system. These interrupts are:
• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
• IRQ8#. RTC interrupt can only be generated internally.
• IRQ13. Floating point error interrupt generated off of the processor assertion of
FERR#.
The ICH7 ignores the state of these interrupts in the serial stream, and does not adjust
their level based on the level seen in the serial stream.
144
Intel ® ICH7 Family Datasheet
Functional Description
5.11.5
Data Frame Format
Table 5-20 shows the format of the data frames. For the PCI interrupts (A–D), the
output from the ICH7 is ANDed with the PCI input signal. This way, the interrupt can be
signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are
shared).
Table 5-20. Data Frame Format
Data
Frame #
Interrupt
Clocks Past
Start
Frame
1
IRQ0
2
2
IRQ1
5
3
SMI#
8
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
Comment
Ignored. IRQ0 can only be generated via the internal
8524
Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
Ignored. IRQ8# can only be generated internally.
13
IRQ12
38
14
IRQ13
41
Ignored. IRQ13 can only be generated from FERR#
15
IRQ14
44
Not attached to PATA or SATA logic
16
IRQ15
47
Not attached to PATA or SATA logic
17
IOCHCK#
50
Same as ISA IOCHCK# going active.
18
PCI INTA#
53
Drive PIRQA#
19
PCI INTB#
56
Drive PIRQB#
20
PCI INTC#
59
Drive PIRQC#
21
PCI INTD#
62
Drive PIRQD#
Intel ® ICH7 Family Datasheet
145
Functional Description
5.12
Real Time Clock (D31:F0)
The Real Time Clock (RTC) module provides a battery backed-up date and time keeping
device with two banks of static RAM with 128 bytes each, although the first bank has
114 bytes for general purpose usage. Three interrupt features are available: time of
day alarm with once a second to once a month range, periodic rates of 122 µs to
500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of
week, month, and year are counted. Daylight savings compensation is available. The
hour is represented in twelve or twenty-four hour format, and data can be represented
in BCD or binary format. The design is functionally compatible with the Motorola
MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is
divided to achieve an update every second. The lower 14 bytes on the lower RAM block
has very specific functions. The first ten are for time and date information. The next
four (0Ah to 0Dh) are registers, which configure and report RTC functions.
The time and calendar data should match the data mode (BCD or binary) and hour
mode (12 or 24 hour) as selected in register B. It is up to the programmer to make
sure that data stored in these locations is within the reasonable values ranges and
represents a possible date and time. The exception to these ranges is to store a value
of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions
must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled.
The SET bit must be 1 while programming these locations to avoid clashes with an
update cycle. Access to time and date information is done through the RAM locations. If
a RAM read from the ten time and date bytes is attempted during an update cycle, the
value read do not necessarily represent the true contents of those locations. Any RAM
writes under the same conditions are ignored.
Note:
The leap year determination for adding a 29th day to February does not take into
account the end-of-the-century exceptions. The logic simply assumes that all years
divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that
are divisible by 100 are typically not leap years. In every fourth century (years divisible
by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note
that the year 2100 will be the first time in which the current RTC implementation would
incorrectly calculate the leap-year.
The ICH7 does not implement month/year alarms.
5.12.1
Update Cycles
An update cycle occurs once a second, if the SET bit of register B is not asserted and
the divide chain is properly configured. During this procedure, the stored time and date
are incremented, overflow is checked, a matching alarm condition is checked, and the
time and date are rewritten to the RAM locations. The update cycle will start at least
488 µs after the UIP bit of register A is asserted, and the entire cycle does not take
more than 1984 µs to complete. The time and date RAM locations (0–9) are
disconnected from the external bus during this time.
To avoid update and data corruption conditions, external RAM access to these locations
can safely occur at two times. When a updated-ended interrupt is detected, almost 999
ms is available to read and write the valid time and date data. If the UIP bit of Register
A is detected to be low, there is at least 488 µs before the update cycle begins.
Warning:
146
The overflow conditions for leap years and daylight savings adjustments are based on
more than one date or time item. To ensure proper operation when adjusting the time,
the new time and data values should be set at least two seconds before one of these
conditions (leap year, daylight savings time adjustments) occurs.
Intel ® ICH7 Family Datasheet
Functional Description
5.12.2
Interrupts
The real-time clock interrupt is internally routed within the ICH7 both to the I/O APIC
and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the
ICH7, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is
ignored. However, the High Performance Event Timers can also be mapped to IRQ8#;
in this case, the RTC interrupt is blocked.
5.12.3
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the
configuration space. If the locking bits are set, the corresponding range in the RAM will
not be readable or writable. A write cycle to those locations will have no effect. A read
cycle to those locations will not return the location’s actual value (resultant value is
undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will
invoke the BIOS and allow it to relock the RAM range.
5.12.4
Century Rollover
The ICH7 detects a rollover when the Year byte (RTC I/O space, index offset 09h)
transitions form 99 to 00. Upon detecting the rollover, the ICH7 sets the
NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this
causes an SMI#. The SMI# handler can update registers in the RTC RAM that are
associated with century value. If the system is in a sleep state (S1–S5) when the
century rollover occurs, the ICH7 also sets the NEWCENTURY_STS bit, but no SMI# is
generated. When the system resumes from the sleep state, BIOS should check the
NEWCENTURY_STS bit and update the century value in the RTC RAM.
5.12.5
Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an ICH7-based platform can be done by using a jumper on
RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
Using RTCRST# to Clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,
the state of those configuration bits that reside in the RTC power well. When the
RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set
and those configuration bits in the RTC power well will be set to their default state.
BIOS can monitor the state of this bit, and manually clear the RTC CMOS array once the
system is booted. The normal position would cause RTCRST# to be pulled up through a
weak pull-up resistor. Table 5-21 shows which bits are set to their default state when
RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved
and then replaced—all while the system is powered off. Then, once booted, the
RTC_PWR_STS can be detected in the set state.
Intel ® ICH7 Family Datasheet
147
Functional Description
Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet 1 of 2)
Bit Name
148
Register
Location
Bit(s)
Default
State
Alarm Interrupt Enable
(AIE)
Register B (General
Configuration)
(RTC_REGB)
I/O space (RTC Index +
0Bh)
5
X
Alarm Flag (AF)
Register C (Flag
Register)
(RTC_REGC)
I/O space (RTC Index +
0Ch)
5
X
SWSMI_RATE_SEL
General PM
Configuration 3
Register
GEN_PMCON_3
D31:F0:A4h
7:6
0
SLP_S4# Minimum
Assertion Width
General PM
Configuration 3
Register
GEN_PMCON_3
D31:F0:A4h
5:4
0
SLP_S4# Assertion
Stretch Enable
General PM
Configuration 3
Register
GEN_PMCON_3
D31:F0:A4h
3
0
RTC Power Status
(RTC_PWR_STS)
General PM
Configuration 3
Register
GEN_PMCON_3
D31:F0:A4h
2
0
Power Failure
(PWR_FLR)
General PM
Configuration 3
Register
(GEN_PMCON_3)
D31:F0:A4h
1
0
AFTERG3_EN
General PM
Configuration 3
Register
GEN_PMCON_3
D31:F0:A4h
0
0
Power Button Override
Status
(PRBTNOR_STS)
Power Management 1
Status Register
(PM1_STS)
PMBase + 00h
11
0
RTC Event Enable
(RTC_EN)
Power Management 1
Enable Register
(PM1_EN)
PMBase + 02h
10
0
Sleep Type (SLP_TYP)
Power Management 1
Control (PM1_CNT)
PMBase + 04h
12:10
0
PME_EN
General Purpose
Event 0 Enables
Register (GPE0_EN)
PMBase + 2Ch
11
0
BATLOW_EN
(Mobile/Ultra Mobile
Only)
General Purpose
Event 0 Enables
Register (GPE0_EN)
PMBase + 2Ch
10
0
RI_EN
General Purpose
Event 0 Enables
Register (GPE0_EN)
PMBase + 2Ch
8
0
Intel ® ICH7 Family Datasheet
Functional Description
Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)
Bit Name
Register
Location
Bit(s)
Default
State
NEWCENTURY_STS
TCO1 Status Register
(TCO1_STS)
TCOBase + 04h
7
0
Intruder Detect
(INTRD_DET)
TCO2 Status Register
(TCO2_STS)
TCOBase + 06h
0
0
Top Swap (TS)
Backed Up Control
Register (BUC)
Chipset Config
Registers:Offset 3414h
0
X
PATA Reset State (PRS)
(Mobile/Ultra Mobile
Only)
Backed Up Control
Register (BUC)
Chipset Config
Registers:Offset 3414h
1
1
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
Note:
The GPI strap technique to clear CMOS requires multiple steps to implement. The
system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again.
Warning:
Clearing CMOS, using a jumper on VccRTC, must not be implemented.
5.13
Processor Interface (D31:F0)
The ICH7 interfaces to the processor with a variety of signals
• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,
IGNNE#, CPUSLP# (supported only on desktop platforms), CPUPWRGD
• Standard Input from processor: FERR#
• Intel SpeedStep® technology output to processor: CPUPWRGOOD (In mobile/Ultra
Mobile configurations)
Most ICH7 outputs to the processor use standard buffers. The ICH7 has separate
V_CPU_IO signals that are pulled up at the system level to the processor voltage, and
thus determines VOH for the outputs to the processor.
5.13.1
Processor Interface Signals
This section describes each of the signals that interface between the ICH7 and the
processor(s). Note that the behavior of some signals may vary during processor reset,
as the signals are used for frequency strapping.
5.13.1.1
A20M# (Mask A20)
The A20M# signal is active (low) when both of the following conditions are true:
• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).
Intel ® ICH7 Family Datasheet
149
Functional Description
5.13.1.2
INIT# (Initialization)
The INIT# signal is active (driven low) based on any one of several events described in
Table 5-22. When any of these events occur, INIT# is driven low for 16 PCI clocks, then
driven high.
Note:
The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if
INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after
STPCLK# goes inactive.
This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as
INIT3_3V# is functionally identical to INIT#, but signaling at 3.3 V.
Table 5-22. INIT# Going Active
Cause of INIT# Going Active
Comment
Shutdown special cycle from processor.
PORT92 write, where INIT_NOW (bit 0) transitions
from a 0 to a 1.
PORTCF9 write, where SYS_RST (bit 1) was a 0
and RST_CPU (bit 2) transitions from 0 to 1.
0 to 1 transition on RCIN# must occur
before the Intel® ICH7 will arm INIT# to be
generated again.
RCIN# input signal goes low. RCIN# is expected
to be driven by the external microcontroller
(KBC).
CPU BIST
5.13.1.3
NOTE: RCIN# signal is expected to be high
during S3HOT and low during
S3COLD, S4, and S5 states.
Transition on the RCIN# signal in
those states (or the transition to
those states) may not necessarily
cause the INIT# signal to be
generated to the processor.
To enter BIST, software sets CPU_BIST_EN
bit and then does a full processor reset
using the CF9 register.
FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error)
The ICH7 supports the coprocessor error function with the FERR#/IGNNE# pins. The
function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset
31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If
FERR# is driven active by the processor, IRQ13 goes active (internally). When it
detects a write to the COPROC_ERR register (I/O Register F0h), the ICH7 negates the
internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven
inactive. IGNNE# is not driven active unless FERR# is active.
150
Intel ® ICH7 Family Datasheet
Functional Description
Figure 5-7.
Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
If COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an
internal IRQ13, nor will the write to F0h generate IGNNE#.
5.13.1.4
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Table 5-23.
Table 5-23. NMI Sources
Cause of NMI
5.13.1.5
Comment
SERR# goes active (either internally,
externally via SERR# signal, or via
message from (G)MCH)
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#)
The ICH7 power management logic controls these active-low signals. Refer to
Section 5.14 for more information on the functionality of these signals.
Note:
CPU Sleep (CPUSLP#) is supported only on desktop platforms.
5.13.1.6
CPU Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. This signal represents a
logical AND of the ICH7’s PWROK and VRMPWRGD signals.
5.13.1.7
Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only)
This active-low signal controls the internal gating of the processor’s core clock. This
signal asserts before and deasserts after the STP_CPU# signal to effectively stop the
processor’s clock (internally) in the states in which STP_CPU# can be used to stop the
processor’s clock externally.
Intel ® ICH7 Family Datasheet
151
Functional Description
5.13.2
Dual-Processor Issues (Desktop Only)
5.13.2.1
Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently
than for uniprocessor designs.
Table 5-24. DP Signal Differences
Signal
A20M# / A20GATE
Difference
Generally not used, but still supported by Intel® ICH7.
Used for S1 State as well as preparation for entry to S3–S5
5.13.2.2
STPCLK#
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both processors.
FERR# / IGNNE#
Generally not used, but still supported by ICH7.
Power Management
For multiple-processor (or Multiple-core) configurations in which more than one Stop
Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and
only pass the last one through to the ICH7. This prevents the ICH7 from getting out of
sync with the processor on multiple STPCLK# assertions.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be
connected to both processors. However, for ACPI implementations, the BIOS must
indicate that the ICH7 only supports the C1 state for dual-processor designs.
In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by
the processors. The ICH7 also has the option to assert the processor’s SLP# signal
(CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the
transition to the S1 state), the processors will not be executing code that is likely to
delay the Stop-Grant cycles.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1
state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both
processors will lose power. Upon exit from those states, the processors will have their
power restored.
152
Intel ® ICH7 Family Datasheet
Functional Description
5.14
Power Management (D31:F0)
5.14.1
Features
• Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI)
providing power and thermal management
— ACPI 24-Bit Timer
— Software initiated throttling of processor performance for Thermal and Power
Reduction
— Hardware Override to throttle processor performance if system too hot
— SCI and SMI# Generation
• PCI PME# signal for Wake Up from Low-Power states
• System Clock Control
— (Mobile/Ultra Mobile Only) ACPI C2 state: Stop Grant (using STPCLK# signal)
halts processor’s instruction stream
— (Mobile/Ultra Mobile Only) ACPI C3 State: Ability to halt processor clock (but
not memory clock)
— (Mobile/Ultra Mobile Only) ACPI C4 State: Ability to lower processor voltage.
— (Mobile/Ultra Mobile Only) CLKRUN# Protocol for PCI Clock Starting/Stopping
• System Sleep State Control
— ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor’s instruction
stream (only STPCLK# active, and CPUSLP# optional)
— ACPI S3 state — Suspend to RAM (STR)
— ACPI S4 state — Suspend-to-Disk (STD)
— ACPI G2/S5 state — Soft Off (SOFF)
— Power Failure Detection and Recovery
• Streamlined Legacy Power Management for APM-Based Systems
5.14.2
Intel® ICH7 and System Power States
Table 5-25 shows the power states defined for ICH7-based platforms. The state names
generally match the corresponding ACPI states.
Table 5-25. General Power States for Systems Using Intel® ICH7 (Sheet 1 of 2)
State/
Substates
Legacy Name / Description
G0/S0/C0
Full On: Processor operating. Individual devices may be shut down to save
power. The different processor operating levels are defined by Cx states, as
shown in Table 5-26. Within the C0 state, the Intel® ICH7 can throttle the
processor using the STPCLK# signal to reduce power consumption. The throttling
can be initiated by software or by the operating system or BIOS.
G0/S0/C1
Auto-Halt: Processor has executed an AutoHalt instruction and is not executing
code. The processor snoops the bus and maintains cache coherency.
G0/S0/C2
(Mobile/Ultra
Mobile Only)
Intel ® ICH7 Family Datasheet
Stop-Grant: The STPCLK# signal goes active to the processor. The processor
performs a Stop-Grant cycle, halts its instruction stream, and remains in that
state until the STPCLK# signal goes inactive. In the Stop-Grant state, the
processor snoops the bus and maintains cache coherency.
153
Functional Description
Table 5-25. General Power States for Systems Using Intel® ICH7 (Sheet 2 of 2)
State/
Substates
Legacy Name / Description
G0/S0/C3
(Mobile/Ultra
Mobile Only)
Stop-Clock: The STPCLK# signal goes active to the processor. The processor
performs a Stop-Grant cycle, halts its instruction stream. ICH7 then asserts
DPSLP# followed by STP_CPU#, which forces the clock generator to stop the
processor clock. This is also used for Intel SpeedStep® technology support.
Accesses to memory (by graphics, PCI, or internal units) is not permitted while in
a C3 state.
G0/S0/C4
(Mobile/Ultra
Mobile Only)
Stop-Clock with Lower Processor Voltage: This closely resembles the G0/
S0/C3 state. However, after the ICH7 has asserted STP_CPU#, it then lowers the
voltage to the processor. This reduces the leakage on the processor. Prior to
exiting the C4 state, the ICH7 increases the voltage to the processor.
G1/S1
Stop-Grant: Similar to G0/S0/C2 state. ICH7 also has the option to assert the
CPUSLP# signal to further reduce processor power consumption (Desktop only).
Note: The behavior for this state is slightly different when supporting iA64
processors.
G1/S3
Suspend-To-RAM (STR): The system context is maintained in system DRAM,
but power is shut off to non-critical circuits. Memory is retained, and refreshes
continue. All clocks stop except RTC clock.
G1/S4
Suspend-To-Disk (STD): The context of the system is maintained on the disk.
All power is then shut off to the system except for the logic required to resume.
G2/S5
Soft Off (SOFF): System context is not maintained. All power is shut off except
for the logic required to restart. A full boot is required when waking.
G3
Mechanical OFF (MOFF): System context not maintained. All power is shut off
except for the RTC. No “Wake” events are possible, because the system does not
have any power. This state occurs if the user removes the batteries, turns off a
mechanical switch, or if the system power supply is at a level that is insufficient
to power the “waking” logic. When system power returns, transition will depends
on the state just prior to the entry to G3 and the AFTERG3 bit in the
GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-33 for more details.
Table 5-26 shows the transitions rules among the various states. Note that transitions
among the various states may appear to temporarily transition through intermediate
states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/
C2 states. These intermediate transitions and states are not listed in the table.
154
Intel ® ICH7 Family Datasheet
Functional Description
Table 5-26. State Transition Rules for Intel® ICH7
Present
State
Transition Trigger
Next State
•
•
•
•
•
•
Processor halt instruction
Level 2 Read
Level 3 Read (Mobile/Ultra Mobile
Only)
Level 4 Read (Mobile/Ultra Mobile
Only)
SLP_EN bit set
Power Button Override
Mechanical Off/Power Failure
•
•
•
G0/S0/C1
G0/S0/C2
G0/S0/C2, G0/S0/C3 or G0/S0/C4 depending on C4onC3_EN bit
(D31:F0:Offset A0h:bit 7) and
BM_STS_ZERO_EN bit (D31:F0:Offset
A9h:bit 2) (Mobile/Ultra Mobile Only)
G1/Sx or G2/S5 state
G2/S5
G3
•
•
•
•
Any Enabled Break Event
STPCLK# goes active
Power Button Override
Power Failure
•
•
•
•
G0/S0/C0
G0/S0/C2
G2/S5
G3
•
•
•
•
Any Enabled Break Event
Power Button Override
Power Failure
Previously in C3/C4 and bus masters
idle
•
•
•
•
G0/S0/C0
G2/S5
G3
C3 or C4 - depending on PDME bit (D31:F0:
Offset A9h: bit 4)
G0/S0/C3
(Mobile/
Ultra
Mobile
Only)
•
•
•
•
•
Any Enabled Break Event
Any Bus Master Event
Power Button Override
Power Failure
Previously in C4 and bus masters idle
•
•
G0/S0/C0
G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:
bit 3) is set, else G0/S0/C0
G2/S5
G3
C4 - depending on PDME bit (D31:F0: Offset
A9h: bit 4
G0/S0/C4
(Mobile/
Ultra
Mobile
Only)
•
•
•
•
Any Enabled Break Event
Any Bus Master Event
Power Button Override
Power Failure
G1/S1,
G1/S3, or
G1/S4
•
•
•
G2/S5
G3
•
•
•
G0/S0/C0
G0/S0/C1
G0/S0/C2
(Mobile/
Ultra
Mobile
Only)
•
•
•
•
•
•
•
•
G0/S0/C0
G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:
bit 3) is set, else G0/S0/C0
G2/S5
G3
Any Enabled Wake Event
Power Button Override
Power Failure
•
•
•
G0/S0/C0 (See Note 2)
G2/S5
G3
•
•
Any Enabled Wake Event
Power Failure
•
•
G0/S0/C0 (See Note 2)
G3
•
Power Returns
•
Optional to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed or other
wake event). (See Note 1 and 2)
NOTES:
1.
Some wake events can be preserved through power failure.
2.
Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is
inactive in mobile/Ultra Mobile configurations.
Intel ® ICH7 Family Datasheet
155
Functional Description
5.14.3
System Power Planes
The system has several independent power planes, as described in Table 5-27. Note
that when a particular power plane is shut off, it should go to a 0 V level.
s
Table 5-27. System Power Plane
Plane
Controlled
By
Description
The SLP_S3# signal can be used to cut the power to the processor
completely. For mobile/Ultra Mobile systems, the DPRSLPVR
support allows lowering the processor’s voltage during the C4
state.
CPU
SLP_S3#
signal
SLP_S3#
signal
(S3COLD)
MAIN
or
SLP_S4#
signal
(S3HOT)
MEMORY
DEVICE[n]
5.14.4
SLP_S4#
signal
SLP_S5#
signal
GPIO
S3HOT: The new S3HOT state keeps more of the platform logic,
including the Intel® ICH7 core well, powered to reduce the cost of
external power plane logic. SLP_S3# is only used to remove power
to the processor and to shut system clocks. This impacts the board
design, but there is no specific ICH7 bit or strap needed to indicate
which option is selected.
S3COLD: When SLP_S3# goes active, power can be shut off to any
circuit not required to wake the system from the S3 state. Since
the S3 state requires that the memory context be preserved,
power must be retained to the main memory.
The processor, devices on the PCI bus, LPC I/F, and graphics will
typically be shut off when the Main power plane is shut, although
there may be small subsections powered.
S3HOT: SLP_S4# is used to cut the main power well, rather than
using SLP_S3#. This impacts the board design, but there is no
specific ICH7 bit or strap needed to indicate which option is
selected.
When the SLP_S4# goes active, power can be shut off to any
circuit not required to wake the system from the S4. Since the
memory context does not need to be preserved in the S4 state,
the power to the memory can also be shut down.
When SLP_S5# goes active, power can be shut to any circuit not
required to wake the system from the S5 state. Since the memory
context does not need to be preserved in the S5 state, the power
to the memory can also be shut.
Individual subsystems may have their own power plane. For
example, GPIO signals may be used to control the power to disk
drives, audio amplifiers, or the display screen.
SMI#/SCI Generation
On any SMI# event taking place, ICH7 asserts SMI# to the processor, which causes it
to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is
set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI#
is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
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Intel ® ICH7 Family Datasheet
Functional Description
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see Section 10.1.14). The interrupt remains asserted until all SCI
sources are removed.
Table 5-28 shows which events can cause an SMI# and SCI. Note that some events can
be programmed to cause either an SMI# or SCI. The usage of the event for SCI
(instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI
source has a corresponding enable and status bit.
Table 5-28. Causes of SMI# and SCI (Sheet 1 of 2)
Cause1-5
SCI
SMI
Additional Enables
Where Reported
PME#
Yes
Yes
PME_EN=1
PME_STS
PME_B0 (internal EHCI
controller)
Yes
Yes
PME_B0_EN=1
PME_B0_STS
PCI Express* PME Messages
(Desktop and Mobile)
Yes
Yes
PCI Express Hot Plug
Message (Desktop and
Mobile)
Yes
Yes
Power Button Press
Yes
Yes
PWRBTN_EN=1
PWRBTN_STS
Yes
No
None
PRBTNOR_STS
6
Power Button Override )
PCI_EXP_EN=1
(Not enabled for SMI)
HOT_PLUG_EN=1
(Not enabled for SMI)
PCI_EXP_STS
HOT_PLUG_STS
RTC Alarm
Yes
Yes
RTC_EN=1
RTC_STS
Ring Indicate
Yes
Yes
RI_EN=1
RI_STS
AC ’97 wakes (Desktop and
Mobile)
Yes
Yes
AC97_EN=1
AC97_STS
USB#1 wakes
Yes
Yes
USB1_EN=1
USB1_STS
USB#2 wakes
Yes
Yes
USB2_EN=1
USB2_STS
USB#3 wakes
Yes
Yes
USB3_EN=1
USB3_STS
USB#4 wakes
Yes
Yes
USB4_EN=1
USB4_STS
THRM# pin active
Yes
Yes
THRM_EN=1
THRM_STS
ACPI Timer overflow (2.34
sec.)
Yes
Yes
TMROF_EN=1
TMROF_STS
Any GPI7
Yes
Yes
GPI[x]_Route=10 (SCI)
GPI[x]_Route=01 (SMI)
GPE0[x]_EN=1
TCO SCI Logic
Yes
No
TCOSCI_EN=1
TCOSCI_STS
TCO SCI message from
(G)MCH
Yes
No
none
MCHSCI_STS
TCO SMI Logic
No
Yes
TCO_EN=1
TCO_STS
TCO SMI — Year 2000
Rollover
No
Yes
none
NEWCENTURY_STS
TCO SMI — TCO TIMEROUT
No
Yes
none
TIMEOUT
TCO SMI — OS writes to
TCO_DAT_IN register
No
Yes
none
OS_TCO_SMI
TCO SMI — Message from
(G)MCH
No
Yes
none
MCHSMI_STS
Intel ® ICH7 Family Datasheet
GPI[x]_STS
GPE0_STS
157
Functional Description
Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2)
Cause1-5
SCI
SMI
Additional Enables
Where Reported
TCO SMI — NMI occurred
(and NMIs mapped to SMI)
No
Yes
NMI2SMI_EN=1
NMI2SMI_STS
TCO SMI — INTRUDER#
signal goes active
No
Yes
INTRD_SEL=10
INTRD_DET
TCO SMI — Change of the
BIOSWP bit from 0 to 1
No
Yes
BLD=1
BIOSWR_STS
TCO SMI — Write attempted
to BIOS
No
Yes
BIOSWP=1
BIOSWR_STS
BIOS_RLS written to
Yes
No
GBL_EN=1
GBL_STS
GBL_RLS written to
No
Yes
BIOS_EN=1
BIOS_STS
Write to B2h register
No
Yes
APMC_EN = 1
APM_STS
Periodic timer expires
No
Yes
PERIODIC_EN=1
PERIODIC_STS
64 ms timer expires
No
Yes
SWSMI_TMR_EN=1
SWSMI_TMR_STS
Enhanced USB Legacy
Support Event
No
Yes
LEGACY_USB2_EN = 1
LEGACY_USB2_STS
Enhanced USB Intel Specific
Event
No
Yes
INTEL_USB2_EN = 1
INTEL_USB2_STS
UHCI USB Legacy logic
No
Yes
LEGACY_USB_EN=1
LEGACY_USB_STS
Serial IRQ SMI reported
No
Yes
none
SERIRQ_SMI_STS
Device monitors match
address in its range
No
Yes
none
DEVMON_STS,
DEVACT_STS
SMBus Host Controller
No
Yes
SMB_SMI_EN
Host Controller Enabled
SMBus host status
reg.
SMBus Slave SMI message
No
Yes
none
SMBUS_SMI_STS
SMBus SMBALERT# signal
active
No
Yes
none
SMBUS_SMI_STS
SMBus Host Notify message
received
No
Yes
HOST_NOTIFY_INTREN
SMBUS_SMI_STS
HOST_NOTIFY_STS
(Mobile/Ultra Mobile Only)
BATLOW# assertion
Yes
Yes
BATLOW_EN=1.
BATLOW_STS
Access microcontroller 62h/
66h
No
Yes
MCSMI_EN
MCSMI_STS
SLP_EN bit written to 1
No
Yes
SMI_ON_SLP_EN=1
SMI_ON_SLP_EN_STS
NOTES:
1.
SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2.
SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3.
GBL_SMI_EN must be 1 to enable SMI.
4.
EOS must be written to 1 to re-enable SMI for the next 1.
5.
IICH7 must have SMI# fully enabled when ICH7 is also enabled to trap cycles. If SMI# is
not enabled in conjunction with the trap enabling, then hardware behavior is undefined.
6.
When a power button override first occurs, the system will transition immediately to S5.
The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)
is not cleared prior to setting SCI_EN.
7.
Only GPI[15:0] may generate an SMI# or SCI.
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Intel ® ICH7 Family Datasheet
Functional Description
5.14.4.1
PCI Express* SCI (Desktop and Mobile Only)
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, the ICH7 will set the PCI_EXP_STS bit. If
the PCI_EXP_EN bit is also set, the ICH7 can cause an SCI via the GPE1_STS register.
5.14.4.2
PCI Express* Hot-Plug (Desktop and Mobile Only)
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1
register. It is also capable of generating an SMI. However, it is not capable of
generating a wake event.
5.14.5
Dynamic Processor Clock Control
The ICH7 has extensive control for dynamically starting and stopping system clocks.
The clock control is used for transitions among the various S0/Cx states, and processor
throttling. Each dynamic clock control method is described in this section. The various
sleep states may also perform types of non-dynamic clock control.
The ICH7 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3 and C4 (in
mobile/Ultra Mobile) states.
The Dynamic Processor Clock control is handled using the following signals:
• STPCLK#: Used to halt processor instruction stream.
• (Mobile/Ultra Mobile Only) STP_CPU#: Used to stop processor’s clock
• (Mobile/Ultra Mobile Only) DPSLP#: Used to force Deeper Sleep for processor.
• (Mobile/Ultra Mobile Only) DPRSLPVR: Used to lower voltage of VRM during C4
state.
• (Mobile/Ultra Mobile Only) DPRSTP#: Used to lower voltage of VRM during C4 state
The C1 state is entered based on the processor performing an auto halt instruction.
(Mobile/Ultra Mobile Only) The C2 state is entered based on the processor reading the
Level 2 register in the ICH7. It can also be entered from C3 or C4 states if bus masters
require snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set.
(Mobile/Ultra Mobile Only) The C3 state is entered based on the processor reading the
Level 3 register in the ICH7 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit
7). This state can also be entered after a temporary return to C2 from a prior C3 or C4
state.
(Mobile/Ultra Mobile Only) The C4 state is entered based on the processor reading the
Level 4 register in the ICH7, or by reading the Level 3 register when the C4onC3_EN bit
is set. This state can also be entered after a temporary return to C2 from a prior C4
state.
A C1 state in desktop only or a C1, C2, C3, or C4 state in mobile/Ultra Mobile only ends
due to a Break event. Based on the break event, the ICH7 returns the system to C0
state.
(Mobile/Ultra Mobile Only) Table 5-29 lists the possible break events from C2, C3, or
C4. The break events from C1 are indicated in the processor’s datasheet.
Intel ® ICH7 Family Datasheet
159
Functional Description
Table 5-29. Break Events (Mobile/Ultra Mobile Only)
Breaks
from
Comment
Any unmasked interrupt goes
active
C2, C3, C4
IRQ[0:15] when using the 8259s, IRQ[0:23]
for I/O APIC. Since SCI is an interrupt, any SCI
will also be a break event.
Any internal event that cause an
NMI or SMI#
C2, C3, C4
Many possible sources
Any internal event that cause
INIT# to go active
C2, C3, C4
Could be indicated by the keyboard controller
via the RCIN input signal.
Event
Need to wake up processor so it can do snoops
Any bus master request
(internal, external or DMA, or
BM_BUSY#) goes active and
BM_RLD=1 (D31:F0:Offset
PMBASE+04h: bit 1)
Processor Pending Break Event
Indication
5.14.5.1
C3, C4
C2, C3, C4
NOTE: If the PUME bit (D31:F0: Offset A9h: bit
3) is set, then bus master activity will
NOT be treated as a break event.
Instead, there will be a return only to
the C2 state.
Only available if FERR# enabled for break event
indication (See FERR# Mux Enable in GCS,
Chipset Config Registers:Offset 3410h:bit 6)
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and
throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This
is because the processor can only perform one register access at a time and Sleep
states have higher priority than thermal throttling.
• When the SLP_EN bit is set (system going to a S1–S5 sleep state), the THTL_EN
and FORCE_THTL bits can be internally treated as being disabled (no throttling
while going to sleep state).
• (Mobile/Ultra Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level
2, Level 3, or Level 4 read then occurs, the system should immediately go and stay
in a C2, C3, or C4 state until a break event occurs. A Level 2, Level 3, or Level 4
read has higher priority than the software initiated throttling.
• (Mobile/Ultra Mobile Only) After an exit from a C2, C3, or C4 state (due to a Break
event), and if the THTL_EN or FORCE_THTL bits are still set the system will
continue to throttle STPCLK#. Depending on the time of break event, the first
transition on STPCLK# active can be delayed by up to one THRM period (1024 PCI
clocks = 30.72 µs).
• The Host controller must post Stop-Grant cycles in such a way that the processor
gets an indication of the end of the special cycle prior to the ICH7 observing the
Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a
sufficient period after the processor observes the response phase.
• (Mobile/Ultra Mobile Only) If in the C1 state and the STPCLK# signal goes active,
the processor will generate a Stop-Grant cycle, and the system should go to the C2
state. When STPCLK# goes inactive, it should return to the C1 state.
160
Intel ® ICH7 Family Datasheet
Functional Description
5.14.5.2
Deferred C3/C4 (Mobile/Ultra Mobile Only)
Due to the new DMI protocol, if there is any bus master activity (other than true isoch),
then the C0-to-C3 transition will pause at the C2 state. ICH7 will keep the processor in
a C2 state until:
• ICH7 does not detect bus master activity.
• A break event occurs. In this case, the ICH7 will perform the C2 to C0 sequence.
Note that bus master traffic is not a break event in this case.
To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be
set. This will cause the BM_STS bit to read as 0 even if some bus master activity is
present. If this is not done, then the software may avoid even attempting to go to the
C3 or C4 state if it sees the BM_STS bit as 1.
If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH7 will treat bus master
activity as a break event. When reaching the C2 state, if there is any bus master
activity, the ICH7 will return the processor to a C0 state.
5.14.5.3
POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only)
When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH7 enables a mode of
operation where standard (non-isoch) bus master activity will not be treated as a full
break event from the C3 or C4 states. Instead, these will be treated merely as bus
master events and return the platform to a C2 state, and thus allow snoops to be
performed.
After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even
if the ARB_DIS bit is set.
5.14.5.4
POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only)
After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4)
is set, the platform can return to a C3 or C4 state (depending on where it was prior to
going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will
keep the processor in a C2 state until:
• Bus masters are no longer active.
• A break event occurs. Note that bus master traffic is not a break event in this case.
5.14.6
Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)
The PCI clock can be dynamically controlled independent of any other low-power state.
This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile
Design Guide, and is transparent to software.
The Dynamic PCI Clock control is handled using the following signals:
• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
• STP_PCI#: Used to stop the system PCI clock
Note:
The 33 MHz clock to the ICH7 is “free-running” and is not affected by the STP_PCI#
signal.
Intel ® ICH7 Family Datasheet
161
Functional Description
5.14.6.1
Conditions for Checking the PCI Clock
When there is a lack of PCI activity the ICH7 has the capability to stop the PCI clocks to
conserve power. “PCI activity” is defined as any activity that would require the PCI
clock to be running.
Any of the following conditions will indicate that it is not okay to stop the PCI clock:
• Cycles on PCI or LPC
• Cycles of any internal device that would need to go on the PCI bus
• SERIRQ activity
Behavioral Description
• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH7
deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.
5.14.6.2
Conditions for Maintaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the
CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.
• When the ICH7 has tri-stated the CLKRUN# signal after deasserting it, the ICH7
then checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the ICH7 again starts
asserting the signal.
• If an internal device needs the PCI bus, the ICH7 asserts the CLKRUN# signal.
5.14.6.3
Conditions for Stopping the PCI Clock
• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,
the ICH7 stops the PCI clock by asserting the STP_PCI# signal to the clock
synthesizer.
5.14.6.4
Conditions for Re-Starting the PCI Clock
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the ICH7 observes the CLKRUN# signal asserted for 1 (free running) clock,
the ICH7 deasserts the STP_PCI# signal to the clock synthesizer within 4 (free
running) clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the
ICH7 again starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the ICH7 re-asserts CLKRUN#,
and simultaneously deasserts the STP_PCI# signal.
5.14.6.5
LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only)
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA (Mobile
only) or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC devices
running DMA or bus master cycles will not need to assert CLKRUN#, since the ICH7
asserts it on their behalf.
The LDRQ# inputs are ignored by the ICH7 when the PCI clock is stopped to the LPC
devices in order to avoid misinterpreting the request. The ICH7 assumes that only one
more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.
Upon deassertion of STP_PCI#, the ICH7 assumes that the LPC device receives its first
clock rising edge corresponding to the ICH7’s second PCI clock rising edge after the
deassertion.
162
Intel ® ICH7 Family Datasheet
Functional Description
5.14.7
Sleep States
5.14.7.1
Sleep State Overview
The ICH7 directly supports different sleep states (S1–S5) that are entered by setting
the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based
on several assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor can only perform one register access at a time. A request to Sleep
has higher priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit disables thermal throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power.
5.14.7.2
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on observing Stop-Grant cycles from the processor or
on clocks other than the RTC clock.
Table 5-30. Sleep Types
Sleep
Type
5.14.7.3
Comment
S1
Intel® ICH7 asserts the STPCLK# signal. It also has the option to assert CPUSLP#
signal (only supported on desktop platforms). This lowers the processor’s power
consumption. No snooping is possible in this state.
S3
ICH7 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical
circuits. Power is only retained to devices needed to wake from this sleeping state,
as well as to the memory.
S4
ICH7 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to
the memory subsystem. Only devices needed to wake from this state should be
powered.
S5
Same power state as S4. ICH7 asserts SLP_S3#, SLP_S4# and SLP_S5#.
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the
system to a full on state (S0), although some non-critical subsystems might still be
shut off and have to be brought back manually. For example, the hard disk may be shut
off during a sleep state, and have to be enabled via a GPIO pin before it can be used.
Upon exit from the ICH7-controlled Sleep states, the WAK_STS bit is set. The possible
causes of Wake Events (and their restrictions) are shown in Table 5-31.
Note:
(Mobile/Ultra Mobile Only) If the BATLOW# signal is asserted, ICH7 does not attempt to
wake from an S1–S5 state, even if the power button is pressed. This prevents the
system from waking when the battery power is insufficient to wake the system. Wake
events that occur while BATLOW# is asserted are latched by the ICH7, and the system
wakes after BATLOW# is de-asserted.
Intel ® ICH7 Family Datasheet
163
Functional Description
Table 5-31. Causes of Wake Events
States Can
Wake From1
Cause
RTC Alarm
S1–S52
Power Button
S1–S5
How Enabled
Set RTC_EN bit in PM1_EN register
Always enabled as Wake event
GPE0_EN register
GPI[0:15]
S1–S52
Classic USB
S1–S5
Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in
GPE0_EN register
LAN
(Desktop and
Mobile only)
S1–S5
Will use PME#. Wake enable set with LAN logic.
RI#
S1–S52
Set RI_EN bit in GPE0_EN register
AC ‘97 / Intel
High Definition
Audio
S1–S52
Set AC97_EN bit in GPE0_EN register
Primary PME#
S1–S5
PME_B0_EN bit in GPE0_EN register
Secondary PME#
S1–S5
Set PME_EN bit in GPE0_EN register.
PCI_EXP_WAKE#
(Desktop and
Mobile only)
S1–S5
PCI_EXP_WAKE bit3
NOTE: GPIs that are in the core well are not capable of waking
the system from sleep states where the core well is not
powered.
®
PCI_EXP PME
Message
(Desktop and
Mobile only)
S1
SMBALERT#
S1–S5
Always enabled as Wake event
SMBus Slave
Message
S1–S5
Wake/SMI# command always enabled as a Wake event.
Note: SMBus Slave Message can wake the system from S1–
S5, as well as from S5 due to Power Button Override.
SMBus Host
Notify message
received
S1–S5
HOST_NOTIFY_WKEN bit SMBus Slave Command register.
Reported in the SMB_WAK_STS bit in the GPEO_STS register.
Must use the PCI Express* WAKE# pin rather than messages
for wake from S3,S4, or S5.
NOTES:
1.
If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events
are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in
Table 5-55), and Hard Reset System (See Command Type 4 in Table 5-55).
2.
This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and
SLP_TYP bits via software, or if there is a power failure.
3.
When the WAKE# pin is active and the PCI Express device is enabled to wake the system,
the ICH7 will wake the platform.
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Intel ® ICH7 Family Datasheet
Functional Description
It is important to understand that the various GPIs have different levels of functionality
when used as wake events. The GPIs that reside in the core power well can only
generate wake events from sleep states where the core well is powered. Also, only
certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in
ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events.
Table 5-32. GPI Wake Events
GPI
Power Well
Wake From
Notes
GPI[12, 7:0]
Core
S1
ACPI
Compliant
GPI[15:13,11:8]
Resume
S1–S5
ACPI
Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to the ICH7 are
insignificant.
5.14.7.4
PCI Express* WAKE# Signal and PME Event Message (Desktop and
Mobile only)
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using
the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go
active in the GPE_STS register.
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, ICH7 will set the PCI_EXP_STS bit.
5.14.7.5
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When the ICH7 exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCCstandby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The ICH7 monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note:
Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Intel ® ICH7 Family Datasheet
165
Functional Description
Table 5-33. Transitions Due to Power Failure
5.14.8
State at Power Failure
AFTERG3_EN bit
Transition When Power Returns
S0, S1, S3
1
0
S5
S0
S4
1
0
S4
S0
S5
1
0
S5
S0
Thermal Management
The ICH7 has mechanisms to assist with managing thermal problems in the system.
5.14.8.1
THRM# Signal
The THRM# signal is used as a status input for a thermal sensor. Based on the THRM#
signal going active, the ICH7 generates an SMI# or SCI (depending on SCI_EN).
If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit
will be set. This is an indicator that the thermal threshold has been exceeded. If the
THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be
generated (depending on the SCI_EN bit being set).
The power management software (BIOS or ACPI) can then take measures to start
reducing the temperature. Examples include shutting off unwanted subsystems, or
halting the processor.
By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated
when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to
turn off the cooling methods.
Note:
THRM# assertion does not cause a TCO event message in S3 or S4. The level of the
signal is not reported in the heartbeat message.
5.14.8.2
Processor Initiated Passive Cooling
This mode is initiated by software setting the THTL_EN (PMBASE+10h:bit 4) or
FORCE_THTL (PMBASE+10h:bit 8) bits.
Software sets the THTL_DTY (PMBASE+10h:bits 3:1) or THRM_DTY (PMBASE+10h:bits
7:5) bits to select throttle ratio and THTL_EN or FORCE_THTL bits to enable the
throttling.
Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of
87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as
little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and
cooling) of the processor depends on the instruction stream, because the processor is
allowed to finish the current instruction. Furthermore, the ICH7 waits for the STOPGRANT cycle before starting the count of the time the STPCLK# signal is active.
166
Intel ® ICH7 Family Datasheet
Functional Description
5.14.8.3
THRM# Override Software Bit
The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI
software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH7
starts throttling using the ratio in the THRM_DTY field.
When this bit is cleared the ICH7 stops throttling, unless the THTL_EN bit is set
(indicating that ACPI software is attempting throttling).
If both the THTL_EN and FORCE_THTL bits are set, then the ICH7 should use the duty
cycle defined by the THRM_DTY field, not the THTL_DTY field.
5.14.8.4
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH7 can be used to turn on/off
a fan.
5.14.9
Event Input Signals and Their Usage
The ICH7 has various input signals that trigger specific events. This section describes
those signals and how they should be used.
5.14.9.1
PWRBTN# (Power Button)
The ICH7 PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16
ms de-bounce on the input. The state transition descriptions are included in Table 5-34.
Note that the transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to Power Button Override
Function section below for further detail.
Table 5-34. Transitions Due to Power Button
Present
State
Event
Transition/Action
Comment
S0/Cx
PWRBTN# goes low
SMI# or SCI generated
(depending on SCI_EN)
Software typically initiates a
Sleep state
S1–S5
PWRBTN# goes low
Wake Event. Transitions to
S0 state
Standard wakeup
G3
PWRBTN# pressed
None
S0–S4
Intel ® ICH7 Family Datasheet
PWRBTN# held low
for at least 4
consecutive seconds
Unconditional transition to
S5 state
No effect since no power
Not latched nor detected
No dependence on processor
(e.g., Stop-Grant cycles) or
any other subsystem
167
Functional Description
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–
S4), even if PWROK is not active. In this case, the transition to the G2/S5 state should
not depend on any particular response from the processor (e.g., a Stop-Grant cycle),
nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable via the
PWRBTN_LVL bit.
Note:
The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The
4-second timer starts counting when the ICH7 is in a S0 state. If the PWRBTN# signal
is asserted and held active when the system is in a suspend state (S1–S5), the
assertion causes a wake event. Once the system has resumed to the S0 state, the 4second timer starts.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a
4-second press of the Power Button is already defined as an Unconditional Power down,
the power button timer will be forced to inactive while the power-cycle timer is in
progress. Once the
power-cycle timer has expired, the Power Button awakes the system. Once the
minimum SLP_S4# power cycle expires, the Power Button must be pressed for another
4 to 5 seconds to create the Override condition to S5.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional
Sleep button. It differs from the power button in that it only is a request to go from S0
to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the
Sleep Button cannot.
Although the ICH7 does not include a specific signal designated as a Sleep Button, one
of the GPIO signals can be used to create a “Control Method” Sleep Button. See the
Advanced Configuration and Power Interface, Version 2.0b for implementation details.
5.14.9.2
RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.
Table 5-35 shows when the wake event is generated or ignored in different states. If in
the G0/S0/Cx states, the ICH7 generates an interrupt based on RI# active, and the
interrupt will be set up as a Break event.
Table 5-35. Transitions Due to RI# Signal
Note:
168
Present State
Event
RI_EN
Event
S0
RI# Active
X
Ignored
S1–S5
RI# Active
0
Ignored
1
Wake Event
Filtering/Debounce on RI# will not be done in ICH7. It can be in modem or external.
Intel ® ICH7 Family Datasheet
Functional Description
5.14.9.3
PME# (PCI Power Management Event)
The PME# signal comes from a PCI device to request that the system be restarted. The
PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs
when the PME# signal goes from high to low. No event is caused when it goes from low
to high.
There is also an internal PME_B0 bit. This is separate from the external PME# signal
and can cause the same effect.
5.14.9.4
SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the
ICH7 attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to
go idle. If the SMBus is idle when the pin is detected active, the reset occurs
immediately; otherwise, the counter starts. If at any point during the count the SMBus
goes idle the reset occurs. If, however, the counter expires and the SMBus is still active,
a reset is forced upon the system even though activity is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the
SYSRESET# input remains asserted or not. It cannot occur again until SYS_RESET#
has been detected inactive after the debounce logic, and the system is back to a full S0
state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then
SYS_RESET# will result in a full power cycle reset.
5.14.9.5
THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the
ICH7 immediately transitions to an S5 state. However, since the processor has
overheated, it does not respond to the ICH7’s STPCLK# pin with a stop grant special
cycle. Therefore, the ICH7 does not wait for one. Immediately upon seeing THRMTRIP#
low, the ICH7 initiates a transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5#
low, and set the CTS bit. The transition looks like a power button override.
It is extremely important that when a THRMTRIP# event occurs, the ICH7 power down
immediately without following the normal S0 -> S5 path. This path may be taken in
parallel, but ICH7 must immediately enter a power down state. It does this by driving
SLP_S3#, SLP_S4#, and SLP_S5# immediately after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very
unlikely) that components around it, such as the ICH7, are no longer executing cycles
properly. Therefore, if THRMTRIP# goes active, and the ICH7 is relying on state
machine logic to perform the power down, the state machine may not be working, and
the system will not power down.
The ICH7 follows this flow for THRMTRIP#.
1. At boot (PLTRST# low), THRMTRIP# ignored.
2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#,
SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts.
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay
active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the
thermal trip event.
4. If S5 state reached, go to step #1, otherwise stay here. If the ICH7 does not reach
S5, the ICH7 does not reboot until power is cycled.
Intel ® ICH7 Family Datasheet
169
Functional Description
During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and
PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry,
power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or
PWROK = 0, or VRMPWRGD/VGATE = 0.
Note:
A thermal trip event will:
• Set the AFTERG3_EN bit
• Clear the PWRBTN_STS bit
• Clear all the GPE0_EN register bits
• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave
receiving message and not set due to SMBAlert
5.14.9.6
BM_BUSY# (Mobile/Ultra Mobile Only)
The BM_BUSY# signal is an input from a graphics component to indicate if it is busy. If
prior to going to the C3 state, the BM_BUSY# signal is active, then the BM_STS bit will
be set. If after going to the C3 state, the BM_BUSY# signal goes back active, the ICH7
will treat this as if one of the PCI REQ# signals went active. This is treated as a break
event.
5.14.10
ALT Access Mode
Before entering a low power state, several registers from powered down parts may
need to be saved. In the majority of cases, this is not an issue, as registers have read
and write paths. However, several of the ISA compatible registers are either read only
or write only. To get data out of
write-only registers, and to restore data into read-only registers, the ICH7 implements
an ALT access mode.
If the ALT access mode is entered and exited after reading the registers of the ICH7
timer (8254), the timer starts counting faster (13.5 ms). The following steps listed
below can cause problems:
1. BIOS enters ALT access mode for reading the ICH7 timer related registers.
2. BIOS exits ALT access mode.
3. BIOS continues through the execution of other needed steps and passes control to
the operating system.
After getting control in step #3, if the operating system does not reprogram the system
timer again, the timer ticks may be happening faster than expected. For example DOS
and its associated software assume that the system timer is running at 54.6 ms and as
a result the time-outs in the software may be happening faster than expected.
Operating systems (e.g., Microsoft Windows* 98, Windows* 2000, and Windows NT*)
reprogram the system timer and therefore do not encounter this problem.
For some other loss (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back
to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT
access mode before entering the suspend state it is not necessary to restore the timer
contents after the exit from ALT access mode.
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Functional Description
5.14.10.1
Write Only Registers with Read Paths in ALT Access Mode
The registers described in Table 5-36 have read paths in ALT access mode. The access
number field in the table indicates which register will be returned per access to that
port.
Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
Restore Data
I/O
Addr
00h
01h
02h
03h
04h
05h
06h
07h
# of
Rds
Restore Data
I/O
Addr
# of
Rds
Access
Data
Access
Data
1
DMA Chan 0 base address low
byte
1
Timer Counter 0 status, bits
[5:0]
2
DMA Chan 0 base address high
byte
2
Timer Counter 0 base count
low byte
1
DMA Chan 0 base count low
byte
3
Timer Counter 0 base count
high byte
2
DMA Chan 0 base count high
byte
4
Timer Counter 1 base count
low byte
1
DMA Chan 1 base address low
byte
5
Timer Counter 1 base count
high byte
2
DMA Chan 1 base address high
byte
6
Timer Counter 2 base count
low byte
1
DMA Chan 1 base count low
byte
7
Timer Counter 2 base count
high byte
2
DMA Chan 1 base count high
byte
41h
1
Timer Counter 1 status, bits
[5:0]
1
DMA Chan 2 base address low
byte
42h
1
Timer Counter 2 status, bits
[5:0]
2
DMA Chan 2 base address high
byte
70h
1
Bit 7 = NMI Enable,
Bits [6:0] = RTC Address
1
DMA Chan 2 base count low
byte
2
DMA Chan 2 base count high
byte
1
DMA Chan 3 base address low
byte
2
DMA Chan 3 base address high
byte
1
DMA Chan 3 base count low
byte
2
DMA Chan 3 base count high
byte
2
2
2
2
2
2
2
2
Intel ® ICH7 Family Datasheet
40h
C4h
C6h
C8h
7
1
DMA Chan 5 base address low
byte
2
DMA Chan 5 base address
high byte
1
DMA Chan 5 base count low
byte
2
DMA Chan 5 base count high
byte
1
DMA Chan 6 base address low
byte
2
DMA Chan 6 base address
high byte
2
2
2
171
Functional Description
Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
Restore Data
I/O
Addr
# of
Rds
Access
Restore Data
Data
I/O
Addr
20h
Data
DMA Chan 6 base count low
byte
DMA Chan 0–3 Request
2
DMA Chan 6 base count high
byte
3
DMA Chan 0 Mode:
Bits(1:0) = 00
1
DMA Chan 7 base address low
byte
4
DMA Chan 1 Mode:
Bits(1:0) = 01
2
DMA Chan 7 base address
high byte
5
DMA Chan 2 Mode:
Bits(1:0) = 10
1
DMA Chan 7 base count low
byte
6
DMA Chan 3 Mode: Bits(1:0)
= 11.
2
DMA Chan 7 base count high
byte
1
PIC ICW2 of Master controller
1
DMA Chan 4–7 Command1
2
PIC ICW3 of Master controller
2
DMA Chan 4–7 Request
3
PIC ICW4 of Master controller
3
DMA Chan 4 Mode: Bits(1:0)
= 00
4
PIC OCW1 of Master
controller2
4
DMA Chan 5 Mode: Bits(1:0)
= 01
5
PIC OCW2 of Master controller
5
DMA Chan 6 Mode: Bits(1:0)
= 10
6
PIC OCW3 of Master controller
6
DMA Chan 7 Mode: Bits(1:0)
= 11.
7
PIC ICW2 of Slave controller
8
PIC ICW3 of Slave controller
9
PIC ICW4 of Slave controller
DMA Chan 0–3 Command2
2
6
12
Access
1
1
CAh
08h
# of
Rds
10
PIC OCW1 of Slave controller1
11
PIC OCW2 of Slave controller
12
PIC OCW3 of Slave controller
CCh
CEh
D0h
2
2
2
6
NOTES:
1.
Bits 5, 3, 1, and 0 return 0.
2.
The OCW1 register must be read before entering ALT access mode.
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Intel ® ICH7 Family Datasheet
Functional Description
5.14.10.2
PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in Table 5-37.
Table 5-37. PIC Reserved Bits Return Values
5.14.10.3
PIC Reserved Bits
Value Returned
ICW2(2:0)
000
ICW4(7:5)
000
ICW4(3:2)
00
ICW4(0)
0
OCW2(4:3)
00
OCW3(7)
0
OCW3(5)
Reflects bit 6
OCW3(4:3)
01
Read Only Registers with Write Paths in ALT Access Mode
The registers described in Table 5-38 have write paths to them in ALT access mode.
Software restores these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
Table 5-38. Register Write Accesses in ALT Access Mode
I/O Address
Register Write Value
08h
DMA Status Register for channels 0–3.
D0h
DMA Status Register for channels 4–7.
5.14.11
System Power Supplies, Planes, and Signals
5.14.11.1
Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#
The usage of SLP_S3# and SLP_S4# depends on whether the platform is configured for
S3HOT and S3COLD.
S3HOT
The SLP_S3# output signal is used to cut power only to the processor and associated
subsystems and to optionally stop system clocks.
S3COLD
The SLP_S3# output signal can be used to cut power to the system core supply, since it
only goes active for the STR state (typically mapped to ACPI S3). Power must be
maintained to the ICH7 resume well, and to any other circuits that need to generate
Wake signals from the STR state.
Intel ® ICH7 Family Datasheet
173
Functional Description
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard.
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is
saved on the disk. Cutting power to the memory may be done via the power supply, or
by external FETs to the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to
the motherboard.
5.14.11.2
SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in the ICH7 provides a mechanism to fully cycle
the power to the DRAM and/or detect if the power is not cycled for a minimum time.
Note:
To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
5.14.11.3
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values.
Note:
1. SYSRESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets, and avoids improperly
reporting power failures.
2. If the PWROK input is used to implement the system reset button, the ICH7 does
not provide any mechanism to limit the amount of time that the processor is held in
reset. The platform must externally ensure that maximum reset assertion
specifications are met.
3. If a design has an active-low reset button electrically AND’d with the PWROK signal
from the power supply and the processor’s voltage regulator module the ICH7
PWROK_FLR bit will be set. The ICH7 treats this internally as if the RSMRST# signal
had gone active. However, it is not treated as a full power failure. If PWROK goes
inactive and then active (but RSMRST# stays high), then the ICH7 reboots
(regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low
before PWROK goes high, then this is a full power failure, and the reboot policy is
controlled by the AFTERG3 bit.
4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by the ICH7.
5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.
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Intel ® ICH7 Family Datasheet
Functional Description
5.14.11.4
CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is
internally AND’d with the PWROK signal that comes from the system power supply.
5.14.11.5
VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the
regulator are on and within specification. VRMPWRGD may go active before or after the
PWROK from the main power supply. ICH7 has no dependency on the order in which
these two signals go active or inactive.
5.14.11.6
BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not
sufficient power. It also causes an SMI# if the system is already in an S0 state.
5.14.11.7
Controlling Leakage and Power Consumption
during Low-Power States
To control leakage in the system, various signals tri-state or go low during some lowpower states.
General principles:
• All signals going to powered down planes (either internally or externally) must be
either tri-stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to
avoid the power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input
(perhaps to some other device). Floating inputs can cause extra power
consumption.
Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes are tri-stated or
driven low.
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Functional Description
5.14.12
Clock Generators
The clock generator is expected to provide the frequencies shown in Table 5-39.
Table 5-39. Intel® ICH7 Clock Inputs
Clock
Domain
SATA_CLK
(Desktop and
Mobile Only)
DMI_CLK
Frequency
Source
Usage
100 MHz
Main Clock
Generator
Used by SATA controller. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Main Clock
Generator
Used by DMI and PCI Express*. Stopped in S3 ~ S5
based on SLP_S3# assertion.
Differential
100 MHz
Differential
Desktop Only: Free-running PCI Clock to Intel® ICH7.
Stopped in S3 ~ S5 based on SLP_S3# assertion.
5.14.12.1
Mobile Only: Free-running (not affected by STP_PCI#
PCI Clock to ICH7. This is not the system PCI clock.
This clock must keep running in S0 while the system
PCI clock may stop based on CLKRUN# protocol.
Stopped in S3 ~ S5 based on SLP_S3# assertion.
PCICLK
33 MHz
Main Clock
Generator
CLK48
48.000
MHz
Main Clock
Generator
Used by USB controllers and Intel® High Definition
Audio controller. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
CLK14
14.318
MHz
Main Clock
Generator
Used by ACPI timers. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
ACZ_BIT_CLK
(Desktop and
Mobile)
12.288
MHz
AC ’97
Codec
LAN_CLK
(Desktop and
Mobile Only)
0.8 to
50 MHz
LAN
Connect
AC-link. Control policy is determined by the clock
source.
NOTE: Becomes clock output when Intel High
Definition Audio is enabled.
LAN Connect Interface. Control policy is determined by
the clock source.
Clock Control Signals from Intel® ICH7 to Clock
Synthesizer (Mobile/Ultra Mobile Only)
The clock generator is assumed to have a direct connection from the following ICH7
signals:
• STP_CPU#: Stops processor clocks in C3 and C4 states
• STP_PCI#: Stops system PCI clocks (not the ICH7 free-running 33 MHz clock) due
to CLKRUN# protocol
• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop
clocks in S3HOT and on the way to S3COLD to S5.
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Functional Description
5.14.13
Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting when
accesses are attempted to idle subsystems.
However, the operating system is assumed to be at least APM enabled. Without APM
calls, there is no quick way to know when the system is idle between keystrokes. The
ICH7 does not support burst modes.
5.14.13.1
APM Power Management (Desktop Only)
The ICH7 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and
Enable register, generates an SMI# once per minute. The SMI handler can check for
system activity by reading the DEVACT_STS register. If none of the system bits are set,
the SMI handler can increment a software counter. When the counter reaches a
sufficient number of consecutive minutes with no activity, the SMI handler can then put
the system into a lower power state.
If there is activity, various bits in the DEVACT_STS register will be set. Software clears
the bits by writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions
on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.
5.14.13.2
Mobile APM Power Management (Mobile/Ultra Mobile Only)
In mobile/ultra mobile systems, there are additional requirements associated with
device power management. To handle this, the ICH7 has specific SMI# traps available.
The following algorithm is used:
1. The periodic SMI# timer checks if a device is idle for the required time. If so, it puts
the device into a low-power state and sets the associated SMI# trap.
2. When software (not the SMI# handler) attempts to access the device, a trap occurs
(the cycle does not really go to the device and an SMI# is generated).
3. The SMI# handler turns on the device and turns off the trap
The SMI# handler exits with an I/O restart. This allows the original software to
continue.
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Functional Description
5.15
System Management (D31:F0)
The ICH7 provides various functions to make a system easier to manage and to lower
the Total Cost of Ownership (TCO) of the system. In addition, ICH7 provides integrated
ASF Management support. Features and functions can be augmented via external A/D
converters and GPIO, as well as an external microcontroller.
The following features and functions are supported by the ICH7:
• Processor present detection
— Detects if processor fails to fetch the first instruction after reset
• Various Error detection (such as ECC Errors) Indicated by host controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed
— INTRUDER# allowed to go active in any power state, including G3
• Detection of bad Firmware Hub programming
— Detects if data on first read is FFh (indicates unprogrammed Firmware Hub)
• Ability to hide a PCI device
— Allows software to hide a PCI device in terms of configuration space through
the use of a device hide register (See Section 7.1.56)
• Integrated ASF Management support (Desktop and Mobile Only)
Note:
Voltage ID from the processor can be read via GPI signals.
5.15.1
Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management
functionality be provided without the aid of an external microcontroller.
5.15.1.1
Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor
fails to fetch the first instruction after reset, the TCO timer times out twice and the
ICH7 asserts PLTRST#.
5.15.1.2
Handling an Intruder
The ICH7 has an input signal, INTRUDER#, that can be attached to a switch that is
activated by the system’s case being open. This input has a two RTC clock debounce. If
INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the
TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH7 to
cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition
to the S5 state by writing to the SLP_EN bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by
clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI
if the intruder function is not required.
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Functional Description
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written
as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes
inactive. Note that this is slightly different than a classic sticky bit, since most sticky
bits would remain active indefinitely when the signal goes active and would
immediately go inactive when a 1 is written to the bit.
Note:
The INTRD_DET bit resides in the ICH7’s RTC well, and is set and cleared
synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET
(by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65
µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be
asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set.
Note:
If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET
bit, the bit remains set and the SMI is generated again immediately. The SMI handler
can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal
goes inactive and then active again, there will not be further SMIs, since the
INTRD_SEL bits would select that no SMI# be generated.
5.15.1.3
Detecting Improper Firmware Hub Programming
The ICH7 can detect the case where the Firmware Hub is not programmed. This results
in the first instruction fetched to have a value of FFh. If this occurs, the ICH7 sets the
BAD_BIOS bit, which can then be reported via the Heartbeat and Event reporting using
an external, Alert on LAN* enabled LAN controller (See Section 5.15.2).
5.15.2
Heartbeat and Event Reporting via SMBus (Desktop and
Mobile Only)
The ICH7 integrated LAN controller supports ASF heartbeat and event reporting
functionality when used with the 82562EM or 82562EX Platform LAN Connect
component. This allows the integrated LAN controller to report messages to a network
management console without the aid of the system processor. This is crucial in cases
where the processor is malfunctioning or cannot function due to being in a low-power
state.
All heartbeat and event messages are sent on the SMBus interface. This allows an
external LAN controller to act upon these messages if the internal LAN controller is not
used.
The basic scheme is for the ICH7 integrated LAN controller to send a prepared Ethernet
message to a network management console. The prepared message is stored in the
non-volatile EEPROM that is connected to the ICH7.
Messages are sent by the LAN controller either because a specific event has occurred,
or they are sent periodically (also known as a heartbeat). The event and heartbeat
messages have the exact same format. The event messages are sent based on events
occurring. The heartbeat messages are sent every 30 to 32 seconds. When an event
occurs, the ICH7 sends a new message and increments the SEQ[3:0] field. For
heartbeat messages, the sequence number does not increment.
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Functional Description
The following rules/steps apply if the system is in a G0 state and the policy is for the
ICH7 to reboot the system after a hardware lockup:
1. On detecting the lockup, the SECOND_TO_STS bit is set. The ICH7 may send up to
1 Event message to the LAN controller. The ICH7 then attempts to reboot the
processor.
2. If the reboot at step 1 is successful then the BIOS should clear the
SECOND_TO_STS bit. This prevents any further Heartbeats from being sent. The
BIOS may then perform addition recovery/boot steps. (See note 2, below.)
3. If the reboot attempt in step 1 is not successful, the timer will timeout a third time.
At this point the system has locked up and was unsuccessful in rebooting. The ICH7
does not attempt to automatically reboot again. The ICH7 starts sending a
message every heartbeat period
(30–32 seconds). The heartbeats continue until some external intervention occurs
(reset, power failure, etc.).
4. After step 3 (unsuccessful reboot after third timeout), if the user does a Power
Button Override, the system goes to an S5 state. The ICH7 continues sending the
messages every heartbeat period.
5. After step 4 (power button override after unsuccessful reboot) if the user presses
the Power Button again, the system should wake to an S0 state and the processor
should start executing the BIOS.
6. If step 5 (power button press) is successful in waking the system, the ICH7
continues sending messages every heartbeat period until the BIOS clears the
SECOND_TO_STS bit. (See note 2)
7. If step 5 (power button press) is unsuccessful in waking the system, the ICH7
continues sending a message every heartbeat period. The ICH7 does not attempt
to automatically reboot again. The ICH7 starts sending a message every heartbeat
period (30–32 seconds). The heartbeats continue until some external intervention
occurs (reset, power failure, etc.).
(See note 3)
8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using
a button that pulses PWROK low or via the message on the SMBus slave I/F), the
ICH7 attempts to reset the system.
9. After step 8 (reset attempt) if the reset is successful, the BIOS is run. The ICH7
continues sending a message every heartbeat period until the BIOS clears the
SECOND_TO_STS bit. (See note 2)
10. After step 8 (reset attempt), if the reset is unsuccessful, the ICH7 continues
sending a message every heartbeat period. The ICH7 does not attempt to reboot
the system again without external intervention. (See note 3)
The following rules/steps apply if the system is in a G0 state and the policy is for the
ICH7 to not reboot the system after a hardware lockup.
1. On detecting the lockup the SECOND_TO_STS bit is set. The ICH7 sends a message
with the Watchdog (WD) Event status bit set (and any other bits that must also be
set). This message is sent as soon as the lockup is detected, and is sent with the
next (incremented) sequence number.
2. After step 1, the ICH7 sends a message every heartbeat period until some external
intervention occurs.
3. Rules/steps 4–10 apply if no user intervention (resets, power button presses,
SMBus reset messages) occur after a third timeout of the watchdog timer. If the
intervention occurs before the third timeout, then jump to rule/step 11.
4. After step 3 (third timeout), if the user does a Power Button Override, the system
goes to an S5 state. The ICH7 continues sending heartbeats at this point.
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Functional Description
5. After step 4 (power button override), if the user presses the power button again,
the system should wake to an S0 state and the processor should start executing
the BIOS.
6. If step 5 (power button press) is successful in waking the system, the ICH7
continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See
note 2)
7. If step 5 (power button press) is unsuccessful in waking the system, the ICH7
continues sending heartbeats. The ICH7 does not attempt to reboot the system
again until some external intervention occurs (reset, power failure, etc.). (See note
3)
8. After step 3 (third timeout), if a reset is attempted (using a button that pulses
PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to
reset the system.
9. If step 8 (reset attempt) is successful, the BIOS is run. The ICH7 continues sending
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
10. If step 8 (reset attempt), is unsuccessful, the ICH7 continues sending heartbeats.
The ICH7 does not attempt to reboot the system again without external
intervention. Note: A system that has locked up and can not be restarted with
power button press is probably broken (bad power supply, short circuit on some
bus, etc.)
11. This and the following rules/steps apply if the user intervention (power button
press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog
timer.
12. After step 1 (second timeout), if the user does a Power Button Override, the system
goes to an S5 state. The ICH7 continues sending heartbeats at this point.
13. After step 12 (power button override), if the user presses the power button again,
the system should wake to an S0 state and the processor should start executing
the BIOS.
14. If step 13 (power button press) is successful in waking the system, the ICH7
continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See
note 2)
15. If step 13 (power button press) is unsuccessful in waking the system, the ICH7
continues sending heartbeats. The ICH7 does not attempt to reboot the system
again until some external intervention occurs (reset, power failure, etc.). (See note
3)
16. After step 1 (second timeout), if a reset is attempted (using a button that pulses
PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to
reset the system.
17. If step 16 (reset attempt) is successful, the BIOS is run. The ICH7 continues
sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
18. If step 16 (reset attempt), is unsuccessful, the ICH7 continues sending heartbeats.
The ICH7 does not attempt to reboot the system again without external
intervention. (See note 3)
If the system is in a G1 (S1–S4) state, the ICH7 sends a heartbeat message every 30–
32 seconds. If an event occurs prior to the system being shutdown, the ICH7
immediately sends an event message with the next incremented sequence number.
After the event message, the ICH7 resumes sending heartbeat messages.
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Functional Description
Note:
Notes for previous two numbered lists.
1. Normally, the ICH7 does not send heartbeat messages while in the G0 state
(except in the case of a lockup). However, if a hardware event (or heartbeat)
occurs just as the system is transitioning into a G0 state, the hardware continues to
send the message even though the system is in a G0 state (and the status bits may
indicate this).
These messages are sent via the SMBus. The ICH7 abides by the SMBus rules
associated with collision detection. It delays starting a message until the bus is idle,
and detects collisions. If a collision is detected the ICH7 waits until the bus is idle,
and tries again.
2. WARNING: It is important the BIOS clears the SECOND_TO_STS bit, as the alerts
interfere with the LAN device driver from working properly. The alerts reset part of
the LAN controller and would prevent an operating system’s device driver from
sending or receiving some messages.
3. A system that has locked up and can not be restarted with power button press is
assumed to have broken hardware (bad power supply, short circuit on some bus,
etc.), and is beyond ICH7’s recovery mechanisms.
4. A spurious alert could occur in the following sequence:
— The processor has initiated an alert using the SEND_NOW bit
— During the alert, the THRM#, INTRUDER# or GPIO11 changes state
— The system then goes to a non-S0 state.
Once the system transitions to the non-S0 state, it may send a single alert with an
incremental SEQUENCE number.
5. An inaccurate alert message can be generated in the following scenario
— The system successfully boots after a second watchdog Timeout occurs.
— PWROK goes low (typically due to a reset button press) or a power button
override occurs (before the SECOND_TO_STS bit is cleared).
— An alert message indicating that the processor is missing or locked up is
generated with a new sequence number.
Table 5-40 shows the data included in the Alert on LAN messages.
Table 5-40. Heartbeat Message Data (Sheet 1 of 2)
Field
182
Comment
Cover Tamper Status
1 = This bit is set if the intruder detect bit is set (INTRD_DET).
Temp Event Status
1 = This bit is set if the Intel® ICH7 THERM# input signal is asserted.
Processor Missing Event
Status
1 = This bit is set if the processor failed to fetch its first instruction.
TCO Timer Event Status
1 = This bit is set when the TCO timer expires.
Software Event Status
1 = This bit is set when software writes a 1 to the SEND_NOW bit.
Unprogrammed
Firmware Hub Event
Status
1 = First BIOS fetch returned a value of FFh, indicating that the
Firmware Hub has not yet been programmed (still erased).
GPIO Status
1 = This bit is set when GPIO11 signal is high.
0 = This bit is cleared when GPIO11 signal is low.
An event message is triggered on an transition of GPIO11.
Intel ® ICH7 Family Datasheet
Functional Description
Table 5-40. Heartbeat Message Data (Sheet 2 of 2)
Field
5.16
Comment
SEQ[3:0]
This is a sequence number. It initially is 0, and increments each time
the ICH7 sends a new message. Upon reaching 1111, the sequence
number rolls over to 0000. MSB (SEQ3) sent first.
System Power State
00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first
MESSAGE1
Will be the same as the MESSAGE1 Register. MSB sent first.
MESSAGE2
Will be the same as the MESSAGE2 Register. MSB sent first.
WDSTATUS
Will be the same as the WDSTATUS Register. MSB sent first.
IDE Controller (D31:F1)
The ICH7 IDE controller features one sets of interface signals that can be enabled, tristated or driven low.
The IDE interfaces of the ICH7 can support several types of data transfers:
• Programmed I/O (PIO): Processor is in control of the data transfer.
• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although
it does not use the 8237 in the ICH7. This protocol off loads the processor from
moving data. This allows higher transfer rate of up to 16 MB/s.
• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 33 MB/s.
• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 66 MB/s.
• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 100 MB/s.
Note:
ICH7-U Ultra Mobile only supports one IDE device.
5.16.1
PIO Transfers
The ICH7 IDE controller includes both compatible and fast timing modes. The fast
timing modes can be enabled only for the IDE data ports. All other transactions to the
IDE registers are run in single transaction mode with compatible timings.
Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1); one
device (connector drive 0) on ICH7-U Ultra Mobile. The IDE_TIMP and IDE_TIMS
Registers permit different timing modes to be programmed for drive 0 and drive 1 of
the same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each
drive by programming the IDE I/O Configuration register and the Synchronous DMA
Control and Timing registers. When a drive is enabled for synchronous DMA mode
operation, the DMA transfers are executed with the synchronous DMA timings. The PIO
transfers are executed using compatible timings or fast timings if also enabled.
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Functional Description
5.16.1.1
PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and
shutdown latency. Startup latency is incurred when a PCI master cycle targeting the
IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup
latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of
the read and write strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time.
Recovery time is provided so that transactions may occur back-to-back on the IDE
interface (without incurring startup and shutdown latency) without violating minimum
cycle periods for the IDE interface. The command strobe assertion width for the
enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,
or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set
to 1, 2, 3, or 4 PCI clocks.
If IORDY is asserted when the initial sample point is reached, no wait-states are added
to the command strobe assertion length. If IORDY is negated when the initial sample
point is reached, additional wait-states are added. Since the rising edge of IORDY must
be synchronized, at least two additional PCI clocks are added.
Shutdown latency is incurred after outstanding scheduled IDE data port transactions
(either a non-empty write post buffer or an outstanding read prefetch cycles) have
completed and before other transactions can proceed. It provides hold time on the
DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and
DIOW#). Shutdown latency is two PCI clocks in duration.
The IDE timings for various transaction types are shown in Table 5-41.
Table 5-41.
IDE Transaction Timings (PCI Clocks)
Startup
Latency
IORDY
Sample
Point (ISP)
Recovery Time
(RCT)
Shutdown
Latency
Non-Data Port Compatible
4
11
22
2
Data Port Compatible
3
6
14
2
Fast Timing Mode
2
2–5
1–4
2
IDE Transaction Type
5.16.1.2
IORDY Masking
The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point
(ISP) on a drive by drive basis via the IDETIM Register.
5.16.1.3
PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two
back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is
enabled for all timings, not just enhanced timing. For compatible timings, a shutdown
and startup latency is incurred between the two, 16-bit halves of the IDE transaction.
This ensures that the chip selects are deasserted for at least two PCI clocks between
the two cycles.
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Functional Description
5.16.1.4
PIO IDE Data Port Prefetching and Posting
The ICH7 can be programmed via the IDETIM registers to allow data to be posted to
and prefetched from the IDE data ports.
Data prefetching is initiated when a data port read occurs. The read prefetch eliminates
latency to the IDE data ports and allows them to be performed back to back for the
highest possible PIO data transfer rates. The first data port read of a sector is called the
demand read. Subsequent data port reads from the sector are called prefetch reads.
The demand read and all prefetch reads much be of the same size (16 or 32 bits) –
software must not mix 32-bit and 16-bit reads.
Data posting is performed for writes to the IDE data ports. The transaction is completed
on the PCI bus after the data is received by the ICH7. The ICH7 then runs the IDE cycle
to transfer the data to the drive. If the ICH7 write buffer is non-empty and an unrelated
(non-data or opposite channel) IDE transaction occurs, that transaction will be stalled
until all current data in the write buffer is transferred to the drive. Only 16-bit buffer
writes are supported.
5.16.2
Bus Master Function
The ICH7 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master
channel is provided for the IDE connector. By performing the IDE data transfer as a PCI
Bus master, the ICH7 off-loads the processor and improves system performance in
multitasking environments. For Desktop and Mobile, both devices attached to the
connector can be programmed for bus master transfers, but only one device can be
active at a time.
5.16.2.1
Physical Region Descriptor Format
The physical memory region to be transferred is described by a Physical Region
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.
The data transfer proceeds until all regions described by the PRDs in the table have
been transferred.
Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8
bytes in length. The first 4 bytes specify the byte address of a physical memory region.
This memory region must be DWord-aligned and must not cross a 64-KB boundary. The
next two bytes specify the size or transfer count of the region in bytes (64-KB limit per
region). A value of 0 in these two bytes indicates 64-KB (thus the minimum transfer
count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this is the final PRD in
the Descriptor table. Bus master operation terminates when the last descriptor has
been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of
the Base Address is masked and byte enables are asserted for all read transfers. When
writing data, bit 1 of the Base Address is not masked and if set, will cause the lower
Word byte enables to be deasserted for the first DWord transfer. The write to PCI
typically consists of a 32-byte cache line. If valid data ends prior to end of the cache
line, the byte enables will be deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to
or greater than the size of the disk transfer request. If greater than the disk transfer
request, the driver must terminate the bus master transaction (by setting bit 0 in the
Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal
transfer completion.
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185
Functional Description
Figure 5-8.
Physical Region Descriptor Table Entry
Main Memory
Memory
Region
Byte 3
Byte 2
Byte 1
Byte 0
Memory Region Physical Base Address [31:1]
EOT
5.16.2.2
Reserved
Byte Count [15:1]
o
o
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO
transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to
program fast timing mode for DMA transactions only. This is useful for IDE devices
whose DMA transfer timings are faster than its PIO transfer timings. The IDE device
DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is
deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI
clock and no more transfers take place until DMA request is asserted again.
5.16.2.3
Interrupts
The ICH7 can generate interrupts based upon a signal coming from the PATA device, or
due to the completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and
active high. The PATA host controller generates IDEIRQ.
When the ICH7 IDE controller is operating independently from the SATA controller
(D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA
controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in
turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV
(D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is
emulating the logical secondary channel (MAP.MV = 1h), the PATA channel will emulate
the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA
controller in combined mode is emulating the logical primary channel (MAP.MV=2h),
IDEIRQ will generate IRQ15.
Note:
IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.
Note:
The combined mode is not supported on ICH7-U Ultra Mobile. ICH7-U does not contain
a SATA controller.
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Functional Description
5.16.2.4
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following
steps are required:
1. Software prepares a PRD table in system memory. The PRD table must be DWordaligned and must not cross a 64-KB boundary.
2. Software provides the starting address of the PRD Table by loading the PRD Table
Pointer Register. The direction of the data transfer is specified by setting the Read/
Write Control bit. The interrupt bit and Error bit in the Status register are cleared.
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the
Command Register. The first entry in the PRD table is fetched and loaded into two
registers which are not visible by software, the Current Base and Current Count
registers. These registers hold the current value of the address and byte count
loaded from the PRD table. The value in these registers is only valid when there is
an active command to an IDE device.
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the
IDE device. The IDE device and the host controller may or may not throttle the
transfer several times. When the last data transfer for a region has been completed
on the IDE interface, the next descriptor is fetched from the table. The descriptor
contents are loaded into the Current Base and Current Count registers.
7. At the end of the transfer, the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command
register. It then reads the controller status followed by the drive status to
determine if the transfer completed successfully.
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data
transfers terminate when the physical region described by the last PRD in the table has
been completely transferred. The active bit in the Status Register is reset and the
DDRQ signal is masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state)
when a terminal count condition exists; that is, the current region descriptor has the
EOL bit set and that region has been exhausted. The buffer is also flushed (write state)
or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register
is set. Software that reads the status register and finds the Error bit reset, and either
the Active bit reset or the Interrupt bit set, can be assured that all data destined for
system memory has been transferred and that data is valid in system memory.
Table 5-42 describes how to interpret the Interrupt and Active bits in the Status
Register after a DMA transfer has started.
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Functional Description
Table 5-42. Interrupt/Active Bit Interaction Definition
Interrupt
Active
Description
0
1
DMA transfer is in progress. No interrupt has been generated by the IDE
device.
0
The IDE device generated an interrupt. The controller exhausted the
Physical Region Descriptors. This is the normal completion case where
the size of the physical memory regions was equal to the IDE device
transfer size.
1
The IDE device generated an interrupt. The controller has not reached
the end of the physical memory regions. This is a valid completion case
where the size of the physical memory regions was larger than the IDE
device transfer size.
0
This bit combination signals an error condition. If the Error bit in the
status register is set, then the controller has some problem transferring
data to/from memory. Specifics of the error have to be determined using
bus-specific information. If the Error bit is not set, then the PRD's
specified a smaller size than the IDE transfer size.
1
1
0
5.16.2.5
Error Conditions
IDE devices are sector based mass storage devices. The drivers handle errors on a
sector basis; either a sector is transferred successfully or it is not. A sector is
512 bytes.
If the IDE device does not complete the transfer due to a hardware or software error,
the command will eventually be stopped by the driver setting Command Start bit to 0
when the driver times out the disk transaction. Information in the IDE device registers
help isolate the cause of the problem.
If the controller encounters an error while doing the bus master transfers it will stop
the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in
the Bus Master IDE Status register. The controller does not generate an interrupt when
this happens. The device driver can use device specific information (PCI Configuration
Space Status register and IDE Drive Register) to determine what caused the error.
Whenever a requested transfer does not complete properly, information in the IDE
device registers (Sector Count) can be used to determine how much of the transfer was
completed and to construct a new PRD table to complete the requested operation. In
most cases the existing PRD table can be used to complete the operation.
5.16.3
Ultra ATA/100/66/33 Protocol
The ICH7 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for
a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to
33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and Ultra ATA/
100 can achieve read transfer rates up to 100 MB/s and write transfer rates up to
88.9 MB/s.
The Ultra ATA/100/66/33 definition also incorporates a Cyclic Redundancy Checking
(CRC-16) error checking protocol.
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Functional Description
5.16.3.1
Operation
Initial setup programming consists of enabling and performing the proper configuration
of the ICH7 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH7, this
consists of enabling synchronous DMA mode and setting up appropriate Synchronous
DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE
programming model is followed. Once programmed, the drive and ICH7 control the
transfer of data via the Ultra ATA/100/66/33 protocol. The actual data transfer consists
of three phases, a start-up phase, a data transfer phase, and a burst termination
phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to
begin the transfer, the ICH7 asserts DMACK# signal. When DMACK# signal is asserted,
the host controller drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the
ICH7 deasserts STOP, waits for the IDE device to assert DMARDY#, and then drives the
first data word and STROBE signal. For read cycles, the ICH7 tri-states the DD lines,
deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word
and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (ICH7 –
writes, IDE device – reads) providing data and toggling STROBE. Data is transferred
(latched by receiver) on each rising and falling edge of STROBE. The transmitter can
pause the burst by holding STROBE high or low, resuming the burst by again toggling
STROBE. The receiver can pause the burst by deasserting DMARDY# and resumes the
transfers by asserting DMARDY#. The ICH7 pauses a burst transaction to prevent an
internal line buffer over or under flow condition, resuming once the condition has
cleared. It may also pause a transaction if the current PRD byte count has expired,
resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst
termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data.
The ICH7 can stop a burst by asserting STOP, with the IDE device acknowledging by
deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the ICH7
acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a
high level. The ICH7 then drives the CRC value onto the DD lines and deassert
DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH7
terminates a burst transfer if it needs to service the opposite IDE channel, if a
Programmed I/O (PIO) cycle is executed to the IDE channel currently running the
burst, or upon transferring the last data from the final PRD.
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Functional Description
5.16.4
Ultra ATA/33/66/100 Timing
The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA
Timing register and the IDE Configuration register. Different timings can be
programmed for each drive in the system. The Base Clock frequency for each drive is
selected in the IDE Configuration register. The Cycle Time (CT) and Ready to Pause
(RP) time (defined as multiples of the Base Clock) are programmed in the Synchronous
DMA Timing Register. The Cycle Time represents the minimum pulse width of the data
strobe (STROBE) signal. The Ready to Pause time represents the number of Base Clock
periods that the ICH7 waits from deassertion of DMARDY# to the assertion of STOP
when it desires to stop a burst read transaction.
Note:
The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle
Time (CT) must be set for three Base Clocks. The ICH7 thus toggles the write strobe
signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means
that the ICH7 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For
read transfers, the read strobe is driven by the ATA/100 device, and the ICH7 supports
reads at the maximum rate of 100 MB/s.
5.16.5
ATA Swap Bay
To support PATA swap bay, the ICH7 allows the IDE output signals to be tri-stated and
input buffers to be turned off. This should be done prior to the removal of the drive. The
output signals can also be driven low. This can be used to remove charge built up on
the signals. Configuration bits are included in the IDE I/O Configuration register, offset
54h in the IDE PCI configuration space.
In a PATA swap bay operation, an IDE device is removed and a new one inserted while
the IDE interface is powered down and the rest of the system is in a fully powered-on
state (SO). During a PATA swap bay operation, if the operating system executes cycles
to the IDE interface after it has been powered down it will cause the ICH7 to hang the
system that is waiting for IORDY to be asserted from the drive.
To correct this issue, the following BIOS procedures are required for performing an IDE
swap:
1. Program IDE SIG_MODE (Configuration register at offset 54h) to 10b (drive low
mode).
2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing reg.). This prevents the
ICH7 from waiting for IORDY assertion when the operating system accesses the
IDE device after the IDE drive powers down, and ensures that 0s are always be
returned for read cycles that occur during swap operation.
Warning:
Software should not attempt to control the outputs (either tri-state or driving low),
while an IDE transfer is in progress. Unpredictable results could occur, including a
system lockup.
5.16.6
SMI Trapping
Device 31:Function 1: Offset C0h (see Section 15.1.26) contain control for generating
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–
1F7h and 3F6h). Accesses to one of these ranges with the appropriate bit set causes
the cycle to not be forwarded to the IDE controller, and for an SMI# to be generated. If
an access to the Bus-Master IDE registers occurs while trapping is enabled for the
device being accessed, then the register is updated, an SMI# is generated, and the
device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating
that a trap occurred.
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Functional Description
5.17
SATA Host Controller (D31:F2) (Desktop and
Mobile Only)
The SATA function in the ICH7 has dual modes of operation to support different
operating system conditions. In the case of Native IDE enabled operating systems, the
ICH7 has separate PCI functions for serial and parallel ATA (“enhanced mode”). To
support legacy operating systems, there is only one PCI function for both the serial and
parallel ATA ports if functionality from both SATA and PATA devices is desired
(“combined mode”).
The MAP register, Section 12.1.33, provides the ability to share PCI functions. When
sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,
Function 1 (IDE controller) is hidden by software writing to the Function Disable
Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used.
The ICH7 SATA controller features four (desktop only) / two (mobile only) sets of
interface signals (ports) that can be independently enabled or disabled (they cannot be
tri-stated or driven low). Each interface is supported by an independent DMA controller.
The ICH7 SATA controller interacts with an attached mass storage device through a
register interface that is equivalent to that presented by a traditional IDE host adapter.
The host software follows existing standards and conventions when accessing the
register interface and follows standard command protocol conventions.
Table 5-43 lists ICH7 SATA Feature support information. Table 5-44 contains
descriptions for the SATA features listed in Table 5-43.
Note:
SATA interface transfer rates are independent of UDMA mode settings. SATA interface
transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode
reported by the SATA device or the system BIOS.
Table 5-43. SATA Features Support in Intel® ICH7
ICH7 & ICH7-M
(AHCI/RAID Disabled)
ICH7 & ICH7-M
(AHCI/RAID Enabled)
Native Command Queing
(NCQ)
N/A
Supported
Auto Activate for DMA
N/A
Supported
Hot Plug Support
N/A
Supported
Asynchronous Signal
Recovery
N/A
Supported
Feature
Supported
Supported
(Desktop Only)
(Desktop Only)
ATAPI Asynchronous
Notification
N/A
Supported
Host Initiated Power
Management
N/A
3 Gb/s Transfer Rate
Staggered Spin-Up
Supported
(Mobile Only)
Supported
Supported
Command Completion
Coalescing
N/A
N/A
Port Multiplier
N/A
N/A
External SATA
N/A
N/A
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Functional Description
Table 5-44. SATA Feature Description
Feature
Description
Native Command Queing
(NCQ)
Allows the device to reorder commands for more efficient
data transfers
Auto Activate for DMA
Collapses a DMA Setup then DMA Activate sequence into a
DMA Setup only
Hot Plug Support
Allows for device detection without power being applied and
ability to connect and disconnect devices without prior
notification to the system
Asynchronous Signal
Recovery
Provides a recovery from a loss of signal or establishing
communication after hot plug
3 Gb/s Transfer Rate
Capable of data transfers up to 3Gb/s
ATAPI Asynchronous
Notification
A mechanism for a device to send a notification to the host
that the device requires attention
Host Initiated Power
Management
Capability for the host controller to request Partial and
Slumber interface power states
Staggered Spin-Up
Enables the host the ability to spin up hard drives
sequentially to prevent power load problems on boot
Command Completion
Coalescing
Reduces interrupt and completion overhead by allowing a
specified number of commands to complete and then
generating an interrupt to process the commands
Port Multiplier
A mechanism for one active host connection to
communicate with multiple devices
External SATA
Technology that allows for an outside the box connection of
up to 2 meters (when using the cable defined in SATA-IO)
5.17.1
Theory of Operation
5.17.1.1
Standard ATA Emulation
The ICH7 contains a set of registers that shadow the contents of the legacy IDE
registers. The behavior of the Command and Control Block registers, PIO, and DMA
data transfers, resets, and interrupts are all emulated.
Note:
The ICH7 will assert INTR when the master device completes the EDD command
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
5.17.1.2
48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed via writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
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Functional Description
If software clears bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
5.17.2
SATA Swap Bay Support
Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SATA host controller
without special support from AHCI and the proper board hardware. However, the ICH7
does provide for basic SATA swap bay support using the PSC register configuration bits
and power management flows. A device can be powered down by software and the port
can then be disabled, allowing removal and insertion of a new device.
Note:
This SATA swap bay operation requires board hardware (implementation specific),
BIOS, and operating system support.
5.17.3
Intel® Matrix Storage Technology Configuration (Intel®
ICH7R, ICH7DH, and ICH7-M DH Only)
The Intel® Matrix Storage Technology offers several diverse options for RAID
(redundant array of independent disks) to meet the needs of the end user. AHCI
support provides higher performance and alleviates disk bottlenecks by taking
advantage of the independent DMA engines that each SATA port offers in ICH7.
• RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for
data intensive applications such as video editing.
• Data security is offered thru RAID Level 1, which performs mirroring.
• RAID Level 10 (ICH7R/ICH7DH only) provides high levels of storage performance
with data protection, combining the fault-tolerance of RAID Level 1 with the
performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates
can be achieved on systems that require both performance and fault-tolerance.
RAID Level 10 requires 4 hard drives, and provides the capacity of two drives.
• RAID Level 5 (ICH7R/ICH7DH only) provides highly efficient storage while
maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it
across all disks, fault tolerance of any single drive is achieved while only consuming
1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or
a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction
rates, with a medium write rate. RAID 5 is well suited for applications that require
high amounts of storage while maintaining fault tolerance.
By using the ICH7’s built-in Intel Matrix Storage Technology, there is no loss of PCI
resources (request/grant pair) or add-in card slot.
Intel Matrix Storage Technology is not available in all ICH7 components. ICH7-M DH
supports RAID Level 0, 1. See Section 1.2.
Intel Matrix Storage Technology functionality requires the following items:
1. ICH7 component enabled for Intel Matrix Storage Technology (see Section 1.2)
2. Intel® Matrix Storage Manager RAID Option ROM must be on the platform
3. Intel® Matrix Storage Manager drivers, most recent revision.
4. At least two SATA hard disk drives (minimum depends on RAID configuration).
Intel Matrix Storage Technology is not available in the following configurations:
1. The SATA controller in compatible mode.
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Functional Description
5.17.3.1
Intel® Matrix Storage Manager RAID Option ROM
The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that
is easily integrated into any System BIOS. When in place, it provides the following
three primary functions:
• Provides a text mode user interface that allows the user to manage the RAID
configuration on the system in a pre-operating system environment. Its feature set
is kept simple to keep size to a minimum, but allows the user to create & delete
RAID volumes and select recovery options when problems occur.
• Provides boot support when using a RAID volume as a boot disk. It does this by
providing Int13 services when a RAID volume needs to be accessed by DOS
applications (such as NTLDR) and by exporting the RAID volumes to the System
BIOS for selection in the boot order.
• At each boot up, provides the user with a status of the RAID volumes and the
option to enter the user interface by pressing CTRL-I.
5.17.4
Power Management Operation
Power management of the ICH7 SATA controller and ports will cover operations of the
host controller and the SATA wire.
5.17.4.1
Power State Mappings
The D0 PCI power management state for device is supported by the ICH7 SATA
controller.
SATA devices may also have multiple power states. From parallel ATA, three device
states are supported through ACPI. They are:
• D0 – Device is working and instantly available.
• D1 – device enters when it receives a STANDBY IMMEDIATE command. Exit latency
from this state is in seconds
• D3 – from the SATA device’s perspective, no different than a D1 state, in that it is
entered via the STANDBY IMMEDIATE command. However, an ACPI method is also
called which will reset the device and then cut its power.
Each of these device states are subsets of the host controller’s D0 state.
Finally, SATA defines three PHY layer power states, which have no equivalent mappings
to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and active
• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer
than 10 ns
• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to
10 ms.
Since these states have much lower exit latency than the ACPI D1 and D3 states, the
SATA controller defines these states as sub-states of the device D0 state.
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Functional Description
Figure 5-9.
SATA Power States
Power
Intel® ICH SATA Controller = D0
Device = D0
PHY =
Ready
PHY =
Partial
PHY =
Slumber
Device = D1
PHY =
Off (port
disabled)
PHY =
Slumber
PHY =
Off (port
disabled)
Device = D3
PHY =
Slumber
PHY =
Off (port
disabled)
Resume Latency
5.17.4.2
Power State Transitions
5.17.4.2.1
Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would
be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the
interface can have power saved while no commands are pending. The SATA controller
defines PHY layer power management (as performed via primitives) as a driver
operation from the host side, and a device proprietary mechanism on the device side.
The SATA controller accepts device transition types, but does not issue any transitions
as a host. All received requests from a SATA device will be ACKed.
When an operation is performed to the SATA controller such that it needs to use the
SATA cable, the controller must check whether the link is in the Partial or Slumber
states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the
SATA device must perform the same action.
5.17.4.2.2
Device D1, D3 States
These states are entered after some period of time when software has determined that
no commands will be sent to this device for some time. The mechanism for putting a
device in these states does not involve any work on the host controller, other then
sending commands over the interface to the device. The command most likely to be
used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
5.17.4.2.3
Host Controller D3HOT State
After the interface and device have been put into a low power state, the SATA host
controller may be put into a low power state. This is performed via the PCI power
management registers in configuration space. There are two very important aspects to
note when using PCI power management.
1. When the power state is D3, only accesses to configuration space are allowed. Any
attempt to access the memory or I/O spaces will result in master abort.
2. When the power state is D3, no interrupts may be generated, even if they are
enabled. If an interrupt status bit is pending when the controller transitions to D0,
an interrupt may be generated.
When the controller is put into D3, it is assumed that software has properly shut down
the device and disabled the ports. Therefore, there is no need to sustain any values on
the port wires. The interface will be treated as if no device is present on the cable, and
power will be minimized.
When returning from a D3 state, an internal reset will not be performed.
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Functional Description
5.17.4.2.4
Non-AHCI Mode PME# Generation
When in non-AHCI mode (legacy mode) of operation, the SATA controller does not
generate PME#. This includes attach events (since the port must be disabled), or
interlock switch events (via the SATAGP pins).
5.17.4.3
SMI Trapping (APM)
Device 31:Function2:Offset C0h (see Section 12.1.40) contain control for generating
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–
1F7h, 3F6h, 170–177h, and 376h). If the SATA controller is in legacy mode and is using
these addresses, accesses to one of these ranges with the appropriate bit set causes
the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated.
If an access to the Bus-Master IDE registers occurs while trapping is enabled for the
device being accessed, then the register is updated, an SMI# is generated, and the
device activity status bits (Section 12.1.41) are updated indicating that a trap
occurred.
5.17.5
SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port. The
SATALED# is an active-low open-collector output. When SATALED# is low, the LED
should be active. When SATALED# is high, the LED should be inactive.
5.17.6
AHCI Operation (Intel® ICH7R, ICH7DH, and Mobile Only)
The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a
programming interface for SATA host controllers developed thru a joint industry effort
(AHCI not available on all ICH7 components; see Section 1.2). AHCI defines
transactions between the SATA controller and software and enables advanced
performance and usability with SATA. Platforms supporting AHCI may take advantage
of performance features such as no master/slave designation for SATA devices—each
device is treated as a master—and hardware assisted native command queuing. AHCI
also provides usability enhancements such as Hot-Plug. AHCI requires appropriate
software support (e.g., an AHCI driver) and for some features, hardware support in the
SATA device or additional platform hardware.
The ICH7 supports all of the mandatory features of the Serial ATA Advanced Host
Controller Interface Specification, Revision 1.0 and many optional features, such as
hardware assisted native command queuing, aggressive power management, LED
indicator support, and Hot-Plug thru the use of interlock switch support (additional
platform hardware and software may be required depending upon the implementation).
Note:
For reliable device removal notification while in AHCI operation without the use of
interlock switches (surprise removal), interface power management should be disabled
for the associated port. See Section 7.3.1 of the AHCI Specification for more
information.
Note:
When there are more than two PRD entries for a PIO data transfer that spans multiple
DATA FISes, the ICH7 does not support intermediate PRD entries that are less than 144
Words in size when the ICH7 is operating in AHCI mode at 1.5 Gb/s.
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Functional Description
5.17.7
Serial ATA Reference Clock Low Power Request
(SATACLKREQ#)
The 100 MHz Serial ATA Reference Clock (SATACLKP, SATACLKN) is implemented on the
system as a ground-terminated low-voltage differential signal pair driven by the system
Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference
Clock is not needed and may be stopped and tri-stated at the clock chip allowing
system-level power reductions.
The ICH7 uses the SATACLKREQ# output signal to communicate with the system Clock
Chip to request either SATA clock running or to tell the system clock chip that it can
stop the SATA Reference Clock. ICH7 drives this signal low to request clock running,
and tristates the signal to indicate that the SATA Reference Clock may be stopped (the
ICH7 does not drive the pin high). When the SATACLKREQ# is tristated by the ICH7,
the clock chip may stop the SATA Reference Clock within 100 ns, anytime after 100 ns,
or not at all. If the SATA Reference Clock is not already running, it will start within 100
ns after a SATACLKREQ# is driven low by the ICH7.
To enable SATA Reference Clock Low Power Request:
1. Configure GPIO35 to native function
2. Set SATA Clock Request Enable (SCRE) bit to ‘1’ (Dev 31:F2:Offset 94h:bit 28).
Note:
The reset default for SATACLKREQ# is low to insure that the SATA Reference Clock is
running after system reset.
5.18
High Precision Event Timers
This function provides a set of timers that can be used by the operating system. The
timers are defined such that in the future, the operating system may be able to assign
specific timers to used directly by specific applications. Each timer can be configured to
cause a separate interrupt.
ICH7 provides three timers. The three timers are implemented as a single counter each
with its own comparator and value register. This counter increases monotonically. Each
individual timer can generate an interrupt when the value in its value register matches
the value in the main counter.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; however, the BIOS sets this space prior to
handing it over to the operating system
(See Section 6.4). It is not expected that the operating system will move the location
of these timers once it is set by the BIOS.
5.18.1
Timer Accuracy
1. The timers are accurate over any 1 ms period to within 0.05% of the time specified
in the timer resolution fields.
2. Within any 100 microsecond period, the timer reports a time that is up to two ticks
too early or too late. Each tick is less than or equal to 100 ns, so this represents an
error of less than 0.2%.
3. The timer is monotonic. It does not return the same value on two consecutive
reads (unless the counter has rolled over and reached the same value).
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Functional Description
The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666
MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but
does have the correct average period. The accuracy of the main counter is as accurate
as the 14.3818 MHz clock.
5.18.2
Interrupt Mapping
Mapping Option #1 (Legacy Replacement Option)
In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the
mapping found in Table 5-45.
Table 5-45. Legacy Replacement Routing
Timer
8259 Mapping
APIC Mapping
Comment
0
IRQ0
IRQ2
In this case, the 8254 timer will
not cause any interrupts
1
IRQ8
IRQ8
In this case, the RTC will not cause
any interrupts.
2
Per IRQ Routing Field.
Per IRQ Routing Field
Mapping Option #2 (Standard Option)
In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its
own routing control. The supported interrupt values are IRQ 20, 21, 22, and 23.
5.18.3
Periodic vs. Non-Periodic Modes
Non-Periodic Mode
Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only
support 32-bit mode (See Section 20.1.5).
All three timers support non-periodic mode.
Consult Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this
mode.
Periodic Mode
Timer 0 is the only timer that supports periodic mode. Consult Section 2.3.9.2.2 of the
IA-PC HPET Specification for a description of this mode.
The following usage model is expected:
1. Software clears the ENABLE_CNF bit to prevent any interrupts
2. Software Clears the main counter by writing a value of 00h to it.
3. Software sets the TIMER0_VAL_SET_CNF bit.
4. Software writes the new value in the TIMER0_COMPARATOR_VAL register
5. Software sets the ENABLE_CNF bit to enable interrupts.
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Functional Description
The Timer 0 Comparator Value register cannot be programmed reliably by a single 64bit write in a 32-bit environment except if only the periodic rate is being changed
during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then
the following software solution will always work regardless of the environment:
1. Set TIMER0_VAL_SET_CNF bit
2. Set the lower 32 bits of the Timer0 Comparator Value register
3. Set TIMER0_VAL_SET_CNF bit
4. 4) Set the upper 32 bits of the Timer0 Comparator Value register
5.18.4
Enabling the Timers
The BIOS or operating system PnP code should route the interrupts. This includes the
Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge
or level type for each timer)
The Device Driver code should do the following for an available timer:
1. Set the Overall Enable bit (Offset 04h, bit 0).
2. Set the timer type field (selects one-shot or periodic).
3. Set the interrupt enable
4. Set the comparator value
5.18.5
Interrupt Levels
Interrupts directed to the internal 8259s are active high. See Section 5.10 for
information regarding the polarity programming of the I/O APIC for detecting internal
interrupts.
If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can
be shared with PCI interrupts. This may be shared although it’s unlikely for the
operating system to attempt to do this.
If more than one timer is configured to share the same IRQ (using the
TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to leveltriggered mode. Edge-triggered interrupts cannot be shared.
5.18.6
Handling Interrupts
If each timer has a unique interrupt and the timer has been configured for edgetriggered mode, then there are no specific steps required. No read is required to
process the interrupt.
If a timer has been configured to level-triggered mode, then its interrupt must be
cleared by the software. This is done by reading the interrupt status register and
writing a 1 back to the bit position for the interrupt to be cleared.
Independent of the mode, software can read the value in the main counter to see how
time has passed between when the interrupt was generated and when it was first
serviced.
If Timer 0 is set up to generate a periodic interrupt, the software can check to see how
much time remains until the next interrupt by checking the timer value register.
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Functional Description
5.18.7
Issues Related to 64-Bit Timers with 32-Bit Processors
A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit
instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.
A race condition comes up if a 32-bit processor reads the 64-bit register using two
separate 32-bit reads. The danger is that just after reading one half, the other half rolls
over and changes the first half.
If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before
reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not
want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the
TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper
32-bits are always 0.
5.19
USB UHCI Host Controllers (D29:F0, F1, F2, and
F3)
The ICH7 contains four USB 2.0 full/low-speed host controllers that support the
standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host
Controller (UHC) includes a root hub with two separate USB ports each, for a total of
eight USB ports.
• Overcurrent detection on all eight USB ports is supported. The overcurrent inputs
are not 5 V tolerant, and can be used as GPIs if not needed.
• The ICH7’s UHCI host controllers are arbitrated differently than standard PCI
devices to improve arbitration latency.
• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows
support for USB full-speed signaling rates, instead of USB I/O buffers.
5.19.1
Data Structures in Main Memory
Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1
details the data structures used to communicate control, status, and data between
software and the ICH7.
5.19.2
Data Transfers to/from Main Memory
Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1
describes the details on how HCD and the ICH7 communicate via the Schedule data
structures.
5.19.3
Data Encoding and Bit Stuffing
The ICH7 USB employs NRZI data encoding (Non-Return to Zero Inverted) when
transmitting packets. Full details on this implementation are given in the Universal
Serial Bus Specification, Revision 2.0.
5.19.4
Bus Protocol
5.19.4.1
Bit Ordering
Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb,
through to the most significant bit (MSb) last.
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Functional Description
5.19.4.2
SYNC Field
All packets begin with a synchronization (SYNC) field, which is a coded sequence that
generates a maximum edge transition density. The SYNC field appears on the bus as
IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the
input circuitry to align incoming data with the local clock and is defined to be 8 bits in
length. SYNC serves only as a synchronization mechanism and is not shown in the
following packet diagrams. The last two bits in the SYNC field are a marker that is used
to identify the first bit of the PID. All subsequent bits in the packet must be indexed
from this point.
5.19.4.3
Packet Field Formats
All packets have distinct start and end of packet delimiters. Full details are given in the
Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1.
5.19.4.4
Address Fields
Function endpoints are addressed using the function address field and the endpoint
field. Full details on this are given in the Universal Serial Bus Specification, Revision
2.0, in Section 8.3.2.
5.19.4.5
Frame Number Field
The frame number field is an 11-bit field that is incremented by the host on a per frame
basis. The frame number field rolls over upon reaching its maximum value of 7FFh, and
is sent only for SOF tokens at the start of each frame.
5.19.4.6
Data Field
The data field may range from 0 to 1023 bytes and must be an integral numbers of
bytes. Data bits within each byte are shifted out LSB first.
5.19.4.7
Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context,
these fields are considered to be protected fields. Full details on this are given in the
Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5.
5.19.5
Packet Formats
The USB protocol calls out several packet types: token, data, and handshake packets.
Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in
section 8.4.
5.19.6
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution
of transactions in the schedule, and those resulting from an ICH7 operation error. All
transaction-based sources can be masked by software through the ICH7’s Interrupt
Enable register. Additionally, individual transfer descriptors can be marked to generate
an interrupt on completion.
When the ICH7 drives an interrupt for USB, it internally drives the PIRQA# pin for USB
function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC#
pin for USB function #2, until all sources of the interrupt are cleared. In order to
accommodate some operating systems, the Interrupt Pin register must contain a
different value for each function of this new multi-function device.
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Functional Description
5.19.6.1
Transaction-Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction
in the frame has been written back to host memory. This ensures that software can
safely process through (Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-Out
A CRC/Time-Out error occurs when a packet transmitted from the ICH7 to a USB device
or a packet transmitted from a USB device to the ICH7 generates a CRC error. The ICH7
is informed of this event by a time-out from the USB device or by the ICH7’s CRC
checker generating an error on reception of the packet. Additionally, a USB bus timeout occurs when USB devices do not respond to a transaction phase within 19-bit times
of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement.
When the C_ERR field decrements to 0, the following occurs:
• The Active bit in the TD is cleared
• The Stalled bit in the TD is set
• The CRC/Time-out bit in the TD is set.
• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware
interrupt will be signaled to the system.
Interrupt on Completion
Transfer Descriptors contain a bit that can be set to cause an interrupt on their
completion. The completion of the transaction associated with that block causes the
USB Interrupt bit in the HC Status Register to be set at the end of the frame in which
the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit
in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is
set to 0 (even if it was set to 0 when initially read).
If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a
hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status
register is set either when the TD completes successfully or because of errors. If the
completion is because of errors, the USB Error bit in the HC status register is also set.
Short Packet Detect
A transfer set is a collection of data which requires more than one USB transaction to
completely move the data across the USB. An example might be a large print file which
requires numerous TDs in multiple frames to completely transfer the data. Reception of
a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or
Interrupt transfers signals the completion of the transfer set, even if there are active
TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to
set the USB Interrupt bit in the HC status register at the end of the frame in which this
event occurs. This feature streamlines the processing of input on these transfer types.
If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a
hardware interrupt is signaled to the system at the end of the frame where the event
occurred.
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Functional Description
Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Max Length, it
is said to be babbling. Since isochrony can be destroyed by a babbling device, this error
results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits
being set to 1. The C_ERR field is not decremented for a babble. The USB Error
Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware
interrupt is signaled to the system.
If an EOF babble was caused by the ICH7 (due to incorrect schedule for instance), the
ICH7 forces a bit stuff error followed by an EOP and the start of the next frame.
Stalled
This event indicates that a device/endpoint returned a STALL handshake during a
transaction or that the transaction ended in an error condition. The TDs Stalled bit is
set and the Active bit is cleared. Reception of a STALL does not decrement the error
counter. A hardware interrupt is signaled to the system.
Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data
has occurred for this transaction. This would generally be caused by the ICH7 not being
able to access required data buffers in memory within necessary latency requirements.
Either of these conditions causes the C_ERR field of the TD to be decremented.
When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set,
the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame
and a hardware interrupt is signaled to the system.
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that six 1s in a row
within the incoming data stream. This causes the C_ERR field of the TD to be
decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared
to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is
set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
5.19.6.2
Non-Transaction Based Interrupts
If an ICH7 process error or system error occur, the ICH7 halts and immediately issues a
hardware interrupt to the system.
Resume Received
This event indicates that the ICH7 received a RESUME signal from a device on the USB
bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register,
a hardware interrupt is signaled to the system allowing the USB to be brought out of
the suspend state and returned to normal operation.
ICH7 Process Error
The HC monitors certain critical fields during operation to ensure that it does not
process corrupted data structures. These include checking for a valid PID and verifying
that the MaxLength field is less than 1280. If it detects a condition that would indicate
that it is processing corrupted data structures, it immediately halts processing, sets the
HC Process Error bit in the HC Status register and signals a hardware interrupt to the
system.
This interrupt cannot be disabled through the Interrupt Enable register.
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Functional Description
Host System Error
The ICH7 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occur.
When this error occurs, the ICH7 clears the Run/Stop bit in the Command register to
prevent further execution of the scheduled TDs. This interrupt cannot be disabled
through the Interrupt Enable register.
5.19.7
USB Power Management
The Host controller can be put into a suspended state and its power can be removed.
This requires that certain bits of information are retained in the resume power plane of
the ICH7 so that a device on a port may wake the system. Such a device may be a faxmodem, which will wake up the machine to receive a fax or take a voice message. The
settings of the following bits in I/O space will be maintained when the ICH7 enters the
S3, S4, or S5 states.
Table 5-46. Bits Maintained in Low Power States
Register
Offset
Bit
Command
00h
3
Enter Global Suspend Mode (EGSM)
Status
02h
2
Resume Detect
2
Port Enabled/Disabled
6
Resume Detect
8
Low-speed Device Attached
Port Status and
Control
10h & 12h
12
Description
Suspend
When the ICH7 detects a resume event on any of its ports, it sets the corresponding
USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system
wakes up and an SCI generated.
5.19.8
USB Legacy Keyboard Operation
When a USB keyboard is plugged into the system, and a standard keyboard is not, the
system may not boot, and MS-DOS legacy software will not run, because the keyboard
will not be identified. The ICH7 implements a series of trapping operations which will
snoop accesses that go to the keyboard controller, and put the expected data from the
USB keyboard into the keyboard controller.
Note:
The scheme described below assumes that the keyboard controller (8042 or
equivalent) is on the LPC bus.
This legacy operation is performed through SMM space. Figure 5-10 shows the Enable
and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the
Status Register. Because the enable is after the latch, it is possible to check for other
events that didn't necessarily cause an SMI. It is the software's responsibility to
logically AND the value with the appropriate enable bits.
Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY#
goes active) to ensure that the processor doesn't complete the cycle before the SMI is
observed. This method is used on MPIIX and has been validated.
The logic also needs to block the accesses to the 8042. If there is an external 8042,
then this is simply accomplished by not activating the 8042 CS. This is simply done by
logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to
determine if 8042CS should go active. An additional term is required for the “passthrough” case.
The state table for the diagram is shown in Table 5-47.
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Functional Description
Figure 5-10. USB Legacy Keyboard Flow Diagram
To Individual
"Caused By"
"Bits"
60 READ
KBC Accesses
S
D
Comb.
Decoder
PCI Config
Clear SMI_60_R
AND
R
EN_SMI_ON_60R
Read, Write
SMI
OR
Same for 60W, 64R, 64W
EN_PIRQD#
AND
To PIRQD#
To "Caused By" Bit
USB_IRQ
S
Clear USB_IRQ
D
R
AND
EN_SMI_ON_IRQ
Table 5-47. USB Legacy Keyboard State Transitions (Sheet 1 of 2)
Current
State
Action
Data
Value
Next
State
IDLE
64h / Write
D1h
GateState1
Standard D1 command. Cycle passed
through to 8042. SMI# doesn't go active.
PSTATE (offset C0, bit 6) goes to 1.
IDLE
64h / Write
Not D1h
IDLE
Bit 3 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
64h / Read
N/A
IDLE
Bit 2 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
60h / Write
Don't Care
IDLE
Bit 1 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
IDLE
60h / Read
N/A
IDLE
Bit 0 in Config Register determines if cycle
passed through to 8042 and if SMI#
generated.
GateState1
60h / Write
Intel ® ICH7 Family Datasheet
XXh
GateState2
Comment
Cycle passed through to 8042, even if trap
enabled in Bit 1 in Config Register. No SMI#
generated. PSTATE remains 1. If data value
is not DFh or DDh then the 8042 may chose
to ignore it.
205
Functional Description
Table 5-47. USB Legacy Keyboard State Transitions (Sheet 2 of 2)
Current
State
GateState1
GateState1
64h / Write
64h / Write
Data
Value
D1h
Not D1h
Next
State
Comment
GateState1
Cycle passed through to 8042, even if trap
enabled via Bit 3 in Config Register. No SMI#
generated. PSTATE remains 1. Stay in
GateState1 because this is part of the
double-trigger sequence.
ILDE
Bit 3 in Config space determines if cycle
passed through to 8042 and if SMI#
generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
GateState1
60h / Read
N/A
IDLE
This is an invalid sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
GateState1
64h / Read
N/A
GateState1
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Config Register. PSTATE
remains 1.
IDLE
Standard end of sequence. Cycle passed
through to 8042. PSTATE goes to 0. Bit 7 in
Config Space determines if SMI# should be
generated.
GateState2
64 / Write
FFh
GateState2
64h / Write
Not FFh
IDLE
Improper end of sequence. Bit 3 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
GateState2
64h / Read
N/A
GateState2
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Config Register. PSTATE
remains 1.
IDLE
Improper end of sequence. Bit 1 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
IDLE
Improper end of sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
GateState2
GateState2
206
Action
60h / Write
60h / Read
XXh
N/A
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Functional Description
5.20
USB EHCI Host Controller (D29:F7)
The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller which
supports up to eight USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to
480 Mb/s using the same pins as the eight USB full-speed/low-speed ports. The ICH7
contains port-routing logic that determines whether a USB port is controlled by one of
the UHCI controllers or by the EHCI controller. USB 2.0 based Debug Port is also
implemented in the ICH7.
A summary of the key architectural differences between the USB UHCI host controllers
and the EHCI host controller are shown in Table 5-48.
Table 5-48. UHCI vs. EHCI
Parameter
5.20.1
USB UHCI
USB EHCI
Accessible by
I/O space
Memory Space
Memory Data Structure
Single linked list
Separated in to Periodic and Asynchronous
lists
Differential Signaling Voltage
3.3 V
400 mV
Ports per Controller
2
8
EHC Initialization
The following descriptions step through the expected ICH7 Enhanced Host Controller
(EHC) initialization sequence in chronological order, beginning with a complete power
cycle in which the suspend well and core well have been off.
5.20.1.1
BIOS Initialization
BIOS performs a number of platform customization steps after the core well has
powered up. Contact your Intel Field Representative for additional ICH7 BIOS
information.
5.20.1.2
Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0.
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Functional Description
5.20.1.3
EHC Resets
In addition to the standard ICH7 hardware resets, portions of the EHC are reset by the
HCRESET bit and the transition from the D3HOT device power management state to the
D0 state. The effects of each of these resets are:
Reset
Does Reset
HCRESET bit set.
Memory space
registers except
Structural
Parameters (which is
written by BIOS).
Software writes
the Device Power
State from D3HOT
(11b) to D0
(00b).
Core well registers
(except BIOSprogrammed
registers).
Does not Reset
Comments
Configuration
registers.
The HCRESET must only affect
registers that the EHCI driver
controls. PCI Configuration
space and BIOS-programmed
parameters can not be reset.
Suspend well
registers; BIOSprogrammed core
well registers.
The D3-to-D0 transition must
not cause wake information
(suspend well) to be lost. It also
must not clear BIOSprogrammed registers because
BIOS may not be invoked
following the D3-to-D0
transition.
If the detailed register descriptions give exceptions to these rules, those exceptions
override these rules. This summary is provided to help explain the reasons for the reset
policies.
5.20.2
Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 for details.
5.20.3
USB 2.0 Enhanced Host Controller DMA
The ICH7 USB 2.0 EHC implements three sources of USB packets. They are, in order of
priority on USB during each microframe:
1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),
2. The Periodic DMA engine, and
3. The Asynchronous DMA engine. The ICH7 always performs any currently-pending
debug port transaction at the beginning of a microframe, followed by any pending
periodic traffic for the current microframe. If there is time left in the microframe,
then the EHC performs any pending asynchronous traffic until the end of the
microframe (EOF1). Note that the debug port traffic is only presented on one port
(Port #0), while the other ports are idle during this time.
5.20.4
Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
5.20.5
Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
The ICH7 EHCI allows entrance to USB test modes, as defined in the USB 2.0
specification, including Test J, Test Packet, etc. However, note that the ICH7 Test Packet
test mode interpacket gap timing may not meet the USB 2.0 specification.
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Functional Description
5.20.6
USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial
Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that
cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only ICH7-specific interrupt and error-reporting behavior is
documented in this section. The EHCI Interrupts Section must be read first, followed by
this section of the datasheet to fully comprehend the EHC interrupt and error-reporting
functionality.
• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer
Error can not occur on the ICH7.
• Master Abort and Target Abort responses from hub interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
• The ICH7 may assert the interrupts which are based on the interrupt threshold as
soon as the status for the last complete transaction in the interrupt interval has
been posted in the internal write buffers. The requirement in the Enhanced Host
Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the
status is written to memory) is met internally, even though the write may not be
seen on DMI before the interrupt is asserted.
• Since the ICH7 supports the 1024-element Frame List size, the Frame List Rollover
interrupt occurs every 1024 milliseconds.
• The ICH7 delivers interrupts using PIRQH#.
• The ICH7 does not modify the CERR count on an Interrupt IN when the “Do
Complete-Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. If subsequent
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
5.20.6.1
Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
• The Host System Error status bit is set
• The DMA engines are halted after completing up to one more transaction on the
USB interface
• If enabled (by the Host System Error Enable), then an interrupt is generated
• If the status is Master Abort, then the Received Master Abort bit in configuration
space is set
• If the status is Target Abort, then the Received Target Abort bit in configuration
space is set
• If enabled (by the SERR Enable bit in the function’s configuration space), then the
Signaled System Error bit in configuration bit is set.
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Functional Description
5.20.7
USB 2.0 Power Management
5.20.7.1
Pause Feature
This feature allows platforms (especially mobile systems) to dynamically enter lowpower states during brief periods when the system is idle (i.e., between keystrokes).
This is useful for enabling power management features like Intel SpeedStep technology
in the ICH7 mobile/ultra mobile only. The policies for entering these states typically are
based on the recent history of system bus activity to incrementally enter deeper power
management states. Normally, when the EHC is enabled, it regularly accesses main
memory while traversing the DMA schedules looking for work to do; this activity is
viewed by the power management software as a non-idle system, thus preventing the
power managed states to be entered. Suspending all of the enabled ports can prevent
the memory accesses from occurring, but there is an inherent latency overhead with
entering and exiting the suspended state on the USB ports that makes this
unacceptable for the purpose of dynamic power management. As a result, the EHCI
software drivers are allowed to pause the EHC’s DMA engines when it knows that the
traffic patterns of the attached devices can afford the delay. The pause only prevents
the EHC from generating memory accesses; the SOF packets continue to be generated
on the USB ports (unlike the suspended state).
5.20.7.2
Suspend Feature
The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,
Section 4.3 describes the details of Port Suspend and Resume.
5.20.7.3
ACPI Device States
The USB 2.0 function only supports the D0 and D3 PCI Power Management states.
Notes regarding the ICH7 implementation of the Device States:
1. The EHC hardware does not inherently consume any more power when it is in the
D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
consumption is reduced.
2. In the D0 state, all implemented EHC features are enabled.
3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
Note that, since the Debug Port uses the same memory range, the Debug Port is
only operational when the EHC is in the D0 state.
4. In the D3 state, the EHC interrupt must not assert for any reason. The internal
PME# signal is used to signal wake events, etc.
5. When the Device Power State field is written to D0 from D3, an internal reset is
generated. See section EHC Resets for general rules on the effects of this reset.
6. Attempts to write any other value into the Device Power State field other than 00b
(D0 state) and 11b (D3 state) will complete normally without changing the current
value in this field.
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Functional Description
5.20.7.4
ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
— The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
— When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic
processor low-power states to be entered.
— The PLL in the EHC is disabled when entering the S3HOT state (48 MHz clock
stops), or the S3COLD/S4/S5 states (core power turns off).
— All core well logic is reset in the S3/S4/S5 states.
5.20.7.5
Mobile/Ultra Mobile Only Considerations
The ICH7 USB 2.0 implementation does not behave differently in the mobile
configurations versus the desktop configurations. However, some features may be
especially useful for the mobile configurations.
• If a system (e.g., mobile) does not implement all eight USB 2.0 ports, the ICH7
provides mechanisms for changing the structural parameters of the EHC and hiding
unused UHCI controllers. See the Intel® ICH7 BIOS Specification for information on
how BIOS should configure the ICH7.
• Mobile/ultra mobile systems may want to minimize the conditions that will wake the
system. The ICH7 implements the “Wake Enable” bits in the Port Status and
Control registers, as specified in the EHCI spec, for this purpose.
• Mobile/Ultra mobile systems may want to cut suspend well power to some or all
USB ports when in a low-power state. The ICH7 implements the optional Port Wake
Capability Register in the EHC Configuration Space for this platform-specific
information to be communicated to software.
5.20.8
Interaction with UHCI Host Controllers
The Enhanced Host controller shares the eight USB ports with four UHCI Host
controllers in the ICH7. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1
shares ports 2 and 3; the UHC at D29:F2 shares ports 4 and 5; and the UHC at D29:F3
shares ports 6 and 7 with the EHC. There is very little interaction between the
Enhanced and the UHCI controllers other than the muxing control which is provided as
part of the EHC.Figure 5-11 shows the USB Port Connections at a conceptual level.
5.20.8.1
Port-Routing Logic
Integrated into the EHC functionality is port-routing logic, which performs the muxing
between the UHCI and EHCI host controllers. The ICH7 conceptually implements this
logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of
USB 2.0’s high-speed signaling protocol or if the EHCI software drivers are not present
as indicated by the Configured Flag, then the UHCI controller owns the port. Owning
the port means that the differential output is driven by the owner and the input stream
is only visible to the owner. The host controller that is not the owner of the port
internally sees a disconnected port.
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Functional Description
Figure 5-11. Intel® ICH7-USB Port Connections
UHCI #3
(D29:F3)
UHCI #2
(D29:F2)
UHCI #1
(D29:F1)
UCHI #0
(D29:F0)
Port 7
Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Debug
Port
Enhanced Host Controller Logic
Note that the port-routing logic is the only block of logic within the ICH7 that observes
the physical (real) connect/disconnect information. The port status logic inside each of
the host controllers observes the electrical connect/disconnect information that is
generated by the port-routing logic.
Only the differential signal pairs are multiplexed/demultiplexed between the UHCI and
EHCI host controllers. The other USB functional signals are handled as follows:
• The Overcurrent inputs (OC[7:0]#) are directly routed to both controllers. An
overcurrent event is recorded in both controllers’ status registers.
The Port-Routing logic is implemented in the Suspend power well so that reenumeration and
re-mapping of the USB ports is not required following entering and exiting a system
sleep state in which the core power is turned off.
The ICH7 also allows the USB Debug Port traffic to be routed in and out of Port #0.
When in this mode, the Enhanced Host controller is the owner of Port #0.
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Functional Description
5.20.8.2
Device Connects
The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision
1.0 describes the details of handling Device Connects in Section 4.2. There are four
general scenarios that are summarized below.
1. Configure Flag = 0 and a full-speed/low-speed-only Device is connected
— In this case, the UHC is the owner of the port both before and after the connect
occurs. The EHC (except for the port-routing logic) does not see the connect
occur. The UHCI driver handles the connection and initialization process.
2. Configure Flag = 0 and a high-speed-capable Device is connected
— In this case, the UHC is the owner of the port both before and after the connect
occurs. The EHC (except for the port-routing logic) not see the connect occur.
The UHCI driver handles the connection and initialization process. Since the
UHC does not perform the high-speed chirp handshake, the device operates in
compatible mode.
3. Configure Flag = 1 and a full-speed/low-speed-only Device is connected
— In this case, the EHC is the owner of the port before the connect occurs. The
EHCI driver handles the connection and performs the port reset. After the reset
process completes, the EHC hardware has cleared (not set) the Port Enable bit
in the EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner
bit in the same register, causing the UHC to see a connect event and the EHC to
see an “electrical” disconnect event. The UHCI driver and hardware handle the
connection and initialization process from that point on. The EHCI driver and
hardware handle the perceived disconnect.
4. Configure Flag = 1 and a high-speed-capable Device is connected
— In this case, the EHC is the owner of the port before, and remains the owner
after, the connect occurs. The EHCI driver handles the connection and performs
the port reset. After the reset process completes, the EHC hardware has set the
Port Enable bit in the EHC’s PORTSC register. The port is functional at this point.
The UHC continues to see an unconnected port.
5.20.8.3
Device Disconnects
The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision
1.0 describes the details of handling Device Connects in Section 4.2. There are three
general scenarios that are summarized below.
1. Configure Flag = 0 and the device is disconnected
— In this case, the UHC is the owner of the port both before and after the
disconnect occurs. The EHC (except for the port-routing logic) not see a device
attached. The UHCI driver handles disconnection process.
2. Configure Flag = 1 and a full-speed/low-speed-capable Device is disconnected
— In this case, the UHC is the owner of the port before the disconnect occurs. The
disconnect is reported by the UHC and serviced by the associated UHCI driver.
The port-routing logic in the EHC cluster forces the Port Owner bit to 0,
indicating that the EHC owns the unconnected port.
3. Configure Flag = 1 and a high-speed-capable Device is disconnected
— In this case, the EHC is the owner of the port before, and remains the owner
after, the disconnect occurs. The EHCI hardware and driver handle the
disconnection process. The UHC does not see a device attached.
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Functional Description
5.20.8.4
Effect of Resets on Port-Routing Logic
As mentioned above, the Port Routing logic is implemented in the suspend power well
so that remuneration and re-mapping of the USB ports is not required following
entering and exiting a system sleep state in which the core power is turned off.
Reset Event
5.20.9
Effect on Configure Flag
Effect on Port Owner Bits
Suspend Well Reset
cleared (0)
Core Well Reset
no effect
set (1)
no effect
D3-to-D0 Reset
no effect
no effect
HCRESET
cleared (0)
set (1)
USB 2.0 Legacy Keyboard Operation
The ICH7 must support the possibility of a keyboard downstream from either a fullspeed/low-speed or a high-speed port. The description of the legacy keyboard support
is unchanged from USB 1.1 (See Section 5.19.8).
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
5.20.10
USB 2.0 Based Debug Port
The ICH7 supports the elimination of the legacy COM ports by providing the ability for
new debugger software to interact with devices on a USB 2.0 port.
High-level restrictions and features are:
• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.
• Works even though non-configured port is default-routed to the UHCI. Note that
the Debug Port can not be used to debug an issue that requires a full-speed/lowspeed device on Port #0 using the UHCI drivers.
• Allows normal system USB 2.0 traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be high-speed capable and connect directly to Port
#0 on ICH7 systems (e.g., the DPD cannot be connected to Port #0 thru a hub).
• Debug Port FIFO always makes forward progress (a bad status on USB is simply
presented back to software).
• The Debug Port FIFO is only given one USB access per microframe.
The Debug port facilitates operating system and device driver debug. It allows the
software to communicate with an external console using a USB 2.0 connection.
Because the interface to this link does not go through the normal USB 2.0 stack, it
allows communication with the external console during cases where the operating
system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is
being debugged. Specific features of this implementation of a debug port are:
• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0
power state.
• Capability is interrupted when port is driving USB RESET
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Functional Description
5.20.10.1
Theory of Operation
There are two operational modes for the USB debug port:
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard
host controller driver. In Mode 1, the Debug Port controller is required to generate a
“keepalive” packets less than 2 ms apart to keep the attached debug device from
suspending. The keepalive packet should be a standalone 32-bit SYNC field.
2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit
is 1). In Mode 2, the normal transmission of SOF packets will keep the debug
device from suspending.
Behavioral Rules
1. In both modes 1 and 2, the Debug Port controller must check for software
requested debug transactions at least every 125 microseconds.
2. If the debug port is enabled by the debug driver, and the standard host controller
driver resets the USB port, USB debug transactions are held off for the duration of
the reset and until after the first SOF is sent.
3. If the standard host controller driver suspends the USB port, then USB debug
transactions are held off for the duration of the suspend/resume sequence and until
after the first SOF is sent.
4. The ENABLED_CNT bit in the debug register space is independent of the similar
port control bit in the associated Port Status and Control register.
Table 5-49 shows the debug port behavior related to the state of bits in the debug
registers as well as bits in the associated Port Status and Control register.
Table 5-49. Debug Port Behavior (Sheet 1 of 2)
OWNER_CNT
ENABLED_CT
Port
Enable
Run /
Stop
Suspend
Debug Port Behavior
0
X
X
X
X
Debug port is not being used.
Normal operation.
1
0
X
X
X
Debug port is not being used.
Normal operation.
1
1
0
0
X
Debug port in Mode 1. SYNC
keepalives sent plus debug
traffic
X
Debug port in Mode 2. SOF
(and only SOF) is sent as
keepalive. Debug traffic is
also sent. Note that no other
normal traffic is sent out this
port, because the port is not
enabled.
0
Invalid. Host controller driver
should not put the controller
into this state (enabled, not
running and not suspended).
1
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1
0
1
1
0
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Functional Description
Table 5-49. Debug Port Behavior (Sheet 2 of 2)
OWNER_CNT
ENABLED_CT
Port
Enable
Run /
Stop
Suspend
1
1
1
0
1
Port is suspended. No debug
traffic sent.
1
1
1
1
0
Debug port in Mode 2. Debug
traffic is interspersed with
normal traffic.
1
1
1
1
1
Port is suspended. No debug
traffic sent.
Debug Port Behavior
5.20.10.1.1 OUT Transactions
An Out transaction sends data to the debug device. It can occur only when the
following are true:
• The debug port is enabled
• The debug software sets the GO_CNT bit
• The WRITE_READ#_CNT bit is set
The sequence of the transaction is:
1. Software sets the appropriate values in the following bits:
— USB_ADDRESS_CNF
— USB_ENDPOINT_CNF
— DATA_BUFFER[63:0]
— TOKEN_PID_CNT[7:0]
— SEND_PID_CNT[15:8]
— DATA_LEN_CNT
— WRITE_READ#_CNT (note: this will always be 1 for OUT transactions)
— GO_CNT (note: this will always be 1 to initiate the transaction)
2. The debug port controller sends a token packet consisting of:
— SYNC
— TOKEN_PID_CNT field
— USB_ADDRESS_CNT field
— USB_ENDPOINT_CNT field
— 5-bit CRC field
3. After sending the token packet, the debug port controller sends a data packet
consisting of:
— SYNC
— SEND_PID_CNT field
— The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER
— 16-bit CRC
NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be
included in the packet.
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Functional Description
4. After sending the data packet, the controller waits for a handshake response from
the debug device.
• If a handshake is received, the debug port controller:
— a. Places the received PID in the RECEIVED_PID_STS field
— b. Resets the ERROR_GOOD#_STS bit
— c. Sets the DONE_STS bit
• If no handshake PID is received, the debug port controller:
— a. Sets the EXCEPTION_STS field to 001b
— b. Sets the ERROR_GOOD#_STS bit
— c. Sets the DONE_STS bit
5.20.10.1.2
IN Transactions
An IN transaction receives data from the debug device. It can occur only when the
following are true:
• The debug port is enabled
• The debug software sets the GO_CNT bit
• The WRITE_READ#_CNT bit is reset
The sequence of the transaction is:
1. Software sets the appropriate values in the following bits:
— USB_ADDRESS_CNF
— USB_ENDPOINT_CNF
— TOKEN_PID_CNT[7:0]
— DATA_LEN_CNT
— WRITE_READ#_CNT (note: this will always be 0 for IN transactions)
— GO_CNT (note: this will always be 1 to initiate the transaction)
2. The debug port controller sends a token packet consisting of:
— SYNC
— TOKEN_PID_CNT field
— USB_ADDRESS_CNT field
— USB_ENDPOINT_CNT field
— 5-bit CRC field.
3. After sending the token packet, the debug port controller waits for a response from
the debug device.
If a response is received:
— The received PID is placed into the RECEIVED_PID_STS field
— Any subsequent bytes are placed into the DATA_BUFFER
— The DATA_LEN_CNT field is updated to show the number of bytes that were
received after the PID.
4. If valid packet was received from the device that was one byte in length (indicating
it was a handshake packet), then the debug port controller:
— Resets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit
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Functional Description
5. If valid packet was received from the device that was more than one byte in length
(indicating it was a data packet), then the debug port controller:
— Transmits an ACK handshake packet
— Resets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit
6. If no valid packet is received, then the debug port controller:
— Sets the EXCEPTION_STS field to 001b
— Sets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit.
5.20.10.1.3
Debug Software
Enabling the Debug Port
There are two mutually exclusive conditions that debug software must address as part
of its startup processing:
• The EHCI has been initialized by system software
• The EHCI has not been initialized by system software
Debug software can determine the current ‘initialized’ state of the EHCI by examining
the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then
system software has initialized the EHCI. Otherwise the EHCI should not be considered
initialized. Debug software will initialize the debug port registers depending on the
state the EHCI. However, before this can be accomplished, debug software must
determine which root USB port is designated as the debug port.
Determining the Debug Port
Debug software can easily determine which USB root port has been designated as the
debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters
register. This 4-bit field represents the numeric value assigned to the debug port (i.e.,
0001=port 0).
Debug Software Startup with Non-Initialized EHCI
Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,
the Current Connect Status bit in the appropriate (See Determining the Debug Port)
PORTSC register is set. If the Current Connect Status bit is not set, then debug
software may choose to terminate or it may choose to wait until a device is connected.
If a device is connected to the port, then debug software must reset/enable the port.
Debug software does this by setting and then clearing the Port Reset bit the PORTSC
register. To ensure a successful reset, debug software should wait at least 50 ms before
clearing the Port Reset bit. Due to possible delays, this bit may not change to 0
immediately; reset is complete when this bit reads as 0. Software must not continue
until this bit reads 0.
If a high-speed device is attached, the EHCI will automatically set the Port Enabled/
Disabled bit in the PORTSC register and the debug software can proceed. Debug
software should set the ENABLED_CNT bit in the Debug Port Control/Status register,
and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the
system host controller driver does not see an enabled port when it is first loaded).
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Functional Description
Debug Software Startup with Initialized EHCI
Debug software can attempt to use the debug port if the Current Connect Status bit in
the appropriate (See Determining the Debug Port) PORTSC register is set. If the
Current Connect Status bit is not set, then debug software may choose to terminate or
it may choose to wait until a device is connected.
If a device is connected, then debug software must set the OWNER_CNT bit and then
the ENABLED_CNT bit in the Debug Port Control/Status register.
Determining Debug Peripheral Presence
After enabling the debug port functionality, debug software can determine if a debug
peripheral is attached by attempting to send data to the debug peripheral. If all
attempts result in an error (Exception bits in the Debug Port Control/Status register
indicates a Transaction Error), then the attached device is not a debug peripheral. If the
debug port peripheral is not present, then debug software may choose to terminate or
it may choose to wait until a debug peripheral is connected.
5.21
SMBus Controller (D31:F3)
The ICH7 provides an System Management Bus (SMBus) 2.0 host controller as well as
an SMBus Slave Interface. The host controller provides a mechanism for the processor
to initiate communications with SMBus peripherals (slaves). The ICH7 is also capable of
operating in a mode in which it can communicate with I2C compatible devices.
The ICH7 can perform SMBus messages with either packet error checking (PEC)
enabled or disabled. The actual PEC calculation and checking is performed in hardware
by the ICH7.
The Slave Interface allows an external master to read from or write to the ICH7. Write
cycles can be used to cause certain events or pass messages, and the read cycles can
be used to determine the state of various status bits. The ICH7’s internal host
controller cannot access the ICH7’s internal Slave Interface.
The ICH7 SMBus logic exists in Device 31:Function 3 configuration space, and consists
of a transmit data path, and host controller. The transmit data path provides the data
flow logic needed to implement the seven different SMBus command protocols and is
controlled by the host controller. The ICH7 SMBus controller logic is clocked by RTC
clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the new Host Notify command
(which is actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done via the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
The ICH7 SMBus host controller checks for parity errors as a target. If an error is
detected, the detected parity error bit in the PCI Status Register (Device 31:Function
3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device
31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit
in the PCI Status Register (bit 14) is set.
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Functional Description
5.21.1
Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or
interrupt, if enabled.
The host controller supports 8 command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,
Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block
Write–Block Read Process Call, and Host Notify.
The SMBus host controller requires that the various data and command fields be setup
for the type of command to be sent. When software sets the START bit, the SMBus Host
controller performs the requested transaction, and interrupts the processor (or
generates an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control, Host Command,
Transmit Slave Address, Data 0, Data 1) should not be changed or read until the
interrupt status bit (INTR) has been set (indicating the completion of the command).
Any register values needed for computation purposes should be saved prior to issuing
of a new command, as the SMBus host controller updates all registers while completing
the new command.
Using the SMB host controller to send commands to the ICH7’s SMB slave port is
supported. The ICH7 supports the System Management Bus (SMBus) Specification,
Version 2.0. Slave functionality, including the Host Notify protocol, is available on the
SMBus pins. The SMLink and SMBus signals should not be tied together externally.
5.21.1.1
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to
determine the progress of the command. While the command is in operation, the
HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set
in the Host Status Register. If the device does not respond with an acknowledge, and
the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the
Host Control Register while the command is running, the transaction will stop and the
FAILED bit will be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent.
The PEC byte is not appended to the Quick Protocol. Software should force the PEC_EN
bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0
when running this command. See section 5.5.1 of the System Management Bus
(SMBus) Specification, Version 2.0 for the format of the protocol.
Send Byte / Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command
Registers are sent
For the Receive Byte command, the Transmit Slave Address Register is sent. The data
received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when
running this command.
The Receive Byte is similar to a Send Byte, the only difference is the direction of data
transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus)
Specification, Version 2.0 for the format of the protocol.
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Functional Description
Write Byte/Word
The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes
are the data to be written. When programmed for a Write Byte/Word command, the
Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,
the Data1 Register is sent on a Write Word command. Software must force the I2C_EN
bit to 0 when running this command. See section 5.5.4 of the System Management Bus
(SMBus) Specification, Version 2.0 for the format of the protocol.
Read Byte/Word
Reading data is slightly more complicated than writing data. First the ICH7 must write a
command to the slave device. Then it must follow that command with a repeated start
condition to denote a read from that device's address. The slave then returns 1 or 2
bytes of data. Software must force the I2C_EN bit to 0 when running this command.
When programmed for the read byte/word command, the Transmit Slave Address and
Device Command Registers are sent. Data is received into the DATA0 on the read byte,
and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System
Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Process Call
The process call is so named because a command sends data and waits for the slave to
return a value dependent on that data. The protocol is simply a Write Word followed by
a Read Word, but without a second command or stop condition.
When programmed for the Process Call command, the ICH7 transmits the Transmit
Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the
device is stored in the DATA0 and DATA1 registers. The Process Call command with
I2C_EN set and the PEC_EN bit set produces undefined results. Software must force
either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the
System Management Bus (SMBus) Specification, Version 2.0 for the format of the
protocol.
Note:
For process call command, the value written into bit 0 of the Transmit Slave Address
Register (SMB I/O register, offset 04h) needs to be 0.
Note:
If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code
(bits 18:11 in the bit sequence) are not sent - as a result, the slave will not
acknowledge (bit 19 in the sequence).
Block Read/Write
The ICH7 contains a 32-byte buffer for read and write data which can be enabled by
setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a
single byte of buffering. This 32-byte buffer is filled with write data before
transmission, and filled with read data on reception. In the ICH7, the interrupt is
generated only after a transmission or reception of 32 bytes, or when the entire byte
count has been transmitted/received.
The byte count field is transmitted but ignored by the ICH7 as software will end the
transfer after all bytes it cares about have been sent or received.
For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and
AAC bits to 0 when running this command.
Intel ® ICH7 Family Datasheet
221
Functional Description
The block write begins with a slave address and a write condition. After the command
code the ICH7 issues a byte count describing how many more bytes will follow in the
message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),
followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is
allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device
Command, and Data0 (count) registers are sent. Data is then sent from the Block Data
Byte register; the total data sent being the value stored in the Data0 Register. On block
read commands, the first byte received is stored in the Data0 register, and the
remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the
System Management Bus (SMBus) Specification, Version 2.0 for the format of the
protocol.
Note:
For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.
The ICH7 will still send the number of bytes (on writes) or receive the number of bytes
(on reads) indicated in the DATA0 register. However, it will not send the contents of the
DATA0 register as part of the message. Also, the Block Write protocol sequence
changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a
result, the slave will not acknowledge (bit 28 in the sequence).
I2C Read
This command allows the ICH7 to perform block reads to certain I2C devices, such as
serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only.
However, this does not allow access to devices using the I2C “Combined Format” that
has data bytes after the address. Typically these data bytes correspond to an offset
(address) within the serial memory chips.
Note:
This command is supported independent of the setting of the I2C_EN bit. The I2C Read
command with the PEC_EN bit set produces undefined results. Software must force
both the PEC_EN and AAC bit to 0 when running this command.
For I2C Read command, the value written into bit 0 of the Transmit Slave Address
Register (SMB I/O register, offset 04h) needs to be 0.
222
Intel ® ICH7 Family Datasheet
Functional Description
The format that is used for the command is shown in Table 5-50.
Table 5-50. I2C Block Read
Bit
1
8:2
9
10
18:11
Description
Start
Slave Address — 7 bits
Write
Acknowledge from slave
Send DATA1 register
19
Acknowledge from slave
20
Repeated Start
27:21
Slave Address — 7 bits
28
Read
29
Acknowledge from slave
37:30
38
46:39
47
Data byte 1 from slave — 8 bits
Acknowledge
Data byte 2 from slave — 8 bits
Acknowledge
–
Data bytes from slave /
Acknowledge
–
Data byte N from slave — 8 bits
–
NOT Acknowledge
–
Stop
The ICH7 will continue reading data from the peripheral until the NAK is received.
Block Write–Block Read Process Call
The block write-block read process call is a two-part message. The call begins with a
slave address and a write condition. After the command code the host issues a write
byte count (M) that describes how many more bytes will be written in the first part of
the message. If a master has 6 bytes to send, the byte count field will have the value 6
(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.
The second part of the message is a block of read data beginning with a repeated start
condition followed by the slave address and a Read bit. The next byte is the read byte
count (N), which may differ from the write byte count (M). The read byte count (N)
cannot be 0.
The combined data payload must not exceed 32 bytes. The byte length restrictions of
this process call are summarized as follows:
• M ≥ 1 byte
• N ≥ 1 byte
• M + N ≤ 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total
message beginning with the first slave address and using the normal PEC
computational rules. It is highly recommended that a PEC byte be used with the Block
Write-Block Read Process Call. Software must do a read to the command register
(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.
Intel ® ICH7 Family Datasheet
223
Functional Description
Note that there is no STOP condition before the repeated START condition, and that a
NACK signifies the end of the read transfer.
Note:
E32B bit in the Auxiliary Control register must be set when using this protocol.
See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0
for the format of the protocol.
5.21.2
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. The ICH7 continuously monitors the
SMBDATA line. When the ICH7 is attempting to drive the bus to a 1 by letting go of the
SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus
and the ICH7 will stop transferring data.
If the ICH7 sees that it has lost arbitration, the condition is called a collision. The ICH7
will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an
interrupt or SMI#. The processor is responsible for restarting the transaction.
When the ICH7 is a SMBus master, it drives the clock. When the ICH7 is sending
address or command as an SMBus master, or data bytes as a master on writes, it drives
data relative to the clock it is also driving. It will not start toggling the clock until the
start or stop condition meets proper setup and hold time. The ICH7 will also provide
minimum time between SMBus transactions as a master.
Note:
The ICH7 supports the same arbitration protocol for both the SMBus and the System
Management (SMLINK) interfaces.
5.21.3
Bus Timing
5.21.3.1
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH7
as an SMBus master would like. They have the capability of stretching the low time of
the clock. When the ICH7 attempts to release the clock (allowing the clock to go high),
the clock will remain low for an extended period of time.
The ICH7 monitors the SMBus clock line after it releases the bus to determine whether
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
5.21.3.2
Bus Time Out (Intel® ICH7 as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The ICH7 will discard the cycle and set the DEV_ERR bit. The time out
minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH7 will start
after the last bit of data is transferred by the ICH7 and it is waiting for a response.
The 25 ms timeout counter will not count under the following conditions:
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that
the system has not locked up).
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Intel ® ICH7 Family Datasheet
Functional Description
5.21.4
Interrupts / SMI#
The ICH7 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).
Table 5-52 and Table 5-53 specify how the various enable bits in the SMBus function
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
Table 5-51. Enable for SMBALERT#
Event
INTREN
(Host Control
I/O Register,
Offset 02h,
Bit 0)
SMB_SMI_EN
(Host
Configuration
Register,
D31:F3:Offset
40h, Bit 1)
SMBALERT_DIS
(Slave Command
I/O Register,
Offset 11h, Bit 2)
X
X
X
Wake generated
X
1
0
Slave SMI#
generated
(SMBUS_SMI_STS)
1
0
0
Interrupt
generated
SMBALERT#
asserted low
(always
reported in
Host Status
Register, Bit
5)
Result
Table 5-52. Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration
Register,
D31:F3:Offset 40h,
Bit1)
Event
Slave Write to
Wake/SMI#
Command
X
X
Wake generated when
asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave Write to
SMLINK_SLAVE_S
MI Command
X
X
Slave SMI# generated when
in the S0 state
(SMBUS_SMI_STS)
0
X
None
Any combination of
Host Status
Register [4:1]
asserted
Intel ® ICH7 Family Datasheet
1
0
Interrupt generated
1
1
Host SMI# generated
225
Functional Description
Table 5-53. Enables for the Host Notify Command
HOST_NOTIFY_INTRE
N (Slave Control I/O
Register, Offset 11h,
bit 0)
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h,
bit 1)
Result
0
X
0
None
X
X
1
Wake generated
1
0
X
Interrupt generated
X
Slave SMI#
generated
(SMBUS_SMI_STS)
1
5.21.5
SMB_SMI_EN
(Host Config
Register,
D31:F3:Off40h, Bit
1)
1
SMBALERT#
SMBALERT# is multiplexed with GPIO11. When enable and the signal is asserted, The
ICH7 can generate an interrupt, an SMI#, or a wake event from S1–S5.
Note:
Any event on SMBALERT# (regardless whether it is programmed as a GPI or not),
causes the event message to be sent in heartbeat mode.
5.21.6
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the ICH7 automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
5.21.7
SMBus Slave Interface
The ICH7’s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will
not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol device. The slave interface allows the ICH7 to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify.
• Receive Slave Address register: This is the address that the ICH7 decodes. A
default value is provided so that the slave interface can be used without the
processor having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller.
• Registers that the external microcontroller can read to get the state of the ICH7.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register (Section 10.8.3.13) for all others
226
Intel ® ICH7 Family Datasheet
Functional Description
Note:
The external microcontroller should not attempt to access the ICH7’s SMBus slave logic
until either:
• 800 milliseconds after both: RTEST# is high and RSMRST# is high, OR
• the PLTRST# de-asserts
The 800 ms case is based on the scenario where the RTC Battery is dead or missing
such that the RTC Power Well comes up simultaneously with Suspend Well. In this case,
the RTC clock may take a while to stabilize. The ICH7 uses the RTC clock to extend the
internal RSMRST# by ~100 ms. Therefore, if the clock is slow to toggle, this time could
be extended. 800 ms is assumed to be sufficient guardband for this.
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, the ICH7 slave logic's behavior is undefined. This is interpreted
as an unexpected idle and should be avoided when performing management activities
to the slave logic.
Note:
When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if the ICH7 slave address (RCV_SLVA) is left at 44h
(default), the external micro controller would use an address of 88h/89h (write/read).
5.21.7.1
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH7 SMBus Slave I/F. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field
(bits 20:27) indicate the value that should be written to that register.
Note:
If the ICH7 is sent a ‘Hard Reset Without Cycling’ command on SMBus while the system
is in S4 or S5, the reset command will not be executed until the next wake event.
SMBus write commands sent after the Hard Reset Without Cycling command and
before the wake event will be NAKed by the ICH7. This also applies to any SMBus wake
commands sent after a Hard Reset Without Cycling command, such that the SMBus
wake command will not cause the system to wake. Any SMBus read that is accepted by
the ICH7 will complete normally. Intel® Active Management Technology is not
impacted as Intel AMT does not use the Hard Reset Without Cycling command while the
system is in S4 or S5.
Table 5-54 has the values associated with the registers.
Table 5-54. Slave Write Registers
Register
Function
0
Command Register. See Table 5-55 below for legal values written to this register.
1–3
Reserved
4
Data Message Byte 0
5
Data Message Byte 1
6–7
Reserved
8
Reserved
9–FFh
Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the
contents of the data byte registers until they have been read by the system processor. The
ICH7 overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read. ICH7
will not attempt to cover this race condition (i.e., unpredictable results in this case).
Intel ® ICH7 Family Datasheet
227
Functional Description
.
Table 5-55. Command Types
Command
Type
0
Reserved
1
WAKE/SMI#. This command wakes the system if it is not already awake. If
system is already awake, an SMI# is generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is
already awake. The SMI handler should then clear this bit.
2
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and
has the same effect as the Powerbutton Override occurring.
3
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the
system (does not include cycling of the power supply). This is equivalent to a write
to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0.
4
HARD RESET SYSTEM. This command causes a hard reset of the system
(including cycling of the power supply). This is equivalent to a write to the CF9h
register with bits 3:1 set to 1.
5
Disable the TCO Messages. This command will disable the Intel® ICH7 from
sending Heartbeat and Event messages (as described in Section 5.15.2). Once this
command has been executed, Heartbeat and Event message reporting can only be
re-enabled by assertion and deassertion of the RSMRST# signal.
6
WD RELOAD: Reload watchdog timer.
7
8
9–FFh
228
Description
Reserved
SMLINK_SLV_SMI. When ICH7 detects this command type while in the S0 state,
it sets the SMLINK_SLV_SMI_STS bit (see Section 10.9.5). This command should
only be used if the system is in an S0 state. If the message is received during S1–
S5 states, the ICH7 acknowledges it, but the SMLINK_SLV_SMI_STS bit does not
get set.
Note: It is possible that the system transitions out of the S0 state at the same time
that the SMLINK_SLV_SMI command is received. In this case, the
SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to
sleep. Once the system returns to S0, the SMI associated with this bit would then
be generated. Software must be able to handle this scenario.
Reserved
Intel ® ICH7 Family Datasheet
Functional Description
5.21.7.2
Format of Read Command
The external master performs Byte Read commands to the ICH7 SMBus Slave I/F. The
“Command” field (bits 18:11) indicate which register is being accessed. The Data field
(bits 30:37) contain the value that should be read from that register. Table Table 5-56
shows the Read Cycle Format. Table 5-57 shows the register mapping for the data
byte.
Table 5-56. Read Cycle Format
Bit
1
8:2
9
Description
Driven by
Comment
Start
External Microcontroller
Slave Address - 7
bits
External Microcontroller
Must match value in Receive Slave
Address register
Write
External Microcontroller
Always 0
ACK
Intel®
Command code - 8
bits
External Microcontroller
19
ACK
ICH7
20
Repeated Start
External Microcontroller
Slave Address - 7
bits
External Microcontroller
Must match value in Receive Slave
Address register
28
Read
External Microcontroller
Always 1
29
ACK
ICH7
Datay Byte
ICH7
38
NOT ACK
External Microcontroller
39
Stop
External Microcontroller
10
18:11
27:21
37:30
ICH7
Indicates which register is being
accessed See Table 5-57
Value depends on register being
accessed. See Table 5-57
Table 5-57. Data Values for Slave Read Registers
Register
Bits
0
7:0
Description
Reserved
System Power State
000 = S0
001 = S1
010 = Reserved
1
2:0
011 = S3
100 = S4
101 = S5
110 = Reserved
111 = Reserved
1
7:3
Reserved
2
3:0
Frequency Strap Register
2
7:4
Reserved
3
5:0
Watchdog Timer current value
3
7:6
Reserved
Intel ® ICH7 Family Datasheet
229
Functional Description
Table 5-57. Data Values for Slave Read Registers
Register
Bits
Description
4
0
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that
the system cover has probably been opened.
4
1
1 = BTI Temperature Event occurred. This bit will be set if the
Intel® ICH7’s THRM# input signal is active. Need to take after
polarity control.
4
2
Boot-status. This bit will be 1 when the processor does not fetch
the first instruction.
4
3
This bit will be set after the TCO timer times out a second time
(Both TIMEOUT and SECOND_TO_STS bits set).
4
6:4
4
7
Reserved
The bit will reflect the state of the GPI11/SMBALERT# signal, and
will depend on the GP_INV11 bit. It does not matter if the pin is
configured as GPI11 or SMBALERT#.
•
•
5.21.7.2.1
If the GP_INV11 bit is 1, the value of register 4 bit 7 will equal the level
of the GPI11/SMBALERT# pin (high = 1, low = 0).
If the GP_INV11 bit is 0, the value of register 4 bit 7 will equal the
inverse of the level of the GPI11/SMBALERT# pin (high = 1, low = 0).
Unprogrammed flash BIOS bit. This bit will be 1 to indicate that the
first BIOS fetch returned FFh, that indicates that the flash BIOS is
probably blank.
5
0
5
1
5
2
Processor Power Failure Status. 1 if the CPUPWR_FLR bit in the
GEN_PMCON_2 register is set.
5
3
INIT# due to receiving Shutdown message. This event is visible
from the reception of the shutdown message until a platform reset
is done. Events on signal will not create an event message.
5
4
LT Range: LT reset indication. Events on signal will not create an
event message.
5
5
POWER_OK_BAD: Indicates the failure core power well ramp during
boot/resume. This bit will be active if the SLP_S3# pin is deasserted and PWROK pin is not asserted.
5
6
Thermal Trip: This bit will shadow the state of CPU Thermal Trip
status bit (CTS). Events on signal will not create an event message.
5
7
Reserved
6
7:0
Contents of the Message 1 register.
7
7:0
Contents of the Message 2 register.
8
7:0
Contents of the WDSTATUS register.
9-FFh
7:0
Reserved
Reserved (Desktop Only)
Battery Low Status (Mobile/Ultra Mobile Only). 1 if BATLOW# is ‘0’
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit –
Address– Write bit sequence. When the ICH7 detects that the address matches the
value in the Receive Slave Address register, it will assume that the protocol is always
followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In
230
Intel ® ICH7 Family Datasheet
Functional Description
other words, if a Start –Address–Read occurs (which is invalid for SMBus Read or Write
protocol), and the address matches the ICH7’s Slave Address, the ICH7 will still grab
the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–
Read sequence beginning at bit 20. Once again, if the Address matches the ICH7’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and
proceed with the Slave Read cycle.
Note:
An external microcontroller must not attempt to access the ICH7’s SMBus Slave logic
until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).
5.21.7.3
Format of Host Notify Command
The ICH7 tracks and responds to the standard Host Notify command as specified in the
System Management Bus (SMBus) Specification, Version 2.0. The host address for this
command is fixed to 0001000b. If the ICH7 already has data for a previously-received
host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address
byte of the protocol. This allows the host to communicate non-acceptance to the
master and retain the host notify address and data values for the previous cycle until
host software completely services the interrupt.
Note:
Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 5-58 shows the Host Notify format.
Table 5-58. Host Notify Format
Bit
1
8:2
9
10
Description
Driven By
Comment
Start
External
Master
SMB Host Address — 7
bits
External
Master
Always 0001_000
Write
External
Master
Always 0
ACK (or NACK)
Intel® ICH7
ICH7 NACKs if HOST_NOTIFY_STS is 1
Device Address – 7 bits
External
Master
Indicates the address of the master;
loaded into the Notify Device Address
Register
18
Unused — Always 0
External
Master
7-bit-only address; this bit is inserted to
complete the byte
19
ACK
ICH7
Data Byte Low — 8 bits
External
Master
ACK
ICH7
Data Byte High — 8 bits
External
Master
37
ACK
ICH7
38
Stop
External
Master
17:11
27:20
28
36:29
Intel ® ICH7 Family Datasheet
Loaded into the Notify Data Low Byte
Register
Loaded into the Notify Data High Byte
Register
231
Functional Description
5.22
AC ’97 Controller (Audio D30:F2, Modem D30:F3)
(Desktop and Mobile Only)
Note:
All references to AC ’97 in this document refer to the AC ’97 Specification, Version 2.3.
For further information on the operation of the AC-link protocol, see the AC ’97
Specification, Version 2.3.
The ICH7 AC ’97 controller features include:
• Independent PCI functions for audio and modem.
• Independent bus master logic for dual Microphone input, dual PCM Audio input (2channel stereo per input), PCM audio output (2-, 4- or 6-channel audio), Modem
input, Modem output and S/PDIF output.
• 20-bit sample resolution
• Multiple sample rates up to 48 kHz
• Support for 16 codec-implemented GPIOs
• Single modem line
• Configure up to three codecs with three ACZ_SDIN pins
Table 5-59 shows a detailed list of features supported by the ICH7 AC ’97 digital
controller
.
Table 5-59. Features Supported by Intel® ICH7 (Sheet 1 of 2)
Feature
Description
•
•
System
Interface
Power
Management
PCI Audio
Function
•
•
•
•
•
•
Power management via PCI Power Management
•
•
Read/write access to audio codec registers 00h–3Ah and vendor registers 5Ah–7Eh
20-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear
channels on slots 3,4,6,7,8,9,10,11)
16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4)
16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono
mix supports mono hardware AEC reference for speakerphone)
16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6)
(supports speech recognition or stereo hardware AEC ref for speakerphone)
During cold reset ACZ_RST# is held low until after POST and software deassertion of
ACZ_RST# (supports passive PC_BEEP to speaker connection during POST)
•
•
•
•
•
PCI Modem
function
232
Isochronous low latency bus master memory interface
Scatter/gather support for word-aligned buffers in memory
(all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types
are supported)
Data buffer size in system memory from 3 to 65535 samples per input
Data buffer size in system memory from 0 to 65535 samples per output
Independent PCI audio and modem functions with configuration and I/O spaces
AC ’97 codec registers are shadowed in system memory via driver
AC ’97 codec register accesses are serialized via semaphore bit in PCI I/O space (new
accesses are not allowed while a prior access is still in progress)
•
•
•
•
Read/write access to modem codec registers 3Ch–58h and vendor registers
5Ah–7Eh
16-bit mono modem line 1 output and input, up to 48 kHz (slot 5)
Low latency GPIO[15:0] via hardwired update between slot 12 and PCI I/O register
Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT
SCI event generation on ACZ_SDIN[2:0] wake-up signal
Intel ® ICH7 Family Datasheet
Functional Description
Table 5-59. Features Supported by Intel® ICH7 (Sheet 2 of 2)
Feature
Description
•
•
AC-link
•
•
•
•
•
•
•
Multiple Codec
•
AC ’97 2.3 AC-link interface
Variable sample rate output support via AC ’97 SLOTREQ protocol (slots
3,4,5,6,7,8,9,10,11)
Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6)
3.3 V digital operation meets AC ’97 2.3 DC switching levels
AC-link I/O driver capability meets AC ’97 2.3 triple codec specifications
Codec register status reads must be returned with data in the next AC-link frame, per
AC ’97 Specification, Version 2.3.
Triple codec addressing: All AC ’97 Audio codec register accesses are addressable to
codec ID 00 (primary), codec ID 01 (secondary), or codec ID 10 (tertiary).
Modem codec addressing: All AC ‘97 Modem codec register accesses are addressable
to codec ID 00 (primary) or codec ID 01 (secondary).
Triple codec receive capability via ACZ_SDIN[2:0] pins
(ACZ_SDIN[2:0] frames are internally validated, synchronized, and OR’d depending
on the Steer Enable bit status in the SDM register)
ACZ_SDIN mapping to DMA engine mapping capability allows for simultaneous input
from two different audio codecs.
NOTES:
1.
Audio Codec IDs are remappable and not limited to 00,01,10.
2.
Modem Codec IDs are remappable and limited to 00, 01.
3.
When using multiple codecs, the Modem Codec must be ID 01.
Note:
Throughout this document, references to D31:F5 indicate that the audio function exists
in PCI Device 31, Function 5. References to D31:F6 indicate that the modem function
exists in PCI Device 31, Function 6.
Note:
Throughout this document references to tertiary, third, or triple codecs refer to the
third codec in the system connected to the ACZ_SDIN2 pin. The AC ’97 Specification,
Version 2.3 refers to non-primary codecs as multiple secondary codecs. To avoid
confusion and excess verbiage, this datasheet refers to it as the third or tertiary codec.
Figure 5-12. Intel® ICH7-Based Audio Codec ’97 Specification, Version 2.3
Audio In (Record)
Audio Out (6 Channel Playback)
PC
S/PDIF* Output
Modem
Mic.1
Mic.2
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233
Functional Description
5.22.1
PCI Power Management
This Power Management section applies for all AC ’97 controller functions. After a
power management event is detected, the AC ’97 controller wakes the host system.
The following sections describe these events and the AC ’97 controller power states.
Device Power States
The AC ’97 controller supports D0 and D3 PCI Power Management states. The following
are notes regarding the AC ’97 controller implementation of the Device States:
1. The AC ’97 controller hardware does not inherently consume any more power when
it is in the D0 state than it does in D3 state. However, software can halt the DMA
engine prior to entering these low power states such that the maximum power
consumption is reduced.
2. In the D0 state, all implemented AC ’97 controller features are enabled.
3. In D3 state, accesses to the AC ’97 controller memory-mapped or I/O range results
in master abort.
4. In D3 state, the AC ’97 controller interrupt will not assert for any reason. The
internal PME# signal is used to signal wake events, etc.
5. When the Device Power State field is written from D3HOT to D0, an internal reset is
generated. See Section 17.1 for general rules on the effects of this reset.
6. AC97 STS bit is set only when the audio or modem resume events were detected
and their respective PME enable bits were set.
7. GPIO Status change interrupt no longer has a direct path to the AC97 STS bit. This
causes a wake up event only if the modem controller was in D3
8. Resume events on ACZ_SDIN[2:0] cause resume interrupt status bits to be set
only if their respective controllers are not in D3.
9. Edge detect logic prevents the interrupts from being asserted in case the AC97
controller is switched from D3 to D0 after a wake event.
10. Once the interrupt status bits are set, they will cause PIRQB# if their respective
enable bits were set. One of the audio or the modem drivers will handle the
interrupt.
5.22.2
AC-Link Overview
The ICH7 is an AC ’97 2.3 controller that communicates with companion codecs via a
digital serial link called the AC-link. All digital audio/modem streams and command/
status information is communicated over the AC-link.
The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and
output data streams, as well as control register accesses, employing a time division
multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through
individual frames transmitted in a serial fashion. Each frame is divided into 12 outgoing
and 12 incoming data streams, or slots. The architecture of the ICH7 AC-link allows a
maximum of three codecs to be connected. Figure 5-13 shows a three codec topology
of the AC-link for the ICH7. The AC-link consists of a five signal interface between the
ICH7 and codec(s).
Note:
234
The ICH7’s AC ‘97 controller shares the signal interface with the Intel High Definition
Audio controller. However, only one controller may be enabled at a time.
Intel ® ICH7 Family Datasheet
Functional Description
Figure 5-13. AC ’97 2.3 Controller-Codec Connection
AC / MC / AMC
ACZ_RST#
ACZ_SDOUT
ACZ_SYNC
ACZ_BIT_CLK
Primary Codec
Intel®
ICH7
ACZ_SDIN2
ACZ_SDIN1
ACZ_SDIN0
AC / MC / AMC
Secondary Codec
AC / MC / AMC
Tertiary Codec
AC97 ICH codec conn
ICH7 core well outputs may be used as strapping options for the ICH7, sampled during
system reset. These signals may have weak pullups/pulldowns; however, this will not
interfere with link operation. ICH7 inputs integrate weak pulldowns to prevent floating
traces when a secondary and/or tertiary codec is not attached. When the Shut Off bit in
the control register is set, all buffers will be turned off and the pins will be held in a
steady state, based on these pullups/pulldowns.
ACZ_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides
the necessary clocking to support the twelve 20-bit time slots. AC-link serial data is
transitioned on each rising edge of ACZ_BIT_CLK. The receiver of AC-link data samples
each serial bit on the falling edge of ACZ_BIT_CLK.
If ACZ_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH7
assumes the primary codec is not present or not working. It sets bit 28 of the Global
Status Register
(I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh
to prevent system hangs.
Intel ® ICH7 Family Datasheet
235
Functional Description
Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via
the ACZ_SYNC signal, as shown in Figure 5-14. The primary codec drives the serial bit
clock onto the AC-link, which the AC ’97 controller then qualifies with the ACZ_SYNC
signal to construct data frames. ACZ_SYNC, fixed at 48 kHz, is derived by dividing
down ACZ_BIT_CLK. ACZ_SYNC remains high for a total duration of 16 ACZ_BIT_CLK
at the beginning of each frame. The portion of the frame where ACZ_SYNC is high is
defined as the tag phase. The remainder of the frame where ACZ_SYNC is low is
defined as the data phase. Each data bit is sampled on the falling edge of
ACZ_BIT_CLK.
Figure 5-14. AC-Link Protocol
Tag Phase
Data Phase
20.8uS
(48 KHz)
SYNC
12.288 MHz
81.4 nS
BIT_CLK
Codec
Ready
SDIN
slot(1) slot(2)
End of previous
Audio Frame
slot(12) "0"
"0"
Time Slot "Valid"
Bits
("1" = time slot contains valid PCM
"0"
19
0
Slot 1
19
0
Slot 2
19
0
Slot 3
19
0
Slot 12
The ICH7 has three ACZ_SDIN pins allowing a single, dual, or triple codec
configuration. When multiple codecs are connected, the primary, secondary, and
tertiary codecs can be connected to any ACZ_SDIN line. The ICH7 does not distinguish
between codecs on its ACZ_SDIN[2:0] pins, however the registers do distinguish
between ACZ_SDIN[0], ACZ_SDIN[1], and ACZ_SDIN[2] for wake events, etc. If using
a Modem Codec it is recommended to connect it to ACZ_SDIN1.
The ICH7 does not support optional test modes as outlined in the AC ’97 Specification,
Version 2.3.
5.22.2.1
Register Access
In the ICH7 implementation of the AC-link, up to three codecs can be connected to the
SDOUT pin. The following mechanism is used to address the primary, secondary, and
tertiary codecs individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits
[18:12] of slot 1 are used for the register index. For I/O writes to the primary codec,
the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in Table 5-60.
Slot 1 is used to transmit the register address, and slot 2 is used to transmit data. For
I/O reads to the primary codec, only slot 1 should be valid since only an address is
transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1
and 2 valid bits are set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as
described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot
0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero value. This
allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and
bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary
codec. If the register access is targeted to the secondary or tertiary codec, slot 1 and 2
will contain the address and data for the register access. Since slots 1 and 2 are
marked invalid, the primary codec will ignore these accesses.
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Intel ® ICH7 Family Datasheet
Functional Description
Table 5-60. Output Tag Slot 0
Bit
Primary
Access
Example
Secondary
Access
Example
15
1
1
Frame Valid
Description
14
1
0
Slot 1 Valid, Command Address bit (Primary codec
only)
13
1
0
Slot 2 Valid, Command Data bit (Primary codec only)
12:
3
X
X
Slot 3–12 Valid
2
0
0
1:0
00
Reserved
Codec ID (00 reserved for primary; 01 indicate
secondary; 10 indicate tertiary)
01
When accessing the codec registers, only one I/O cycle can be pending across the AClink at any time. The ICH7 implements write posting on I/O writes across the AC-link
(i.e., writes across the link are indicated as complete before they are actually sent
across the link). In order to prevent a second I/O write from occurring before the first
one is complete, software must monitor the CAS bit in the Codec Access Semaphore
register which indicates that a codec access is pending. Once the CAS bit is cleared,
then another codec access (read or write) can go through. The exception to this being
reads to offset 54h/D4h/154h (slot 12) which are returned immediately with the most
recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary, secondary
and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a normal
register access. Slot 12 is also updated immediately to reflect the data being written.
The controller does not issue back to back reads. It must get a response to the first
read before issuing a second. In addition, codec reads and writes are only executed
once across the link, and are not repeated.
5.22.3
AC-Link Low Power Mode
The AC-link signals can be placed in a low-power mode. When the AC ’97 Powerdown
register (26h), is programmed to the appropriate value, both ACZ_BIT_CLK and
ACZ_SDIN will be brought to, and held at a logic low voltage level.
Figure 5-15. AC-Link Powerdown Timing
SYNC
BIT_CLK
SDOUT
slot 12
prev. frame
TAG
SDIN
slot 12
prev. frame
TAG
Write to
0x20
Data
PR4
Note:
BIT_CLK not to scale
Intel ® ICH7 Family Datasheet
237
Functional Description
ACZ_BIT_CLK and ACZ_SDIN transition low immediately after a write to the
Powerdown Register (26h) with PR4 enabled. When the AC ’97 controller driver is at the
point where it is ready to program the AC-link into its low-power mode, slots 1 and 2
are assumed to be the only valid stream in the audio output frame.
The AC ’97 controller also drives ACZ_SYNC, and ACZ_SDOUT low after programming
AC ’97 to this low power, halted mode
Once the codec has been instructed to halt, ACZ_BIT_CLK, a special wake up protocol
must be used to bring the AC-link to the active mode since normal output and input
frames can not be communicated in the absence of ACZ_BIT_CLK. Once in a low-power
mode, the ICH7 provides three methods for waking up the AC-link; external wake
event, cold reset and warm reset.
Note:
Before entering any low-power mode where the link interface to the codec is expected
to be powered down while the rest of the system is awake, the software must set the
“Shut Off” bit in the control register.
5.22.3.1
External Wake Event
Codecs can signal the controller to wake the AC-link, and wake the system using
ACZ_SDIN.
Figure 5-16. SDIN Wake Signaling
Power Down
Frame
Sleep State
New Audio
Frame
Wake Event
SYNC
BIT_CLK
SDOUT
slot 12
prev. frame
TAG
SDIN
slot 12
prev. frame
TAG
Write to
0x20
Data
PR4
TAG
Slot 1
Slot 2
TAG
Slot 1
Slot 2
The minimum ACZ_SDIN wake up pulse width is 1 us. The rising edge of ACZ_SDIN0,
ACZ_SDIN1 or ACZ_SDIN2 causes the ICH7 to sequence through an AC-link warm
reset and set the AC97_STS bit in the GPE0_STS register to wake the system. The
primary codec must wait to sample ACZ_SYNC high and low before restarting
ACZ_BIT_CLK as diagrammed in Figure 5-16. The codec that signaled the wake event
must keep its ACZ_SDIN high until it has sampled ACZ_SYNC having gone high, and
then low.
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used
depends on the system’s current power down state. Unless a cold or register reset (a
write to the Reset register in the codec) is performed, wherein the AC ’97 codec
registers are initialized to their default values, registers are required to keep state
during all power down modes.
Once powered down, activation of the AC-link via re-assertion of the ACZ_SYNC signal
must not occur for a minimum of four audio frame times following the frame in which
the power down was triggered. When AC-link powers up, it indicates readiness via the
codec ready bit.
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Intel ® ICH7 Family Datasheet
Functional Description
5.22.4
AC ’97 Cold Reset
A cold reset is achieved by asserting ACZ_RST# for 1 µs. By driving ACZ_RST# low,
ACZ_BIT_CLK, and ACZ_SDOUT will be activated and all codec registers will be
initialized to their default power on reset values. ACZ_RST# is an asynchronous AC ’97
input to the codec.
5.22.5
AC ’97 Warm Reset
A warm reset re-activates the AC-link without altering the current codec register
values. A warm reset is signaled by driving ACZ_SYNC high for a minimum of 1 µs in
the absence of ACZ_BIT_CLK.
Within normal frames, ACZ_SYNC is a synchronous AC ’97 input to the codec. However,
in the absence of ACZ_BIT_CLK, ACZ_SYNC is treated as an asynchronous input to the
codec used in the generation of a warm reset.
The codec must not respond with the activation of ACZ_BIT_CLK until ACZ_SYNC has
been sampled low again by the codec. This prevents the false detection of a new frame.
Note:
On receipt of wake up signaling from the codec, the digital controller issues an interrupt
if enabled. Software then has to issue a warm or cold reset to the codec by setting the
appropriate bit in the Global Control Register.
5.22.6
Hardware Assist to Determine ACZ_SDIN Used Per Codec
Software first performs a read to one of the audio codecs. The read request goes out on
ACZ_SDOUT. Since the ICH7 allows one read to be performed at a time on the link,
eventually the read data will come back in on one of the ACZ_SDIN[2:0] lines.
The codec does this by indicating that status data is valid in its TAG, then echoes the
read address in slot 1 followed by the read data in slot 2.
The new function of the ICH7 hardware is to notice which ACZ_SDIN line contains the
read return data, and to set new bits in the new register indicating which ACZ_SDIN
line the register read data returned on. If it returned on ACZ_SDIN[0], bits [1:0]
contain the value 00. If it returned on ACZ_SDIN[1], the bits contain the value 01, etc.
ICH7 hardware can set these bits every time register read data is returned from a
function 5 read. No special command is necessary to cause the bits to be set. The new
driver/BIOS software reads the bits from this register when it cares to, and can ignore
it otherwise. When software is attempting to establish the codec-to-ACZ_SDIN
mapping, it will single feed the read request and not pipeline to ensure it gets the right
mapping, we cannot ensure the serialization of the access.
Intel ® ICH7 Family Datasheet
239
Functional Description
5.23
Intel® High Definition Audio Overview
The ICH7’s Intel High Definition Audio controller shares pins with the AC ’97 controller.
However, only one controller may be enabled at a time.
Note:
The ICH7-U Ultra Mobile component does not contain an AC ‘97 controller.
The ICH7’s controller communicates with the external codec(s) over the Intel High
Definition Audio serial link. The controller consists of a set of DMA engines that are
used to move samples of digitally encoded data between system memory and an
external codec(s). The ICH7 implements four output DMA engines and 4 input DMA
engines. The output DMA engines move digital data from system memory to a D-A
converter in a codec. ICH7 implements a single Serial Data Output signal
(ACZ_SDOUT) that is connected to all external codecs. The input DMA engines move
digital data from the A-D converter in the codec to system memory. The ICH7
implements three Serial Digital Input signals (ACZ_SDI[2:0]) supporting up to three
codecs.
Audio software renders outbound and processes inbound data to/from buffers in
system memory. The location of individual buffers is described by a Buffer Descriptor
List (BDL) that is fetched and processed by the controller. The data in the buffers is
arranged in a predefined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bit/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the external codecs over the Intel High Definition Audio link. The input
DMA engines receive data from the codecs over the Intel High Definition Audio link and
format the data based on the programmable attributes for that stream. The data is
then written to memory in the predefined format for software to process. Each DMA
engine moves one stream of data. A single codec can accept or generate multiple
streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can
accept the same output stream processed by a single DMA engine.
Codec commands and responses are also transported to and from the codecs via DMA
engines.
5.23.1
Intel® High Definition Audio Docking (Mobile Only)
5.23.1.1
Dock Sequence
Note that this sequence is followed when the system is running and a docking event
occurs.
1. Since the ICH7 supports docking, the Docking Supported (DCKSTS. DS) bit defaults
to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD
Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST
to effectively turn off the docking feature.
2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and
the Dock Mate (DCKSTS.DM) bit are both de-asserted. The AZ_DOCK_EN# signal is
de-asserted and AZ_DOCK_RST# is asserted. BCLK, SYNC and SDO signals may or
may not be running at the point in time that the docking event occurs.
3. The physical docking event is signaled to ACPI BIOS software via ACPI control
methods. This is normally accomplished through a GPIO signal on the ICH7 and is
outside the scope of this section.
4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1
and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1
to the DCKCTL.DA bit.
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Intel ® ICH7 Family Datasheet
Functional Description
5. The HD Audio controller then asserts the AZ_DOCK_EN# signal so that the BCLK
signal begins toggling to the dock codec. AZ_DOCK_EN# shall be asserted
synchronously to BCLK and timed such that BCLK is low, SYNC is low, and SDO is
low. Pull-down resistors on these signals in the docking station discharge the
signals low so that the state of the signal on both sides of the switch is the same
when the switch is turned on. This reduces the potential for charge coupling
glitches on these signals. Note that in the ICH7 the first 8 bits of the Command field
are “reserved” and always driven to 0s. This creates a predictable point in time to
assert AZ_DOCK_EN#. Note that the HD Audio link reset exit specification that
requires that SYNC and SDO be driven low during BCLK startup is not ensured.
Note also that the SDO and BCLK signals may not be low while AZ_DOCK_RST# is
asserted which also does not comply with the specification.
6. After the controller asserts AZ_DOCK_EN# it waits for a minimum of 2400 BCLKs
(100 us) and then de-asserts AZ_DOCK_RST#. This is accomplished in such a way
to meet the HD Audio link reset exit specification. AZ_DOCK_RST# de-assertion
should be synchronous to BCLK and timed such that there are least 4 full BCLKS
from the de-assertion of AZ_DOCK_RST# to the first frame SYNC assertion.
7. The Connect/Turnaround/Address Frame hardware initialization sequence will now
occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high
on the last BCLK cycle of the Frame Sync of a Connect Frame. The appropriate
bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround
and Address Frame initialization sequence then occurs on the dock codec's SDI(s).
8. After this hardware initialization sequence is complete (approximately 32 frames),
the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now
mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,
conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD
Audio Bus Driver, which then begins its codec discovery, enumeration, and
configuration process.
9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an
interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs
attached to them. When a corresponding STATESTS bit gets set, an interrupt is
generated. In this case the HD Audio Bus Driver is called directly by this interrupt
instead of being notified by the plug-N-play IRP.
10. HD Audio Bus Driver software “discovers” the dock codecs by comparing the bits
now set in the STATESTS register with the bits that were set prior to the docking
event.
5.23.1.2
Exiting D3/CRST# when Docked
1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted
resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the
dock state machines are reset, the dock is electrically isolated (AZ_DOCK_EN# deasserted) and DOCK_RST# is asserted.
2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits
approximately 7ms, then checks the STATESTS bits to see which codecs are
present.
3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is
still set and the controller hardware sequences through steps to electrically connect
the dock by asserting AZ_DOCK_EN# and then eventually de-asserts DOCK_RST#.
This completes within the 7 ms mentioned in step 2).
4. The Bus Driver enumerates the codecs present as indicated via the STATESTS bits.
5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.
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Functional Description
5.23.1.3
Cold Boot/Resume from S3 When Docked
1. When booting and resuming from S3, PLTRST# switches from asserted to deasserted. This clears the DCKCTL.DA bit and the dock state machines. Because the
dock state machines are reset, the dock is electrically isolated (AZ_DOCK_EN# deasserted) and DOCK_RST# is asserted.
2. POST BIOS detects that the dock is attached and sets the DCKCTL.DA bit to 1. Note
that at this point CRST# is still asserted so the dock state machine will remain in its
reset state.
3. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits
approximately 7 ms, then checks the STATESTS bits to see which codecs are
present.
4. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is
still set and the controller hardware sequences through steps to electrically connect
the dock by asserting AZ_DOCK_EN# and then eventually de-asserts DOCK_RST#.
This completes within the 7 ms mentioned in step 3).
5. The Bus Driver enumerates the codecs present as indicated via the STATESTS bits.
5.23.1.4
Undock Sequence
There are two possible undocking scenarios. The first is the one that is initiated by the
user that invokes software and gracefully shuts down the dock codecs before they are
undocked. The second is referred to as the “surprise undock” where the user undocks
while the dock codec is running. Both of these situations appear the same to the
controller as it is not cognizant of the “surprise removal”. But both sequences will be
discussed here.
5.23.1.4.1
Normal Undock
1. In the docked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate
(DCKSTS.DM) bit are both asserted. The AZ_DOCK_EN# signal is asserted and
AZ_DOCK_RST# is de-asserted.
2. The user initiates an undock event through the GUI interface or by pushing a
button. This mechanism is outside the scope of this section of the document. Either
way ACPI BIOS software will be invoked to manage the undock process.
3. ACPI BIOS will call the HD Audio Bus Driver software in order to halt the stream to
the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not
capable of halting the stream to the docked codec, ACPI BIOS will initiate the
hardware undocking sequence as described in the next step while the dock stream
is still running. From this standpoint, the result is similar to the “surprise undock”
scenario where an audio glitch may occur to the docked codec(s) during the undock
process.
4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the
DCKCTL.DA bit.
5. The HD Audio controller asserts AZ_DOCK_RST#. AZ_DOCK_RST# assertion shall
be synchronous to BCLK. There are no other timing requirements for
AZ_DOCK_RST# assertion. Note that the HD Audio link reset specification
requirement that the last Frame sync be skipped will not be met.
6. A minimum of 4 BCLKs after AZ_DOCK_RST# the controller will de-assert
AZ_DOCK_EN# to isolate the dock codec signals from the ICH7 HD Audio link
signals. AZ_DOCK_EN# is de-asserted synchronously to BCLK and timed such that
BCLK, SYNC, and SDO are low.
7. After this hardware undocking sequence is complete (a maximum of TBD from
DCKCTL.DA being written from “1” to “0”), the controller hardware clears the
DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS software
polls DCKSTS.DM and when it sees DM set, conveys to the end user that physical
undocking can proceed. The controller is now ready for a subsequent docking
event.
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Intel ® ICH7 Family Datasheet
Functional Description
5.23.1.4.2
Surprise Undock
1. In the surprise undock case the user undocks before software has had the
opportunity to gracefully halt the stream to the dock codec and initiate the
hardware undock sequence.
2. A signal on the docking connector is connected to the switch that isolates the dock
codec signals from the ICH7 HD Audio link signals (DOCK_DET# in the conceptual
diagram). When the undock event begins to occur the switch will be put into isolate
mode.
3. The undock event is communicated to the ACPI BIOS via ACPI control methods that
are outside the scope of this section of the document.
4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD
Audio Bus Driver via plug-N-play IRP. The Bus Driver then posthumously cleans up
the dock codec stream.
5. The HD Audio controller hardware is oblivious to the fact that a surprise undock
occurred. The flow from this point on is identical to the normal undocking sequence
described in section 0 starting at step 3). It finishes with the hardware clearing the
DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is
now ready for a subsequent docking event.
5.23.1.5
Interaction Between Dock/Undock and Power Management States
When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for
initiating the docking sequence if the dock is already attached when PLTRST# is deasserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver deasserting CRTS# and detecting and enumerating the codecs attached to the
AZ_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware
signal indicating that a dock is attached. Therefore, a method outside the scope of this
document must be used to cause the POST BIOS to initiate the docking sequence.
When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the
DCKCTL.DA bit is not cleared. The dock state machine will be reset such that
AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST# will be asserted and the
DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted,
the dock state machine will detect that DCKCTL.DA is set to “1” and will begin
sequencing through the dock process. Note that this does not require any software
intervention.
5.23.1.6
Relationship between AZ_DOCK_RST# and AZ_RST#
AZ_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As long
as AZ_RST# is asserted, the DOCK_RST# signal will also be asserted.
When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to
their default state (0's), and the dock state machine will be reset such that
AZ_DOCK_EN# will be de-asserted, and AZ_DOCK_RST# will be asserted. After any
PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and
then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting
CRST#.
When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state
machine will be reset such that AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST#
will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the
CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to
“1” and will begin sequencing through the dock process. Note that this does not require
any software intervention.
Intel ® ICH7 Family Datasheet
243
Functional Description
5.24
Intel® Active Management Technology (Intel®
AMT) (Desktop and Mobile Only)
Intel Active Management Technology is a set of advanced manageability features
developed as a direct result of IT customer feedback gained through Intel market
research. Reducing the Total Cost of Ownership (TCO) through improved asset tracking,
remote manageability, and fewer desk-side visits were identified as key IT priorities. PT
extends the capabilities of existing management solutions by making the asset
information, remote diagnostics, and recovery capabilities always available, or Out of
Band (OOB), even when the system is in a low-power “off” state or the OS is hung.
5.24.1
Intel® AMT Features
• E-Asset Tag
• OOB HW and SW Inventory Logs
• OOB Alerts
• IDE Redirect
• Serial over LAN for Remote Control
• Remote Diagnostics Execution
• OS Lock-Up Alert
• OS Repair
• Remote BIOS Recovery and Update
5.24.2
Intel® AMT Requirements
Intel AMT is a platform-level solution that uses multiple system components including:
• Intel AMT-Ready ICH7 component for the SMBus, PCI Express, SPI flash bus, and
system sensors
• Intel® PRO 82573E Gigabit Ethernet Controller with Intel® Active Management
Technology for remote access
• An embedded microcontroller to run OOB firmware/software
• SPI flash memory (4 Mb for Intel AMT) to store asset information, management
software code, and logs
• BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can
optionally share same flash memory device)
• Familiar ISV software packages to take advantage of Intel AMT’s platform
management capabilities
244
Intel ® ICH7 Family Datasheet
Functional Description
5.25
Serial Peripheral Interface (SPI) (Desktop and
Mobile Only)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially
lower-cost alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(CS#).
Communication on the SPI bus is done with a Master – Slave protocol. The typical bus
topology consists of a single SPI Master (ICH7) with a single SPI Slave (flash device).
The Slave is connected to the ICH7 and is implemented as a tri-state bus.
Arbitration has been added that enables an optional shared flash configuration where
the ICH7 shares access to the SPI flash device with the PCI Express based Intel PRO
82573E Gigabit Ethernet Controller. This configuration allows a single larger density
flash device to replace two smaller density flash devices on the motherboard to
potentially reduce bill of material (BOM) costs.
Note:
When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by the ICH7, LPC based BIOS flash is disabled.
5.25.1
SPI Arbitration between Intel® ICH7 and Intel PRO
82573E
The Shared Flash implementation consists of two SPI masters (ICH7 and Intel PRO
82573E) that arbitrate for access to a single shared SPI Device. This allows for
consolidation of Non-Volatile memory required by the Intel PRO 82573E GbE device
with the system BIOS offering the potential for BOM and board real estate savings.
The arbitration between Intel PRO 82573E and ICH7 occurs with the addition of an ARB
signal. The SPI flash device is connected to both the Intel PRO 82573E and ICH7 chips
and implemented as a shared tri-state bus; the ARB signal is connected directly from
Intel PRO 82573E to ICH7 and not to the SPI device.
The Shared Flash configuration allows each master to complete write and erase
commands to the SPI Flash, before allowing the other master to take ownership of the
bus
5.25.2
Flash Device Configurations
The ICH7, Intel PRO 82573E GbE LAN with Intel® Active Management Technology, and
SPI flash may be used in multiple configurations. Table 5-61 focuses on these various
configurations involving the ICH7.
Table 5-61. SPI Implementation Options
Configuration
Intel PRO
82573E with
Intel AMT
Present
Intel PRO
82573E
Firmware with
Intel AMT
System
BIOS
Location
System BIOS
and Intel
AMT Shared
Flash
FWH
Present
Number of
SPI
Device(s)
1
No
No
FWH
No
Yes
0
2
No
No
SPI
No
No
1
3
Yes
SPI
FWH
No
Yes
1
4
Yes
SPI
SPI
No
No
2
5
Yes
SPI
SPI
Yes
No
1
Note:
The ICH7 SPI interface supports a single Chip Select pin for a single SPI device.
Intel ® ICH7 Family Datasheet
245
Functional Description
5.25.3
SPI Device Compatibility Requirements
A variety of SPI flash devices exist in the market. In order for a SPI device to be
compatible with the ICH7 it must meet the minimum requirements detailed in the
following sections.
5.25.3.1
Intel® ICH7 SPI Based BIOS Only Configuration Requirements
(Non-Shared Flash Configuration)
A SPI flash device must meet the following minimum requirements to be compatible
with the ICH7 in a non-shared flash configuration:
• Erase size capability of at least one of the following: 64 KB, 32 KB, 4 KB, 2 KB, 512
bytes, or 256 bytes.
• Required command set and associated opcodes (Refer to Section 5.25.4.1).
• Device identification command (Refer to Section 5.25.4.2).
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.25.4.3)
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh simply aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported, the device must complete
the cycle gracefully without any impact on the flash content.
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
inside the designated area (page, sector, block, chip, or etc.).
• Minimum density of 4 Mb (Platform dependent based on size of BIOS).
Note:
The ICH7 only supports Mode 0 on SPI flash devices
5.25.3.2
Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware
Configuration Requirements (Shared Flash Configuration)
A SPI flash device must meet the following minimum requirements to be compatible
with the ICH7 and the Intel PRO 82573E GbE with Intel AMT device in a shared flash
configuration:
The following are requirements that are in common with the BIOS only configuration
listed in Section 5.25.3.1:
• Required command set and associated opcodes (Refer to Section 5.25.4.1)
• Device identification command (Refer to Section 5.25.4.2)
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.25.4.3)
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh simply aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported, the device must complete
the cycle gracefully without any impact on the flash content.
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
inside the designated area (page, sector, block, chip, or etc.).
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Intel ® ICH7 Family Datasheet
Functional Description
The following is a list of additional requirements specific to the ICH7 with Intel PRO
82573E configuration:
• Erase size capability of at least one of the following: 4 KBytes (preferred) or 256
bytes.
• Byte write must be supported.
• A serial flash device that requires the Write Enable command must automatically
clear the Write Enable Latch at the end of Data Program instructions
• Status Register bit 0 must be set to 1 when a write or erase is in progress and
cleared to 0 when a write or erase is not in progress.
• Minimum density of 4 Mb for non-BIOS data storage
• Minimum density of 8 Mb for shared flash configurations (4 Mb for non-BIOS data +
4 Mb for BIOS - platform dependant based on size of BIOS)
Note:
The ICH7 only supports Mode 0 on SPI flash devices.
5.25.4
Intel® ICH7 Compatible Command Set
5.25.4.1
Required Command Set for Inter Operability
Table 5-62 contains a list of commands and the associated opcodes that a SPI based
serial flash device must support in order to be interoperable with the serial flash
interface.
Table 5-62. Required Commands and Opcodes
Commands
5.25.4.2
OPCODE
Program Data
02h
Read Data
03h
Read Status
05h
Recommended Standard Commands
The following table contains a list of standard commands that a SPI device should
support to be compatible with the ICH7. This list only contains standard commands and
is not meant to be an all inclusive list of commands that SPI devices can support.
Table 5-63. Intel® ICH7 Standard SPI Commands
Commands
OPCODE
Notes
Write Status
01h
Write Disable
04h
Write Enable
06h
If command is supported by a device, 06h must be supported.
Fast Read
0Bh
Intel® ICH7 does not support this command.
JEDEC ID
9Fh
Either JEDEC ID (9Fh) or an Identify Device with ABh is required,
not both.
Identify Device
ABh
Either JEDEC ID (9Fh) or an Identify Device with ABh is required,
not both
Intel ® ICH7 Family Datasheet
If command is supported by a device, 01h must be supported.
247
Functional Description
5.25.4.3
Multiple Page Write Usage Model
The system BIOS and Intel® Active Management Technology firmware usage models
require that the serial flash device support multiple writes (minimum of 512 writes) to
a page (256 bytes) without requiring a preceding erase command. BIOS commonly
uses capabilities such as counters that are typically implemented by using byte writes
to ‘increment’ the bits within a page that have been designated as the counter. The
Intel AMT firmware usage model requires the capability for multiple data updates within
any given page. These data updates occur via byte writes without executing a
preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple
page write usage models apply to sequential and non-sequential data writes.
Note:
This usage model requirement is based on any given bit only being written once from a
‘1’ to a ‘0’ without requiring the preceding erase. An erase would be required to change
bits back to the ‘1’ state.
5.25.5
Flash Protection
There are three types of Flash Protection mechanisms:
1. BIOS Range Write Protection
2. SMI#-Based Global Write Protection
3. Shared Flash Address Range Protection
The three mechanisms are conceptually OR’d together such that if any of the
mechanisms indicate that the access should be blocked, then it is blocked. Table 5-64
provides a summary of the Three Mechanisms.
Table 5-64. Flash Protection Mechanism Summary
Mechanism
Accesses
Blocked
Range
Specific
?
Reset-Override
or SMI#Override?
Equivalent Function on FWH
BIOS Range
Write
Protection
Writes
Yes
Reset Override
FWH Sector Protection
Write Protect
Writes
No
SMI# Override
Same as Write Protect in
previous ICH components for
FWH
BIOS BAR
Reads and
Writes
Yes
Reset Override
Not Applicable- Specific to
Flash Sharing
A blocked command will appear to software to finish, except that the Blocked Access
status bit is set in this case.
5.25.5.1
BIOS Range Write Protection
The ICH7 provides a method for blocking writes to specific ranges in the SPI flash when
the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) and the address of the
requested command against the base and limit fields of a Write Protected BIOS range.
Note:
248
Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
Intel ® ICH7 Family Datasheet
Functional Description
5.25.5.2
SMI# Based Global Write Protection
The ICH7 provides a method for blocking writes to the SPI flash when the Write Protect
bit is cleared (i.e., protected). This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) of the requested
command.
The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as
they do for the FWH BIOS.
5.25.5.3
Shared Flash Address Range Protection
The System Flash (BIOS) occupies the top part of the SPI Flash Memory Device when
sharing this space with the LAN and Manageability functions. To prevent the system
from inappropriately accessing or modifying information in the LAN and Manageability
areas, the ICH7 checks outgoing addresses with the BIOS Base Address register and
blocks any cycles with addresses below that value. This includes Direct Memory Reads
to the SPI flash.
Note:
Once BIOS has locked down the BIOS BAR, this mechanism remains in place until the
next system reset.
5.26
Intel® Quick Resume Technology (Digital Home
Only)
ICH7 implements the following Intel® Quick Resume Technology (QRT) features:
• Visual Off
• Consumer Electronics (CE) like On/Off
5.26.1
Visual Off
Intel Quick Resume Technology provides a new functional state called Visual Off. In
Visual Off the PC appears to be Off but is actually active and able to run program tasks.
The Visual Off state is transparent to the user. It is entered by simply pressing the
power button when the system is On. This turns off the display, sound, front panel
lights and HID devices (e.g. keyboard and mouse) but the PC stays active. Perceptually
to the user, the system appears Off in this state. Pressing the power button again will
turn back On the perceptual components that were “muted” in Visual Off.
From the Visual Off state, the system's power management can place the PC in a low
power suspend state (S3) using existing mechanisms. Again, this is transparent to the
end user.
5.26.2
CE-like On/Off
Intel Quick Resume Technology redefines the PC's power button behavior to switch
between user perceived On and Off states like a consumer electronics (CE) device. For
example when a television is turned off there is no shutdown procedure. The viewer
simply turns it Off. Likewise when a modern television is turned On it returns to the
same channel, volume level, color balance, etc. as when it was turned Off. Intel Quick
Resume Technology gives the PC this similar functionality. A simple press of the power
button turns it On or Off. There is no user visible lengthy boot up or shutdown process
as the Visual Off state is used. Therefore, there is no need to exit running applications.
Intel ® ICH7 Family Datasheet
249
Functional Description
Just as televisions may have multiple power buttons (e.g., on the TV and on a remote
control) so may the PC (e.g., a power button on the system unit and another on the
keyboard). However, all power buttons behave the same — On/Off. The PC will not
turn On (wake up) when any key is pressed or the mouse moved just as pressing the
volume button or TV channel button does not cause the TV to turn On. Only a power
button press turns it On and Off.
5.26.3
Intel® Quick Resume Technology Signals (ICH7DH Only)
To provide the end user notification of the system power state, it is recommended that
the front panel LED be used to indicate Visual Off in the same way that the front panel
LED is used to indicate the S3 system state. For example, if in the S3 state the front
panel LED is solid amber, also set the front panel LED to be solid amber upon entrance
into Visual Off.
To provide for platform implementation flexibility, the ICH7DH implements two Intel
Quick Resume Technology (QRT) signals that are multiplexed with GPIOs: EL_STATE0/
GPIO27 and EL_STATE1/GPIO28. The EL_STATE[1:0] pins may be used to control
LED(s) to provide end-user notification of the current system state or may be used as
GPIO pins (independently or combined). See Chapter 14 for further details on
controlling these signals.
The ICH7DH has an additional Intel QRT pin: EL_RSVD/GPIO26. When Intel QRT is
enabled, this signal is used exclusively as EL_RSVD and should be left as no connect.
Note:
EL_RSVD should be left as a no connect on motherboards that will implement Intel
QRT.
5.26.4
Power Button Sequence (ICH7DH Only)
When Intel Quick Resume Technology (QRT) is enabled and the user presses the
PWRBTN# to put the system into the Visual Off state, the following sequence is
assumed:
1. User presses the Power Button, which causes the PWRBTN# signal to go low.
2. Intel QRT logic sets the EL_PB_STS bit. If the PWRBTN_INT_EN bit is set, the ICH7
does NOT set the PWRBTN_STS bit at this point.
3. Intel QRT logic causes an SMI or SCI (depending on the SMI_OPTION_CNT bit.)
4. If the Intel QRT logic was set to cause an SMI, the SMI handler executes and then
sets the SCI_NOW_CNT bit.
5. The Intel QRT SCI handler executes.
6. The Intel QRT SCI handler needs to cause the PWRBTN_STS bit to be set, it can do
so by setting the PWRBTN_EVENT bit.
Note:
250
When PWRBTN_STS is set, the ICH7 causes an SCI and the normal OS handler for
PWRBTN_STS is called.
Intel ® ICH7 Family Datasheet
Functional Description
5.27
Feature Capability Mechanism
A new set of registers have been added into ICH7 LPC Interface (Device 31, Function 0,
offset E0h - EBh) that allows the system software or BIOS to easily determine the
features supported by ICH7. These registers can be accessed through LPC PCI
configuration space; thus allowing for convenient single point access mechanism for
chipset feature detection.
This set of registers consists of:
Capability ID (FDCAP)
Capability Length (FDLEN)
Capability Version and Vendor-Specific Capability ID (FDVER)
Feature Vector (FVECT)
§
Intel ® ICH7 Family Datasheet
251
Functional Description
252
Intel ® ICH7 Family Datasheet
Register and Memory Mapping
6
Register and Memory Mapping
The ICH7 contains registers that are located in the processor’s I/O space and memory
space and sets of PCI configuration registers that are located in PCI configuration
space. This chapter describes the ICH7 I/O and memory maps at the register-set level.
Register access is also described. Register-level address maps and Individual register
bit descriptions are provided in the following chapters. The following notations and
definitions are used in the register/instruction description chapters.
RO
Read Only. In some cases, If a register is read only, writes to this
register location have no effect. However, in other cases, two
separate registers are located at the same location where a read
accesses one of the registers and a write accesses the other
register. See the I/O and memory map tables for details.
WO
Write Only. In some cases, If a register is write only, reads to
this register location have no effect. However, in other cases,
two separate registers are located at the same location where a
read accesses one of the registers and a write accesses the
other register. See the I/O and memory map tables for details.
R/W
Read/Write. A register with this attribute can be read and
written.
R/WC
Read/Write Clear. A register bit with this attribute can be read
and written. However, a write of 1 clears (sets to 0) the
corresponding bit and a write of 0 has no effect.
R/WO
Read/Write-Once. A register bit with this attribute can be
written only once after power up. After the first write, the bit
becomes read only.
R/WLO
Read/Write, Lock-Once. A register bit with this attribute can be
written to the non-locked value multiple times, but to the locked
value only once. After the locked value has been written, the bit
becomes read only.
Default
When ICH7 is reset, it sets its registers to predetermined default
states. The default state represents the minimum functionality
feature set required to successfully bring up the system. Hence,
it does not represent the optimal system configuration. It is the
responsibility of the system initialization software to determine
configuration, operating parameters, and optional system
features that are applicable, and to program the ICH7 registers
accordingly.
Bold
Register bits that are highlighted in bold text indicate that the
bit is implemented in the ICH7. Register bits that are not
implemented or are hardwired will remain in plain text.
All bit(s) or bit-fields must be correctly dealt with by software. On reads, software must
use appropriate masks to extract the defined bits and not rely on reserved bits being
any particular value. On writes, software must ensure that the values of reserved bit
locations are preserved. Any ICH7 configuration register or I/O or memory mapped
location not explicitly indicated in this document must be considered reserved.
Intel ® ICH7 Family Datasheet
253
Register and Memory Mapping
6.1
PCI Devices and Functions
The ICH7 incorporates a variety of PCI functions as shown in Table 6-1. These functions
are divided into six logical devices (B0:D30, B0:D31, B0:D29, B0:D28, B0:D27 and
B1:D8). D30 contains the DMI interface-to-PCI bridge and the AC ’97 Audio and Modem
controller. D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and the
SMBus controller. D29 contains the four USB UHCI controllers and one USB EHCI
controller. D27 contains the Intel High Definition Audio controller. B1:D8 is the
integrated LAN controller.
Note:
From a software perspective, the integrated LAN controller resides on the ICH7’s
external PCI bus. This is typically Bus 1, but may be assigned a different number
depending on system configuration.
If for some reason, the particular system platform does not want to support any one of
the Device Functions, with the exception of D30:F0, they can individually be disabled.
The integrated LAN controller will be disabled if no Platform LAN Connect component is
detected (See Chapter 5.3). When a function is disabled, it does not appear at all to the
software. A disabled function will not respond to any register reads or writes, insuring
that these devices appear hidden to software.
b
Table 6-1.
PCI Devices and Functions
Bus:Device:Function1
Function Description
Bus 0:Device 30:Function 0
PCI-to-PCI Bridge
Bus 0:Device 30:Function 2
AC ’97 Audio Controller (Desktop and Mobile Only)
Bus 0:Device 30:Function 3
AC ’97 Modem Controller (Desktop and Mobile Only)
Bus 0:Device 31:Function 0
LPC Controller1
Bus 0:Device 31:Function 1
IDE Controller
Bus 0:Device 31:Function 2
SATA Controller (Desktop and Mobile Only)
Bus 0:Device 31:Function 3
SMBus Controller
Bus 0:Device 29:Function 0
USB UHCI Controller #1
Bus 0:Device 29:Function 1
USB UHCI Controller #2
Bus 0:Device 29:Function 2
USB UHCI Controller #3
Bus 0:Device 29:Function 3
USB UHCI Controller #4
Bus 0:Device 29:Function 7
USB 2.0 EHCI Controller
Bus 0:Device 28:Function 0
PCI Express* Port 1 (Desktop and Mobile Only)
Bus 0:Device 28:Function 1
PCI Express Port 2 (Desktop and Mobile Only)
Bus 0:Device 28:Function 2
PCI Express Port 3 (Desktop and Mobile Only)
Bus 0:Device 28:Function 3
PCI Express Port 4 (Desktop and Mobile Only)
Bus 0:Device 28:Function 4
PCI Express Port 5 (Intel® ICH7R, and ICH7DH, and ICH7-M
Only)
Bus 0:Device 28:Function 5
PCI Express Port 6 (Intel® ICH7R, and ICH7DH, and ICH7-M
Only)
Bus 0:Device 27:Function 0
Intel® High Definition Audio Controller
Bus n:Device 8:Function 0
LAN Controller (Desktop and Mobile Only)
NOTES:
1.
The LPC controller contains registers that control LPC, Power Management, System
Management, GPIO, processor Interface, RTC, Interrupts, Timers, DMA.
254
Intel ® ICH7 Family Datasheet
Register and Memory Mapping
6.2
PCI Configuration Map
Each PCI function on the ICH7 has a set of PCI configuration registers. The register
address map tables for these register sets are included at the beginning of the chapter
for the particular function. Configuration Space registers are accessed through
configuration cycles on the PCI bus by the Host bridge using configuration mechanism
#1 detailed in the PCI Local Bus Specification, Revision 2.3.
Some of the PCI registers contain reserved bits. Software must deal correctly with
fields that are reserved. On reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular value. On writes,
software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for
other bit positions and then written back. Note the software does not need to perform
read, merge, write operation for the configuration address register.
In addition to reserved bits within a register, the configuration space contains reserved
locations. Software should not write to reserved PCI configuration locations in the
device-specific region (above address offset 3Fh).
6.3
I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be
moved, but in some cases can be disabled. Variable ranges can be moved and can also
be disabled.
6.3.1
Fixed I/O Address Ranges
Table 6-2 shows the Fixed I/O decode ranges from the processor perspective. Note that
for each I/O range, there may be separate behavior for reads and writes. DMI (Direct
Media Interface) cycles that go to target ranges that are marked as “Reserved” will not
be decoded by the ICH7, and will be passed to PCI unless the Subtractive Decode Policy
bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target
ranges, it will be positively decoded by the ICH7 in medium speed.
Address ranges that are not listed or marked “Reserved” are not decoded by the ICH7
(unless assigned to one of the variable ranges).
Intel ® ICH7 Family Datasheet
255
Register and Memory Mapping
Table 6-2.
256
Fixed I/O Ranges Decoded by Intel® ICH7 (Sheet 1 of 2)
I/O
Address
Read Target
Write Target
Internal Unit
00h–08h
DMA Controller
DMA Controller
DMA
09h–0Eh
RESERVED
DMA Controller
DMA
0Fh
DMA Controller
DMA Controller
DMA
10h–18h
DMA Controller
DMA Controller
DMA
19h–1Eh
RESERVED
DMA Controller
DMA
1Fh
DMA Controller
DMA Controller
DMA
20h–21h
Interrupt Controller
Interrupt Controller
Interrupt
24h–25h
Interrupt Controller
Interrupt Controller
Interrupt
28h–29h
Interrupt Controller
Interrupt Controller
Interrupt
2Ch–2Dh
Interrupt Controller
Interrupt Controller
Interrupt
2E–2F
LPC SIO
LPC SIO
Forwarded to LPC
30h–31h
Interrupt Controller
Interrupt Controller
Interrupt
34h–35h
Interrupt Controller
Interrupt Controller
Interrupt
38h–39h
Interrupt Controller
Interrupt Controller
Interrupt
3Ch–3Dh
Interrupt Controller
Interrupt Controller
Interrupt
40h–42h
Timer/Counter
Timer/Counter
PIT (8254)
43h
RESERVED
Timer/Counter
PIT
4E–4F
LPC SIO
LPC SIO
Forwarded to LPC
50h–52h
Timer/Counter
Timer/Counter
PIT
53h
RESERVED
Timer/Counter
PIT
60h
Microcontroller
Microcontroller
Forwarded to LPC
61h
NMI Controller
NMI Controller
Processor I/F
62h
Microcontroller
Microcontroller
Forwarded to LPC
64h
Microcontroller
Microcontroller
Forwarded to LPC
66h
Microcontroller
Microcontroller
Forwarded to LPC
70h
RESERVED
NMI and RTC Controller
RTC
71h
RTC Controller
RTC Controller
RTC
72h
RTC Controller
NMI and RTC Controller
RTC
73h
RTC Controller
RTC Controller
RTC
74h
RTC Controller
NMI and RTC Controller
RTC
75h
RTC Controller
RTC Controller
RTC
76h
RTC Controller
NMI and RTC Controller
RTC
77h
RTC Controller
RTC Controller
RTC
80h
DMA Controller, or LPC, or
PCI
DMA Controller and LPC or
PCI
DMA
81h–83h
DMA Controller
DMA Controller
DMA
Intel ® ICH7 Family Datasheet
Register and Memory Mapping
Table 6-2.
Fixed I/O Ranges Decoded by Intel® ICH7 (Sheet 2 of 2)
I/O
Address
Read Target
Write Target
Internal Unit
84h–86h
DMA Controller
DMA Controller and LPC or
PCI
DMA
87h
DMA Controller
DMA Controller
DMA
88h
DMA Controller
DMA Controller and LPC or
PCI
DMA
89h–8Bh
DMA Controller
DMA Controller
DMA
8Ch–8Eh
DMA Controller
DMA Controller and LPC or
PCI
DMA
08Fh
DMA Controller
DMA Controller
DMA
90h–91h
DMA Controller
DMA Controller
DMA
92h
Reset Generator
Reset Generator
Processor I/F
93h–9Fh
DMA Controller
DMA Controller
DMA
A0h–A1h
Interrupt Controller
Interrupt Controller
Interrupt
A4h–A5h
Interrupt Controller
Interrupt Controller
Interrupt
A8h–A9h
Interrupt Controller
Interrupt Controller
Interrupt
ACh–ADh
Interrupt Controller
Interrupt Controller
Interrupt
B0h–B1h
Interrupt Controller
Interrupt Controller
Interrupt
B2h–B3h
Power Management
Power Management
Power
Management
B4h–B5h
Interrupt Controller
Interrupt Controller
Interrupt
B8h–B9h
Interrupt Controller
Interrupt Controller
Interrupt
BCh–BDh
Interrupt Controller
Interrupt Controller
Interrupt
C0h–D1h
DMA Controller
DMA Controller
DMA
D2h–DDh
RESERVED
DMA Controller
DMA
DEh–DFh
DMA Controller
DMA Controller
DMA
F0h
FERR#/IGNNE# / Interrupt
Controller
FERR#/IGNNE# / Interrupt
Controller
170h–177h
IDE Controller, SATA
Controller, or PCI
IDE Controller, SATA
Controller, or PCI
Forwarded to IDE
or SATA
1F0h–1F7h
IDE Controller, SATA
Controller, or PCI 1
IDE Controller, SATA
Controller, or PCI
Forwarded to IDE
or SATA
376h
IDE Controller, SATA
Controller, or PCI
IDE Controller, SATA
Controller, or PCI
Forwarded to IDE
or SATA
3F6h
IDE Controller, SATA
Controller, or PCI 1
IDE Controller, SATA
Controller, or PCI
Forwarded IDE or
SATA
4D0h–4D1h
Interrupt Controller
Interrupt Controller
Interrupt
CF9h
Reset Generator
Reset Generator
Processor I/F
Processor I/F
NOTES:
1.
Only if IDE I/O space is enabled (D31:F1:40 bit 15) and the IDE controller is in legacy
mode. Otherwise, the target is PCI.
Intel ® ICH7 Family Datasheet
257
Register and Memory Mapping
6.3.2
Variable I/O Decode Ranges
Table 6-3 shows the Variable I/O Decode Ranges. They are set using Base Address
Registers (BARs) or other configuration bits in the various PCI configuration spaces.
The PNP software (PCI or ACPI) can use their configuration mechanisms to set and
adjust these values.
Warning:
The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges.
Unpredictable results if the configuration software allows conflicts to occur. The ICH7
does not perform any checks for conflicts.
Table 6-3.
Variable I/O Decode Ranges
Mappable
Size
(Bytes)
Target
ACPI
Anywhere in 64 KB I/O
Space
64
Power Management
IDE Bus Master
Anywhere in 64 KB I/O
Space
16
IDE Unit
Range Name
258
Native IDE Command
Anywhere in 64 KB I/O
Space
8
IDE Unit
Native IDE Control
Anywhere in 64 KB I/O
Space
4
IDE Unit
USB UHCI Controller #1
Anywhere in 64 KB I/O
Space
32
USB Unit 1
USB UHCI Controller #2
Anywhere in 64 KB I/O
Space
32
USB Unit 2
USB UHCI Controller #3
Anywhere in 64 KB I/O
Space
32
USB Unit 3
USB UHCI Controller #4
Anywhere in 64 KB I/O
Space
32
USB Unit 4
SMBus
Anywhere in 64 KB I/O
Space
32
SMB Unit
AC ’97 Audio Mixer
Anywhere in 64 KB I/O
Space
256
AC ’97 Unit
AC ’97 Audio Bus Master
Anywhere in 64 KB I/O
Space
64
AC ’97 Unit
AC ’97 Modem Mixer
Anywhere in 64 KB I/O
Space
256
AC ’97 Unit
AC ’97 Modem Bus Master
Anywhere in 64 KB I/O
Space
128
AC ’97 Unit
TCO
96 Bytes above ACPI Base
32
TCO Unit
GPIO
Anywhere in 64 KB I/O
Space
64
GPIO Unit
Parallel Port
3 Ranges in 64 KB I/O
Space
8
LPC Peripheral
Serial Port 1
8 Ranges in 64 KB I/O
Space
8
LPC Peripheral
Serial Port 2
8 Ranges in 64 KB I/O
Space
8
LPC Peripheral
Floppy Disk Controller
2 Ranges in 64 KB I/O
Space
8
LPC Peripheral
Intel ® ICH7 Family Datasheet
Register and Memory Mapping
Table 6-3.
Variable I/O Decode Ranges
Mappable
Size
(Bytes)
Target
LAN
Anywhere in 64 KB I/O
Space
64
LAN Unit
LPC Generic 1
Anywhere in 64 KB I/O
Space
4 to 256
LPC Peripheral
LPC Generic 21
Anywhere in 64 KB I/O
Space
4 to 256
LPC Peripheral
LPC Generic 3
Anywhere in 64 KB I/O
Space
4 to 256
LPC Peripheral
LPC Generic 4
Anywhere in 64 KB I/O
Space
4 to 256
LPC Peripheral
Range Name
I/O Trapping Ranges
Anywhere in 64 KB I/O
Space
1 to 256
Trap on Backbone
NOTE:
1.
Decode range size determined by D31:F0:ADh:bits 5:4
6.4
Memory Map
Table 6-4 shows (from the processor perspective) the memory ranges that the ICH7
decodes. Cycles that arrive from DMI that are not directed to any of the internal
memory targets that decode directly from DMI will be driven out on PCI unless the
Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The ICH7 may then
claim the cycle for the internal LAN controller.
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to DMI. Software must not attempt locks to the ICH7’s memorymapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which
means potential deadlock conditions may occur.
Table 6-4.
Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
Memory Range
Target
Dependency/Comments
0000 0000h–000D FFFFh
0010 0000h–TOM
(Top of Memory)
Main Memory
TOM registers in Host controller
000E 0000h–000E FFFFh
Firmware Hub
Bit 6 in Firmware Hub Decode Enable register
is set
000F 0000h–000F FFFFh
Firmware Hub
Bit 7 in Firmware Hub Decode Enable register
is set
FEC0 0000h–FEC0 0100h
I/O APIC inside
Intel® ICH7
FED4 0000h–FED4 0FFFh
TPM on LPC
FFC0 0000h–FFC7 FFFFh
Firmware Hub (or
PCI)1
Bit 8 in Firmware Hub Decode Enable register
is set
Firmware Hub (or
PCI)1
Bit 9 in Firmware Hub Decode Enable register
is set
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
Intel ® ICH7 Family Datasheet
259
Register and Memory Mapping
Table 6-4.
Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)
Memory Range
Target
FFD0 0000h–FFD7 FFFFh
Firmware Hub (or
PCI)1
Bit 10 in Firmware Hub Decode Enable
register is set
Firmware Hub (or
PCI)1
Bit 11 in Firmware Hub Decode Enable
register is set
Firmware Hub (or
PCI)1
Bit 12 in Firmware Hub Decode Enable
register is set
Firmware Hub (or
PCI)1
Bit 13 in Firmware Hub Decode Enable
register is set
Firmware Hub (or
PCI)1
Bit 14 in Firmware Hub Decode Enable
register is set
Firmware Hub (or
PCI)1
Always enabled.
The top two, 64 KB blocks of this range can
be swapped, as described in Section 7.4.1.
Firmware Hub (or
PCI)1
Bit 3 in Firmware Hub Decode Enable register
is set
Firmware Hub (or
PCI)1
Bit 2 in Firmware Hub Decode Enable register
is set
Firmware Hub (or
PCI)1
Bit 1 in Firmware Hub Decode Enable register
is set
FF00 0000h–FF0F FFFFh
Firmware Hub (or
PCI)1
Bit 0 in Firmware Hub Decode Enable register
is set
4 KB anywhere in 4-GB
range
Integrated LAN
Controller2
1 KB anywhere in 4-GB
range
USB EHCI
Controller 2
Enable via standard PCI mechanism (Device
29, Function 7)
512 B anywhere in 4-GB
range
AC ’97 Host
Controller (Mixer)
Enable via standard PCI mechanism (Device
30, Function 2)
256 B anywhere in 4-GB
range
AC ’97 Host
Controller (Bus
Master)
Enable via standard PCI mechanism (Device
30, Function 3)
512 B anywhere in 64-bit
addressing space
Intel® High
Definition Audio
Host Controller
Enable via standard PCI mechanism (Device
30, Function 1)
FED0 X000h–FED0 X3FFh
High Precision
Event Timers 3
BIOS determines the “fixed” location which is
one of four, 1-KB ranges where X (in the first
column) is 0h, 1h, 2h, or 3h.
FF90 0000h–FF97 FFFFh
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
All other
PCI
Dependency/Comments
Enable via BAR in Device 29:Function 0
(Integrated LAN Controller)
None
NOTES:
1.
PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Config
Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits
have no effect.
2.
Only LAN cycles can be seen on PCI.
3.
Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High
Precision Event Timers. If attempted, the lock is not honored, which means potential
deadlock conditions may occur.
260
Intel ® ICH7 Family Datasheet
Register and Memory Mapping
6.4.1
Boot-Block Update Scheme
The ICH7 supports a “top-block swap” mode that has the ICH7 swap the top block in
the Firmware Hub (the boot block) with another location. This allows for safe update of
the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is
set, the ICH7 will invert A16 for cycles targeting Firmware Hub space. When this bit is
0, the ICH7 will not invert A16. This bit is automatically set to 0 by RTCRST#, but not
by PLTRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block,
and the block immediately below the top block is reserved for doing boot-block
updates.
The algorithm is:
1. Software copies the top block to the block immediately below the top
2. Software checks that the copied block is correct. This could be done by performing
a checksum calculation.
3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the
Firmware Hub. processor access to FFFF_0000h through FFFF_FFFFh will be
directed to FFFE_0000h through FFFE_FFFFh in the Firmware Hub, and processor
accesses to FFFE_0000h through FFFE_FFFF will be directed to FFFF_0000h
through FFFF_FFFFh.
4. Software erases the top block
5. Software writes the new top block
6. Software checks the new top block
7. Software clears the TOP_SWAP bit
8. Software sets the Top_Swap Lock-Down bit
If a power failure occurs at any point after step 3, the system will be able to boot from
the copy of the boot block that is stored in the block below the top. This is because the
TOP_SWAP bit is backed in the RTC well.
Note:
The top-block swap mode may be forced by an external strapping option (See
Section 2.24.1). When top-block swap mode is forced in this manner, the TOP_SWAP
bit cannot be cleared by software. A re-boot with the strap removed will be required to
exit a forced top-block swap mode.
Note:
Top-block swap mode only affects accesses to the Firmware Hub space, not feature
space.
Note:
The top-block swap mode has no effect on accesses below FFFE_0000h.
§
Intel ® ICH7 Family Datasheet
261
Register and Memory Mapping
262
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7
Chipset Configuration Registers
This chapter describes all registers and base functionality that is related to chipset
configuration and not a specific interface (e.g., LPC, PCI, or PCI Express*). It contains
the root complex register block that describes the behavior of the upstream internal
link.
This block is mapped into memory space, using register RCBA of the PCI-to-LPC bridge.
Accesses in this space must be limited to 32-(DWord) bit quantities. Burst accesses are
not allowed.
7.1
Chipset Configuration Registers (Memory Space)
Note:
Address locations that are not shown should be treated as Reserved (see Section 6.2
for details).
.
Table 7-1.
Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 3)
Offset
Mnemonic
0000–0003h
VCH
Register Name
Default
Type
Virtual Channel Capability
Header
10010002h
RO
0004–0007h
VCAP1
Virtual Channel Capability #1
00000801h
RO
0008–000Bh
VCAP2
Virtual Channel Capability #2
00000001h
RO
000C–000Dh
PVC
Port Virtual Channel Control
0000h
R/W, RO
000E–000Fh
PVS
Port Virtual Channel Status
0000h
RO
0010–0013h
V0CAP
Virtual Channel 0 Resource
Capability
00000001h
RO
0014–0017h
V0CTL
Virtual Channel 0 Resource
Control
800000FFh
R/W, RO
001A–001Bh
V0STS
Virtual Channel 0 Resource
Status
0000h
RO
001C–001Fh
V1CAP
Virtual Channel 1 Resource
Capability
30008010h
R/WO, RO
0020–0023h
V1CTL
Virtual Channel 1 Resource
Control
00000000h
R/W, RO
0026–0027h
V1STS
Virtual Channel 1 Resource
Status
0000h
RO
0100–0103h
RCTCL
Root Complex Topology
Capability List
1A010005h
RO
0104–0107h
ESD
Element Self Description
00000602h
R/WO, RO
0110–0113h
ULD
Upstream Link Descriptor
00000001h
R/WO, RO
0118–011Fh
ULBA
Upstream Link Base Address
0120–0123h
RP1D
Root Port 1 Descriptor
0128–012Fh
RP1BA
0130–0133h
RP2D
0138–013Fh
RP2BA
0140–0143h
RP3D
Intel ® ICH7 Family Datasheet
Root Port 1 Base Address
Root Port 2 Descriptor
Root Port 2 Base Address
Root Port 3 Descriptor
0000000000000000h
R/WO
01xx0002h
R/WO, RO
00000000000E0000h
RO
02xx0002h
R/WO, RO
00000000000E1000h
RO
03xx0002h
R/WO, RO
263
Chipset Configuration Registers
Table 7-1.
264
Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 3)
Offset
Mnemonic
0148–014Fh
RP3BA
0150–0153h
RP4D
0158–015Fh
RP4BA
Register Name
Root Port 3 Base Address
Root Port 4 Descriptor
Root Port 4 Base Address
0160–0163h
HDD
Intel® High Definition Audio
Descriptor
0168–016Fh
HDBA
Intel® High Definition Audio
Base Address
0170–0173h
RP5D
Root Port 5 Descriptor
0178–017Fh
RP5BA
0180–0183h
RP6D
Root Port 5 Base Address
Root Port 6 Descriptor
Root Port 6 Base Address
Default
Type
00000000000E2000h
RO
04xx0002h
R/WO, RO
00000000000E3000h
RO
05xx0002h
R/WO, RO
00000000000D8000
h
RO
05xx0002h
R/WO, RO
00000000000E4000h
RO
06xx0002h
R/WO, RO
0188–018Fh
RP6BA
00000000000E5000h
RO
01A0–01A3h
ILCL
Internal Link Capability List
00010006h
RO
01A4–01A7h
LCAP
Link Capabilities
00012441h
RO, R/WO
01A8–01A9h
LCTL
Link Control
0000h
R/W
01AA–01ABh
LSTS
Link Status
0041h
RO
0224–0227h
RPC
Root Port Configuration
0000000xh
R/W, RO
0238–023Bh
RPFN
Root Port Function Number for
PCI Express Root Ports
(Desktop and Mobile only)
00543210h
R/WO, RO
1E00–1E03h
TRSR
Trap Status Register
00h
R/WC, RO
1E10–1E17h
TRCR
Trapped Cycle Register
0000000000000000h
RO
1E18-1E1Fh
TWDR
Trapped Write Data Register
0000000000000000h
RO
1E80-1E87h
IOTR0
I/O Trap Register 0
0000000000000000h
R/W, RO
1E88-1E8Fh
IOTR1
I/O Trap Register 1
0000000000000000h
R/W, RO
1E90-1E97h
IOTR2
I/O Trap Register 2
0000000000000000h
R/W, RO
1E98-1E9Fh
IOTR3
I/O Trap Register 3
0000000000000000h
R/W, RO
3000–3001h
TCTL
TCO Control
00h
R/W
3100–3103h
D31IP
Device 31 Interrupt Pin
00042210h
R/W, RO
3104–3107h
D30IP
Device 30 Interrupt Pin
00002100h
R/W, RO
3108–310Bh
D29IP
Device 29 Interrupt Pin
10004321h
R/W
310C–310Fh
D28IP
Device 28 Interrupt Pin
00004321h
R/W
3110–3113h
D27IP
Device 27 Interrupt Pin
00000001h
R/W
3140–3141h
D31IR
Device 31 Interrupt Route
3210h
R/W
3142–3143h
D30IR
Device 30 Interrupt Route
3210h
R/W
3144–3145h
D29IR
Device 29 Interrupt Route
3210h
R/W
3146–3147h
D28IR
Device 28 Interrupt Route
3210h
R/W
3148–3149h
D27IR
Device 27 Interrupt Route
3210h
R/W
31FF–31FFh
OIC
Other Interrupt Control
00h
R/W
3400–3403h
RC
RTC Configuration
00000000h
R/W,
R/WLO
3404–3407h
HPTC
High Precision Timer
Configuration
00000000h
R/W
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
Table 7-1.
Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)
Offset
Mnemonic
3410–3413h
GCS
3414–3414h
BUC
Register Name
General Control and Status
Default
Type
0000000xh
R/W,
R/WLO
0000001xb
(Mobile/Ultra Mobile
Only)
Backed Up Control
R/W
0000000xb
(Desktop Only)
3418–341Bh
341C–341Fh
7.1.1
FD
Function Disable
CG
Clock Gating (Mobile/Ultra
Mobile Only)
R/W, RO
00000000h
R/W, RO
VCH—Virtual Channel Capability Header Register
Offset Address: 0000–0003h
Default Value:
10010002h
Bit
7.1.2
See bit description
Attribute:
Size:
RO
32-bit
Description
31:20
Next Capability Offset (NCO) — RO.This field indicates the next item in the list.
19:16
Capability Version (CV) — RO. This field indicates support as a version 1 capability
structure.
15:0
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability
item.
VCAP1—Virtual Channel Capability #1 Register
Offset Address: 0004–0007h
Default Value:
00000801h
Bit
Attribute:
Size:
RO
32-bit
Description
31:12
Reserved
11:10
Port Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the port
arbitration table is 4 bits (to allow up to 8 ports).
9:8
7
6:4
3
2:0
Reference Clock (RC) — RO. Fixed at 100 ns.
Reserved
Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there are no
additional VCs of low priority with extended capabilities.
Reserved
Extended VC Count (EVC) — RO. This field indicates that there is one additional VC
(VC1) that exists with extended capabilities.
Intel ® ICH7 Family Datasheet
265
Chipset Configuration Registers
7.1.3
VCAP2—Virtual Channel Capability #2 Register
Offset Address: 0008–000Bh
Default Value:
00000001h
Bit
31:24
23:8
7:0
7.1.4
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present
for VC arbitration since it is fixed.
Reserved
VC Arbitration Capability (AC) — RO. This field indicates that the VC arbitration is
fixed in the root complex. VC1 is highest priority and VC0 is lowest priority.
PVC—Port Virtual Channel Control Register
Bit
15:04
Attribute:
Size:
R/W, RO
16-bit
Description
Reserved
3:1
VC Arbitration Select (AS) — RO. This field indicates which VC should be programmed
in the VC arbitration table. The root complex takes no action on the setting of this
field since there is no arbitration table.
0
Load VC Arbitration Table (LAT) — RO. This bit indicates that the table programmed
should be loaded into the VC arbitration table. This bit is defined as read/write with
always returning 0 on reads.
PVS—Port Virtual Channel Status Register
Offset Address: 000E–000Fh
Default Value:
0000h
Bit
15:01
0
266
RO
32-bit
Description
Offset Address: 000C–000Dh
Default Value:
0000h
7.1.5
Attribute:
Size:
Attribute:
Size:
RO
16-bit
Description
Reserved
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the
VC Arbitration table when it is being updated. This field is always 0 in the root
complex since there is no VC arbitration table.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.6
V0CAP—Virtual Channel 0 Resource Capability Register
Offset Address: 0010–0013h
Default Value:
00000001h
RO
32-bit
Bit
Description
31:24
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table
since the arbitration is fixed.
23
22:16
Reserved
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and
therefore this field is not used.
15
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
14
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not
just advanced packet switching transactions.
13:8
7:0
7.1.7
Attribute:
Size:
Reserved
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed
port arbitration.
V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h
Default Value:
800000FFh
Bit
31
Attribute:
Size:
R/W, RO
32-bit
Description
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and
cannot be disabled.
30:27
Reserved
26:24
Virtual Channel Identifier (ID) — RO. This field indicates the ID to use for this virtual
channel.
23:20
Reserved
19:17
Port Arbitration Select (PAS) — R/W. This field indicates which port table is being
programmed. The root complex takes no action on this setting since the arbitration is
fixed and there is no arbitration table.
16
15:8
7:1
0
Load Port Arbitration Table (LAT) — RO. The root complex does not implement an
arbitration table for this virtual channel.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates
which transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
Intel ® ICH7 Family Datasheet
267
Chipset Configuration Registers
7.1.8
V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 001A–001Bh
Default Value:
0000h
Bit
15:02
7.1.9
RO
16-bit
Description
Reserved
1
VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual
channel is still being negotiated with ingress ports.
0
Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for this
VC, so this bit is reserved at 0.
V1CAP—Virtual Channel 1 Resource Capability Register
Offset Address: 001C–001Fh
Default Value:
30008010h
Bit
31:24
23
22:16
Attribute:
Size:
R/WO, RO
32-bit
Description
Port Arbitration Table Offset (AT) — RO. This field indicates the location of the port
arbitration table in the root complex. A value of 3h indicates the table is at offset
30h.
Reserved
Maximum Time Slots (MTS) — R/WO. This value is updated by platform BIOS
based upon the determination of the number of time slots available in the platform.
15
Reject Snoop Transactions (RTS) — RO. All snoopable transactions on VC1 are
rejected. This VC is for isochronous transfers only.
14
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not
just advanced packet switching transactions.
13:8
7:0
268
Attribute:
Size:
Reserved
Port Arbitration Capability (PAC) — RO. This field indicates the port arbitration
capability is time-based WRR of 128 phases.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.10
V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 0020–0023h
Default Value:
00000000h
Bit
Attribute:
Size:
R/W, RO
32-bit
Description
Virtual Channel Enable (EN) — R/W.
31
30:27
Reserved
26:24
Virtual Channel Identifier (ID) — R/W. This field indicates the ID to use for this
virtual channel.
23:20
Reserved
19:17
Port Arbitration Select (PAS) — R/W. This field indicates which port table is being
programmed. The only permissible value of this field is 4h for the time-based WRR
entries.
16
15:8
7:1
0
7.1.11
0 = Disables the VC.
1 = Enables the VC.
Load Port Arbitration Table (LAT) — RO/W. When set, the port arbitration table
loaded is based upon the PAS field in this register. This bit always returns 0 when
read.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates
which transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
V1STS—Virtual Channel 1 Resource Status Register
Offset Address: 0026–0027h
Default Value:
0000h
Bit
15:02
Attribute:
Size:
RO
16-bit
Description
Reserved
VC Negotiation Pending (NP) — RO.
1
0
0 = Virtual channel is Not being negotiated with ingress ports.
1 = The virtual channel is still being negotiated with ingress ports.
Port Arbitration Tables Status (ATS) — RO. This field indicates the coherency
status of the port arbitration table. This bit is set when LAT (offset 000Ch:bit 0) is
written with value 1 and PAS (offset 0014h:bits19:17) has value of 4h. This bit is
cleared after the table has been updated.
Intel ® ICH7 Family Datasheet
269
Chipset Configuration Registers
7.1.12
RCTCL—Root Complex Topology Capabilities List Register
Offset Address: 0100–0103h
Default Value:
1A010005h
Bit
Description
Next Capability (NEXT) — RO. This field indicates the next item in the list.
19:16
Capability Version (CV) — RO. This field indicates the version of the capability
structure.
Capability ID (CID) — RO. This field indicates this is a PCI Express* link capability
section of an RCRB.
ESD—Element Self Description Register
Offset Address: 0104–0107h
Default Value:
00000602h
R/WO, RO
32-bit
Description
31:24
Port Number (PN) — RO. A value of 0 to indicate the egress port for the Intel® ICH7.
23:16
Component ID (CID) — R/WO. This field indicates the component ID assigned to
this element by software. This is written once by platform BIOS and is locked until a
platform reset.
Number of Link Entries (NLE) — RO. This field indicates that one link entry
(corresponding to DMI), 6 root port entries (for the downstream ports), and the
Intel® High Definition Audio device are described by this RCRB.
7:4
Reserved
3:0
Element Type (ET) — RO. This field indicates that the element type is a root complex
internal link.
ULD—Upstream Link Descriptor Register
Offset Address: 0110–0113h
Default Value:
00000001h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to
match the port number of the (G)MCH RCRB that is attached to this RCRB.
23:16
Target Component ID (TCID) — R/WO. This field is programmed by platform BIOS
to match the component ID of the (G)MCH RCRB that is attached to this RCRB.
15:2
270
Attribute:
Size:
Bit
15:8
7.1.14
RO
32-bit
31:20
15:0
7.1.13
Attribute:
Size:
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to the (G)MCH RCRB.
0
Link Valid (LV) — RO. This bit indicates that the link entry is valid.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.15
ULBA—Upstream Link Base Address Register
Offset Address: 0118–011Fh
Default Value:
0000000000000000h
7.1.16
R/WO
64-bit
Bit
Description
63:32
Base Address Upper (BAU) — R/WO. This field is programmed by platform BIOS to
match the upper 32-bits of base address of the (G)MCH RCRB that is attached to this
RCRB.
31:0
Base Address Lower (BAL) — R/WO. This field is programmed by platform BIOS to
match the lower 32-bits of base address of the (G)MCH RCRB that is attached to this
RCRB.
RP1D—Root Port 1 Descriptor Register
Offset Address: 0120–0123h
Default Value:
01xx0002h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
Target Port Number (PN) — RO. This field indicates that the target port number is 1h
(root port #1).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
15:2
7.1.17
Attribute:
Size:
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When FD.PE1D (offset 3418h, bit 16) is set, this link is not
valid (returns 0). When FD.PE1D is cleared, this link is valid (returns 1).
RP1BA—Root Port 1 Base Address Register
Offset Address: 0128–012Fh
Default Value:
00000000000E0000h
Bit
Attribute:
Size:
RO
64-bit
Description
63:32
Reserved
31:28
Reserved
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #28.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #0.
11:0
Reserved
Intel ® ICH7 Family Datasheet
271
Chipset Configuration Registers
7.1.18
RP2D—Root Port 2 Descriptor Register
Offset Address: 0130–0133h
Default Value:
02xx0002h
Description
31:24
Target Port Number (PN) — RO. This field indicates the target port number is 2h (root
port #2).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘01’, ‘10’, or ‘11’, or
FD.PE2D (offset 3418h, bit 17) is set, the link for this root port is not valid (return 0).
When RPC.PC is ‘00’ and FD.PE2D is cleared, the link for this root port is valid (return
1).
RP2BA—Root Port 2 Base Address Register
Offset Address: 0138–013Fh
Default Value:
00000000000E1000h
Bit
RO
64-bit
Description
Reserved
31:28
Reserved
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #28.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #1.
Reserved
RP3D—Root Port 3 Descriptor Register
Offset Address: 0140–0143h
Default Value:
03xx0002h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
Target Port Number (PN) — RO. This field indicates the target port number is 3h (root
port #3).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
15:2
272
Attribute:
Size:
63:32
11:0
7.1.20
R/WO, RO
32-bit
Bit
15:2
7.1.19
Attribute:
Size:
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘11’, or FD.PE3D
(offset 3418h, bit 18) is set, the link for this root port is not valid (return 0). When
RPC.PC is ‘00’, ‘01’, or “10’, and FD.PE3D is cleared, the link for this root port is valid
(return 1).
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.21
RP3BA—Root Port 3 Base Address Register
Offset Address: 0148–014Fh
Default Value:
00000000000E2000h
Bit
Description
Reserved
31:28
Reserved
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #28.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #2.
Reserved
RP4D—Root Port 4 Descriptor Register
Offset Address: 0150–0153h
Default Value:
04xx0002h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
Target Port Number (PN) — RO. This field indicates the target port number is 4h (root
port #4).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
15:2
7.1.23
RO
64-bit
63:32
11:0
7.1.22
Attribute:
Size:
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘10’ or ‘11’, or
FD.PE4D (offset 3418h, bit 19) is set, the link for this root port is not valid (return 0).
When RPC.PC is ‘00’ or ‘01’ and FD.PE4D is cleared, the link for this root port is valid
(return 1).
RP4BA—Root Port 4 Base Address Register
Offset Address: 0158–015Fh
Default Value:
00000000000E3000h
Bit
Attribute:
Size:
RO
64-bit
Description
63:32
Reserved
31:28
Reserved
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #28.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #3.
11:0
Reserved
Intel ® ICH7 Family Datasheet
273
Chipset Configuration Registers
7.1.24
HDD—Intel® High Definition Audio Descriptor Register
Offset Address: 0160–0163h
Default Value:
15xx0002h
Bit
Description
Target Port Number (PN) — RO. This field indicates the target port number is 15h
(Intel® High Definition Audio).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When FD.ZD (offset 3418h, bit 4) is set, the link to Intel High
Definition Audio is not valid (return 0). When FD.ZD is cleared, the link to Intel High
Definition Audio is valid (return 1).
HDBA—Intel® High Definition Audio Base Address Register
Offset Address: 0168–016Fh
Default Value:
00000000000D8000h
Bit
Reserved
31:28
Reserved
RO
64-bit
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #27.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #0.
Reserved
RP5D—Root Port 5 Descriptor Register
Offset Address: 0170–0173h
Default Value:
05xx0002h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
Target Port Number (PN) — RO. This field indicates the target port number is 5h (root
port #5).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
15:2
274
Attribute:
Size:
Description
63:32
11:0
7.1.26
R/WO, RO
32-bit
31:24
15:2
7.1.25
Attribute:
Size:
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When FD.PE5D (offset 3418h, bit 20) is set, the link for this
root port is not valid (return 0). When FD.PE5D is cleared, the link for this root port is
valid (return 1).
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.27
RP5BA—Root Port 5 Base Address Register
Offset Address: 0178–017Fh
Default Value:
00000000000E4000h
Bit
Description
Reserved
31:28
Reserved
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #28.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #4.
Reserved
RP6D—Root Port 6 Descriptor Register
Offset Address: 0180–0183h
Default Value:
06xx0002h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
Target Port Number (PN) — RO. This field indicates the target port number is 6h (root
port #6).
23:16
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
15:2
7.1.29
RO
64-bit
63:32
11:0
7.1.28
Attribute:
Size:
Reserved
1
Link Type (LT) — RO. This bit indicates that the link points to a root port.
0
Link Valid (LV) — RO. When RPC.PC2 (offset 0224h, bits 1:0) is ‘01’ or FD.PE6D
(offset 3418h, bit 21) is set, the link for this root port is not valid (return 0). When
RPC.PC is ‘00’ and FD.PE6D is cleared, the link for this root port is valid (return 1).
RP6BA—Root Port 6 Base Address Register
Offset Address: 0188–018Fh
Default Value:
00000000000E5000h
Bit
63:32
Attribute:
Size:
RO
64-bit
Description
Reserved
31:28
Reserved
27:20
Bus Number (BN) — RO. This field indicates the root port is on bus #0.
19:15
Device Number (DN) — RO. This field indicates the root port is on device #28.
14:12
Function Number (FN) — RO. This field indicates the root port is on function #5.
11:0
Reserved
Intel ® ICH7 Family Datasheet
275
Chipset Configuration Registers
7.1.30
ILCL—Internal Link Capabilities List Register
Offset Address: 01A0–01A3h
Default Value:
00010006h
Bit
RO
32-bit
Description
31:20
Next Capability Offset (NEXT) — RO. Indicates this is the last item in the list.
19:16
Capability Version (CV) — RO. This field indicates the version of the capability
structure.
15:0
7.1.31
Attribute:
Size:
Capability ID (CID) — RO. This field indicates this is capability for DMI.
LCAP—Link Capabilities Register
Offset Address: 01A4–01A7h
Default Value:
00012441h
Bit
31:18
Attribute:
Size:
RO/ R/WO
32-bit
Description
Reserved
17:15
Desktop
Only
L1 Exit Latency (EL1) — L1 not supported on DMI.
17:15
Mobile/
Ultra
Mobile
Only
14:12
11:10
Desktop
Only
11:10
Mobile/
Ultra
Mobile
Only
276
L1 Exit Latency (EL1) — RO. This field is set to 010b to indicate an exit latency of
2 us to 4 us.
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to less
than 256 ns.
Active State Link PM Support (ASPM) — R/WO. This field indicates that L0s is
supported on DMI.
Active State Link PM Support (ASPM) — R/WO. This field indicates the level of active
state power management on DMI.
00 = Neither L0s nor L1s are supported
01 = L0s Entry supported on DMI
10 = L1 Entry supported on DMI
11 = Both L0s and L1 supported on DMI
9:4
Maximum Link Width (MLW) — Indicates the maximum link width is 4 ports.
3:0
Maximum Link Speed (MLS) — Indicates the link speed is 2.5 Gb/s.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.32
LCTL—Link Control Register
Offset Address: 01A8–01A9h
Default Value:
0000h
Bit
15:8
7
6:2
1:0
Desktop
Only
Attribute:
Size:
R/W
16-bit
Description
Reserved
Extended Synch (ES) — R/W. When set, this bit forces extended transmission of
FTS ordered sets when exiting L0s prior to entering L0 and extra sequences (Mobile/
Ultra Mobile Only) at exit from L1 prior to entering L0.
Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
1:0
Mobile/
Ultra
Mobile
Only
7.1.33
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s or L1 or both.
00 = Disabled
01 = L0s entry enabled
10 = L1 Entry enabled
11 = L0s and L1 Entry enabled
LSTS—Link Status Register
Offset Address: 01AA–01ABh
Default Value:
0041h
Bit
15:10
Attribute:
Size:
RO
16-bit
Description
Reserved
9:4
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
Mobile/Ultra Mobile only: The ICH7 may also indicate x2 (000010b), depending on
(G)MCH configuration.
3:0
Link Speed (LS) — RO. Link is 2.5 Gb/s.
Intel ® ICH7 Family Datasheet
277
Chipset Configuration Registers
7.1.34
RPC—Root Port Configuration Register
Offset Address: 0224–0227h
Default Value:
0000000yh (y = 00xxb)
Bit
31:8
Attribute:
Size:
R/W, RO
32-bit
Description
Reserved
High Priority Port Enable (HPE) — R/W.
7
0 = The high priority path is not enabled.
1 = The port selected by the HPP field in this register is enabled for high priority. It
will be arbitrated above all other VC0 (including integrated VC0) devices.
High Priority Port (HPP) — R/W. This field controls which port is enabled for high
priority when the HPE bit in this register is set.
111 = Reserved
110 = Reserved
6:4
101 = Port 6
100 = Port 5
100 = Port 4
010 = Port 3
001 = Port 2
000 = Port 1
3
Reserved
Port Configuration2 (PC2) — RO. This bit controls how the PCI bridges are
organized in various modes of operation for Ports 5 and 6.
2
1 = Reserved
0 = 2 x1s, Port 5 (x1), Port 6 (x1)
This bit is in the resume well and is only reset by RSMRST#.
Port Configuration (PC) — RO. This field controls how the PCI bridges are
organized in various modes of operation. For the following mappings, if a port is not
shown, it is considered a x1 port with no connection.
1:0
These bits represent the strap values of ACZ_SDOUT (bit 1) and ACZ_SYNC (bit 0)
when TP3 is not pulled low at the rising edge of PWROK.
11 = 1 x4, Port 1 (x4)
10 = Reserved
01 = Reserved
00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1)
These bits live in the resume well and are only reset by RSMRST#.
278
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.35
RPFN—Root Port Function Number for PCI Express Root
Ports (Desktop and Mobile only)
Offset Address: 0238–023Bh
Default Value:
00543210h
Attribute:
Size:
R/WO, RO
32-bit
For the PCI Express root ports, the assignment of a function number to a root port is
not fixed. BIOS may re-assign the function numbers on a port by port basis. This
capability will allow BIOS to disable/hide any root port and have still have functions 0
thru N-1 where N is the total number of enabled root ports.
Port numbers will remain fixed to a physical root port.
The existing root port Function Disable registers operate on physical ports (not
functions).
Port Configuration (1x4, 4x1, etc.) is not affected by the logical function number
assignment and is associated with physical ports.
Bit
Description
31:23
Reserved
22:20
Root Port 6 Function Number (RP6FN) — R/WO. These bits set the function
number for PCI Express Root Port 6. This root port function number must be a
unique value from the other root port function numbers.
19
18:16
15
14:12
11
10:8
7
6:4
3
2:0
Reserved
Root Port 5 Function Number (RP5FN) — R/WO. These bits set the function
number for PCI Express Root Port 5. This root port function number must be a
unique value from the other root port function numbers.
Reserved
Root Port 4 Function Number (RP4FN) — R/WO. These bits set the function
number for PCI Express Root Port 4. This root port function number must be a
unique value from the other root port function numbers.
Reserved
Root Port 3 Function Number (RP3FN) — R/WO. These bits set the function
number for PCI Express Root Port 3. This root port function number must be a
unique value from the other root port function numbers.
Reserved
Root Port 2 Function Number (RP2FN) — R/WO. These bits set the function
number for PCI Express Root Port 2. This root port function number must be a
unique value from the other root port function numbers.
Reserved
Root Port 1 Function Number (RP1FN) — R/WO. These bits set the function
number for PCI Express Root Port 1. This root port function number must be a
unique value from the other root port function numbers.
Intel ® ICH7 Family Datasheet
279
Chipset Configuration Registers
7.1.36
TRSR—Trap Status Register
Offset Address: 1E00–1E03h
Default Value:
00000000h
Bit
31:4
Attribute:
Size:
R/WC, RO
32-bit
Description
Reserved
Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and
trapped). These bits are OR’ed together to create a single status bit in the Power
Management register space.
3:0
Note that the SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby
ensuring that the processor can enter the SMI# handler when the instruction
completes. Each status bit is cleared by writing a 1 to the corresponding bit location
in this register.
7.1.37
TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h
Default Value:
0000000000000000h
Attribute:
Size:
RO
64-bit
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
Bit
63:25
Description
Reserved
Read/Write# (RWI) — RO.
24
23:20
Reserved
19:16
Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables
associated with the trapped cycle. A 1 in any bit location indicates that the
corresponding byte is enabled in the cycle.
15:2
1:0
7.1.38
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the
trapped cycle.
Reserved
TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh
Default Value:
0000000000000000h
Attribute:
Size:
RO
64-bit
This register saves the data from I/O write cycles that are trapped for software to read.
Bit
63:32
31:0
280
Description
Reserved
Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined
after trapping a read cycle.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.39
IOTRn — I/O Trap Register (0-3)
Offset Address: 1E80–1E87h Register 0
1E88–1E8Fh Register 1
1E90–1E97h Register 2
1E98–1E9Fh Register 3
Default Value:
0000000000000000h
Attribute:
R/W, RO
Size:
64-bit
These registers are used to specify the set of I/O cycles to be trapped and to enable
this functionality.
Bit
63:50
Description
Reserved
Read/Write Mask (RWM) — R/W.
49
0 = The cycle must match the type specified in bit 48.
1 = Trapping logic will operate on both read and write cycles.
Read/Write# (RWIO) — R/W.
48
0 = Write
1 = Read
NOTE: The value in this field does not matter if bit 49 is set.
47:40
Reserved
39:36
Byte Enable Mask (BEM) — R/W. A 1 in any bit position indicates that any value in
the corresponding byte enable bit in a received cycle will be treated as a match. The
corresponding bit in the Byte Enables field, below, is ignored.
35:32
Byte Enables (TBE) — R/W. Active-high DWord-aligned byte enables.
31:24
Reserved
23:18
Address[7:2] Mask (ADMA) — R/W. A 1 in any bit position indicates that any value
in the corresponding address bit in a received cycle will be treated as a match. The
corresponding bit in the Address field, below, is ignored. The mask is only provided
for the lower 6 bits of the DWord address, allowing for traps on address ranges up to
256 bytes in size.
17:16
Reserved
15:2
1
I/O Address[15:2] (IOAD) — R/W. DWord-aligned address
Reserved
Trap and SMI# Enable (TRSE) — R/W.
0
0 = Trapping and SMI# logic disabled.
1 = The trapping logic specified in this register is enabled.
Intel ® ICH7 Family Datasheet
281
Chipset Configuration Registers
7.1.40
TCTL—TCO Configuration Register
Offset Address: 3000–3000h
Default Value:
00h
Bit
Attribute:
Size:
R/W
8-bit
Description
TCO IRQ Enable (IE) — R/W.
7
6:3
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
Reserved
TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear.
If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that
interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI
interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and
can be shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
011 = Reserved
2:0
100 = IRQ 20 (only if APIC enabled)
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
NOTE: When setting the these bits, the IE bit should be cleared to prevent glitching.
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should
be programmed for active-high reception. When the interrupt is mapped to
APIC interrupts 20 through 23, the APIC should be programmed for activelow reception.
282
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.41
D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h
Default Value:
00042210h
Bit
31:16
Attribute:
Size:
R/W, RO
32-bit
Description
Reserved
SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller
drives as its interrupt.
0h = No interrupt
15:12
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as
its interrupt.
0h = No interrupt
11:8
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
PATA Pin (PIP) — R/W. This field indicates which pin the PATA controller drives as
its interrupt.
0h = No interrupt
7:4
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
3:0
PCI Bridge Pin (PCIP) — RO. Currently, the PCI bridge does not generate an interrupt,
so this field is read-only and 0.
Intel ® ICH7 Family Datasheet
283
Chipset Configuration Registers
7.1.42
D30IP—Device 30 Interrupt Pin Register
Offset Address: 3104–3107h
Default Value:
00002100h
Bit
31:16
Attribute:
Size:
R/W, RO
32-bit
Description
Reserved
AC ‘97 Modem Pin (AMIP) — R/W. This field indicates which pin the AC ‘97 Modem
controller drives as its interrupt.
15:12
(Desktop
and
Mobile
Only)
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
15:12
(Ultra
Mobile
Only)
Reserved
AC ‘97 Audio Pin (AAIP) — R/W. This field indicates which pin the AC ‘97 audio
controller drives as its interrupt.
11:8
(Desktop
and
Mobile
Only)
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
284
11:8
(Ultra
Mobile
Only)
Reserved
7:4
Reserved
3:0
LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an interrupt,
so this field is read-only and 0.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.43
D29IP—Device 29 Interrupt Pin Register
Offset Address: 3108–310Bh
Default Value:
10004321h
Bit
Attribute:
Size:
R/W
32-bit
Description
EHCI Pin (EIP) — R/W. This field indicates which pin the EHCI controller drives as
its interrupt.
0h = No interrupt
31:28
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
27:16
Reserved
UHCI #3 Pin (U3P) — R/W. This field indicates which pin the UHCI controller #3
(ports 6 and 7) drives as its interrupt.
0h = No interrupt
15:12
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–Fh = Reserved
UHCI #2 Pin (U2P) — R/W. This field indicates which pin the UHCI controller #2
(ports 4 and 5) drives as its interrupt.
0h = No interrupt
11:8
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
UHCI #1 Pin (U1P) — R/W. This field indicates which pin the UHCI controller #1
(ports 2 and 3) drives as its interrupt.
0h = No interrupt
7:4
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
UHCI #0 Pin (U0P) — R/W. This field indicates which pin the UHCI controller #0
(ports 0 and 1) drives as its interrupt.
0h = No interrupt
3:0
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Intel ® ICH7 Family Datasheet
285
Chipset Configuration Registers
7.1.44
D28IP—Device 28 Interrupt Pin Register (Desktop and
Mobile Only)
Offset Address: 310C–310Fh
Default Value:
00214321h
Bit
31:24
Attribute:
Size:
R/W
32-bit
Description
Reserved
PCI Express #6 Pin (P6IP) — R/W. This field indicates which pin the PCI Express*
port #6 drives as its interrupt.
23:20
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
PCI Express #5 Pin (P5IP) — R/W. This field indicates which pin the PCI Express
port #5 drives as its interrupt.
19:16
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
PCI Express #4 Pin (P4IP) — R/W. This field indicates which pin the PCI Express*
port #4 drives as its interrupt.
15:12
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–Fh = Reserved
PCI Express #3 Pin (P3IP) — R/W. This field indicates which pin the PCI Express
port #3 drives as its interrupt.
11:8
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
PCI Express #2 Pin (P2IP) — R/W. This field indicates which pin the PCI Express
port #2 drives as its interrupt.
7:4
286
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
Bit
Description
PCI Express #1 Pin (P1IP) — R/W.This field iIndicates which pin the PCI Express
port #1 drives as its interrupt.
3:0
7.1.45
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
D27IP—Device 27 Interrupt Pin Register
Offset Address: 3110–3113h
Default Value:
00000001h
Bit
31:4
Attribute:
Size:
R/W
32-bit
Description
Reserved
Intel® High Definition Audio Pin (ZIP) — R/W. This field indicates which pin the
Intel High Definition Audio controller drives as its interrupt.
0h = No interrupt
3:0
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h-Fh = Reserved
7.1.46
D31IR—Device 31 Interrupt Route Register
Offset Address: 3140–3141h
Default Value:
3210h
Bit
15
Attribute:
Size:
R/W
16-bit
Description
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel® ICH7 is connected to the INTD# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
3h = PIRQD# (Default)
14:12
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: Ultra Mobile. PIRQA#–PIRQD# are not on the ICH7U. Eventhough the register
defaults to a non-ICH7U pin routing, BIOS default sets the register for
PIRQE#–PIRQH#.
11
Reserved
Intel ® ICH7 Family Datasheet
287
Chipset Configuration Registers
Bit
Description
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTC# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
3h = PIRQD#
10:8
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7
Reserved
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
Intel® ICH7 is connected to the INTB# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
3h = PIRQD#
6:4
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
3
Reserved
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 31 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
2:0
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
288
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.47
D30IR—Device 30 Interrupt Route Register
Offset Address: 3142–3143h
Default Value:
3210h
Bit
15
Attribute:
Size:
R/W
16-bit
Description
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel® ICH7 is connected to the INTD# pin reported for device 30 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
3h = PIRQD# (Default)
14:12
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a nonICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
11
Reserved
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTC# pin reported for device 30 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
3h = PIRQD#
10:8
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7
Reserved
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTB# pin reported for device 30 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
3h = PIRQD#
6:4
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
3
Reserved
Intel ® ICH7 Family Datasheet
289
Chipset Configuration Registers
Bit
Description
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 30 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
2:0
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7.1.48
D29IR—Device 29 Interrupt Route Register
Offset Address: 3144–3145h
Default Value:
3210h
Bit
15
Attribute:
Size:
R/W
16-bit
Description
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel® ICH7 is connected to the INTD# pin reported for device 29 functions.
14:12
0h
1h
2h
3h
4h
5h
6h
7h
=
=
=
=
=
=
=
=
PIRQA#
PIRQB#
PIRQC#
PIRQD# (Default)
PIRQE#
PIRQF#
PIRQG#
PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
11
Reserved
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTC# pin reported for device 29 functions.
10:8
0h
1h
2h
3h
4h
5h
6h
7h
=
=
=
=
=
=
=
=
PIRQA#
PIRQB#
PIRQC# (Default)
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7
290
Reserved
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
Bit
Description
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTB# pin reported for device 29 functions.
6:4
0h
1h
2h
3h
4h
5h
6h
7h
=
=
=
=
=
=
=
=
PIRQA#
PIRQB# (Default)
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
3
Reserved
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 29 functions.
2:0
0h
1h
2h
3h
4h
5h
6h
7h
=
=
=
=
=
=
=
=
PIRQA# (Default)
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
Intel ® ICH7 Family Datasheet
291
Chipset Configuration Registers
7.1.49
D28IR—Device 28 Interrupt Route Register
Offset Address: 3146–3147h
Default Value:
3210h
Bit
15
Attribute:
Size:
R/W
16-bit
Description
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel® ICH7 is connected to the INTD# pin reported for device 28 functions.
14:12
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA#
PIRQB#
PIRQC#
PIRQD# (Default)
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
11
Reserved
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTC# pin reported for device 28 functions.
10:8
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA#
PIRQB#
PIRQC# (Default)
PIRQD#
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7
Reserved
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTB# pin reported for device 28 functions.
6:4
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA#
PIRQB# (Default)
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
3
292
Reserved
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
Bit
Description
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 28 functions.
2:0
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA# (Default)
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7.1.50
D27IR—Device 27 Interrupt Route Register
Offset Address: 3148–3149h
Default Value:
3210h
Bit
15
Attribute:
Size:
R/W
16-bit
Description
Reserved
Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the
Intel® ICH7 is connected to the INTD# pin reported for device 27 functions.
14:12
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA#
PIRQB#
PIRQC#
PIRQD# (Default)
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
11
Reserved
Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTC# pin reported for device 27 functions.
10:8
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA#
PIRQB#
PIRQC# (Default)
PIRQD#
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7
Reserved
Intel ® ICH7 Family Datasheet
293
Chipset Configuration Registers
Bit
Description
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTB# pin reported for device 27 functions.
6:4
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA#
PIRQB# (Default)
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
3
Reserved
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 27 functions.
2:0
0h
1h
2h
3h
4h
5h
6h
=
=
=
=
=
=
=
PIRQA# (Default)
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
7.1.51
OIC—Other Interrupt Control Register
Offset Address: 31FF–31FFh
Default Value:
00h
Bit
7:2
Attribute:
Size:
R/W
8-bit
Description
Reserved
Coprocessor Error Enable (CEN) — R/W.
1
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel® ICH7 generates IRQ13 internally and holds it until an
I/O port F0h write. It will also drive IGNNE# active.
APIC Enable (AEN) — R/W.
0
294
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.52
RC—RTC Configuration Register
Offset Address: 3400–3403h
Default Value:
00000000h
Bit
31:5
Attribute:
Size:
R/W, R/WLO
32-bit
Description
Reserved
Upper 128 Byte Lock (UL) — R/WLO.
4
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return valid data. This bit is
reset on system reset.
Lower 128 Byte Lock (LL) — R/WLO.
3
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return valid data. Bit reset on
system reset.
Upper 128 Byte Enable (UE) — R/W.
2
1:0
7.1.53
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
Reserved
HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h
Default Value:
00000000h
Bit
31:8
Attribute:
Size:
R/W
32-bit
Description
Reserved
Address Enable (AE) — R/W.
7
6:2
0 = Address disabled.
1 = The Intel® ICH7 will decode the High Precision Timer memory address range
selected by bits 1:0 below.
Reserved
Address Select (AS) — R/W. This field selects 1 of 4 possible memory address
ranges for the High Precision Timer functionality. The encodings are:
1:0
00 = FED0_0000h – FED0_03FFh
01 = FED0_1000h – FED0_13FFh
10 = FED0_2000h – FED0_23FFh
11 = FED0_3000h – FED0_33FFh
Intel ® ICH7 Family Datasheet
295
Chipset Configuration Registers
7.1.54
GCS—General Control and Status Register
Offset Address: 3410–3413h
Default Value:
00000yy0h (yy = xx0000x0b)
Bit
31:12
Attribute:R/W, R/WLO
Size:
32-bit
Description
Reserved
Boot BIOS Straps (BBS): This field determines the destination of accesses to the
BIOS memory range. The default values for these bits represent the strap values of
GNT5#/GPIO17 (bit 11) and GNT4#/GPIO48 (bit 10) (active-high logic levels) at the
rising edge of PWROK.
Bits 11:10
11:10
Description
00b
Reserved
01b
SPI (supports shared flash with LAN)
10b
PCI
11b
LPC
When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to
FFFF_FFFFh) is accepted by the primary side of the PCI-to-PCI bridge and forwarded
to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot
from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to
be set (nor any other bits) for these cycles to go to PCI. Note that BIOS decode range
bits and the other BIOS protection bits have no effect when PCI is selected.
When SPI or LPC is selected, the range that is decoded is further qualified by other
configuration bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface
Lock-Down (bit 0) is not set.
Server Error Reporting Mode (SERM) — R/W.
9
8
7
(Mobile/
Ultra
Mobile
Only)
0 = The Intel® ICH7 is the final target of all errors. The (G)MCH sends a messages to
the ICH7 for the purpose of generating NMI.
1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this
mode, if the ICH7 detects a fatal, non-fatal, or correctable error on DMI or its
downstream ports, it sends a message to the (G)MCH. If the ICH7 receives an
ERR_* message from the downstream port, it sends that message to the
(G)MCH.
Reserved
Mobile IDE Configuration Lock Down (MICLD) — R/WLO.
0 = Disabled.
1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system
reset occurs. This prevents rogue software from changing the default state of
the PATA pins during boot after BIOS configures them. This bit is write once, and
is cleared by system reset and when returning from the S3/S4/S5 states.
7
(Desktop
Only)
6
(Mobile/
Ultra
Mobile
Only)
296
Reserved
FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break
event indication.
0 = Disabled.
1 = The ICH7-M examines FERR# during a C2, C3, or C4 state as a break event.
See Chapter 5.14.5 for a functional description.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
Bit
Description
6
(Desktop
Only)
5
Reserved
No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on
Intel® ICH7) is sampled high on PWROK. This bit may be set or cleared by software if
the strap is sampled low but may not override the strap when it indicates “No
Reboot”.
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but
will not reboot on the second timeout.
Alternate Access Mode Enable (AME) — R/W.
4
3
0 = Disabled.
1 = Alternate access read only registers can be written, and write only registers can
be read. Before entering a low power state, several registers from powered down
parts may need to be saved. In the majority of cases, this is not an issue, as
registers have read and write paths. However, several of the ISA compatible
registers are either read only or write only. To get data out of write-only
registers, and to restore data into read-only registers, the ICH7 implements an
alternate access mode. For a list of these registers see Section 5.14.10.
Reserved.
Reserved Page Route (RPR) — R/W. This bit determines where to send the
reserved page registers. These addresses are sent to PCI or LPC for the purpose of
generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h,
86h, 88h, 8Ch, 8Dh, and 8Eh.
2
0 = Writes will be forwarded to LPC, shadowed within the ICH7, and reads will be
returned from the internal shadow
1 = Writes will be forwarded to PCI, shadowed within the ICH7, and reads will be
returned from the internal shadow.
NOTE: If some writes are completed to LPC/PCI to these I/O ranges, and then this
bit is flipped such that writes will now go to the other interface, the reads will
not return what was last written. Shadowing is performed on each interface.
The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are
always decoded to LPC.
1
Reserved
0
0 = Disabled.
1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10)
from being changed. This bit can only be written from 0 to 1 once.
BIOS Interface Lock-Down (BILD) — R/WLO.
Intel ® ICH7 Family Datasheet
297
Chipset Configuration Registers
7.1.55
BUC—Backed Up Control Register
Offset Address: 3414–3414h
Attribute:
Size:
Default Value:
0000000xb (Desktop Only)
0000001xb (Mobile/Ultra Mobile Only)
R/W
8-bit
All bits in this register are in the RTC well and only cleared by RTCRST#.
Bit
7:3
Description
Reserved
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by
RSMRST#, but not PLTRST# nor CF9h writes.
2
1
(Mobile/
Ultra
Mobile
Only)
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and
INIT3_3V# will go inactive with the same timings as the other processor I/F
signals (hold time after CPURST# inactive).
PATA Reset State (PRS) — R/W.
0 = Disabled.
1 = The reset state of the PATA pins will be driven/tri-state.
1
(Desktop
Only)
Reserved
Top Swap (TS) — R/W.
0
0 = Intel® ICH7 will not invert A16.
1 = ICH7 will invert A16 for cycles going to the BIOS space (but not the feature
space) in the FWH.
If the ICH7 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then
this bit cannot be cleared by software. The strap jumper should be removed and the
system rebooted.
298
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
7.1.56
FD—Function Disable Register
Offset Address: 3418–341Bh
Default Value:
See bit description
Attribute:
Size:
R/W, RO
32-bit
The UHCI functions must be disabled from highest function number to lowest. For
example, if only three UHCIs are wanted, software must disable UHCI #4 (UD4 bit set).
When disabling UHCIs, the EHCI Structural Parameters Registers must be updated with
coherent information in “Number of Companion Controllers” and “N_Ports” fields.
When disabling a function, only the configuration space is disabled. Software must
ensure that all functionality within a controller that is not desired (such as memory
spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.
When a function is disabled, software must not attempt to re-enable it. A disabled
function can only be re-enabled by a platform reset.
Bit
31:22
Description
Reserved
PCI Express 6 Disable (PE6D) — R/W. When disabled, the link for this port is put
into the “link down” state.
21
0 = PCI Express* port #6 is enabled. (Default)
1 = PCI Express port #6 is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
PCI Express 5 Disable (PE5D) — R/W. When disabled, the link for this port is put
into the link down state.
20
0 = PCI Express port #5 is enabled. (Default)
1 = PCI Express port #5 is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
PCI Express 4 Disable (PE4D) — R/W. DWhen disabled, the link for this port is put
into the “link down” state.
19
0 = PCI Express* port #4 is enabled. (Default)
1 = PCI Express port #4 is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
PCI Express 3 Disable (PE3D) — R/W. When disabled, the link for this port is put
into the link down state.
18
0 = PCI Express port #3 is enabled. (Default)
1 = PCI Express port #3 is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
PCI Express 2 Disable (PE2D) — R/W. When disabled, the link for this port is put
into the link down state.
17
0 = PCI Express port #2 is enabled. (Default)
1 = PCI Express port #2 is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
PCI Express 1 Disable (PE1D) — R/W. When disabled, the link for this port is put
into the link down state.
16
0 = PCI Express port #1 is enabled. (Default)
1 = PCI Express port #1 is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
Intel ® ICH7 Family Datasheet
299
Chipset Configuration Registers
Bit
Description
EHCI Disable (EHCID) — R/W.
15
0 = The EHCI is enabled. (Default)
1 = The EHCI is disabled.
LPC Bridge Disable (LBD) — R/W.
0 = The LPC bridge is enabled. (Default)
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following
additional spaces will no longer be decoded by the LPC bridge:
14
•
•
•
Memory cycles below 16 MB (1000000h)
I/O cycles below 64 KB (10000h)
The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is
set, but the aliases at the top of 1 MB (the E and F segment) no longer will be
decoded.
13:12
Reserved
UHCI #4 Disable (U4D) — R/W.
11
0 = The 4th UHCI (ports 6 and 7) is enabled. (Default)
1 = The 4th UHCI (ports 6 and 7) is disabled.
UHCI #3 Disable (U3D) — R/W.
10
0 = The 3rd UHCI (ports 4 and 5) is enabled. (Default)
1 = The 3rd UHCI (ports 4 and 5) is disabled.
UHCI #2 Disable (U2D) — R/W.
9
0 = The 2nd UHCI (ports 2 and 3) is enabled. (Default)
1 = The 2nd UHCI (ports 2 and 3) is disabled.
UHCI #1 Disable (U1D) — R/W.
8
0 = The 1st UHCI (ports 0 and 1) is enabled. (Default)
1 = The 1st UHCI (ports 0 and 1) is disabled.
Hide Internal LAN (HIL) — R/W.
7
0 = The LAN controller is enabled. (Default)
1 = The LAN controller is disabled and will not decode configuration cycles off of PCI
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. .
AC ‘97 Modem Disable (AMD) — R/W.
6
0 = The AC ‘97 modem function is enabled. (Default)
1 = The AC ‘97 modem function is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
AC ‘97 Audio Disable (AAD) — R/W.
5
0 = The AC ‘97 audio function is enabled. (Default)
1 = The AC ‘97 audio function is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
Intel® High Definition Audio Disable (ZD) — R/W.
4
0 = The Intel High Definition Audio controller is enabled. (Default)
1 = The Intel High Definition Audio controller is disabled and its PCI configuration
space is not accessible.
SM Bus Disable (SD) — R/W.
3
300
0 = The SM Bus controller is enabled. (Default)
1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the I/
O space. In the Intel® ICH7, it only disables the configuration space.
Intel ® ICH7 Family Datasheet
Chipset Configuration Registers
Bit
Description
Serial ATA Disable (SAD) — R/W. Default is 0.
2
0 = The SATA controller is enabled.
1 = The SATA controller is disabled.
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.
Parallel ATA Disable (PAD) — R/W.
7.1.57
1
0 = The PATA controller is enabled. (Default)
1 = The PATA controller is disabled and its PCI configuration space is not accessible.
0
Reserved
CG—Clock Gating (Mobile/Ultra Mobile Only)
Offset Address: 341C–341Fh
Default Value:
00000000h
Bit
Attribute:
Size:
R/W, RO
32-bit
Description
Legacy (LPC) Dynamic Clock Gate Enable — R/W.
31
0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
PATA Dynamic Clock Gate Enable — R/W.
30
0 = PATA Dynamic Clock Gating is Disabled
1 = PATA Dynamic Clock Gating is Enabled
USB UHCI Dynamic Clock Gate Enable — R/W.
29:28
0 = USB UHCI Dynamic Clock Gating is Disabled
1 = USB UHCI Dynamic Clock Gating is Enabled
0 = Reserved
1 = Reserved
SATA Port 3 Dynamic Clock Gate Enable — R/W.
27
0 = SATA Port 3 Dynamic Clock Gating is Disabled
1 = SATA Port 3 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
SATA Port 2 Dynamic Clock Gate Enable — R/W.
26
0 = SATA Port 2 Dynamic Clock Gating is Disabled
1 = SATA Port 2 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
SATA Port 1 Dynamic Clock Gate Enable — R/W.
25
0 = SATA Port 1 Dynamic Clock Gating is Disabled
1 = SATA Port 1 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
SATA Port 0 Dynamic Clock Gate Enable — R/W.
24
0 = SATA Port 0 Dynamic Clock Gating is Disabled
1 = SATA Port 0 Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
Intel ® ICH7 Family Datasheet
301
Chipset Configuration Registers
Bit
Description
AC ‘97 Static Clock Gate Enable — R/W.
23
0 = AC ‘97 Static Clock Gating is Disabled
1 = AC ‘97 Static Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
27:23
Reserved
High Definition Audio Dynamic Clock Gate Enable — R/W.
22
0 = HIgh Definition Audio Dynamic Clock Gating is Disabled
1 = HIgh Definition Audio Dynamic Clock Gating is Enabled
High Definition Audio Static Clock Gate Enable — R/W.
21
0 = HIgh Definition Audio Static Clock Gating is Disabled
1 = HIgh Definition Audio Static Clock Gating is Enabled
USB EHCI Static Clock Gate Enable — R/W.
20
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
USB EHCI Dynamic Clock Gate Enable — R/W.
19
18:17
16
15:4
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
Reserved
PCI Dynamic Gate Enable — R/W. Funcitonality reserved. BIOS must ensure bit is
0.
Reserved
DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.
3
0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled
1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled
PCI Express TX Dynamic Clock Gate Enable — R/W.
2
0 = PCI Express root port TX Dynamic Clock Gating is Disabled
1 = PCI Express root port TX Dynamic Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
DMI TX Dynamic Clock Gate Enable — R/W.
1
0 = DMI TX Dynamic Clock Gating is Disabled
1 = DMI TX Dynamic Clock Gating is Enabled
PCI Express Root Port Static Clock Gate Enable — R/W.
0
0 = PCI Express root port Static Clock Gating is Disabled
1 = PCI Express root port Static Clock Gating is Enabled
NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.
§
302
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8
LAN Controller Registers
(B1:D8:F0) (Desktop and
Mobile Only)
Note:
LAN is not supported on ICH7-U Ultra Mobile.
The ICH7 integrated LAN controller appears to reside at PCI Device 8, Function 0 on the
secondary side of the ICH7’s virtual PCI-to-PCI bridge. This is typically Bus 1, but may
be assigned a different number depending upon system configuration. The LAN
controller acts as both a master and a slave on the PCI bus. As a master, the LAN
controller interacts with the system main memory to access data for transmission or
deposit received data. As a slave, some of the LAN controller’s control structures are
accessed by the host processor to read or write information to the on-chip registers.
The processor also provides the LAN controller with the necessary commands and
pointers that allow it to process receive and transmit data.
8.1
PCI Configuration Registers
(LAN Controller—B1:D8:F0)
Note:
Address locations that are not shown should be treated as Reserved (See Section 6.2
for details).
.
Table 8-1.
LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) (Sheet 1
of 2)
Offset
Mnemonic
Default
Type
00h–01h
VID
Vendor Identification
Register Name
8086h
RO
02h–03h
DID
Device Identification
See register
description.
RO
04h–05h
PCICMD
PCI Command
0000h
RO, R/W
06h–07h
PCISTS
PCI Status
0290h
RO, R/WC
See register
description.
RO
08h
RID
Revision Identification
0Ah
SCC
Sub Class Code
00h
RO
0Bh
BCC
Base Class Code
02
RO
0Ch
CLS
0Dh
PMLT
0Eh
HEADTYP
10h–13h
CSR_MEM_BASE
14h–17h
CSR_IO_BASE
2Ch–2Dh
SVID
2Eh–2Fh
SID
34h
CAP_PTR
Cache Line Size
00h
R/W
Primary Master Latency Timer
00h
R/W
Header Type
00h
RO
CSR Memory–Mapped Base
Address
00000008h
R/W, RO
CSR I/O–Mapped Base Address
00000001h
R/W, RO
Subsystem Vendor Identification
0000h
RO
Subsystem Identification
0000h
RO
DCh
RO
R/W
Capabilities Pointer
3Ch
INT_LN
Interrupt Line
00h
3Dh
INT_PN
Interrupt Pin
01h
RO
3Eh
MIN_GNT
Minimum Grant
08h
RO
Intel ® ICH7 Family Datasheet
303
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Table 8-1.
8.1.1
LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) (Sheet 2
of 2)
Offset
Mnemonic
3Fh
MAX_LAT
DCh
CAP_ID
DDh
Register Name
Maximum Latency
38h
RO
01h
RO
NXT_PTR
Next Item Pointer
00h
RO
DEh–DFh
PM_CAP
Power Management Capabilities
FE21h
(Desktop Only)
7E21h
(Mobile Only)
RO
E0h–E1h
PMCSR
Power Management Control/
Status
0000h
R/W, RO,
R/WC
E3
PCIDATA
PCI Power Management Data
00h
RO
VID—Vendor Identification Register
(LAN Controller—B1:D8:F0)
Bit
15:0
Attribute:
Size:
RO
16 bits
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel.
DID—Device Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: 02h–03h
Default Value:
See bit description
304
Type
Capability ID
Offset Address: 00h–01h
Default Value:
8086h
8.1.2
Default
Attribute:
Size:
RO
16 bits
Bit
Description
15:0
Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 integrated LAN
controller.
NOTES:
1.
If the EEPROM is not present (or not properly programmed), reads to the Device
ID return the default value referred to in the Intel® I/O Controller Hub 7 (ICH7)
Family Specification Update.
2.
If the EEPROM is present (and properly programmed) and if the value of word
23h is not 0000h or FFFFh, the Device ID is loaded from the EEPROM, word 23h
after the hardware reset. (See Section 8.1.14 - SID, Subsystem ID of LAN
controller for detail)
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.3
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address: 04h–05h
Default Value:
0000h
Bit
15:11
Attribute:
Size:
RO, R/W
16 bits
Description
Reserved
Interrupt Disable — R/W.
10
9
0 = Enable.
1 = Disables LAN controller to assert its INTA signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN controller
will not run fast back-to-back PCI cycles.
SERR# Enable (SERR_EN) — R/W.
8
0 = Disable.
1 = Enable. Allow SERR# to be asserted.
7
Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented.
Parity Error Response (PER) — R/W.
6
5
0 = The LAN controller will ignore PCI parity errors.
1 = The integrated LAN controller will take normal action when a PCI parity error is
detected and will enable generation of parity on DMI.
VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented.
Memory Write and Invalidate Enable (MWIE) — R/W.
4
3
0 = Disable. The LAN controller will not use the Memory Write and Invalidate command.
1 = Enable.
Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN controller ignores special
cycles.
Bus Master Enable (BME) — R/W.
2
0 = Disable.
1 = Enable. The Intel® ICH7’s integrated LAN controller may function as a PCI bus
master.
Memory Space Enable (MSE) — R/W.
1
0 = Disable.
1 = Enable. The ICH7’s integrated LAN controller will respond to the memory space
accesses.
I/O Space Enable (IOSE) — R/W.
0
0 = Disable.
1 = Enable. The ICH7’s integrated LAN controller will respond to the I/O space
accesses.
Intel ® ICH7 Family Datasheet
305
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.4
PCISTS—PCI Status Register
(LAN Controller—B1:D8:F0)
Offset Address: 06h–07h
Default Value:
0290h
Note:
Attribute:
Size:
RO, R/WC
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15
0 = Parity error Not detected.
1 = The Intel® ICH7’s integrated LAN controller has detected a parity error on the PCI
bus (will be set even if Parity Error Response is disabled in the PCI Command
register).
Signaled System Error (SSE) — R/WC.
14
0 = Integrated LAN controller has not asserted SERR#
1 = The ICH7’s integrated LAN controller has asserted SERR#. SERR# can be routed to
cause NMI, SMI#, or interrupt.
Master Abort Status (RMA) — R/WC.
13
0 = Master Abort not generated
1 = The ICH7’s integrated LAN controller (as a PCI master) has generated a master
abort.
Received Target Abort (RTA) — R/WC.
12
11
10:9
0 = Target abort not received.
1 = The ICH7’s integrated LAN controller (as a PCI master) has received a target abort.
Signaled Target Abort (STA) — RO. Hardwired to 0. The device will not signal Target
Abort.
DEVSEL# Timing Status (DEV_STS) — RO.
01h = Medium timing.
Data Parity Error Detected (DPED) — R/WC.
8
0 = Parity error not detected (conditions below are not met).
1 = All of the following three conditions have been met:
1.
The LAN controller is acting as bus master
2.
The LAN controller has asserted PERR# (for reads) or detected PERR# asserted
(for writes)
3.
The Parity Error Response bit in the LAN controller’s PCI Command Register is
set.
7
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast
back-to-back transactions.
6
User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.
5
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66
MHz PCI.
Capabilities List (CAP_LIST) — RO.
4
3
2:0
306
0 = The EEPROM indicates that the integrated LAN controller does not support PCI
Power Management.
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power
Management.
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is
independent from the state of the Interrupt Enable bit in the command register.
Reserved
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.5
RID—Revision Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: 08h
Default Value:
See bit description
8.1.6
RO
8 bits
Bit
Description
7:0
Revision ID (RID) — RO. This field is an 8-bit value that indicates the revision number
for the integrated LAN controller. The three least significant bits in this register may be
overridden by the ID and REV ID fields in the EEPROM. Refer to the Intel® I/O
Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID
Register.
SCC—Sub Class Code Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Ah
Default Value:
00h
8.1.7
Attribute:
Size:
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Sub Class Code (SCC) — RO. This 8-bit value specifies the sub-class of the device as an
Ethernet controller.
BCC—Base-Class Code Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Bh
Default Value:
02h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Base Class Code (BCC) — RO. This 8-bit value specifies the base class of the device as
a network controller.
Intel ® ICH7 Family Datasheet
307
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.8
CLS—Cache Line Size Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Ch
Default Value:
00h
Bit
7:5
Attribute:
Size:
R/W
8 bits
Description
Reserved
Cache Line Size (CLS) — R/W.
00 = Memory Write and Invalidate (MWI) command will not be used by the integrated
LAN controller.
4:3
01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a
value of 08h is written to this register).
10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a
value of 10h is written to this register).
11 = Invalid. MWI command will not be used.
2:0
8.1.9
Reserved
PMLT—Primary Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Dh
Default Value:
00h
Bit
8.1.10
R/W
8 bits
Description
7:3
Master Latency Timer Count (MLTC) — R/W. This field defines the number of PCI
clock cycles that the integrated LAN controller may own the bus while acting as bus
master.
2:0
Reserved
HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value:
00h
Attribute:
Size:
RO
8 bits
Bit
Description
7
Multi-Function Device (MFD) — RO. Hardwired to 0 to indicate a single function device.
6:0
308
Attribute:
Size:
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space as an Ethernet controller.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.11
CSR_MEM_BASE — CSR Memory-Mapped Base
Address Register (LAN Controller—B1:D8:F0)
Offset Address: 10h–13h
Default Value:
00000008h
Note:
Bit
Description
31:12
Base Address (MEM_ADDR) — R/W. This field contains the upper 20 bits of the base
address provides 4 KB of memory-Mapped space for the LAN controller’s Control/Status
registers.
3
2:1
0
Reserved
Prefetchable (MEM_PF) — RO. Hardwired to 0 to indicate that this is not a pre-fetchable
memory-Mapped address range.
Type (MEM_TYPE) — RO. Hardwired to 00b to indicate the memory-Mapped address
range may be located anywhere in 32-bit address space.
Memory-Space Indicator (MEM_SPACE) — RO. Hardwired to 0 to indicate that this base
address maps to memory space.
CSR_IO_BASE — CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0)
Offset Address: 14h–17h
Default Value:
00000001h
Note:
Attribute:
Size:
R/W, RO
32 bits
The ICH7’s integrated LAN controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the LAN controller’s CSR
registers.
Bit
31:16
15:6
5:1
0
8.1.13
R/W, RO
32 bits
The ICH7’s integrated LAN controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the LAN controller’s CSR
registers.
11:4
8.1.12
Attribute:
Size:
Description
Reserved
Base Address (IO_ADDR)— R/W. This field provides 64 bytes of I/O-Mapped address
space for the LAN controller’s Control/Status registers.
Reserved
I/O Space Indicator (IO_SPACE) — RO. Hardwired to 1 to indicate that this base
address maps to
I/O space.
SVID — Subsystem Vendor Identification
(LAN Controller—B1:D8:F0)
Offset Address: 2Ch–2D
Default Value:
0000h
Bit
15:0
Attribute:
Size:
RO
16 bits
Description
Subsystem Vendor ID (SVID) — RO. See Section 8.1.14 for details.
Intel ® ICH7 Family Datasheet
309
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.14
SID — Subsystem Identification
(LAN Controller—B1:D8:F0)
Offset Address: 2Eh–2Fh
Default Value:
0000h
Attribute:
Size:
Bit
15:0
RO
16 bits
Description
Subsystem ID (SID) — RO.
Note:
The ICH7’s integrated LAN controller provides support for configurable Subsystem ID
and Subsystem Vendor ID fields. After reset, the LAN controller automatically reads
addresses Ah through Ch, and 23h of the EEPROM. The LAN controller checks bits
15:13 in the EEPROM word Ah, and functions according to Table 8-2.
Table 8-2.
Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM
Bits 15:14
Bit
13
Device
ID1
Vendor ID
Revision ID2
Subsystem ID
Subsystem
Vendor ID
11b, 10b,
00b
X
1051h
8086h
00h
0000h
0000h
01b
0b
Word 23h
8086h
00h
Word Bh
Word Ch
Word Ch
80h + Word
Ah,
bits 10:8
Word Bh
Word Ch
01b
1b
Word 23h
NOTES:
1.
The Device ID is loaded from Word 23h only if the value of Word 23h is not 0000h or FFFFh
2.
The Revision ID is subject to change according to the silicon stepping.
8.1.15
CAP_PTR — Capabilities Pointer
(LAN Controller—B1:D8:F0)
Offset Address: 34h
Default Value:
DCh
Bit
7:0
8.1.16
RO
8 bits
Description
Capabilities Pointer (CAP_PTR) — RO. Hardwired to DCh to indicate the offset within
configuration space for the location of the Power Management registers.
INT_LN — Interrupt Line Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Ch
Default Value:
00h
Bit
7:0
310
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
Description
Interrupt Line (INT_LN) — R/W. This field identifies the system interrupt line to
which the LAN controller’s PCI interrupt request pin (as defined in the Interrupt Pin
Register) is routed.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.17
INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Dh
Default Value:
01h
8.1.18
Description
7:0
Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s
interrupt request is connected to PIRQA#. However, in the Intel® ICH7 implementation,
when the LAN controller interrupt is generated PIRQE# will go active, not PIRQA#. Note
that if the PIRQE# signal is used as a GPI, the external visibility will be lost (though
PIRQE# will still go active internally).
MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in
increments of 0.25 μs) that the LAN controller needs to retain ownership of the PCI bus
when it initiates a transaction.
MAX_LAT — Maximum Latency Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Fh
Default Value:
38h
Bit
7:0
8.1.20
RO
8 bits
Bit
Offset Address: 3Eh
Default Value:
08h
8.1.19
Attribute:
Size:
Attribute:
Size:
RO
8 bits
Description
Maximum Latency (MAX_LAT) — RO. This field defines how often (in increments of
0.25 μs) the LAN controller needs to access the PCI bus.
CAP_ID — Capability Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: DCh
Default Value:
01h
Bit
7:0
Attribute:
Size:
RO
8 bits
Description
Capability ID (CAP_ID) — RO. Hardwired to 01h to indicate that the Intel® ICH7’s
integrated LAN controller supports PCI power management.
Intel ® ICH7 Family Datasheet
311
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.21
NXT_PTR — Next Item Pointer
(LAN Controller—B1:D8:F0)
Offset Address: DDh
Default Value:
00h
Bit
7:0
8.1.22
RO
8 bits
Description
Next Item Pointer (NXT_PTR) — RO. Hardwired to 00b to indicate that power
management is the last item in the capabilities list.
PM_CAP — Power Management Capabilities
(LAN Controller—B1:D8:F0)
Offset Address: DEh–DFh
Default Value:
FE21h (Desktop Only)
7E21h (Mobile Only)
Bit
15:11
312
Attribute:
Size:
Attribute:
Size:
RO
16 bits
Description
PME Support (PME_SUP) — RO. Hardwired to 11111b. This 5-bit field indicates the
power states in which the LAN controller may assert PME#. The LAN controller
supports wake-up in all power states.
10
D2 Support (D2_SUP) — RO. Hardwired to 1 to indicate that the LAN controller
supports the D2 power state.
9
D1 Support (D1_SUP) — RO. Hardwired to 1 to indicate that the LAN controller
supports the D1 power state.
8:6
Auxiliary Current (AUX_CUR) — RO. Hardwired to 000b to indicate that the LAN
controller implements the Data registers. The auxiliary power consumption is the same
as the current consumption reported in the D3 state in the Data register.
5
Device Specific Initialization (DSI) — RO. Hardwired to 1 to indicate that special
initialization of this function is required (beyond the standard PCI configuration header)
before the generic class device driver is able to use it. DSI is required for the LAN
controller after D3-to-D0 reset.
4
Reserved
3
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that the LAN controller does
not require a clock to generate a power management event.
2:0
Version (VER) — RO. Hardwired to 010b to indicate that the LAN controller complies
with of the PCI Power Management Specification, Revision 1.1.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.23
PMCSR — Power Management Control/
Status Register (LAN Controller—B1:D8:F0)
Offset Address: E0h–E1h
Default Value:
0000h
Bit
Attribute:
Size:
RO, R/W, R/WC
16 bits
Description
PME Status (PME_STAT) — R/WC.
15
14:13
12:9
8
7:5
4
3:2
0 = Software clears this bit by writing a 1 to it. This also deasserts the PME# signal and
clears the PME status bit in the Power Management Driver Register. When the
PME# signal is enabled, the PME# signal reflects the state of the PME status bit.
1 = Set upon occurrence of a wake-up event, independent of the state of the PME
enable bit.
Data Scale (DSCALE) — RO. This field indicates the data register scaling factor. It
equals 10b for registers 0 through 8 and 00b for registers nine through fifteen, as
selected by the “Data Select” field.
Data Select (DSEL) — R/W. This field is used to select which data is reported through
the Data register and Data Scale field.
PME Enable (PME_EN) — R/W. This bit enables the Intel® ICH7’s integrated LAN
controller to assert PME#.
0 = The device will not assert PME#.
1 = Enable PME# assertion when PME Status is set.
Reserved
Dynamic Data (DYN_DAT) — RO. Hardwired to 0 to indicate that the device does not
support the ability to monitor the power consumption dynamically.
Reserved
Power State (PWR_ST) — R/W. This 2-bit field is used to determine the current
power state of the integrated LAN controller, and to put it into a new power state. The
definition of the field values is as follows:
1:0
00 = D0
01 = D1
10 = D2
11 = D3
Intel ® ICH7 Family Datasheet
313
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.24
PCIDATA — PCI Power Management Data Register
(LAN Controller—B1:D8:F0)
Offset Address: E3h
Default Value:
00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Power Management Data (PWR_MGT) — RO. State dependent power consumption and
heat dissipation data.
The data register is an 8-bit read only register that provides a mechanism for the
ICH7’s integrated LAN controller to report state dependent maximum power
consumption and heat dissipation. The value reported in this register depends on the
value written to the Data Select field in the PMCSR register. The power measurements
defined in this register have a dynamic range of 0 W to 2.55 W with 0.01 W resolution,
scaled according to the Data Scale field in the PMCSR. The structure of the Data
Register is given in Table 8-3.
Table 8-3.
314
Data Register Structure
Data Select
Data Scale
Data Reported
0
2
D0 Power Consumption
1
2
D1 Power Consumption
2
2
D2 Power Consumption
3
2
D3 Power Consumption
4
2
D0 Power Dissipated
5
2
D1 Power Dissipated
6
2
D2 Power Dissipated
7
2
D3 Power Dissipated
8
2
Common Function Power
Dissipated
9–15
0
Reserved
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2
LAN Control / Status Registers (CSR)
(LAN Controller—B1:D8:F0)
Table 8-4.
Intel® ICH7 Integrated LAN Controller CSR Space Register Address Map
Offset
Mnemonic
Register Name
Default
Type
00h–01h
SCB_STA
System Control Block Status Word
0000h
R/WC, RO
02h–03h
SCB_CMD
System Control Block Command
Word
0000h
R/W, WO
04h–07h
SCB_GENPNT
System Control Block General
Pointer
0000 0000h
R/W
08h–0Bh
Port
PORT Interface
0000 0000h
R/W (special)
0Ch–
0Dh
—
Reserved
—
—
0Eh
EEPROM_CNTL
EEPROM Control
00
R/W, RO, WO
0Fh
—
Reserved
—
—
10h–13h
MDI_CNTL
Management Data Interface
Control
0000 0000h
R/W (special)
14h–17h
REC_DMA_BC
Receive DMA Byte Count
0000 0000h
RO
18h
EREC_INTR
Early Receive Interrupt
00h
R/W
19–1Ah
FLOW_CNTL
Flow Control
0000h
RO, R/W
(special)
1Bh
PMDR
Power Management Driver
00h
R/WC
1Ch
GENCNTL
General Control
00h
R/W
1Dh
GENSTA
General Status
00h
RO
1Eh
—
—
—
1Fh
SMB_PCI
27h
R/W
20h–3Ch
—
—
—
Intel ® ICH7 Family Datasheet
Reserved
SMB via PCI
Reserved
315
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.1
SCB_STA—System Control Block Status Word Register
(LAN Controller—B1:D8:F0)
Offset Address: 00h–01h
Default Value:
0000h
Attribute:
Size:
R/WC, RO
16 bits
The ICH7’s integrated LAN controller places the status of its Command Unit (CU) and
Receive Unit (RC) and interrupt indications in this register for the processor to read.
Bit
Description
Command Unit (CU) Executed (CX) — R/WC.
15
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Interrupt signaled because the CU has completed executing a command with its
interrupt bit set.
Frame Received (FR) — R/WC.
14
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.
CU Not Active (CNA) — R/WC.
13
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = The Command Unit left the Active state or entered the Idle state. There are 2
distinct states of the CU. When configured to generate CNA interrupt, the interrupt
will be activated when the CU leaves the Active state and enters either the Idle or
the Suspended state. When configured to generate CI interrupt, an interrupt will be
generated only when the CU enters the Idle state.
Receive Not Ready (RNR) — R/WC.
12
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Interrupt signaled because the Receive Unit left the Ready state. This may be
caused by an RU Abort command, a no resources situation, or set suspend bit due
to a filled Receive Frame Descriptor.
Management Data Interrupt (MDI) — R/WC.
11
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Set when a Management Data Interface read or write cycle has completed. The
management data interrupt is enabled through the interrupt enable bit (bit 29 in
the Management Data Interface Control register in the CSR).
Software Interrupt (SWI) — R/WC.
10
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Set when software generates an interrupt.
Early Receive (ER) — R/WC.
9
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Indicates the occurrence of an Early Receive Interrupt.
Flow Control Pause (FCP) — R/WC.
8
316
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Indicates Flow Control Pause interrupt.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
Description
Command Unit Status (CUS) — RO.
7:6
00
01
10
11
=
=
=
=
Idle
Suspended
LPQ (Low Priority Queue) active
HPQ (High Priority Queue) active
Receive Unit Status (RUS) — RO.
5:2
1:0
8.2.2
Value
Status
Value
Status
0000b
Idle
1000b
Reserved
0001b
Suspended
1001b
Suspended with no more RBDs
0010b
No Resources
1010b
No resources due to no more
RBDs
0011b
Reserved
1011b
Reserved
0100b
Ready
1100b
Ready with no RBDs present
0101b
Reserved
1101b
Reserved
0110b
Reserved
1110b
Reserved
0111b
Reserved
1111b
Reserved
Reserved
SCB_CMD—System Control Block Command Word
Register (LAN Controller—B1:D8:F0)
Offset Address: 02h–03h
Default Value:
0000h
Attribute:
Size:
R/W, WO
16 bits
The processor places commands for the Command and Receive units in this register.
Interrupts are also acknowledged in this register.
Bit
Description
CX Mask (CX_MSK) — R/W.
15
0 = Interrupt not masked.
1 = Disable the generation of a CX interrupt.
FR Mask (FR_MSK) — R/W.
14
0 = Interrupt not masked.
1 = Disable the generation of an FR interrupt.
CNA Mask (CNA_MSK) — R/W.
13
0 = Interrupt not masked.
1 = Disable the generation of a CNA interrupt.
RNR Mask (RNR_MSK) — R/W.
12
0 = Interrupt not masked.
1 = Disable the generation of an RNR interrupt.
ER Mask (ER_MSK) — R/W.
11
0 = Interrupt not masked.
1 = Disable the generation of an ER interrupt.
FCP Mask (FCP_MSK) — R/W.
10
0 = Interrupt not masked.
1 = Disable the generation of an FCP interrupt.
Intel ® ICH7 Family Datasheet
317
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
Description
Software Generated Interrupt (SI) — WO.
9
8
0 = No Effect.
1 = Setting this bit causes the LAN controller to generate an interrupt.
Interrupt Mask (IM) — R/W. This bit enables or disables the LAN controller’s
assertion of the INTA# signal. This bit has higher precedence that the Specific Interrupt
Mask bits and the SI bit.
0 = Enable the assertion of INTA#.
1 = Disable the assertion of INTA#.
Command Unit Command (CUC) — R/W. Valid values are listed below. All other
values are Reserved.
0000 = NOP: Does not affect the current state of the unit.
0001 = CU Start: Start execution of the first command on the CBL. A pointer to the
first CB of the CBL should be placed in the SCB General Pointer before issuing
this command. The CU Start command should only be issued when the CU is in
the Idle or Suspended states (not when the CU is in the active state), and all of
the previously issued Command Blocks have been processed and completed by
the CU. Sometimes it is only possible to determine that all Command Blocks are
completed by checking that the Complete bit is set in all previously issued
Command Blocks.
0010 = CU Resume: Resume operation of the Command unit by executing the next
command. This command will be ignored if the CU is idle.
0011 = CU HPQ Start: Start execution of the first command on the high priority CBL.
A pointer to the first CB of the HPQ CBL should be placed in the SCB General
POinter before issuing this command.
7:4
0100 = Load Dump Counters Address: Indicates to the device where to write dump
data when using the Dump Statistical Counters or Dump and Reset Statistical
Counters commands. This command must be executed at least once before any
usage of the Dump Statistical Counters or Dump and Reset Statistical Counters
commands. The address of the dump area must be placed in the General
Pointer register.
0101 = Dump Statistical Counters: Tells the device to dump its statistical counters
to the area designated by the Load Dump Counters Address command.
0110 = Load CU Base: The device’s internal CU Base Register is loaded with the value
in the CSB General Pointer.
0111 = Dump and Reset Statistical Counters: Indicates to the device to dump its
statistical counters to the area designated by the Load Dump Counters Address
command, and then to clear these counters.
1010 = CU Static Resume: Resume operation of the Command unit by executing the
next command. This command will be ignored if the CU is idle. This command
should be used only when the CU is in the Suspended state and has no pending
CU Resume commands.
1011 = CU HPQ Resume: Resume execution of the first command on the HPQ CBL.
this command will be ignored if the HPQ was not started.
3
318
Reserved
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
Description
Receive Unit Command (RUC) — R/W. Valid values are:
000 = NOP: Does not affect the current state of the unit.
001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in
the SCB General POinter before using this command. The device pre-fetches
the first RFD and the first RBD (if in flexible mode) in preparation to receive
incoming frames that pass its address filtering.
010 = RU Resume: Resume frame reception (only when in suspended state).
011 = RCV DMA Redirect: Resume the RCV DMA when configured to “Direct DMA
Mode.” The buffers are indicated by an RBD chain which is pointed to by an
offset stored in the General Pointer Register (this offset will be added to the RU
Base).
2:0
100 = RU Abort: Abort RU receive operation immediately.
101 = Load Header Data Size (HDS): This value defines the size of the Header
portion of the RFDs or Receive buffers. The HDS value is defined by the lower
14 bits of the SCB General Pointer, so bits 31:15 should always be set to 0’s
when using this command. Once a Load HDS command is issued, the device
expects only to find Header RFDs, or be used in “RCV Direct DMA mode” until it
is reset. Note that the value of HDS should be an even, non-zero number.
110 = Load RU Base: The device’s internal RU Base Register is loaded with the value
in the SCB General Pointer.
111 = RBD Resume: Resume frame reception into the RFA. This command should
only be used when the RU is already in the “No Resources due to no RBDs”
state or the “Suspended with no more RBDs” state.
8.2.3
SCB_GENPNT—System Control Block General Pointer
Register (LAN Controller—B1:D8:F0)
Offset Address: 04h–07h
Default Value:
0000 0000h
8.2.4
Attribute:
Size:
R/W
32 bits
Bit
Description
15:0
SCB General Pointer — R/W. The SCB General Pointer register is programmed by
software to point to various data structures in main memory depending on the current
SCB Command word.
PORT—PORT Interface Register
(LAN Controller—B1:D8:F0)
Offset Address: 08h–0Bh
Default Value:
0000 0000h
Attribute:
Size:
R/W (special)
32 bits
The PORT interface allows the processor to reset the ICH7’s internal LAN controller, or
perform an internal self test. The PORT DWord may be written as a 32-bit entity, two
16-bit entities, or four
8-bit entities. The LAN controller will only accept the command after the high byte
(offset 0Bh) is written; therefore, the high byte must be written last.
Intel ® ICH7 Family Datasheet
319
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
Description
31:4
Pointer Field (PORT_PTR) — R/W (special). A 16-byte aligned address must be
written to this field when issuing a Self-Test command to the PORT interface.The results
of the Self Test will be written to the address specified by this field.
PORT Function Selection (PORT_FUNC) — R/W (special). Valid values are listed
below. All other values are reserved.
0000 = PORT Software Reset: Completely resets the LAN controller (all CSR and PCI
registers). This command should not be used when the device is active. If a
PORT Software Reset is desired, software should do a Selective Reset
(described below), wait for the PORT register to be cleared (completion of the
Selective Reset), and then issue the PORT Software Reset command. Software
should wait approximately 10 μs after issuing this command before attempting
to access the LAN controller’s registers again.
3:0
0001 = Self Test: The Self-Test begins by issuing an internal Selective Reset followed
by a general internal self-test of the LAN controller. The results of the self-test
are written to memory at the address specified in the Pointer field of this
register. The format of the self-test result is shown in Table 8-5. After
completing the self-test and writing the results to memory, the LAN controller
will execute a full internal reset and will re-initialize to the default configuration.
Self-Test does not generate an interrupt of similar indicator to the host
processor upon completion.
0010 = Selective Reset: Sets the CU and RU to the Idle state, but otherwise
maintains the current configuration parameters (RU and CU Base, HDSSize,
Error Counters, Configure information and Individual/Multicast Addresses are
preserved). Software should wait approximately 10 μs after issuing this
command before attempting to access the LAN controller’s registers again.
Table 8-5.
Self-Test Results Format
Bit
31:13
Description
Reserved
General Self-Test Result (SELF_TST) — R/W (special).
12
11:6
5
4
3
2
1:0
320
0 = Pass
1 = Fail
Reserved
Diagnose Result (DIAG_RSLT) — R/W (special). This bit provides the result of an
internal diagnostic test of the Serial Subsystem.
0 = Pass
1 = Fail
Reserved
Register Result (REG_RSLT) — R/W (special). This bit provides the result of a test of
the internal Parallel Subsystem registers.
0 = Pass
1 = Fail
ROM Content Result (ROM_RSLT) — R/W (special). This bit provides the result of a
test of the internal microcode ROM.
0 = Pass
1 = Fail
Reserved
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.5
EEPROM_CNTL—EEPROM Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value:
00h
Attribute:
Size:
RO, R/W, WO
8 bits
The EEPROM Control Register is a 16-bit field that enables a read from and a write to
the external EEPROM.
Bit
7:4
Description
Reserved
3
EEPROM Serial Data Out (EEDO) — RO. Note that this bit represents “Data Out”
from the perspective of the EEPROM device. This bit contains the value read from the
EEPROM when performing read operations.
2
EEPROM Serial Data In (EEDI) — WO. Note that this bit represents “Data In” from
the perspective of the EEPROM device. The value of this bit is written to the EEPROM
when performing write operations.
EEPROM Chip Select (EECS) — R/W.
1
0
0 = Drives the Intel® ICH7’s EE_CS signal low to disable the EEPROM. this bit must be
set to 0 for a minimum of 1 μs between consecutive instruction cycles.
1 = Drives the ICH7’s EE_CS signal high, to enable the EEPROM.
EEPROM Serial Clock (EESK) — R/W. Toggling this bit clocks data into or out of the
EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM
component’s minimum clock frequency specification.
0 = Drives the ICH7’s EE_SHCLK signal low.
1 = Drives the ICH7’s EE_SHCLK signal high.
Intel ® ICH7 Family Datasheet
321
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.6
MDI_CNTL—Management Data Interface (MDI) Control
Register (LAN Controller—B1:D8:F0)
Offset Address: 10h–13h
Default Value:
0000 0000h
Attribute:
Size:
R/W (special)
32 bits
The Management Data Interface (MDI) Control register is a 32-bit field and is used to
read and write bits from the LAN Connect component. This register may be written as a
32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN controller will only
accept the command after the high byte (offset 13h) is written; therefore, the high
byte must be written last.
Bit
31:30
Description
These bits are reserved and should be set to 00b.
Interrupt Enable — R/W (special).
29
0 = Disable.
1 = Enables the LAN controller to assert an interrupt to indicate the end of an MDI
cycle.
Ready — R/W (special).
28
0 = Expected to be reset by software at the same time the command is written.
1 = Set by the LAN controller at the end of an MDI transaction.
Opcode — R/W (special). These bits define the opcode:
00 = Reserved
27:26
01 = MDI write
10 = MDI read
11 = Reserved
8.2.7
25:21
LAN Connect Address — R/W (special). This field of bits contains the LAN Connect
address.
20:16
LAN Connect Register Address — R/W (special). This field contains the LAN Connect
Register Address.
15:0
Data — R/W (special). In a write command, software places the data bits in this field,
and the LAN controller transfers the data to the external LAN Connect component.
During a read command, the LAN controller reads these bits serially from the LAN
Connect, and software reads the data from this location.
REC_DMA_BC—Receive DMA Byte Count Register
(LAN Controller—B1:D8:F0)
Offset Address: 14h–17h
Default Value:
0000 0000h
322
Attribute:
Size:
RO
32 bits
Bit
Description
31:0
Receive DMA Byte Count — RO. This field keeps track of how many bytes of receive
data have been passed into host memory via DMA.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.8
EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0)
Offset Address: 18h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
The Early Receive Interrupt register allows the internal LAN controller to generate an
early interrupt depending on the length of the frame. The LAN controller will generate
an interrupt at the end of the frame regardless of whether or not Early Receive
Interrupts are enabled.
Note:
8.2.9
It is recommended that software not use this register unless receive interrupt latency
is a critical performance issue in that particular software environment. Using this
feature may reduce receive interrupt latency, but will also result in the generation of
more interrupts, which can degrade system efficiency and performance in some
environments.
Bit
Description
7:0
Early Receive Count — R/W. When some non-zero value x is programmed into this
register, the LAN controller will set the ER bit in the SCB Status Word Register and assert
INTA# when the byte count indicates that there are x qwords remaining to be received
in the current frame (based on the Type/Length field of the received frame). No Early
Receive interrupt will be generated if a value of 00h (the default value) is programmed
into this register.
FLOW_CNTL—Flow Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 19h–1Ah
Default Value:
0000h
Bit
15:13
Attribute:
Size:
RO, R/W (special)
16 bits
Description
Reserved
FC Paused Low — RO.
12
0 = Cleared when the FC timer reaches 0, or a Pause frame is received.
1 = Set when the LAN controller receives a Pause Low command with a value greater
than 0.
FC Paused — RO.
11
0 = Cleared when the FC timer reaches 0.
1 = Set when the LAN controller receives a Pause command regardless of its cause
(FIFO reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its
Flow Control Pause bit set, or software writing a 1 to the Xoff bit).
FC Full — RO.
10
0 = Cleared when the FC timer reaches 0.
1 = Set when the LAN controller sends a Pause command with a value greater than 0.
Xoff — R/W (special). This bit should only be used if the LAN controller is configured to
operate with IEEE frame-based flow control.
9
0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register).
1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN controller to
behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff
request due to an “RFD Xoff” bit.
Intel ® ICH7 Family Datasheet
323
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
Description
Xon — WO. This bit should only be used if the LAN controller is configured to operate
with IEEE frame-based flow control.
8
7:3
0 = This bit always returns 0 on reads.
1 = Writing a 1 to this bit resets the Xoff request to the LAN controller, clearing bit 9 in
this register.
Reserved
Flow Control Threshold — R/W. The LAN controller can generate a Flow Control Pause
frame when its Receive FIFO is almost full. The value programmed into this field
determines the number of bytes still available in the Receive FIFO when the Pause
frame is generated.
2:0
8.2.10
Bits 2:0
Free Bytes in RX
FIFO
000b
0.50 KB
001b
1.00 KB
010b
1.25 KB
011b
1.50 KB
100b
1.75 KB
101b
2.00 KB
110b
2.25 KB
111b
2.50 KB
Comment
Fast system (recommended
default)
Slow system
PMDR—Power Management Driver Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Bh
Default Value:
00h
Attribute:
Size:
R/WC
8 bits
The ICH7’s internal LAN controller provides an indication in the PMDR that a wake-up
event has occurred.
Bit
Description
Link Status Change Indication — R/WC.
7
0 = Software clears this bit by writing a 1 to it.
1 = The link status change bit is set following a change in link status.
Magic Packet — R/WC.
6
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wakeup disable bit in the configuration command and the PME Enable bit in the Power
Management Control/ Status Register.
Interesting Packet — R/WC.
5
4:3
324
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when an “interesting” packet is received. Interesting packets are
defined by the LAN controller packet filters.
Reserved
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
2
Description
ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode.
TCO Request — R/WC.
1
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set to 1b when the LAN controller is busy with TCO activity.
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power
Management Control/Status Register (PMCSR).
0
8.2.11
0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the
PMCSR and deasserts the PME signal.
1 = Set upon a wake-up event, independent of the PME Enable bit.
GENCNTL—General Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Ch
Default Value:
00h
Attribute:
Size:
Bit
7:4
Description
Reserved. These bits should be set to 0000b.
LAN Connect Software Reset
3
2
— R/W.
0 = Cleared by software to begin normal LAN Connect operating mode. Software must
not attempt to access the LAN Connect interface for at least 1ms after clearing this
bit.
1 = Software can set this bit to force a reset condition on the LAN Connect interface.
Reserved. This bit should be set to 0.
Deep Power-Down on Link Down Enable
1
0
R/W
8 bits
— R/W.
0 = Disable
1 = Enable. The Intel® ICH7’s internal LAN controller may enter a deep power-down
state (sub-3 mA) in the D2 and D3 power states while the link is down. In this
state, the LAN controller does not keep link integrity. This state is not supported for
point-to-point connection of two end stations.
Reserved
Intel ® ICH7 Family Datasheet
325
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.12
GENSTA—General Status Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Dh
Default Value:
00h
Attribute:
Size:
Bit
7:3
RO
8 bits
Description
Reserved
Duplex Mode — RO. This bit indicates the wire duplex mode.
2
0 = Half duplex
1 = Full duplex
Speed — RO. This bit indicates the wire speed.
1
0 = 10 Mb/s
1 = 100 Mb/s
Link Status Indication — RO. This bit indicates the status of the link.
0
8.2.13
0 = Invalid
1 = Valid
SMB_PCI—SMB via PCI Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Fh
Default Value:
27h
Attribute:
Size:
R/W, RO
8 bits
Software asserts SREQ when it wants to isolate the PCI-accessible SMBus to the ASF
registers/commands. It waits for SGNT to be asserted. At this point SCLI, SDAO, SCLO,
and SDAI can be toggled/read to force ASF controller SMBus transactions without
affecting the external SMBus. After all operations are completed, the bus is returned to
idle (SCLO=1b,SDAO=1b, SCLI=1b, SDAI=1b), SREQ is released (written 0b). Then
SGNT goes low to indicate released control of the bus. The logic in the ASF controller
only asserts or deasserts SGNT at times when it determines that it is safe to switch (all
SMBuses that are switched in/out are idle).
When in isolation mode (SGNT=1), software can access the ICH7 SMBus slaves that
allow configuration without affecting the external SMBus. This includes configuration
register accesses and ASF command accesses. However, this capability is not available
to the external TCO controller. When SGNT=0, the bit-banging and reads are reflected
on the main SMBus and the PCISML_SDA0, PCISML_SCL0 read only bits.
Bit
7:6
326
Description
Reserved
5
PCISML_SCLO
— RO. SMBus Clock from the ASF controller.
4
PCISML_SGNT
— RO. SMBus Isolation Grant from the ASF controller.
3
PCISML_SREQ
— R/W. SMBus Isolation Request to the ASF controller.
2
PCISML_SDAO
— RO. SMBus Data from the ASF controller.
1
PCISML_SDAI
— R/W. SMBus Data to the ASF controller.
0
PCISML_SCLI
— R/W. SMBus Clock to the ASF controller.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.14
Statistical Counters (LAN Controller—B1:D8:F0)
The ICH7’s integrated LAN controller provides information for network management
statistics by providing on-chip statistical counters that count a variety of events
associated with both transmit and receive. The counters are updated by the LAN
controller when it completes the processing of a frame (that is, when it has completed
transmitting a frame on the link or when it has completed receiving a frame). The
Statistical Counters are reported to the software on demand by issuing the Dump
Statistical Counters command or Dump and Reset Statistical Counters command in the
SCB Command Unit Command (CUC) field.
Table 8-6.
Statistical Counters (Sheet 1 of 2)
ID
Counter
Description
0
Transmit Good
Frames
This counter contains the number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the frame
was read from memory as is done for the Transmit Command
Block status.
4
Transmit Maximum
Collisions (MAXCOL)
Errors
This counter contains the number of frames that were not
transmitted because they encountered the configured maximum
number of collisions.
8
Transmit Late
Collisions
(LATECOL) Errors
This counter contains the number of frames that were not
transmitted since they encountered a collision later than the
configured slot time.
12
Transmit Underrun
Errors
A transmit underrun occurs because the system bus cannot keep
up with the transmission. This counter contains the number of
frames that were either not transmitted or retransmitted due to a
transmit DMA underrun. If the LAN controller is configured to
retransmit on underrun, this counter may be updated multiple
times for a single frame.
16
Transmit Lost
Carrier Sense (CRS)
This counter contains the number of frames that were
transmitted by the LAN controller despite the fact that it detected
the de-assertion of CRS during the transmission.
20
Transmit Deferred
This counter contains the number of frames that were deferred
before transmission due to activity on the link.
24
Transmit Single
Collisions
This counter contains the number of transmitted frames that
encountered one collision.
28
Transmit Multiple
Collisions
This counter contains the number of transmitted frames that
encountered more than one collision.
32
Transmit Total
Collisions
This counter contains the total number of collisions that were
encountered while attempting to transmit. This count includes
late collisions and frames that encountered MAXCOL.
36
Receive Good
Frames
This counter contains the number of frames that were received
properly from the link. It is updated only after the actual
reception from the link is completed and all the data bytes are
stored in memory.
Receive CRC Errors
This counter contains the number of aligned frames discarded
because of a CRC error. This counter is updated, if needed,
regardless of the Receive Unit state. The Receive CRC Errors
counter is mutually exclusive of the Receive Alignment Errors
and Receive Short Frame Errors counters.
40
Intel ® ICH7 Family Datasheet
327
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Table 8-6.
Statistical Counters (Sheet 2 of 2)
ID
Counter
Description
Receive Alignment
Errors
This counter contains the number of frames that are both
misaligned (for example, CRS de-asserts on a non-octal
boundary) and contain a CRC error. The counter is updated, if
needed, regardless of the Receive Unit state. The Receive
Alignment Errors counter is mutually exclusive of the Receive
CRC Errors and Receive Short Frame Errors counters.
Receive Resource
Errors
This counter contains the number of good frames discarded due
to unavailability of resources. Frames intended for a host whose
Receive Unit is in the No Resources state fall into this category. If
the LAN controller is configured to Save Bad Frames and the
status of the received frame indicates that it is a bad frame, the
Receive Resource Errors counter is not updated.
52
Receive Overrun
Errors
This counter contains the number of frames known to be lost
because the local system bus was not available. If the traffic
problem persists for more than one frame, the frames that follow
the first are also lost; however, because there is no lost frame
indicator, they are not counted.
56
Receive Collision
Detect (CDT)
This counter contains the number of frames that encountered
collisions during frame reception.
60
Receive Short
Frame Errors
This counter contains the number of received frames that are
shorter than the minimum frame length. The Receive Short
Frame Errors counter is mutually exclusive to the Receive
Alignment Errors and Receive CRC Errors counters. A short frame
will always increment only the Receive Short Frame Errors
counter.
64
Flow Control
Transmit Pause
This counter contains the number of Flow Control frames
transmitted by the LAN controller. This count includes both the
Xoff frames transmitted and Xon (PAUSE(0)) frames transmitted.
68
Flow Control
Receive Pause
This counter contains the number of Flow Control frames
received by the LAN controller. This count includes both the Xoff
frames received and Xon (PAUSE(0)) frames received.
72
Flow Control
Receive
Unsupported
This counter contains the number of MAC Control frames
received by the LAN controller that are not Flow Control Pause
frames. These frames are valid MAC control frames that have the
predefined MAC control Type value and a valid address but has
an unsupported opcode.
76
Receive TCO Frames
This counter contains the number of TCO packets received by the
LAN controller.
78
Transmit TCO
Frames
This counter contains the number of TCO packets transmitted.
44
48
The Statistical Counters are initially set to 0 by the ICH7’s integrated LAN controller
after reset. They cannot be preset to anything other than 0. The LAN controller
increments the counters by internally reading them, incrementing them and writing
them back. This process is invisible to the processor and PCI bus. In addition, the
counters adhere to the following rules:
• The counters are wrap-around counters. After reaching FFFFFFFFh the counters
wrap around to 0.
• The LAN controller updates the required counters for each frame. It is possible for
more than one counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE
802.1 standard. The LAN controller supports all mandatory and recommend
328
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
statistics functions through the status of the receive header and directly through
these Statistical Counters.
The processor can access the counters by issuing a Dump Statistical Counters SCB
command. This provides a “snapshot”, in main memory, of the internal LAN controller
statistical counters. The LAN controller supports 21 counters. The dump could consist
of the either 16, 19, or all 21 counters, depending on the status of the Extended
Statistics Counters and TCO Statistics configuration bits in the Configuration command.
8.3
ASF Configuration Registers
(LAN Controller—B1:D8:F0)
The ASF registers in this table are accessible through the ICH7 SMBus slave interface.
Table 8-7.
ASF Register Address Map
Offset
Mnemonic
E0h
ASF_RID
E1h
E2h
E3h
ASF_CNTL_EN
E4h
ENABLE
Register Name
Default
Type
ASF Revision Identification
ECh
RO
SMB_CNTL
SMBus Control
40h
R/W
ASF_CNTL
ASF Control
00h
R/W, RO
ASF Control Enable
00h
R/W
Enable
00h
R/W
APM
08h
R/W
—
—
E5h
APM
E6h–E7h
—
E8h
WTIM_CONF
Watchdog Timer Configuration
00h
R/W
E9h
HEART_TIM
Heartbeat Timer
02h
R/W
Reserved
EAh
RETRAN_INT
Retransmission Interval
02h
R/W
EBh
RETRAN_PCL
Retransmission Packet Count Limit
03h
R/W
ECh
ASF_WTIM1
ASF Watchdog Timer 1
01h
R/W
EDh
ASF_WTIM2
ASF Watchdog Timer 2
00h
R/W
F0h
PET_SEQ1
PET Sequence 1
00h
R/W
F1h
PET_SEQ2
PET Sequence 2
00h
R/W
F2h
STA
F3h
FOR_ACT
F4h
RMCP_SNUM
F5h
SP_MODE
F6h
INPOLL_TCONF
F7h
PHIST_CLR
F8h
F9h
Status
40h
R/W
Forced Actions
02h
R/W
RMCP Sequence Number
00h
R/W
Special Modes
x0h
R/WC, RO
Inter-Poll Timer Configuration
10h
R/W
Poll History Clear
00h
R/WC
PMSK1
Polling Mask 1
XXh
R/W
PMSK2
Polling Mask 2
XXh
R/W
FAh
PMSK3
Polling Mask 3
XXh
R/W
FBh
PMSK4
Polling Mask 4
XXh
R/W
FCh
PMSK5
Polling Mask 5
XXh
R/W
FDh
PMSK6
Polling Mask 6
XXh
R/W
FEh
PMSK7
Polling Mask 7
XXh
R/W
FFh
PMSK8
Polling Mask 8
XXh
R/W
Intel ® ICH7 Family Datasheet
329
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.1
ASF_RID—ASF Revision Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: E0h
Default Value:
ECh
Bit
8.3.2
Attribute:
Size:
RO
8 bits
Description
7:3
ASF ID — RO. Hardwired to 11101 to identify the ASF controller.
2:0
ASF Silicon Revision — RO. This field provides the silicon revision.
SMB_CNTL—SMBus Control Register
(LAN Controller—B1:D8:F0)
Offset Address: E1h
Default Value:
40h
Attribute:
Size:
R/W
8 bits
This register is used to control configurations of the SMBus ports.
Bit
Description
SMBus Remote Control ASF Enable (SMB_RCASF) — R/W.
7
0 = Legacy descriptors and operations are used.
1 = ASF descriptors and operations are used.
SMBus ARP Enable (SMB_ARPEN) — R/W.
6
5:4
0 = Disable.
1 = ASF enables the SMBus ARP protocol.
Reserved
SMBus Drive Low (SMB_DRVLO) — R/W.
3
2:0
330
0 = ASF will not drive the main SMBus signals low while PWR_GOOD = 0.
1 = ASF will drive the main SMBus signals low while PWR_GOOD = 0.
Reserved
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.3
ASF_CNTL—ASF Control Register
(LAN Controller—B1:D8:F0)
Offset Address: E2h
Default Value:
00h
Attribute:
Size:
R/W, RO
8 bits
This register contains enables for special modes and SOS events. CTL_PWRLS should
be set if ASF should be expecting a power loss due to software action. Otherwise, an
EEPROM reload will happen when the power is lost.
Bit
Description
SMBus Hang SOS Enable (CTL_SMBHG) — R/W.
7
0 = Disable
1 = Enables SMBus Hang SOS to be sent.
Watchdog SOS Enable (CTL_WDG) — R/W.
6
0 = Disable.
1 = Enables Watchdog SOS to be sent.
Link Loss SOS Enable (CTL_LINK) — R/W.
5
4
0 = Disable.
1 = Enables Link Loss SOS to be sent.
OS Hung Status (CTL_OSHUNG) — RO.
1 = This bit will be set to 1 when ASF has detected a Watchdog Expiration.
NOTE: This condition is only clearable by a PCI RST# assertion (system reset).
Power-Up SOS Enable (CTL_PWRUP) — R/W.
3
0 = Disable.
1 = Enables Power-Up SOS to be sent.
2
Reserved
Receive ARP Enable (CTL_RXARP) — R/W. The LAN controller interface provides a
mode where all packets can be requested.
1
0 = Disable.
1 = Enable. ASF requests all packets when doing a Receive Enable. This is necessary in
LAN controller to get ARP packets.
NOTE: Changes to this bit will not take effect until the next Receive Enable command
to the LAN.
Power Loss OK (CTL_PWRLS) — R/W.
0
0 = Power Loss will reload EEPROM
1 = Power Loss will not reload EEPROM
Intel ® ICH7 Family Datasheet
331
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.4
ASF_CNTL_EN—ASF Control Enable Register
(ASF Controller—B1:D8:F0)
Offset Address: E3h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register is used to enable global processing as well as polling. GLOBAL ENABLE
controls all of the SMBus processing and packet creation.
Bit
Description
Global Enable (CENA_ALL) — R/W.
7
0 = Disable
1 = All control and polling enabled
Receive Enable (CENA_RX) — R/W.
6
0 = Disable
1 = TCO Receives enabled.
Transmit Enable (CENA_TX) — R/W.
5
0 = Disable
1 = SOS and RMCP Transmits enabled
ASF Polling Enable (CENA_APOL) — R/W.
4
0 = Disable
1 = Enable ASF Sensor Polling.
Legacy Polling Enable (CENA_LPOL) — R/W.
3
0 = Disable
1 = Enable Legacy Sensor Polling.
Number of Legacy Poll Devices (CENA_NLPOL) — R/W. This 3-bit value indicates
how many of the eight possible polling descriptors are active.
2:0
000 = First polling descriptor is active.
001 = First two polling descriptors are active.
...
111 = Enables all eight descriptors.
332
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.5
ENABLE—Enable Register
(ASF Controller—B1:D8:F0)
Offset Address: E4h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register provides the mechanism to enable internal SOS operations and to enable
the remote control functions.
Bit
Description
Enable OSHung ARPs (ENA_OSHARP) — R/W.
7
0 = Disable
1 = ASF will request all packets when in a OSHung state. This allows ASF to receive
ARP frames and respond as appropriate.
State-based Security Destination Port Select (ENA_SB0298) — R/W.
6
0 = State-based security will be honored on packets received on port 026Fh.
1 = Packets received on port 0298h will be honored.
PET VLAN Enable (ENA_VLAN) — R/W.
5
0 = Disable
1 = Indicates a VLAN header for PET
NOTE: If this bit is set, the PET packet in EEPROM must have the VLAN tag within the
packet.
4
Reserved
System Power Cycle Enable (ENA_CYCLE) — R/W.
3
0 = Disable
1 = Enables RMCP Power Cycle action.
System Power-Down Enable (ENA_DWN) — R/W.
2
0 = Disable
1 = Enables RMCP Power-Down action.
System Power-Up Enable (ENA_UP) — R/W.
1
0 = Disable
1 = Enables RMCP Power-Up action.
System Reset Enable (ENA_RST) — R/W.
0
0 = Disable
1 = Enables RMCP Reset action
Intel ® ICH7 Family Datasheet
333
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.6
APM—APM Register
(ASF Controller—B1:D8:F0)
Offset Address: E5h
Default Value:
08h
Attribute:
Size:
R/W
8 bits
This register contains the configuration bit to disable state-based security.
Bit
7:4
Description
Reserved
Disable State-based Security (APM_DISSB) — R/W.
3
2:0
8.3.7
0 = State-based security on OSHung is enabled.
1 = State-based security is disabled and actions are not gated by OSHung.
Reserved
WTIM_CONF—Watchdog Timer Configuration Register
(ASF Controller—B1:D8:F0)
Offset Address: E8h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register contains a single bit that enables the Watchdog timer. This bit is not
intended to be accessed by software, but should be configured appropriately in the
EEPROM location for this register default. The bit provides real-time control for
enabling/disabling the Watchdog timer. When set the timer will count down. When
cleared the counter will stop. Timer Start ASF SMBUS messages will set this bit. Timer
Stop ASF SMBus transactions will clear this bit.
Bit
7:1
Description
Reserved
Timer Enable (WDG_ENA) — R/W.
0
334
0 = Disable
1 = Enable Counter
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.8
HEART_TIM—Heartbeat Timer Register
(ASF Controller—B1:D8:F0)
Offset Address: E9h
Default Value:
02h
Attribute:
Size:
R/W
8 bits
The HeartBeat Timer register implements the heartbeat timer. This defines the period
of the heartbeats packets. It contains a down counting value when enabled and the
time-out value when the counter is disabled. The timer can be configured and enabled
in a single write.
Note:
The heartbeat timer controls the heartbeat status packet frequency. The timer is freerunning and the configured time is only valid from one heartbeat to the next. When
enabled by software, the next heartbeat may occur in any amount of time less than the
configured time.
.
Bit
7:1
Description
Heartbeat Timer Value (HBT_VAL) — R/W. Heartbeat timer load value in
10.7-second resolution. This field can only be written while the timer is disabled.
(10.7 sec – 23 min range). Read as load value when HBT_ENA=0. Read as
decrementing value when HBT_ENA=1. Timer resolution is 10.7 seconds. A value of
00h is invalid.
Timer Enable (HBT_ENA) — R/W.
0
8.3.9
0 = Disable
1 = Enable / Reset Counter
RETRAN_INT—Retransmission Interval Register
(ASF Controller—B1:D8:F0)
Offset Address: EAh
Default Value:
02h
Attribute:
Size:
R/W
8 bits
This register implements the retransmission timer. This is the time between packet
transmissions for multiple packets due to a SOS.
Bit
Description
7:1
Retransmit Timer Value (RTM_VAL) — R/W. Retransmit timer load value 2.7 second
resolution. This field is always writable (2.7 sec – 5.7 min range). Timer is accurate to
+0 seconds, –0.336 seconds. Reads always show the load value (decrement value not
shown). A value of 00h is invalid.
0
Reserved
Intel ® ICH7 Family Datasheet
335
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.10
RETRAN_PCL—Retransmission Packet Count Limit
Register (ASF Controller—B1:D8:F0)
Offset Address: EBh
Default Value:
03h
Attribute:
Size:
R/W
8 bits
This register defines the number of packets that are to be sent due to an SOS.
Bit
7:0
8.3.11
Description
Retransmission Packet Count Limit (RPC_VAL) — R/W. This field provides the
number of packets to be sent for all SOS packets that require retransmissions.
ASF_WTIM1—ASF Watchdog Timer 1 Register
(ASF Controller—B1:D8:F0)
Offset Address: ECh
Default Value:
01h
Attribute:
Size:
R/W
8 bits
This register is used to load the low byte of the timer. When read, it reports the
decrementing value. This register is not intended to be written by software, but should
be configured appropriately in the EEPROM location for this register default. Timer Start
ASF SMBus transactions will load values into this register. Once the timer has expired
(0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will
remain at 00h until otherwise changed.
8.3.12
Bit
Description
7:0
ASF Watchdog Timer 1 (AWD1_VAL) — R/W. This field provides the low byte of the
ASF 1-second resolution timer. The timer is accurate to +0 seconds, –0.336 seconds.
ASF_WTIM2—ASF Watchdog Timer 2 Register
(ASF Controller—B1:D8:F0)
Offset Address: EDh
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register is used to load the high byte of the timer. When read, it reports the
decrementing value. This register is not intended to be written by software, but should
be configured appropriately in the EEPROM location for this register default. Timer Start
ASF SMBus transactions will load values into this register. Once the timer has expired
(0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will
remain at 00h until otherwise changed.
Bit
7:0
336
Description
ASF Watchdog Timer 2 (AWD2_VAL) — R/W. This field provides the high byte of
the ASF 1-second resolution timer. The timer is accurate to +0 seconds, –0.336
seconds.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.13
PET_SEQ1—PET Sequence 1 Register
(ASF Controller—B1:D8:F0)
Offset Address: F0h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register (low byte) holds the current value of the PET sequence number. This field
is read/write-able through this register, and is also automatically incremented by the
hardware when new PET packets are generated. By policy, software should not write to
this register unless transmission is disabled.
Bit
7:0
8.3.14
Description
PET Sequence Byte 1 (PSEQ1_VAL) — R/W. This field provides the low byte.
PET_SEQ2—PET Sequence 2 Register
(ASF Controller—B1:D8:F0)
Offset Address: F1h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register (high byte) holds the current value of the PET sequence number. This field
is read/write-able through this register, and is also automatically incremented by the
hardware when new PET packets are generated. By policy, software should not write to
this register unless transmission is disabled.
Bit
7:0
Description
PET Sequence Byte 2 (PSEQ2_VAL) — R/W. This field provides the high byte.
Intel ® ICH7 Family Datasheet
337
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.15
STA—Status Register
(ASF Controller—B1:D8:F0)
Offset Address: F2h
Default Value:
40h
Attribute:
Size:
R/W
8 bits
This register gives status indication about several aspects of ASF.
Bit
Description
7
EEPROM Loading (STA_LOAD) — R/W. EEPROM defaults are in the process of being
loaded when this bit is a 1.
6
5:4
EEPROM Invalid Checksum Indication (STA_ICRC) — R/W. This bit should be read
only after the EEC_LOAD bit is a 0.
0 = Valid
1 = Invalid checksum detected for ASF portion of the EEPROM.
Reserved
Power Cycle Status (STA_CYCLE) — R/W.
3
0 = Software clears this bit by writing a 1.
1 = This bit is set when a Power Cycle operation has been issued.
Power Down Status (STA_DOWN) — R/W.
2
0 = Software clears this bit by writing a 1
1 = This bit is set when a Power Down operation has been issued.
Power Up Status (STA_UP) — R/W.
1
0 = Software clears this bit by writing a 1
1 = This bit is set when a Power Up operation has been issued.
System Reset Status (STA_RST) — R/W.
0
338
0 = Software clears this bit by writing a 1
1 = This bit is set when a System Reset operation has been issued.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.16
FOR_ACT—Forced Actions Register
(ASF Controller—B1:D8:F0)
Offset Address: F3h
Default Value:
02h
Attribute:
Size:
R/W
8 bits
This register contains many different forcible actions including APM functions, flushing
internal pending SOS operations, software SOS operations, software reset, and
EEPROM reload. Writes to this register must only set one bit per-write. Setting multiple
bits in a single write can have indeterminate results.
Note:
For bits in this register, writing a 1 invokes the operation. The bits self-clear
immediately.
Bit
Description
7
Software Reset (FRC_RST) — R/W. This bit is used to reset the ASF controller. It
performs the equivalent of a hardware reset and re-read the EEPROM. This bit selfclears immediately. Software should wait for the EEC_LOAD bit to clear.
6
Force EEPROM Reload (FRC_EELD) — R/W. Force Reload of EEPROM without affect
current monitoring state of the ASF controller. This bit self-clears immediately.
NOTE: Software registers in EEPROM are not loaded by this action. Software should
disable the ASF controller before issuing this command and wait for STA_LOAD
to clear before enabling again.
5
Flush SOS (FRC_FLUSH) — R/W. This bit is used to flush any pending SOSes or
history internal to the ASF controller. This is necessary because the Status register only
shows events that have happened as opposed to SOS events sent. Also, the history bits
in the ASF controller are not software visible. Self-clears immediately.
4
Reserved
3
Force APM Power Cycle (FRC_ACYC) — R/W. This mode forces the ASF controller to
initiate a power cycle to the system. The bit self-clears immediately.
2
Force APM Hard Power Down (FRC_AHDN) — R/W. This mode forces the ASF
controller to initiate a hard power down of the system immediately. The bit self-clears
immediately.
1
Clear ASF Polling History (FRC_CLRAPOL) — R/W. Writing a 1b to this bit position
will clear the Poll History associated with all ASF Polling. Writing a 0b has no effect. This
bit self-clears immediately.
0
Force APM Reset (FRC_ARST) — R/W. This mode forces the ASF controller to initiate
a hard reset of the system immediately. The bit self-clears immediately.
Intel ® ICH7 Family Datasheet
339
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.17
RMCP_SNUM—RMCP Sequence Number Register
(ASF Controller—B1:D8:F0)
Offset Address: F4h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
This register is a means for software to read the current sequence number that
hardware is using in RMCP packets. Software can also change the value. Software
should only write to this register while the GLOBAL ENABLE is off.
8.3.18
Bit
Description
7:0
RMCP Sequence Number (RSEQ_VAL) — R/W. This is the current sequence number
of the RMCP packet being sent or the sequence number of the next RMCP packet to be
sent. This value can be set by software. At reset, it defaults to 00h. If the sequence
number is not FFh, the ASF controller will automatically increment this number by one
(or rollover to 00h if incrementing from FEh) after a successful RMCP packet
transmission.
SP_MODE—Special Modes Register
(ASF Controller—B1:D8:F0)
Offset Address: F5h
Default Value:
x0h
Attribute:
Size:
R/WC, RO
8 bits
The register contains miscellaneous functions.
Bit
7
Description
SMBus Activity Bit (SPE_ACT) — RO.
1 = ASF controller is active with a SMBus transaction. This is an indicator to software
that the ASF controller is still processing commands on the SMBus.
Watchdog Status (SPE_WDG) — R/WC.
6
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a watchdog expiration occurs.
Link Loss Status (SPE_LNK) — R/WC.
5
4:0
8.3.19
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a link loss occurs (link is down for more than 5 seconds).
Reserved
INPOLL_TCONF—Inter-Poll Timer Configuration Register
(ASF Controller—B1:D8:F0)
Offset Address: F6h
Default Value:
10h
Attribute:
Size:
R/W
8 bits
This register is used to load and hold the value (in increments of 5 ms) for the polling
timer. This value determines how often the ASF polling timer expires which determines
the minimum idle time between sensor polls.
340
Bit
Description
7:0
Inter-Poll Timer Configuration (IPTC_VAL) — R/W. This field identifies the time, in
5.24 ms units that the ASF controller will wait between the end of the one ASF Poll Alert
Message to start on the next. The value 00h is invalid and unsupported.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.20
PHIST_CLR—Poll History Clear Register
(ASF Controller—B1:D8:F0)
Offset Address: F7h
Default Value:
00h
Attribute:
Size:
R/WC
8 bits
This register is used to clear the history of the Legacy Poll operations. ASF maintains
history of the last poll data for each Legacy Poll operation to compare against the
current poll to detect changes. By setting the appropriate bit, the history for that
Legacy Poll is cleared to 0s.
Bit
8.3.21
Description
7
Clear Polling Descriptor 8 History (PHC_POLL8) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #8. Writing a 0b
has no effect.
6
Clear Polling Descriptor 7 History (PHC_POLL7) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #7. Writing a 0b
has no effect.
5
Clear Polling Descriptor 6 History (PHC_POLL6) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #6. Writing a 0b
has no effect.
4
Clear Polling Descriptor 5 History (PHC_POLL5) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #5. Writing a 0b
has no effect.
3
Clear Polling Descriptor 4 History (PHC_POLL4) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #4. Writing a 0b
has no effect.
2
Clear Polling Descriptor 3 History (PHC_POLL3) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #3. Writing a 0b
has no effect.
1
Clear Polling Descriptor 2 History (PHC_POLL2) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #2. Writing a 0b
has no effect.
0
Clear Polling Descriptor 1 History (PHC_POLL1) — R/WC. Writing a 1b to this bit
position will clear the Poll History associated with Polling Descriptor #1. Writing a 0b
has no effect.
PMSK1—Polling Mask 1 Register
(ASF Controller—B1:D8:F0)
Offset Address: F8h
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #1 Data Mask.
Bit
7:0
Description
Polling Mask for Polling Descriptor #1 (POL1_MSK) — R/W. This field is used to
read and write the data mask for Polling Descriptor #1. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Intel ® ICH7 Family Datasheet
341
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.22
PMSK2—Polling Mask 2 Register
(ASF Controller—B1:D8:F0)
Offset Address: F9h
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #2 Data Mask.
Bit
7:0
8.3.23
Description
Polling Mask for Polling Descriptor #2 (POL2_MSK) — R/W. This field is used to
read and write the data mask for Polling Descriptor #2. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
PMSK3—Polling Mask 3 Register
(ASF Controller—B1:D8:F0)
Offset Address: FAh
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #3 Data Mask.
8.3.24
Bit
Description
7:0
Polling Mask for Polling Descriptor #3 (POL3_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #3. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
PMSK4—Polling Mask 4 Register
(ASF Controller—B1:D8:F0)
Offset Address: FBh
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #4 Data Mask.
342
Bit
Description
7:0
Polling Mask for Polling Descriptor #4 (POL4_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #4. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Intel ® ICH7 Family Datasheet
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.25
PMSK5—Polling Mask 5 Register
(ASF Controller—B1:D8:F0)
Offset Address: FCh
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #5 Data Mask.
8.3.26
Bit
Description
7:0
Polling Mask for Polling Descriptor #5 (POL5_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #5. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
PMSK6—Polling Mask 6 Register
(ASF Controller—B1:D8:F0)
Offset Address: FDh
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #6 Data Mask.
8.3.27
Bit
Description
7:0
Polling Mask for Polling Descriptor #6 (POL6_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #6. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
PMSK7—Polling Mask 7 Register
(ASF Controller—B1:D8:F0)
Offset Address: FEh
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #7 Data Mask.
Bit
Description
7:0
Polling Mask for Polling Descriptor #7 (POL7_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #7. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
Intel ® ICH7 Family Datasheet
343
LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.28
PMSK8—Polling Mask 8 Register
(ASF Controller—B1:D8:F0)
Offset Address: FFh
Default Value:
XXh
Attribute:
Size:
R/W
8 bits
This register provides software an interface for the Polling #8 Data Mask.
Bit
Description
7:0
Polling Mask for Polling Descriptor #8 (POL8_MSK) — R/W. This register is used
to read and write the data mask for Polling Descriptor #8. Software should only access
this register when the ASF controller is GLOBAL DISABLED.
§
344
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
9
PCI-to-PCI Bridge Registers
(D30:F0)
The ICH7 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements
the buffering and control logic between PCI and the backbone. The arbitration for the
PCI bus is handled by this PCI device.
9.1
PCI Configuration Registers (D30:F0)
Note:
Address locations that are not shown should be treated as Reserved (see Section 6.2
for details).
.
Table 9-1.
PCI Bridge Register Address Map (PCI-PCI—D30:F0)
Offset
00h–01h
Mnemonic
VID
Register Name
Default
Type
Vendor Identification
8086h
RO
See
register
description
RO
02h–03h
DID
Device Identification
04h–05h
PCICMD
PCI Command
0000h
R/W, RO
06h–07h
PSTS
PCI Status
0010h
R/WC, RO
Revision Identification
See
register
description
RO
00060401h
RO
00h
RO
08h
RID
09h-0Bh
CC
Class Code
0Dh
PMLT
Primary Master Latency Timer
0Eh
HEADTYP
Header Type
81h
RO
18h-1Ah
BNUM
Bus Number
000000h
R/W, RO
1Bh
SMLT
Secondary Master Latency Timer
1Ch-1Dh
IOBASE_LIMIT
I/O Base and Limit
1Eh–1Fh
SECSTS
Secondary Status
20h–23h
MEMBASE_LIMIT
Memory Base and Limit
24h–27h
PREF_MEM_BASE
_LIMIT
Prefetchable Memory Base and Limit
00010001h
R/W, RO
28h–2Bh
PMBU32
Prefetchable Memory Upper 32 Bits
00000000h
R/W
2Ch–2Fh
PMLU32
Prefetchable Memory Limit Upper 32
Bits
00000000h
R/W
34h
CAPP
Capability List Pointer
50h
RO
3Ch-3Dh
INTR
Interrupt Information
0000h
R/W, RO
3Eh–3Fh
BCTRL
Bridge Control
0000h
R/WC, RO
R/W, RO
00h
R/W, RO
0000h
R/W, RO
0280h
R/WC, RO
00000000h
R/W, RO
40h–41h
SPDH
Secondary PCI Device Hiding
00h
44h-47h
DTC
Delayed Transaction Control
00000000h
R/W, RO
48h-4Bh
BPS
Bridge Proprietary Status
00000000h
R/WC, RO
4Ch-4Fh
BPC
Bridge Policy Configuration
00001200h
R/W RO
50–51h
SVCAP
Subsystem Vendor Capability Pointer
54h-57h
SVID
Subsystem Vendor IDs
Intel ® ICH7 Family Datasheet
000Dh
RO
00000000
R/WO
345
PCI-to-PCI Bridge Registers (D30:F0)
9.1.1
VID— Vendor Identification Register (PCI-PCI—D30:F0)
Offset Address: 00h–01h
Default Value:
8086h
Bit
15:0
9.1.2
Attribute:
Size:
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
DID— Device Identification Register (PCI-PCI—D30:F0)
Offset Address: 02h–03h
Default Value:
See bit description
9.1.3
RO
16 bits
Attribute:
Size:
RO
16 bits
Bit
Description
15:0
Device ID — RO.This is a 16-bit value assigned to the PCI bridge. Refer to the Intel®
I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device
ID Register.
PCICMD—PCI Command (PCI-PCI—D30:F0)
Offset Address: 04h–05h
Default Value:
0000h
Bit
15:11
Attribute:
Size:
R/W, RO
16 bits
Description
Reserved
10
Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to
disable
9
Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
SERR# Enable (SERR_EN) — R/W.
8
7
0 = Disable.
1 = Enable the Intel® ICH7 to generate an NMI (or SMI# if NMI routed to SMI#) when
the D30:F0 SSE bit (offset 06h, bit 14) is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
Parity Error Response (PER) — R/W.
6
346
0 = The ICH7 ignores parity errors on the PCI bridge.
1 = The ICH7 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are
detected on the PCI bridge.
5
VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a.
4
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI
Express* Base Specification, Revision 1.0a
3
Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Bus Master Enable (BME) — R/W.
2
1
0
9.1.4
0 = Disable
1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.
Memory Space Enable (MSE) — R/W. Controls the response as a target for memory
cycles targeting PCI.
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles
targeting PCI.
0 = Disable
1 = Enable
PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06h–07h
Default Value:
0010h
Note:
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15
0 = Parity error Not detected.
1 = Indicates that the Intel® ICH7 detected a parity error on the internal backbone.
This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set.
Intel ® ICH7 Family Datasheet
347
PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Signaled System Error (SSE) — R/WC. Several internal and external sources of the
bridge can cause SERR#. The first class of errors is parity errors related to the
backbone. The PCI bridge captures generic data parity errors (errors it finds on the
backbone) as well as errors returned on backbone cycles where the bridge was the
master. If either of these two conditions is met, and the primary side of the bridge is
enabled for parity error response, SERR# will be captured as shown below.
As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge
captures generic data parity errors (errors it finds on PCI) as well as errors returned on
PCI cycles where the bridge was the master. If either of these two conditions is met,
and the secondary side of the bridge is enabled for parity error response, SERR# will be
captured as shown below.
14
The final class of errors is system bus errors. There are three status bits associated with
system bus errors, each with a corresponding enable. The diagram capturing this is
shown below.
After checking for the three above classes of errors, an SERR# is generated, and
PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown
below.
Received Master Abort (RMA) — R/WC.
13
0 = No master abort received.
1 = Set when the bridge receives a master abort status from the backbone.
Received Target Abort (RTA) — R/WC.
12
348
0 = No target abort received.
1 = Set when the bridge receives a target abort status from the backbone.
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Signaled Target Abort (STA) — R/WC.
11
10:9
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the
backbone.
Reserved.
Data Parity Error Detected (DPD) — R/WC.
8
7:5
Reserved.
4
Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.
3
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate
interrupts.
2:0
9.1.5
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a
previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit
6).
Reserved
RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h
Default Value:
See bit description
Bit
7:0
9.1.6
Attribute:
Size:
RO
8 bits
Description
®
Revision ID — RO. Refer to the Intel I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h-0Bh
Default Value:
060401h
Bit
23:16
15:8
7:0
Attribute:
Size:
RO
24 bits
Description
Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI
bridge.
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractive
decode
Intel ® ICH7 Family Datasheet
349
PCI-to-PCI Bridge Registers (D30:F0)
9.1.7
PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh
Default Value:
00h
Attribute:
Size:
Bit
9.1.8
RO
8 bits
Description
7:3
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base
Specification, Revision 1.0a.
2:0
Reserved
HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh
Default Value:
81h
Attribute:
Size:
Bit
RO
8 bits
Description
Multi-Function Device (MFD) — RO. The value reported here depends upon the state
of the AC ‘97 function hide (FD) register (Chipset Config Registers:Offset 3418h), per
the following table:
7
6:0
9.1.9
FD.AAD
FD.AMD
MFD
0
0
1
0
1
1
1
0
1
1
1
0
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge in this case.
BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18h-1Ah
Default Value:
000000h
Bit
23:16
15:8
7:0
350
Attribute:
Size:
R/W, RO
24 bits
Description
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number
below the bridge.
Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.
Primary Bus Number (PBN) — RO. Hardwired to 00h for legacy software compatibility.
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
9.1.10
SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 1Bh
Default Value:
00h
Attribute:
Size:
R/W, RO
8 bits
This timer controls the amount of time the ICH7 PCI-to-PCI bridge will burst data on its
secondary interface. The counter starts counting down from the assertion of FRAME#.
If the grant is removed, then the expiration of this counter will result in the deassertion of FRAME#. If the grant has not been removed, then the ICH7 PCI-to-PCI
bridge may continue ownership of the bus.
9.1.11
Bit
Description
7:3
Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of
PCI clocks, in 8-clock increments, that the Intel® ICH7 remains as master of the bus.
2:0
Reserved
IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 1Ch-1Dh
Default Value:
0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:12
I/O Limit Address Limit bits[15:12] — R/W. I/O Base bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8
II/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support
32-bit I/O addressing.
7:4
I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12
for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0
I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not support
32-bit I/O addressing.
Intel ® ICH7 Family Datasheet
351
PCI-to-PCI Bridge Registers (D30:F0)
9.1.12
SECSTS—Secondary Status Register (PCI-PCI—D30:F0)
Offset Address: 1Eh–1Fh
Default Value:
0280h
Note:
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15
0 = Parity error not detected.
1 = Intel® ICH7 PCI bridge detected an address or data parity error on the PCI bus
14
0 = SERR# assertion not received
1 = SERR# assertion is received on PCI.
Received System Error (RSE) — R/WC.
Received Master Abort (RMA) — R/WC.
13
0 = No master abort.
1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the
cycle is master-aborted. For (G)MCH/ICH7 interface packets that have completion
required, this must also cause a target abort to be returned and sets PSTS.STA.
(D30:F0:06 bit 11)
Received Target Abort (RTA) — R/WC.
12
0 = No target abort.
1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is
target-aborted on PCI. For (G)MCH/ICH7 interface packets that have completion
required, this event must also cause a target abort to be returned, and sets
PSTS.STA. (D30:F0:06 bit 11).
Signaled Target Abort (STA) — R/WC.
11
10:9
0 = No target abort.
1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a
target abort.
DEVSEL# Timing (DEVT) — RO.
01h = Medium decode timing.
Data Parity Error Detected (DPD) — R/WC.
8
•
•
•
The bridge is the initiator on PCI.
PERR# is detected asserted or a parity error is detected internally
BCTRL.PERE (D30:F0:3E bit 0) is set.
7
Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI
target logic is capable of receiving fast back-to-back cycles.
6
Reserved
5
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable
only.
4:0
352
0 = Conditions described below not met.
1 = The ICH7 sets this bit when all of the following three conditions are met:
Reserved
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
9.1.13
MEMBASE_LIMIT—Memory Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 20h–23h
Default Value:
00000000h
Attribute:
Size:
R/W, RO
32 bits
This register defines the base and limit, aligned to a 1-MB boundary, of the nonprefetchable memory area of the bridge. Accesses that are within the ranges specified
in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside
the ranges specified will be accepted by the bridge if CMD.BME is set.
Bit
31-20
Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the upper 1-MB aligned value (exclusive) of the range. The
incoming address must be less than this value.
19-16
Reserved
15:4
3:0
9.1.14
Description
Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the lower 1-MB aligned value (inclusive) of the range. The
incoming address must be greater than or equal to this value.
Reserved
PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0)
Offset Address: 24h–27h
Default Value:
00010001h
Attribute:
Size:
R/W, RO
32-bit
Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory
area of the bridge. Accesses that are within the ranges specified in this register will be
sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified
will be accepted by the bridge if CMD.BME is set.
Bit
Description
31-20
Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the upper 1-MB aligned value (exclusive) of the
range. The incoming address must be less than this value.
19-16
15:4
3:0
64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing.
Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the lower 1-MB aligned value (inclusive) of the
range. The incoming address must be greater than or equal to this value.
64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing.
Intel ® ICH7 Family Datasheet
353
PCI-to-PCI Bridge Registers (D30:F0)
9.1.15
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28h–2Bh
Default Value:
00000000h
Bit
31:0
9.1.16
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Bit
31:0
R/W
32 bits
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Bit
7:0
Attribute:
Size:
RO
8 bits
Description
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3Ch–3Dh
Default Value:
0000h
Bit
15:8
7:0
354
Attribute:
Size:
Description
Offset Address: 34h
Default Value:
50h
9.1.18
R/W
32 bits
Description
Offset Address: 2C–2Fh
Default Value:
00000000h
9.1.17
Attribute:
Size:
Attribute:
Size:
R/W, RO
16 bits
Description
Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Since the bridge does not generate an interrupt, BIOS should program this value to FFh
as per the PCI bridge specification.
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
9.1.19
BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
Offset Address: 3Eh–3Fh
Default Value:
0000h
Bit
15:12
11
10
9
Attribute:
Size:
R/WC, RO
16 bits
Description
Reserved
Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on
the primary interface in response to the DTS bit being set:
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard
timer (see the SDT bit below) expires for a delayed transaction in the hard state.
Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI
clock cycles that the Intel® ICH7 waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed transaction data is has been
returned by the system and is in a buffer in the ICH7 PCI bridge. If the master has not
repeated the transaction at least once before the counter expires, the ICH7 PCI bridge
discards the transaction from its queue.
0 = The PCI master timeout value is between 215 and 216 PCI clocks
1 = The PCI master timeout value is between 210 and 211 PCI clocks
8
Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.
7
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate
fast back-to-back cycles on the PCI bus.
Secondary Bus Reset (SBR) — R/W. This bit controls PCIRST# assertion on PCI.
6
0 = Bridge de-asserts PCIRST#
1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction
buffers, posting buffers, and the PCI bus are initialized back to reset conditions.
The rest of the part and the configuration registers are not affected.
Master Abort Mode (MAM) — R/W. This bit controls the ICH7 PCI bridge’s behavior
when a master abort occurs:
Master Abort on (G)MCH/ICH7 Interconnect (DMI):
0 = Bridge asserts TRDY# on PCI. It drives all 1’s for reads, and discards data on
writes.
1 = Bridge returns a target abort on PCI.
5
Master Abort PCI (non-locked cycles):
0 = Normal completion status will be returned on the (G)MCH/ICH7 interconnect.
1 = Target abort completion status will be returned on the (G)MCH/ICH7 interconnect.
NOTE: All locked reads will return a completer abort completion status on the (G)MCH/
ICH7 interconnect.
4
VGA 16-Bit Decode (V16D) — R/W. This bit controls enables the ICH7 PCI bridge to
provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias
addresses every 1 KB. This bit requires the VGAE bit in this register be set.
Intel ® ICH7 Family Datasheet
355
PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
VGA Enable (VGAE) — R/W. When set to a 1, the ICH7 PCI bridge forwards the
following transactions to PCI regardless of the value of the I/O base and limit registers.
The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE
(D30:F0:04 bit 0) being set.
3
•
•
Memory addresses: 000A0000h-000BFFFFh
I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address
must be 0, and bits [15:10] of the address are ignored (i.e., aliased).
The same holds true from secondary accesses to the primary interface in reverse. That
is, when the bit is 0, memory and I/O addresses on the secondary interface between
the above ranges will be claimed.
2
1
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is
set, the ICH7 PCI bridge will block any forwarding from primary to secondary of I/O
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).
SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface
SERR# assertions on the primary interface. When set, the PCI bridge will forward
SERR# pin.
•
•
•
SERR# is asserted on the secondary interface.
This bit is set.
CMD.SEE (D30:F0:04 bit 8) is set.
Parity Error Response Enable (PERE) — R/W.
0
9.1.20
0 = Disable
1 = The ICH7 PCI bridge is enabled for parity error reporting based on parity errors on
the PCI bus.
SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)
Offset Address: 40h–41h
Default Value:
00h
Attribute:
Size:
R/W, RO
16 bits
This register allows software to hide the PCI devices, either plugged into slots or on the
motherboard.
Bit
15:8
356
Description
Reserved
7
Hide Device 7 (HD7) — R/W, RO. Same as bit 0 of this register, except for device 7
(AD[23])
6
Hide Device 6 (HD6) — R/W, RO. Same as bit 0 of this register, except for device 6
(AD[22])
5
Hide Device 5 (HD5) — R/W, RO. Same as bit 0 of this register, except for device 5
(AD[21])
4
Hide Device 4 (HD4) — R/W, RO. Same as bit 0 of this register, except for device 4
(AD[20])
3
Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3
(AD[19])
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
2
Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2
(AD[18])
1
Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1
(AD[17])
Hide Device 0 (HD0) — R/W, RO.
0
9.1.21
0 = The PCI configuration cycles for this slot are not affected.
1 = Intel® ICH7 hides device 0 on the PCI bus. This is done by masking the IDSEL
(keeping it low) for configuration cycles to that device. Since the device will not see
its IDSEL go active, it will not respond to PCI configuration cycles and the
processor will think the device is not present. AD[16] is used as IDSEL for device 0.
DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)
Offset Address: 44h–47h
Default Value:
00000000h
Bit
Attribute:
Size:
R/W, RO
32 bits
Description
Discard Delayed Transactions (DDT) — R/W.
31
0 = Logged delayed transactions are kept.
1 = The Intel® ICH7 PCI bridge will discard any delayed transactions it has logged. This
includes transactions in the pending queue, and any transactions in the active
queue, whether in the hard or soft DT state. The prefetchers will be disabled and
return to an idle state.
NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will
continue until either the PCI master disconnects (by de-asserting FRAME#) or
the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI
bridge when the delayed transaction queues are empty and have returned to an
idle state. Software sets this bit and polls for its completion
Block Delayed Transactions (BDT) — R/W.
30
29: 8
0 = Delayed transactions accepted
1 = The ICH7 PCI bridge will not accept incoming transactions which will result in
delayed transactions. It will blindly retry these cycles by asserting STOP#. All
postable cycles (memory writes) will still be accepted.
Reserved
Maximum Delayed Transactions (MDT) — R/W. This field controls the maximum
number of delayed transactions that the ICH7 PCI bridge will run. Encodings are:
7: 6
00 =) 2 Active, 5 pending
01 =) 2 active, no pending
10 =) 1 active, no pending
11 =) Reserved
5
Reserved
Auto Flush After Disconnect Enable (AFADE) — R/W.
4
0 = The PCI bridge will retain any fetched data until required to discard by producer/
consumer rules.
1 = The PCI bridge will flush any prefetched data after either the PCI master (by deasserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI
transfer.
Intel ® ICH7 Family Datasheet
357
PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Never Prefetch (NP) — R/W.
3
0 = Prefetch enabled
1 = The ICH7 will only fetch a single DW and will not enable prefetching, regardless of
the command being an Memory read (MR), Memory read line (MRL), or Memory
read multiple (MRM).
Memory Read Multiple Prefetch Disable (MRMPD) — R/W.
2
0 = MRM commands will fetch multiple cache lines as defined by the prefetch
algorithm.
1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte
aligned cache line.
Memory Read Line Prefetch Disable (MRLPD) — R/W.
1
0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.
1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned
cache line.
Memory Read Prefetch Disable (MRPD) — R/W.
0
358
0 = MR commands will fetch up to a 64-byte aligned cache line.
1 = Memory read (MR) commands will fetch only a single DW.
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
9.1.22
BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0)
Offset Address: 48h–4Bh
Default Value:
00000000h
Bit
31:17
16
Attribute:
Size:
R/WC, RO
32 bits
Description
Reserved
PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the
PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the
chipset is the agent driving PERR#. It remains asserted until cleared by software
writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the
Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and
be a source for the NMI logic.
This bit can be used by software to determine the source of a system problem.
15:7
Reserved
Number of Pending Transactions (NPT) — RO. This field indicates to debug
software how many transactions are in the pending queue. Possible values are:
000 = No pending transaction
001 = 1 pending transaction
010 = 2 pending transactions
6:4
011 = 3 pending transactions
100 = 4 pending transactions
101 = 5 pending transactions
110 - 111 = Reserved
NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than
‘00’.
3:2
Reserved
Number of Active Transactions (NAT) — RO. This field indicates to debug software
how many transactions are in the active queue. Possible values are:
1:0
00 = No active transactions
01 = 1 active transaction
10 = 2 active transactions
11 = Reserved
Intel ® ICH7 Family Datasheet
359
PCI-to-PCI Bridge Registers (D30:F0)
9.1.23
BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0)
Offset Address: 4Ch–4Fh
Default Value:
00001200h
Bit
31:14
13:8
Attribute:
Size:
R/W, RO
32 bits
Description
Reserved
Upstream Read Latency Threshold (URLT) — R/W: This field specifies the number
of PCI clocks after internally enqueuing an upstream memory read request at which
point the PCI target logic should insert wait states in order to optimize lead-off latency.
When the master returns after this threshold has been reached and data has not
arrived in the Delayed Transaction completion queue, then the PCI target logic will
insert wait states instead of immediately retrying the cycle. The PCI target logic will
insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or
STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived
yet).
Note that the starting event for this Read Latency Timer is not explicitly visible
externally.
A value of 0h disables this policy completely such that wait states will not be inserted
on the read lead-off data phase.
The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks
less than the typical idle lead-off latency expected for desktop Intel® ICH7 systems.
This value may need to be changed by BIOS, depending on the platform.
Subtractive Decode Policy (SDP) — R/W.
7
6
0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any
other device on the backbone (primary interface) to the PCI bus (secondary
interface).
1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the
corresponding Space Enable bit is set in the Command register.
NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.
PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR#
Assertion status bit (in the Bridge Proprietary Status register) will result in an internal
SERR# assertion on the primary side of the bridge (if also enabled by the SERR#
Enable bit in the primary Command register). SERR# is a source of NMI.
Secondary Discard Timer Testmode (SDTT) — R/W.
5
4:3
0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E,
bit 9)
1 = The secondary discard timer will expire after 128 PCI clocks.
Reserved
Peer Decode Enable (PDE) — R/W.
2
360
0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O
cycles are not claimed.
1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that
falls outside of the memory and I/O window registers
1
Reserved
0
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will
report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are
set, and CMD.SEE (D30:F0:04 bit 8) is set.
Intel ® ICH7 Family Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
9.1.24
SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0)
Offset Address: 50h–51h
Default Value:
000Dh
Attribute:
Size:
Bit
15:8
7:0
9.1.25
RO
16 bits
Description
Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem
vendor capability.
SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)
Offset Address: 54h–57h
Default Value:
00000000h
Attribute:
Size:
R/WO
32 bits
Bit
Description
31:16
Subsystem Identifier (SID) — R/WO. This field indicates the subsystem as identified
by the vendor. This field is write once and is locked down until a bridge reset occurs
(not the PCI bus reset).
15:0
Subsystem Vendor Identifier (SVID) — R/WO. This field indicates the manufacturer
of the subsystem. This field is write once and is locked down until a bridge reset occurs
(not the PCI bus reset).
§
Intel ® ICH7 Family Datasheet
361
PCI-to-PCI Bridge Registers (D30:F0)
362
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10
LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. This function
contains many other functional units, such as DMA and Interrupt controllers, Timers,
Power Management, System Management, GPIO, RTC, and LPC Configuration
Registers.
Registers and functions associated with other functional units (EHCI, UHCI, IDE, etc.)
are described in their respective sections.
10.1
PCI Configuration Registers (LPC I/F—D31:F0)
Note:
Address locations that are not shown should be treated as Reserved.
.
Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset
Mnemonic
00h–01h
VID
02h–03h
DID
04h–05h
PCICMD
PCI Command
06h–07h
PCISTS
PCI Status
08h
RID
Register Name
Default
Type
Vendor Identification
8086h
RO
Device Identification
See register
description.
RO
0007h
R/W, RO
0200h
R/WC, RO
See register
description.
RO
Revision Identification
09h
PI
Programming Interface
00h
RO
0Ah
SCC
Sub Class Code
01h
RO
0Bh
BCC
Base Class Code
06h
RO
0Dh
PLT
Primary Latency Timer
00h
RO
0Eh
HEADTYP
2Ch–2Fh
SS
34h
CAPP
40h–43h
PMBASE
Header Type
Sub System Identifiers
Capability List Pointer
ACPI Base Address
44h
ACPI_CNTL
ACPI Control
48h–4Bh
GPIOBASE
GPIO Base Address
4C
GC
60h–63h
PIRQ[n]_ROUT
64h
SIRQ_CNTL
68h–6Bh
PIRQ[n]_ROUT
80h
LPC_I/O_DEC
82h–83h
LPC_EN
Intel ® ICH7 Family Datasheet
80h
RO
00000000h
R/WO
E0h
RO
00000001h
R/W, RO
00h
R/W
00000001h
R/W, RO
GPIO Control
00h
R/W
PIRQ[A–D] Routing Control
(Desktop and Mobile Only)
80h
R/W
Serial IRQ Control
10h
R/W, RO
PIRQ[E–H] Routing Control
80h
R/W
I/O Decode Ranges
0000h
R/W
LPC Interface Enables
0000h
R/W
363
LPC Interface Bridge Registers (D31:F0)
Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)
10.1.1
Offset
Mnemonic
84h–87h
GEN1_DEC
88h–8Bh
Register Name
Default
Type
LPC Interface Generic Decode
Range 1
00000000h
R/W
GEN2_DEC
LPC Interface Generic Decode
Range 2
00000000h
R/W
8Ch–8Eh
GEN3_DEC
LPC Interface Generic Decode
Range 3
00000000h
R/W
90h–93h
GEN4_DEC
LPC Interface Generic Decode
Range 4
00000000h
R/W
A0h–CFh
—
—
—
Power Management (See
Section 10.8.1)
D0h–D3h
FWH_SEL1
Firmware Hub Select 1
00112233h
R/W, RO
D4h–D5h
FWH_SEL2
Firmware Hub Select 2
4567h
R/W
D8h–D9h
FWH_DEC_EN1
Firmware Hub Decode Enable 1
FFCFh
R/W, RO
DCh
BIOS_CNTL
00h
R/WLO, R/W
E0h–E1h
FDCAP
Feature Detection Capability ID
0009h
RO
E2h
FDLEN
Feature Detection Capability
Length
0Ch
RO
E3h
FDVER
Feature Detection Version
10h
RO
RO
R/W
BIOS Control
E4h–EBh
FDVCT
Feature Vector
See
Description
F0h–F3h
RCBA
Root Complex Base Address
00000000h
VID—Vendor Identification Register (LPC I/F—D31:F0)
Offset Address: 00h–01h
Default Value:
8086h
Lockable:
No
Bit
15:0
10.1.2
RO
16-bit
Core
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
DID—Device Identification Register (LPC I/F—D31:F0)
Offset Address: 02h–03h
Default Value:
See bit description
Lockable:
No
364
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
RO
16-bit
Core
Bit
Description
15:0
Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 LPC bridge. Refer
to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update for the value of
the Device ID Register.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.3
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h–05h
Default Value:
0007h
Lockable:
No
Bit
15:10
Attribute:
Size:
Power Well:
R/W, RO
16-bit
Core
Description
Reserved
9
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8
SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
7
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
6
10.1.4
0 = No action is taken when detecting a parity error.
1 = Enables the Intel® ICH7 LPC bridge to respond to parity errors detected on
backbone interface.
5
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
3
Special Cycle Enable (SCE) — RO. Hardwired to 0.
2
Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
1
Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
0
I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06–07h
Default Value:
0210h
Lockable:
Noh
Note:
Attribute:
Size:
Power Well:
RO, R/WC
16-bit
Core
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
15
Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity
error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is
0.
0 = Parity Error Not detected.
1 = Parity Error detected.
14
Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system
error to the internal SERR# logic.
Master Abort Status (RMA) — R/WC.
13
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the
backbone.
Received Target Abort (RTA) — R/WC.
12
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
Intel ® ICH7 Family Datasheet
365
LPC Interface Bridge Registers (D31:F0)
Bit
Description
Signaled Target Abort (STA) — R/WC.
11
10:9
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the
backbone.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
8
•
•
•
LPC bridge receives a completion packet from the backbone from a previous request,
Parity error has been detected (D31:F0:06, bit 15)
PCICMD.PERE bit (D31:F0:04, bit 6) is set.
7
Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal
backbone.
6
Reserved.
5
66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal
backbone.
4
Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.
3
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
2:0
10.1.5
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
Reserved.
RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h
Default Value:
See bit description
Bit
7:0
10.1.6
RO
8 bits
Description
Revision ID (RID) — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family
Specification Update for the value of the Revision ID Register.
PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h
Default Value:
00h
Bit
7:0
366
Attribute:
Size:
Attribute:
Size:
RO
8 bits
Description
Programming Interface — RO.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.7
SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah
Default Value:
01h
Bit
7:0
Attribute:
Size:
RO
8 bits
Description
Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC
bridge.
01h = PCI-to-ISA bridge.
10.1.8
BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh
Default Value:
06h
Bit
7:0
Attribute:
Size:
RO
8 bits
Description
Base Class Code — RO. 8-bit value that indicates the type of device for the LPC
bridge.
06h = Bridge device.
10.1.9
PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh
Default Value:
00h
Bit
10.1.10
Attribute:
Size:
RO
8 bits
Description
7:3
Master Latency Count (MLC) — Reserved.
2:0
Reserved.
HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh
Default Value:
80h
Bit
7
6:0
Attribute:
Size:
RO
8 bits
Description
Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration
space.
Intel ® ICH7 Family Datasheet
367
LPC Interface Bridge Registers (D31:F0)
10.1.11
SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch–2Fh
Default Value:
00000000h
Attribute:
Size:
R/WO
32 bits
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
10.1.12
Bit
Description
31:16
Subsystem ID (SSID) — R/WO This is written by BIOS. No hardware action taken on
this value.
15:0
Subsystem Vendor ID (SSVID) — R/WO This is written by BIOS. No hardware action
taken on this value.
CAPP—Capability List Pointer (LPC I/F—D31:F0)
Offset Address: 34h
Default Value:
E0h
Bit
7:0
10.1.13
Attribute:
Size:
Power Well:
RO
8 bits
Core
Description
Capability Pointer (CP) — RO. Indicates the offset of the first item.
PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h–43h
Default Value:
00000001h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO
32 bit
ACPI, Legacy
Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
Bit
31:16
15:7
6:1
0
368
Description
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
TCO logic. This is placed on a 128-byte boundary.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.14
ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h
Default Value:
00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
Bit
R/W
8 bit
ACPI, Legacy
Core
Description
ACPI Enable (ACPI_EN) — R/W.
7
6:3
0 = Disable.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the
ACPI power management function is enabled. Note that the APM power
management ranges (B2/B3h) are always enabled and are not affected by this bit.
Reserved
SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI
must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream,
but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ20–23, and can be shared with other interrupts.
2:0
Bits
SCI Map
000b
IRQ9
001b
IRQ10
010b
IRQ11
011b
Reserved
100b
IRQ20 (Only available if APIC enabled)
101b
IRQ21 (Only available if APIC enabled)
110b
IRQ22 (Only available if APIC enabled)
111b
IRQ23 (Only available if APIC enabled)
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be
programmed for active-high reception. When the interrupt is mapped to APIC
interrupts 20 through 23, the APIC should be programmed for active-low
10.1.15
GPIOBASE—GPIO Base Address Register (LPC I/F —
D31:F0)
Offset Address: 48h–4Bh
Default Value:
00000001h
Bit
31:16
15:6
5:1
0
Attribute:
Size:
R/W, RO
32 bit
Description
Reserved. Always 0.
Base Address (BA) — R/W. Provides the 64 bytes of I/O space for GPIO.
Reserved. Always 0.
RO. Hardwired to 1 to indicate I/O space.
Intel ® ICH7 Family Datasheet
369
LPC Interface Bridge Registers (D31:F0)
10.1.16
GC—GPIO Control Register (LPC I/F — D31:F0)
Offset Address: 4Ch
Default Value:
00h
Attribute:
Size:
Bit
7:5
4
3:0
10.1.17
R/W
8 bit
Description
Reserved.
GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed
to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.
0 = Disable.
1 = Enable.
Reserved.
PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0) (Desktop and Mobile Only)
Offset Address: PIRQA – 60h, PIRQB – 61h,
PIRQC – 62h, PIRQD – 63h
Default Value:
80h
Lockable:
No
Bit
Attribute:
R/W
Size:
8 bit
Power Well: Core
Description
Interrupt Routing Enable (IRQEN) — R/W.
7
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts
specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS
when setting up for I/O APIC interrupt delivery mode.
6:4
Reserved
IRQ Routing — R/W. (ISA compatible.)
3:0
370
Value
IRQ
Value
0000b
Reserved
1000b
Reserved
IRQ
0001b
Reserved
1001b
IRQ9
0010b
Reserved
1010b
IRQ10
0011b
IRQ3
1011b
IRQ11
0100b
IRQ4
1100b
IRQ12
0101b
IRQ5
1101b
Reserved
0110b
IRQ6
1110b
IRQ14
0111b
IRQ7
1111b
IRQ15
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.18
SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0)
Offset Address: 64h
Default Value:
10h
Lockable:
No
Bit
Attribute:
Size:
Power Well:
R/W, RO
8 bit
Core
Description
Serial IRQ Enable (SIRQEN) — R/W.
7
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
6
5:2
1:0
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for
at least one frame after coming out of reset before switching back to Quiet
Mode. Failure to do so will result in the Intel® ICH7 not recognizing SERIRQ
interrupts.
Serial IRQ Frame Size (SIRQSZ) — RO. Fixed field that indicates the size of the
SERIRQ frame as 21 frames.
Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the
SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In
continuous mode, the ICH7 will drive the start frame for the number of clocks specified.
In quiet mode, the ICH7 will drive the start frame for the number of clocks specified
minus one, as the first clock was driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
Intel ® ICH7 Family Datasheet
371
LPC Interface Bridge Registers (D31:F0)
10.1.19
PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute:
PIRQG – 6Ah, PIRQH – 6Bh
Default Value:
80h
Size:
Lockable:
No
Power Well:
Bit
R/W
8 bit
Core
Description
Interrupt Routing Enable (IRQEN) — R/W.
7
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified
in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS when
setting up for I/O APIC interrupt delivery mode.
6:4
Reserved
IRQ Routing — R/W. (ISA compatible.)
3:0
372
Value
IRQ
Value
0000b
Reserved
1000b
Reserved
IRQ
0001b
Reserved
1001b
IRQ9
0010b
Reserved
1010b
IRQ10
0011b
IRQ3
1011b
IRQ11
0100b
IRQ4
1100b
IRQ12
0101b
IRQ5
1101b
Reserved
0110b
IRQ6
1110b
IRQ14
0111b
IRQ7
1111b
IRQ15
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.20
LPC_I/O_DEC—I/O Decode Ranges Register
(LPC I/F—D31:F0)
Offset Address: 80h
Default Value:
0000h
Bit
15:13
Attribute:
Size:
R/W
16 bit
Description
Reserved
FDD Decode Range — R/W. Determines which range to decode for the FDD Port
12
11:10
0 = 3F0h – 3F5h, 3F7h (Primary)
1 = 370h – 375h, 377h (Secondary)
Reserved
LPT Decode Range — R/W. This field determines which range to decode for the LPT
Port.
9:8
7
00
01
10
11
=
=
=
=
378h – 37Fh and 778h – 77Fh
278h – 27Fh (port 279h is read only) and 678h – 67Fh
3BCh –3BEh and 7BCh – 7BEh
Reserved
Reserved
COMB Decode Range — R/W. This field determines which range to decode for the
COMB Port.
000 = 3F8h – 3FFh (COM1)
001 = 2F8h – 2FFh (COM2)
6:4
010 = 220h – 227h
011 = 228h – 22Fh
100 = 238h – 23Fh
101 = 2E8h – 2EFh (COM4)
110 = 338h – 33Fh
111 = 3E8h – 3EFh (COM3)
3
Reserved
COMA Decode Range — R/W. This field determines which range to decode for the
COMA Port.
000 = 3F8h – 3FFh (COM1)
001 = 2F8h – 2FFh (COM2)
2:0
010 = 220h – 227h
011 = 228h – 22Fh
100 = 238h – 23Fh
101 = 2E8h – 2EFh (COM4)
110 = 338h – 33Fh
111 = 3E8h – 3EFh (COM3)
Intel ® ICH7 Family Datasheet
373
LPC Interface Bridge Registers (D31:F0)
10.1.21
LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address: 82h – 83h
Default Value:
0000h
Bit
15:14
Attribute:
Size:
Power Well:
R/W
16 bit
Core
Description
Reserved
CNF2_LPC_EN — R/W. Microcontroller Enable # 2.
13
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This
range is used for a microcontroller.
CNF1_LPC_EN — R/W. Super I/O Enable.
12
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This
range is used for Super I/O devices.
MC_LPC_EN — R/W. Microcontroller Enable # 1.
11
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This
range is used for a microcontroller.
KBC_LPC_EN — R/W. Keyboard Enable.
10
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This
range is used for a microcontroller.
GAMEH_LPC_EN — R/W. High Gameport Enable
9
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This
range is used for a gameport.
GAMEL_LPC_EN — R/W. Low Gameport Enable
8
7:4
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This
range is used for a gameport.
Reserved
FDD_LPC_EN — R/W. Floppy Drive Enable
3
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected
in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).
LPT_LPC_EN — R/W. Parallel Port Enable
2
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in
the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).
COMB_LPC_EN — R/W. Com Port B Enable
1
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).
COMA_LPC_EN — R/W. Com Port A Enable
0
374
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.22
GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h – 87h
Default Value:
00000000h
Bit
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Description
31:24
Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16
Reserved
15:2
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is
aligned on a 128-byte boundary, and must have address lines 31:16 as 0.
NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.
1
Reserved
0
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
10.1.23
GEN2_DEC—LPC I/F Generic Decode Range 2Register
(LPC I/F—D31:F0)
Offset Address: 88h – 8Bh
Default Value:
00000000h
Bit
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Description
31:24
Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16
Reserved
Generic I/O Decode Range 2Base Address (GEN1_BASE) — R/W.
15:2
1
NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.
Reserved
Generic Decode Range 2Enable (GEN2_EN) — R/W.
0
0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
Intel ® ICH7 Family Datasheet
375
LPC Interface Bridge Registers (D31:F0)
10.1.24
GEN3_DEC—LPC I/F Generic Decode Range 3Register
(LPC I/F—D31:F0)
Offset Address: 8Ch – 8Eh
Default Value:
00000000h
Bit
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Description
31:24
Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16
Reserved
Generic I/O Decode Range 3Base Address (GEN3_BASE) — R/W.
15:2
1
NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.
Reserved
Generic Decode Range 3Enable (GEN3_EN) — R/W.
0
10.1.25
0 = Disable.
1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F
GEN4_DEC—LPC I/F Generic Decode Range 4Register
(LPC I/F—D31:F0)
Offset Address: 90h – 93h
Default Value:
00000000h
Bit
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Description
31:24
Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16
Reserved
Generic I/O Decode Range 4Base Address (GEN4_BASE) — R/W.
15:2
1
NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.
Reserved
Generic Decode Range 4Enable (GEN4_EN) — R/W.
0
376
0 = Disable.
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.26
FWH_SEL1—Firmware Hub Select 1 Register
(LPC I/F—D31:F0)
Offset Address: D0h–D3h
Default Value:
00112233h
Bit
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Attribute:
Size:
R/W, RO
32 bits
Description
FWH_F8_IDSEL — RO. IDSEL for two 512-KB Firmware Hub memory ranges and one
128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field
addresses the following memory ranges:
FFF8 0000h – FFFF FFFFh
FFB8 0000h – FFBF FFFFh
000E 0000h – 000F FFFFh
FWH_F0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFF0 0000h – FFF7 FFFFh
FFB0 0000h – FFB7 FFFFh
FWH_E8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFE8 0000h – FFEF FFFFh
FFA8 0000h – FFAF FFFFh
FWH_E0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFE0 0000h – FFE7 FFFFh
FFA0 0000h – FFA7 FFFFh
FWH_D8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFD8 0000h – FFDF FFFFh
FF98 0000h – FF9F FFFFh
FWH_D0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFD0 0000h – FFD7 FFFFh
FF90 0000h – FF97 FFFFh
FWH_C8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFC8 0000h – FFCF FFFFh
FF88 0000h – FF8F FFFFh
FWH_C0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The
IDSEL programmed in this field addresses the following memory ranges:
FFC0 0000h – FFC7 FFFFh
FF80 0000h – FF87 FFFFh
Intel ® ICH7 Family Datasheet
377
LPC Interface Bridge Registers (D31:F0)
10.1.27
FWH_SEL2—Firmware Hub Select 2 Register
(LPC I/F—D31:F0)
Offset Address: D4h–D5h
Default Value:
4567h
Bit
15:12
11:8
7:4
3:0
10.1.28
Attribute:
Size:
R/W
16 bits
Description
FWH_70_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
FWH_60_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FWH_50_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FWH_40_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
FWH_DEC_EN1—Firmware Hub Decode Enable Register
(LPC I/F—D31:F0)
Offset Address: D8h–D9h
Default Value:
FFCFh
Bit
Attribute:
Size:
R/W, RO
16 bits
Description
FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory
ranges, and one
128-KB memory range.
15
0 = Disable
1 = Enable the following ranges for the Firmware Hub
FFF80000h – FFFFFFFFh
FFB80000h – FFBFFFFFh
FWH_F0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
14
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFF00000h – FFF7FFFFh
FFB00000h – FFB7FFFFh
FWH_E8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
13
378
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFE80000h – FFEFFFFh
FFA80000h – FFAFFFFFh
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
Description
FWH_E0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
12
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
FFE00000h – FFE7FFFFh
FFA00000h – FFA7FFFFh
FWH_D8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
11
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFD80000h – FFDFFFFFh
FF980000h – FF9FFFFFh
FWH_D0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
10
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFD00000h – FFD7FFFFh
FF900000h – FF97FFFFh
FWH_C8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
9
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFC80000h – FFCFFFFFh
FF880000h – FF8FFFFFh
FWH_C0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
8
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFC00000h – FFC7FFFFh
FF800000h – FF87FFFFh
FWH_Legacy_F_EN — R/W. This enables the decoding of the legacy 128-K range at
F0000h – FFFFFh.
7
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
F0000h – FFFFFh
FWH_Legacy_E_EN — R/W. This enables the decoding of the legacy 128-K range at
E0000h – EFFFFh.
6
5:4
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
E0000h – EFFFFh
Reserved
FWH_70_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
3
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
Intel ® ICH7 Family Datasheet
379
LPC Interface Bridge Registers (D31:F0)
Bit
Description
FWH_60_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
2
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FWH_50_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
1
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FWH_40_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0
Note:
380
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
This register effects the BIOS decode regardless of whether the BIOS is resident on LPC
or SPI (Desktop and Mobile Only). The concept of Feature Space does not apply to SPIbased flash. The ICH7simply decodes these ranges as memory accesses when enabled
for the SPI flash interface.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.29
BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address: DCh
Default Value:
00h
Lockable:
No
Attribute:
Size:
Power Well:
Bit
7:5
4
R/WLO, R/W, RO
8 bit
Core
Description
Reserved
Top Swap Status (TSS)— RO: This bit provides a read-only path to view the
state of the Top Swap bit that is at offset 3414h, bit 0.
SPI Read Configuration (SRC)— R/W: This 2-bit field controls two policies
related to BIOS reads on the SPI interface:
Bit 3- Prefetch Enable
Bit 2- Cache Disable
Settings are summarized below:
Bits 3:2
3:2
(Desktop
and Mobile
Only)
3:2
(Ultra
Mobile
Only)
Description
00b
No prefetching, but caching enabled. 64B demand reads
load the read buffer cache with “valid” data, allowing repeated
code fetches to the same line to complete quickly
01b
No prefetching and no caching. One-to-one correspondence
of host BIOS reads to SPI cycles. This value can be used to
invalidate the cache.
10b
Prefetching and Caching enabled. This mode is used for long
sequences of short reads to consecutive addresses (i.e.,
shadowing).
11b
Reserved. This is an invalid configuration, caching must be
enabled when prefetching is enabled.
Reserved
BIOS Lock Enable (BLE) — R/WLO.
1
0 = Setting the BIOSWE will not cause SMIs.
1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be
cleared by a PLTRST#
BIOS Write Enable (BIOSWE) — R/W.
0
0 = Only read cycles permitted to Firmware Hub or SPI flash.
1 = Access to the BIOS space is enabled for both read and write cycles. When this
bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI#
is generated. This ensures that only SMI code can update BIOS.
NOTE: Writes to the Firmware Hub’s Feature Space are not blocked when the
BIOSWE is cleared in order to allow access to registers. The Feature Space
is the second range that is located 4 MB below the BIOS range for each
Firmware Hub.
Intel ® ICH7 Family Datasheet
381
LPC Interface Bridge Registers (D31:F0)
10.1.30
FDCAP—Feature Detection Capability ID
(LPC I/F—D31:F0)
Offset Address: E0h-E1h
Default Value:
0009h
Bit
15:8
7:0
10.1.31
Next Item Pointer (NEXT): Configuration offset of the next Capability Item. 00h
indicates the last item in the Capability List.
Capability ID: Indicates a Vendor Specific Capability
FDLEN—Feature Detection Capability Length
(LPC I/F—D31:F0)
Attribute:
Size:
Power Well:
RO
8 bit
Core
Bit
Description
7:0
Capability Length: Indicates the length of this Vendor Specific capability, as required by
PCI Spec.
FDVER—Feature Detection Version
(LPC I/F—D31:F0)
Offset Address: E3h
Default Value:
10h
Bit
382
RO
16 bit
Core
Description
Offset Address: E2h
Default Value:
0Ch
10.1.32
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
RO
8 bit
Core
Description
7:4
Vendor-Specific Capability ID: A value of 1h in this 4-bit field identifies this Capability
as Feature Detection Type. This field allows software to differentiate the Feature
Detection Capability from other Vendor-Specific capabilities
3:0
Capability Version: This field indicates the version of the Feature Detection capability
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.1.33
FDVCT—Feature Vector Register (LPC I/F—D31:F0)
Offset Address: E4h–EBh
Default Value:
See Description
Bit
63:33
32
(Desktop
and Mobile
Only)
Attribute:
Size:
Power Well:
RO
64 bit
Core
Description
Reserved
Intel® Active Management Technology Capability— RO:
0 = Capable
1 = Disabled
32
(Ultra
Mobile
Only)
Reserved
31:22
Reserved
Intel® ICH7DH Only:
21
(Desktop
Only)
Intel® Quick Resume Technology Capability— RO:
0 = Capable
1 = Disabled
ICH7 and ICH7R Only:
Reserved
21
(Mobile/
Ultra Mobile
Only)
Reserved.
20:19
Reserved
18
(Desktop
and Mobile
Only)
SATA RAID 5 Capability— RO:
0 = Capable
1 = Disabled
18
(Ultra
Mobile)
Reserved
17:10
Reserved
9
(Mobile/
Utlra Mobile
Only)
Mobile Features Capability— RO:
0 = Disabled
1 = Capable
9
(Desktop
Only)
Reserved
8
Reserved
7
(Desktop
and Mobile
Only)
Intel ® ICH7 Family Datasheet
PCI Express* 6 x1 Capability— RO:
0 = Capable
1 = Disabled - 4 PCI Express x1 Ports available
383
LPC Interface Bridge Registers (D31:F0)
Bit
Description
7
(Ultra
Mobile
Only)
Reserved
6
Reserved
5
(Desktop
and Mobile
Only)
0 = Capable
1 = Disabled
5
(Ultra
Mobile
Only)
Reserved
4
Reserved
3
(Desktop
and Mobile
Only)
10.1.34
SATA RAID 0/1/10 Capability— RO:
SATA AHCI Capability— RO:
0 = Capable
1 = Disabled
3
(Ultra
Mobile
Only)
Reserved
2:0
Reserved
RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0h
Default Value:
00000000h
R/W
32 bit
Bit
Description
31:14
Base Address (BA) — R/W. Base Address for the root complex register block decode
range. This address is aligned on a 16-KB boundary.
13:1
0
384
Attribute:
Size:
Reserved
Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed
as the Root Complex Register Block.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.2
DMA I/O Registers (LPC I/F—D31:F0)
Table 10-2. DMA Registers (Sheet 1 of 2)
Port
Alias
Register Name
Default
Type
00h
10h
Channel 0 DMA Base & Current Address
Undefined
R/W
01h
11h
Channel 0 DMA Base & Current Count
Undefined
R/W
02h
12h
Channel 1 DMA Base & Current Address
Undefined
R/W
03h
13h
Channel 1 DMA Base & Current Count
Undefined
R/W
04h
14h
Channel 2 DMA Base & Current Address
Undefined
R/W
05h
15h
Channel 2 DMA Base & Current Count
Undefined
R/W
06h
16h
Channel 3 DMA Base & Current Address
Undefined
R/W
07h
17h
Channel 3 DMA Base & Current Count
Undefined
R/W
08h
18h
Channel 0–3 DMA Command
Undefined
WO
Channel 0–3 DMA Status
Undefined
RO
0Ah
1Ah
Channel 0–3 DMA Write Single Mask
000001XXb
WO
0Bh
1Bh
Channel 0–3 DMA Channel Mode
000000XXb
WO
0Ch
1Ch
Channel 0–3 DMA Clear Byte Pointer
Undefined
WO
0Dh
1Dh
Channel 0–3 DMA Master Clear
Undefined
WO
0Eh
1Eh
Channel 0–3 DMA Clear Mask
Undefined
WO
0Fh
1Fh
Channel 0–3 DMA Write All Mask
0Fh
R/W
80h
90h
Reserved Page
Undefined
R/W
81h
91h
Channel 2 DMA Memory Low Page
Undefined
R/W
82h
—
Channel 3 DMA Memory Low Page
Undefined
R/W
83h
93h
Channel 1 DMA Memory Low Page
Undefined
R/W
84h–86h
94h–96h
Reserved Pages
Undefined
R/W
87h
97h
Channel 0 DMA Memory Low Page
Undefined
R/W
88h
98h
Reserved Page
Undefined
R/W
89h
99h
Channel 6 DMA Memory Low Page
Undefined
R/W
8Ah
9Ah
Channel 7 DMA Memory Low Page
Undefined
R/W
8Bh
9Bh
Channel 5 DMA Memory Low Page
Undefined
R/W
8Ch–8Eh
9Ch–9Eh
Reserved Page
Undefined
R/W
8Fh
9Fh
Refresh Low Page
Undefined
R/W
C0h
C1h
Channel 4 DMA Base & Current Address
Undefined
R/W
C2h
C3h
Channel 4 DMA Base & Current Count
Undefined
R/W
C4h
C5h
Channel 5 DMA Base & Current Address
Undefined
R/W
C6h
C7h
Channel 5 DMA Base & Current Count
Undefined
R/W
C8h
C9h
Channel 6 DMA Base & Current Address
Undefined
R/W
CAh
CBh
Channel 6 DMA Base & Current Count
Undefined
R/W
CCh
CDh
Channel 7 DMA Base & Current Address
Undefined
R/W
Intel ® ICH7 Family Datasheet
385
LPC Interface Bridge Registers (D31:F0)
Table 10-2. DMA Registers (Sheet 2 of 2)
10.2.1
Port
Alias
CEh
CFh
D0h
D1h
Register Name
Default
Type
Channel 7 DMA Base & Current Count
Undefined
R/W
Channel 4–7 DMA Command
Undefined
WO
Channel 4–7 DMA Status
Undefined
RO
D4h
D5h
Channel 4–7 DMA Write Single Mask
000001XXb
WO
D6h
D7h
Channel 4–7 DMA Channel Mode
000000XXb
WO
D8h
D9h
Channel 4–7 DMA Clear Byte Pointer
Undefined
WO
DAh
DBh
Channel 4–7 DMA Master Clear
Undefined
WO
DCh
DDh
Channel 4–7 DMA Clear Mask
Undefined
WO
DEh
DFh
Channel 4–7 DMA Write All Mask
0Fh
R/W
DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bit
Ch. #0
Ch. #2
Ch. #5
Ch. #7
Undef
No
=
=
=
=
00h; Ch. #1 = 02h
04h; Ch. #3 = 06h
C4h Ch. #6 = C8h
CCh;
Attribute:
Size:
R/W
16 bit (per channel),
but accessed in two 8-bit
quantities
Power Well: Core
Description
Base and Current Address — R/W. This register determines the address for the
transfers to be performed. The address specified points to two separate registers. On
writes, the value is stored in the Base Address register and copied to the Current
Address register. On reads, the value is returned from the Current Address register.
15:0
The address increments/decrements in the Current Address register after each transfer,
depending on the mode of the transfer. If the channel is in auto-initialize mode, the
Current Address register will be reloaded from the Base Address register after a
terminal count is generated.
For transfers to/from a 16-bit slave (channel’s 5-7), the address is shifted left one bit
location. Bit 15 will be shifted into Bit 16.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte
pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should
be cleared to ensure that the low byte is accessed first.
386
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.2.2
DMABASE_CC—DMA Base and Current Count Registers
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bit
Ch. #0 = 01h; Ch. #1 = 03h
Ch. #2 = 05h; Ch. #3 = 07h
Ch. #5 = C6h; Ch. #6 = CAh
Ch. #7 = CEh;
Undefined
No
Attribute:
Size:
R/W
16-bit (per channel),
but accessed in two 8-bit
quantities
Power Well: Core
Description
Base and Current Count — R/W. This register determines the number of transfers to
be performed. The address specified points to two separate registers. On writes, the
value is stored in the Base Count register and copied to the Current Count register. On
reads, the value is returned from the Current Count register.
15:0
The actual number of transfers is one more than the number programmed in the Base
Count Register (i.e., programming a count of 4h results in 5 transfers). The count is
decrements in the Current Count register after each transfer. When the value in the
register rolls from 0 to FFFFh, a terminal count is generated. If the channel is in autoinitialize mode, the Current Count register will be reloaded from the Base Count
register after a terminal count is generated.
For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the
number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5–7),
the count register indicates the number of words to be transferred.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte
pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be
cleared to ensure that the low byte is accessed first.
10.2.3
DMAMEM_LP—DMA Memory Low Page Registers
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0 = 87h; Ch. #1 = 83h
Ch. #2 = 81h; Ch. #3 = 82h
Ch. #5 = 8Bh; Ch. #6 = 89h
Ch. #7 = 8Ah;
Attribute:
Undefined
Size:
No
Power Well:
R/W
8-bit
Core
Bit
Description
7:0
DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction
with the DMA controller's Current Address Register to define the complete 24-bit
address for the DMA channel. This register remains static throughout the DMA transfer.
Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is
replaced by the bit 15 shifted out from the current address register.
Intel ® ICH7 Family Datasheet
387
LPC Interface Bridge Registers (D31:F0)
10.2.4
DMACMD—DMA Command Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 08h;
Ch. #4–7 = D0h
Undefined
No
Bit
7:5
4
Attribute:
Size:
Power Well:
WO
8-bit
Core
Description
Reserved. Must be 0.
DMA Group Arbitration Priority — WO. Each channel group is individually assigned
either fixed or rotating arbitration priority. At part reset, each group is initialized in
fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
3
Reserved. Must be 0.
DMA Channel Group Enable — WO. Both channel groups are enabled following part
reset.
2
1:0
10.2.5
0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is
cascaded through channel 4.
Reserved. Must be 0.
DMASTA—DMA Status Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 08h;
Ch. #4–7 = D0h
Undefined
No
Attribute:
Size:
Power Well:
RO
8-bit
Core
Bit
Description
7:4
Channel Request Status — RO. When a valid DMA request is pending for a channel,
the corresponding bit is set to 1. When a DMA request is not pending for a particular
channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or
a software request. Note that channel 4 is the cascade channel, so the request status of
channel 4 is a logical OR of the request status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
Channel Terminal Count Status — RO. When a channel reaches terminal count (TC),
its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4
is programmed for cascade, so the TC bit response for channel 4 is irrelevant:
3:0
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
388
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.2.6
DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Ah;
Ch. #4–7 = D4h
0000 01xx
No
Bit
7:3
Attribute:
Size:
Power Well:
WO
8-bit
Core
Description
Reserved. Must be 0.
Channel Mask Select — WO.
2
0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0].
Therefore, only one channel can be masked / unmasked at a time.
1 = Disable DREQ for the selected channel.
DMA Channel Select — WO. These bits select the DMA Channel Mode Register to
program.
1:0
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Intel ® ICH7 Family Datasheet
389
LPC Interface Bridge Registers (D31:F0)
10.2.7
DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Bh;
Ch. #4–7 = D6h
0000 00xx
No
Bit
Attribute:
Size:
Power Well:
WO
8-bit
Core
Description
DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four
different modes:
7:6
00 = Demand mode
01 = Single mode
10 = Reserved
11 = Cascade mode
5
Address Increment/Decrement Select — WO. This bit controls address increment/
decrement during DMA transfers.
0 = Address increment. (default after part reset or Master Clear)
1 = Address decrement.
Autoinitialize Enable — WO.
4
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count.
A part reset or Master Clear disables autoinitialization.
1 = DMA restores the Base Address and Count registers to the current registers
following a terminal count (TC).
DMA Transfer Type — WO. These bits represent the direction of the DMA transfer.
When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type
is irrelevant.
3:2
00 = Verify – No I/O or memory strobes generated
01 = Write – Data transferred from the I/O devices to memory
10 = Read – Data transferred from memory to the I/O device
11 = Invalid
DMA Channel Select — WO. These bits select the DMA Channel Mode Register that
will be written by bits [7:2].
1:0
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
390
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.2.8
DMA Clear Byte Pointer Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
10.2.9
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:0
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the
I/O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
DMA Master Clear Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
10.2.10
Ch. #0–3 = 0Ch;
Ch. #4–7 = D8h
xxxx xxxx
No
Ch. #0–3 = 0Dh;
Ch. #4–7 = DAh
xxxx xxxx
Attribute:
Size:
WO
8-bit
Bit
Description
7:0
Master Clear — WO. No specific pattern. Enabled with a write to the port. This has the
same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Eh;
Ch. #4–7 = DCh
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:0
Clear Mask Register — WO. No specific pattern. Command enabled with a write to the
port.
Intel ® ICH7 Family Datasheet
391
LPC Interface Bridge Registers (D31:F0)
10.2.11
DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Fh;
Ch. #4–7 = DEh
0000 1111
No
Bit
7:4
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Description
Reserved. Must be 0.
Channel Mask Bits — R/W. This register permits all four channels to be
simultaneously enabled/disabled instead of enabling/disabling each channel
individually, as is the case with the Mask Register – Write Single Mask Bit. In addition,
this register has a read path to allow the status of the channel mask bits to be read. A
channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register
reaches terminal count (unless the channel is in auto-initialization mode).
3:0
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0
enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master
Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channel’s
0 – 3 through channel 4.
10.3
Timer I/O Registers (LPC I/F—D31:F0)
Port
Aliases
40h
50h
Register Name
Counter 0 Interval Time Status Byte
Format
Counter 0 Counter Access Port
41h
51h
Counter 1 Interval Time Status Byte
Format
Counter 1 Counter Access Port
42h
52h
Counter 2 Interval Time Status Byte
Format
Counter 2 Counter Access Port
Timer Control Word
43h
53h
Timer Control Word Register
Counter Latch Command
392
Default Value
Type
0XXXXXXXb
RO
Undefined
R/W
0XXXXXXXb
RO
Undefined
R/W
0XXXXXXXb
RO
Undefined
R/W
Undefined
WO
XXXXXXX0b
WO
X0h
WO
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.3.1
TCW—Timer Control Word Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
43h
All bits undefined
Attribute:
Size:
WO
8 bits
This register is programmed prior to any counter being accessed to specify counter
modes. Following part reset, the control words for each register are undefined and each
counter output is 0. Each timer must be programmed to bring it into a known state.
Bit
Description
Counter Select — WO. The Counter Selection bits select the counter the control word
acts upon as shown below. The Read Back Command is selected when bits[7:6] are
both 1.
7:6
00 = Counter 0 select
01 = Counter 1 select
10 = Counter 2 select
11 = Read Back Command
Read/Write Select — WO. These bits are the read/write control bits. The actual
counter programming is done through the counter port (40h for counter 0, 41h for
counter 1, and 42h for counter 2).
5:4
00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Counter Mode Selection — WO. These bits select one of six possible modes of
operation for the selected counter.
Bit Value
3:1
Mode
000b
Mode 0 Out signal on end of count (=0)
001b
Mode 1 Hardware retriggerable oneshot
x10b
Mode 2 Rate generator (divide by n
counter)
x11b
Mode 3 Square wave output
100b
Mode 4 Software triggered strobe
101b
Mode 5 Hardware triggered strobe
Binary/BCD Countdown Select — WO.
0
0 = Binary countdown is used. The largest possible binary count is 216
1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104
There are two special commands that can be issued to the counters through this
register, the Read Back Command and the Counter Latch Command. When these
commands are chosen, several bits within this register are redefined. These register
formats are described below:
RDBK_CMD—Read Back Command (LPC I/F—D31:F0)
The Read Back Command is used to determine the count value, programmed mode,
and current states of the OUT pin and Null count flag of the selected counter or
counters. Status and/or count may be latched in any or all of the counters by selecting
the counter during the register write. The count and status remain latched until read,
and further latch commands are ignored until the count is read. Both count and status
of the selected counters may be latched simultaneously by setting both bit 5 and bit 4
Intel ® ICH7 Family Datasheet
393
LPC Interface Bridge Registers (D31:F0)
to 0. If both are latched, the first read operation from that counter returns the latched
status. The next one or two reads, depending on whether the counter is programmed
for one or two byte counts, returns the latched count. Subsequent reads return an
unlatched count.
Bit
7:6
Description
Read Back Command. Must be 11 to select the Read Back Command
Latch Count of Selected Counters.
5
0 = Current count value of the selected counters will be latched
1 = Current count will not be latched
Latch Status of Selected Counters.
4
0 = Status of the selected counters will be latched
1 = Status will not be latched
3
Counter 2 Select.
1 = Counter 2 count and/or status will be latched
2
Counter 1 Select.
1 = Counter 1 count and/or status will be latched
1
Counter 0 Select.
1 = Counter 0 count and/or status will be latched.
0
Reserved. Must be 0.
LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0)
The Counter Latch Command latches the current count value. This command is used to
insure that the count read from the counter is accurate. The count value is then read
from each counter's count register through the Counter Ports Access Ports Register
(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read
according to the programmed format, i.e., if the counter is programmed for two byte
counts, two bytes must be read. The two bytes do not have to be read one right after
the other (read, write, or programming operations for other counters may be inserted
between the reads). If a counter is latched once and then latched again before the
count is read, the second Counter Latch Command is ignored.
Bit
Description
Counter Selection. These bits select the counter for latching. If “11” is written, then
the write is interpreted as a read back command.
7:6
00 = Counter 0
01 = Counter 1
10 = Counter 2
5:4
3:0
394
Counter Latch Command.
00 = Selects the Counter Latch Command.
Reserved. Must be 0.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.3.2
SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Counter 0 = 40h,
Counter 1 = 41h,
Counter 2 = 42h
Bits[6:0] undefined, Bit 7=0
Attribute:
Size:
RO
8 bits per counter
Each counter's status byte can be read following a Read Back Command. If latch status
is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the
next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for
counter 1, and 42h for counter 2) returns the status byte. The status byte returns the
following:
Bit
Description
Counter OUT Pin State — RO.
7
6
0 = OUT pin of the counter is also a 0
1 = OUT pin of the counter is also a 1
Count Register Status — RO. This bit indicates when the last count written to the
Count Register (CR) has been loaded into the counting element (CE). The exact time
this happens depends on the counter mode, but until the count is loaded into the
counting element (CE), the count value will be incorrect.
0 = Count has been transferred from CR to CE and is available for reading.
1 = Null Count. Count has not been transferred from CR to CE and is not yet available
for reading.
Read/Write Selection Status — RO. These bits reflect the read/write selection made
through bits[5:4] of the control register. The binary codes returned during the status
read match the codes used to program the counter read/write selection.
5:4
00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Mode Selection Status — RO. These bits return the counter mode programming. The
binary code returned matches the code used to program the counter mode, as listed
under the bit function above.
000 = Mode 0 — Out signal on end of count (=0)
3:1
001 = Mode 1 — Hardware retriggerable one-shot
x10 = Mode 2 — Rate generator (divide by n counter)
x11 = Mode 3 — Square wave output
100 = Mode 4 — Software triggered strobe
101 = Mode 5 — Hardware triggered strobe
Countdown Type Status — RO. This bit reflects the current countdown type.
0
0 = Binary countdown
1 = Binary Coded Decimal (BCD) countdown.
Intel ® ICH7 Family Datasheet
395
LPC Interface Bridge Registers (D31:F0)
10.3.3
Counter Access Ports Register (LPC I/F—D31:F0)
I/O Address:
Counter 0 – 40h,
Counter 1 – 41h,
Counter 2 – 42h
All bits undefined
Default Value:
Attribute:
R/W
Size:
8 bit
Bit
Description
7:0
Counter Port — R/W. Each counter port address is used to program the 16-bit Count
Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is
defined with the Interval Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and return the status of the
counter programming following a Read Back Command.
10.4
8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0)
10.4.1
Interrupt Controller I/O MAP (LPC I/F—D31:F0)
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them. Table 10-3 shows
the different register possibilities for each address.
Table 10-3. PIC Registers (LPC I/F—D31:F0)
Port
20h
21h
Aliases
Type
Undefined
WO
24h, 28h,
Master PIC ICW1 Init. Cmd Word 1
2Ch, 30h,
Master PIC OCW2 Op Ctrl Word 2
001XXXXXb
WO
34h, 38h, 3Ch
Master PIC OCW3 Op Ctrl Word 3
X01XXX10b
WO
25h, 29h,
Master PIC ICW2 Init. Cmd Word 2
Undefined
WO
2Dh, 31h,
Master PIC ICW3 Init. Cmd Word 3
Undefined
WO
35h, 39h,
3Dh
Master PIC ICW4 Init. Cmd Word 4
01h
WO
Master PIC OCW1 Op Ctrl Word 1
00h
R/W
A4h, A8h,
Slave PIC ICW1 Init. Cmd Word 1
Undefined
WO
Slave PIC OCW2 Op Ctrl Word 2
001XXXXXb
WO
B4h, B8h,
BCh
Slave PIC OCW3 Op Ctrl Word 3
X01XXX10b
WO
Slave PIC ICW2 Init. Cmd Word 2
Undefined
WO
ADh, B1h,
Slave PIC ICW3 Init. Cmd Word 3
Undefined
WO
B5h, B9h,
BDh
Slave PIC ICW4 Init. Cmd Word 4
01h
WO
Slave PIC OCW1 Op Ctrl Word 1
00h
R/W
4D0h
–
Master PIC Edge/Level Triggered
00h
R/W
4D1h
–
Slave PIC Edge/Level Triggered
00h
R/W
A5h, A9h,
A1h
396
Default
Value
ACh, B0h,
A0h
Note:
Register Name
Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section (Chapter 5.9).
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.4.2
ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 20h
Slave Controller – A0h
Default Value:
All bits undefined
Attribute:
Size:
WO
8 bit /controller
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
Bit
7:5
Description
ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.
000 = Should be programmed to “000”
ICW/OCW Select — WO.
4
3
2
1
1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4
sequence.
Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level
triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).
ADI — WO.
0 = Ignored for the Intel® ICH7. Should be programmed to 0.
Single or Cascade (SNGL) — WO.
0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.
ICW4 Write Required (IC4) — WO.
0
1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be
programmed.
Intel ® ICH7 Family Datasheet
397
LPC Interface Bridge Registers (D31:F0)
10.4.3
ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 21h
Slave Controller – A1h
Default Value:
All bits undefined
Attribute:
Size:
WO
8 bit /controller
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
Bit
7:3
Description
Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the
interrupt vector table for the interrupt routines associated with each interrupt request
level input.
Interrupt Request Level — WO. When writing ICW2, these bits should all be 0.
During an interrupt acknowledge cycle, these bits are programmed by the interrupt
controller with the interrupt to be serviced. This is combined with bits [7:3] to form the
interrupt vector driven onto the data bus during the second INTA# cycle. The code is a
three bit binary code:
2:0
10.4.4
Code
Master Interrupt
Slave Interrupt
000b
IRQ0
IRQ8
001b
IRQ1
IRQ9
010b
IRQ2
IRQ10
011b
IRQ3
IRQ11
100b
IRQ4
IRQ12
101b
IRQ5
IRQ13
110b
IRQ6
IRQ14
111b
IRQ7
IRQ15
ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0)
Offset Address: 21h
Default Value:
All bits undefined
Bit
7:3
2
1:0
398
Attribute:
Size:
WO
8 bits
Description
0 = These bits must be programmed to 0.
Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the
slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through
the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2.
IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR
signal is asserted to the processor, and the returning interrupt acknowledge returns the
interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
0 = These bits must be programmed to 0.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.4.5
ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0)
Offset Address: A1h
Default Value:
All bits undefined
Bit
10.4.6
Attribute:
Size:
WO
8 bits
Description
7:3
0 = These bits must be programmed to 0.
2:0
Slave Identification Code — WO. These bits are compared against the slave
identification code broadcast by the master controller from the trailing edge of the first
internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits
must be programmed to 02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the INTA# sequence, the slave
controller assumes responsibility for broadcasting the interrupt vector.
ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 021h
Slave Controller – 0A1h
Default Value:
01h
Bit
7:5
Attribute:
Size:
WO
8 bits
Description
0 = These bits must be programmed to 0.
Special Fully Nested Mode (SFNM) — WO.
4
3
2
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode (BUF) — WO.
0 = Must be programmed to 0 for the Intel® ICH7. This is non-buffered mode.
Master/Slave in Buffered Mode — WO. Not used.
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI) — WO.
1
0
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
Microprocessor Mode — WO.
1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
Architecture-based system.
Intel ® ICH7 Family Datasheet
399
LPC Interface Bridge Registers (D31:F0)
10.4.7
OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0)
Offset Address: Master Controller – 021h
Slave Controller – 0A1h
Default Value:
00h
10.4.8
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the
corresponding IRQ line is masked. When a 0 is written to any bit in this register, the
corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by
the controller. Masking IRQ2 on the master controller will also mask the interrupt
requests from the slave controller.
OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 020h
Attribute:
Slave Controller – 0A0h
Size:
Default Value:
Bit[4:0]=undefined, Bit[7:5]=001
WO
8 bits
Following a part reset or ICW initialization, the controller enters the fully nested mode
of operation. Non-specific EOI without rotation is the default. Both rotation mode and
specific EOI mode are disabled following initialization.
Bit
Description
Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and
End of Interrupt modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
7:5
011 = *Specific EOI Command
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 = *Set Priority Command
111 = *Rotate on Specific EOI Command
*L0 – L2 Are Used
4:3
OCW2 Select — WO. When selecting OCW2, bits 4:3 = “00”
Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt
level acted upon when the SL bit is active. A simple binary code, outlined below, selects
the channel for the command to act upon. When the SL bit is inactive, these bits do not
have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case.
2:0
400
Code
Interrupt Level
Code
Interrupt Level
000b
IRQ0/8
000b
IRQ4/12
001b
IRQ1/9
001b
IRQ5/13
010b
IRQ2/10
010b
IRQ6/14
011b
IRQ3/11
011b
IRQ7/15
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.4.9
OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 020h
Attribute:
Slave Controller – 0A0h
Size:
Default Value:
Bit[6,0]=0, Bit[7,4:2]=undefined,
Bit[5,1]=1
Bit
WO
8 bits
Description
7
Reserved. Must be 0.
6
Special Mask Mode (SMM) — WO.
1 = The Special Mask Mode can be used by an interrupt service routine to dynamically
alter the system priority structure while the routine is executing, through selective
enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be
set for this bit to have any meaning.
Enable Special Mask Mode (ESMM) — WO.
5
4:3
0 = Disable. The SMM bit becomes a “don't care”.
1 = Enable the SMM bit to set or reset the Special Mask Mode.
OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01
Poll Mode Command — WO.
2
1:0
0 = Disable. Poll Command is not issued.
1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt
acknowledge cycle. An encoded byte is driven onto the data bus, representing the
highest priority level requesting service.
Register Read Command — WO. These bits provide control for reading the In-Service
Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not
affect the register read selection. When bit 1=1, bit 0 selects the register status
returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR
will be read. Following ICW initialization, the default OCW3 port address read will be
“read IRR”. To retain the current selection (read ISR or read IRR), always write a 0 to
bit 1 when programming this register. The selected register can be read repeatedly
without reprogramming OCW3. To select a new status register, OCW3 must be
reprogrammed prior to attempting the read.
00 = No Action
01 = No Action
10 = Read IRQ Register
11 = Read IS Register
Intel ® ICH7 Family Datasheet
401
LPC Interface Bridge Registers (D31:F0)
10.4.10
ELCR1—Master Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address: 4D0h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade
channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),
cannot be put into level mode.
Bit
Description
IRQ7 ECL — R/W.
7
0 = Edge.
1 = Level.
IRQ6 ECL — R/W.
6
0 = Edge.
1 = Level.
IRQ5 ECL — R/W.
5
0 = Edge.
1 = Level.
IRQ4 ECL — R/W.
4
0 = Edge.
1 = Level.
IRQ3 ECL — R/W.
3
2:0
402
0 = Edge.
1 = Level.
Reserved. Must be 0.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.4.11
ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address: 4D1h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Bit
Description
IRQ15 ECL — R/W.
7
0 = Edge
1 = Level
IRQ14 ECL — R/W.
6
5
0 = Edge
1 = Level
Reserved. Must be 0.
IRQ12 ECL — R/W.
4
0 = Edge
1 = Level
IRQ11 ECL — R/W.
3
0 = Edge
1 = Level
IRQ10 ECL — R/W.
2
0 = Edge
1 = Level
IRQ9 ECL — R/W.
1
0 = Edge
1 = Level
0
Reserved.
Intel ® ICH7 Family Datasheet
Must be 0.
403
LPC Interface Bridge Registers (D31:F0)
10.5
Advanced Programmable Interrupt Controller
(APIC)(D31:F0)
10.5.1
APIC Register Map (LPC I/F—D31:F0)
The APIC is accessed via an indirect addressing scheme. Two registers are visible by
software for manipulation of most of the APIC registers. These registers are mapped
into memory space. The registers are shown in Table 10-4.
Table 10-4. APIC Direct Registers (LPC I/F—D31:F0)
Address
Mnemoni
c
FEC0_0000h
IND
Register Name
Size
Type
Index
8 bits
R/W
FEC0_0010h
DAT
Data
32 bits
R/W
FECO_0040h
EOIR
EOI
32 bits
WO
Table 10-5 lists the registers which can be accessed within the APIC via the Index
Register. When accessing these registers, accesses must be done one DWord at a time.
For example, software should not access byte 2 from the Data register before accessing
bytes 0 and 1. The hardware will not attempt to recover from a bad programming
model in this case.
Table 10-5. APIC Indirect Registers (LPC I/F—D31:F0)
10.5.2
Index
Mnemonic
00
ID
01
VER
Register Name
Size
Type
Identification
32 bits
R/W
Version
32 bits
RO
02–0F
—
—
RO
10–11
REDIR_TBL0
Reserved
Redirection Table 0
64 bits
R/W, RO
12–13
REDIR_TBL1
Redirection Table 1
64 bits
R/W, RO
...
...
...
...
3E–3F
REDIR_TBL23
64 bits
R/W, RO
40–FF
—
—
RO
...
Redirection Table 23
Reserved
IND—Index Register (LPC I/F—D31:F0)
Memory Address FEC0_0000h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
The Index Register will select which APIC indirect register to be manipulated by
software. The selector values for the indirect registers are listed in Table 10-5. Software
will program this register to select the desired APIC internal register
.
Bit
7:0
404
Description
APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.5.3
DAT—Data Register (LPC I/F—D31:F0)
Memory Address FEC0_0010h
Default Value:
00000000h
Attribute:
Size:
R/W
32 bits
This is a 32-bit register specifying the data to be read or written to the register pointed
to by the Index register. This register can only be accessed in DWord quantities.
Bit
7:0
10.5.4
Description
APIC Data — R/W. This is a 32-bit register for the data to be read or written to the
APIC indirect register (Figure 10-5) pointed to by the Index register (Memory Address
FEC0_0000h).
EOIR—EOI Register (LPC I/F—D31:F0)
Memory Address FEC0h_0040h
Default Value:
N/A
Attribute:
Size:
WO
32 bits
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit
14) for that I/O Redirection Entry will be cleared.
Note:
If multiple I/O Redirection entries, for any reason, assign the same vector for more
than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
The interrupt which was prematurely reset will not be lost because if its input remained
active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced
at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the
ICH7.
Note:
To provide for future expansion, the processor should always write a value of 0 to Bits
31:8.
Bit
Description
31:8
Reserved. To provide for future expansion, the processor should always write a value of
0 to Bits 31:8.
7:0
Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC
will check this field, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
Intel ® ICH7 Family Datasheet
405
LPC Interface Bridge Registers (D31:F0)
10.5.5
ID—Identification Register (LPC I/F—D31:F0)
Index Offset:
Default Value:
00h
00000000h
Attribute:
Size:
R/W
32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
Bit
31:28
Reserved
27:24
APIC ID — R/W. Software must program this value before using the APIC.
23:16
Reserved
15
14:0
10.5.6
Description
Scratchpad Bit.
Reserved
VER—Version Register (LPC I/F—D31:F0)
Index Offset:
Default Value:
01h
00170020h
Attribute:
Size:
RO
32 bits
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
Bit
31:24
Reserved
23:16
Maximum Redirection Entries — RO. This field is the entry number (0 being the lowest
entry) of the highest entry in the redirection table. It is equal to the number of
interrupt input pins minus one and is in the range 0 through 239. In the Intel® ICH7
this field is hardwired to 17h to indicate 24 interrupts.
15
14:8
7:0
406
Description
PRQ — RO. This bit indicate that the IOxAPIC does not implement the Pin Assertion
Register.
Reserved
Version — RO. This is a version number that identifies the implementation version.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.5.7
REDIR_TBL—Redirection Table (LPC I/F—D31:F0)
Index Offset:
Default Value:
10h–11h (vector 0) through
3E–3Fh (vector 23)
Bit 16 = 1,. All other bits undefined
Attribute:R/W, RO
Size: 64 bits each, (accessed
as two 32 bit quantities)
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held
until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC unit that the interrupt message was sent. Only
then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new
edge will only result in a new invocation of the handler if its acceptance by the
destination APIC causes the Interrupt Request Register bit to go from 0 to 1.
(In other words, if the interrupt was not already pending at the destination.)
Bit
Description
63:56
Destination — R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an
APIC ID. In this case, bits 63:59 should be programmed by software to 0.
If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination
address of a set of processors.
55:48
Extended Destination ID (EDID) — RO. These bits are sent to a local APIC only
when in Processor System Bus mode. They become bits 11:4 of the address.
47:17
Reserved
Mask — R/W.
16
15
14
13
12
0 = Not masked: An edge or level on this interrupt pin results in the delivery of the
interrupt to the destination.
1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the
interrupt is accepted by a local APIC has no effect on that interrupt. This behavior
is identical to the device withdrawing the interrupt before it is posted to the
processor. It is software's responsibility to deal with the case where the mask bit is
set after the interrupt message has been accepted by a local APIC unit but before
the interrupt is dispensed to the processor.
Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that
triggers an interrupt.
0 = Edge triggered.
1 = Level triggered.
Remote IRR — R/W. This bit is used for level triggered interrupts; its meaning is
undefined for edge triggered interrupts.
0 = Reset when an EOI message is received from a local APIC.
1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.
Interrupt Input Pin Polarity — R/W. This bit specifies the polarity of each interrupt
signal connected to the interrupt pins.
0 = Active high.
1 = Active low.
Delivery Status — RO. This field contains the current status of the delivery of this
interrupt. Writes to this bit have no effect.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is not complete.
Intel ® ICH7 Family Datasheet
407
LPC Interface Bridge Registers (D31:F0)
Bit
Description
Destination Mode — R/W. This field determines the interpretation of the Destination
field.
11
0 = Physical. Destination APIC ID is identified by bits 59:56.
1 = Logical. Destinations are identified by matching bit 63:56 with the Logical
Destination in the Destination Format Register and Logical Destination Register in
each Local APIC.
10:8
Delivery Mode — R/W. This field specifies how the APICs listed in the destination field
should act upon reception of this signal. Certain Delivery Modes will only operate as
intended when used in conjunction with a specific trigger mode. These encodings are
listed in the note below:
7:0
Vector — R/W. This field contains the interrupt vector for this interrupt. Values range
between 10h and FEh.
NOTE: Delivery Mode encoding:
408
000 =
Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.
Trigger Mode can be edge or level.
001 =
Lowest Priority. Deliver the signal on the INTR signal of the processor core that is
executing at the lowest priority among all the processors listed in the specified
destination. Trigger Mode can be edge or level.
010 =
SMI (System Management Interrupt). Requires the interrupt to be programmed as edge
triggered. The vector information is ignored but must be programmed to all 0’s for future
compatibility: not supported
011 =
Reserved
100 =
NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.
Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is
programmed as level triggered. For proper operation this redirection table entry must be
programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the
redirection table is incorrectly set to level, the loop count will continue counting through
the redirection table addresses. Once the count for the NMI pin is reached again, the
interrupt will be sent again: not supported
101 =
INIT. Deliver the signal to all processor cores listed in the destination by asserting the
INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated
as an edge triggered interrupt even if programmed as level triggered. For proper
operation this redirection table entry must be programmed to edge triggered. The INIT
delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level,
the loop count will continue counting through the redirection table addresses. Once the
count for the INIT pin is reached again, the interrupt will be sent again: not supported
110 =
Reserved
111 =
ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination
as an interrupt that originated in an externally connected 8259A compatible interrupt
controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the
external controller that is expected to supply the vector. Requires the interrupt to be
programmed as edge triggered.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.6
Real Time Clock Registers (LPC I/F—D31:F0)
10.6.1
I/O Register Address Map (LPC I/F—D31:F0)
The RTC internal registers and RAM are organized as two banks of 128 bytes each,
called the standard and extended banks. The first 14 bytes of the standard bank
contain the RTC time and date information along with four registers, A–D, that are used
for configuration of the RTC. The extended bank contains a full 128 bytes of battery
backed SRAM, and will be accessible even when the RTC module is disabled (via the
RTC configuration register). Registers A–D do not physically exist in the RAM.
All data movement between the host processor and the real-time clock is done through
registers mapped to the standard I/O space. The register map appears in Table 10-6.
Table 10-6. RTC I/O Registers (LPC I/F—D31:F0)
I/O
Locations
If U128E bit = 0
70h and 74h
Also alias to 72h and 76h
71h and 75h
Also alias to 73h and 77h
Function
Real-Time Clock (Standard RAM) Index Register
Real-Time Clock (Standard RAM) Target Register
72h and 76h
Extended RAM Index Register (if enabled)
73h and 77h
Extended RAM Target Register (if enabled)
NOTES:
1. I/O locations 70h and 71h are the standard legacy location for the real-time clock.
The map for this bank is shown in Table 10-7. Locations 72h and 73h are for
accessing the extended RAM. The extended RAM bank is also accessed using an
indexed scheme. I/O address 72h is used as the address pointer and I/O address
73h is used as the data register. Index addresses above 127h are not valid. If the
extended RAM is not needed, it may be disabled.
2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When
writing to this address, software must first read the value, and then write the same
value for bit 7 during the sequential address write. Note that port 70h is not
directly readable. The only way to read this register is through Alt Access mode.
Although RTC Index bits 6:0 are readable from port 74h, bit 7 will always return 0.
If the NMI# enable is not changed during normal operation, software can
alternatively read this bit once and then retain the value for all subsequent writes
to port 70h.
Intel ® ICH7 Family Datasheet
409
LPC Interface Bridge Registers (D31:F0)
10.6.2
Indexed Registers (LPC I/F—D31:F0)
The RTC contains two sets of indexed registers that are accessed using the two
separate Index and Target registers (70/71h or 72/73h), as shown in Table 10-7.
Table 10-7. RTC (Standard) RAM Bank (LPC I/F—D31:F0)
Index
00h
Seconds
01h
Seconds Alarm
02h
Minutes
03h
Minutes Alarm
04h
Hours
05h
Hours Alarm
06h
Day of Week
07h
Day of Month
08h
Month
09h
Year
0Ah
Register A
0Bh
Register B
0Ch
Register C
0Dh
Register D
0Eh–7Fh
410
Name
114 Bytes of User RAM
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.6.2.1
RTC_REGA—Register A (LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0A
Undefined
No
Attribute:
Size:
Power Well:
R/W
8-bit
RTC
This register is used for general configuration of the RTC functions.
are affected by RSMRST# or any other Intel® ICH7 reset signal.
Bit
None of the bits
Description
Update In Progress (UIP) — R/W. This bit may be monitored as a status flag.
7
0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm
information in RAM is always available when the UIP bit is 0.
1 = The update is soon to occur or is in progress.
Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain
for the oscillator, and are not affected by RSMRST# or any other reset signal. DV2
corresponds to bit 6.
010 = Normal Operation
6:4
11X = Divider Reset
101 = Bypass 15 stages (test mode only)
100 = Bypass 10 stages (test mode only)
011 = Bypass 5 stages (test mode only)
001 = Invalid
000 = Invalid
Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain.
The selected tap can generate a periodic interrupt if the PIE bit is set in Register B.
Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be
used, these bits should all be set to 0. RS3 corresponds to bit 3.
0000 = Interrupt does not toggle
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 µs
0100 = 244.141 µs
3:0
0101 = 488.281 µs
0110 = 976.5625 µs
0111 = 1.953125 ms
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15.625 ms
1011 = 31.25 ms
1100 = 62.5 ms
1101 = 125 ms
1110 = 250 ms
1111= 500 ms
Intel ® ICH7 Family Datasheet
411
LPC Interface Bridge Registers (D31:F0)
10.6.2.2
RTC_REGB—Register B (General Configuration)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
Bit
0Bh
Attribute:
U0U00UUU (U: Undefined) Size:
No
Power Well:
R/W
8-bit
RTC
Description
Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not
affected by RSMRST# nor any other reset signal.
7
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update cycles will not occur until
SET is returned to 0. When set is one, the BIOS may initialize time and calendar
bytes safely.
NOTE: This bit should be set then cleared early in BIOS POST after each powerup
directly after coin-cell battery insertion.
Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on
any other reset.
6
0 = Disable.
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register
A.
Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any
other reset.
5
4
3
412
0 = Disable.
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the
update cycle. An alarm can occur once a second, one an hour, once a day, or one a
month.
Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but
not on any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
Square Wave Enable (SQWE) — R/W. This bit serves no function in the Intel® ICH7.
It is left in this register bank to provide compatibility with the Motorola 146818B. The
ICH7 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
2
Description
Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation.
This bit is not affected by RSMRST# nor any other reset signal.
0 = BCD
1 = Binary
Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is
not affected by RSMRST# nor any other reset signal.
1
0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and
PM as one.
1 = Twenty-four hour mode.
Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per
year. The days for the hour adjustment are those specified in United States federal law
as of 1987, which is different than previous years. This bit is not affected by RSMRST#
nor any other reset signal.
0
10.6.2.3
0 = Daylight Savings Time updates do not occur.
1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to
3:00:00 AM.
b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it
is changed to 1:00:00 AM. The time must increment normally for at least two
update cycles (seconds) previous to these conditions for the time change to occur
properly.
RTC_REGC—Register C (Flag Register)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Ch
Attribute:
00U00000 (U: Undefined) Size:
No
Power Well:
RO
8-bit
RTC
Writes to Register C have no effect.
Bit
Description
7
Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE).
This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST#
or a read of Register C.
Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of
Register C.
6
0 = If no taps are specified via the RS bits in Register A, this flag will not be set.
1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is
1.
Alarm Flag (AF) — RO.
5
0 = This bit is cleared upon RTCRST# or a read of Register C.
1 = Alarm Flag will be set after all Alarm values match the current time.
Update-Ended Flag (UF) — RO.
4
3:0
0 = The bit is cleared upon RSMRST# or a read of Register C.
1 = Set immediately following an update cycle for each second.
Reserved.
Intel ® ICH7 Family Datasheet
Will always report 0.
413
LPC Interface Bridge Registers (D31:F0)
10.6.2.4
RTC_REGD—Register D (Flag Register)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
Bit
0Dh
Attribute:
10UUUUUU (U: Undefined) Size:
No
Power Well:
R/W
8-bit
RTC
Description
Valid RAM and Time Bit (VRT) — R/W.
7
6
5:0
414
0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for
read cycles.
1 = This bit is hardwired to 1 in the RTC power well.
Reserved. This bit always returns a 0 and should be set to 0 for write cycles.
Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b,
then a don’t care state is assumed. The host must configure the date alarm for these
bits to do anything, yet they can be written at any time. If the date alarm is not
enabled, these bits will return 0’s to mimic the functionality of the Motorola 146818B.
These bits are not affected by any reset assertion.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.7
Processor Interface Registers (LPC I/F—D31:F0)
Table 10-8 is the register address map for the processor interface registers.
Table 10-8. Processor Interface PCI Register Address Map (LPC I/F—D31:F0)
10.7.1
Offset
Mnemonic
Register Name
Default
Type
61h
NMI_SC
NMI Status and Control
00h
R/W, RO
70h
NMI_EN
NMI Enable
80h
R/W (special)
92h
PORT92
Fast A20 and Init
00h
R/W
F0h
COPROC_ERR
Coprocessor Error
00h
R/W
CF9h
RST_CNT
Reset Control
00h
R/W
NMI_SC—NMI Status and Control Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
61h
00h
No
Attribute:
Size:
Power Well:
R/W, RO
8-bit
Core
Bit
Description
7
SERR# NMI Source Status (SERR#_NMI_STS) — RO.
1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and
if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2
to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port
61h, this bit must be 0.
NOTE: This bit is set by any of the Intel® ICH7 internal sources of SERR; this includes
SERR assertions forwarded from the secondary PCI bus, errors on a PCI
Express* port, or other internal functions that generate SERR#.
6
IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.
1 = Bit is set if an LPC agent (via SERIRQ) asserted IOCHK# and if bit 3
(IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0.
To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h,
this bit must be a 0.
5
Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current
state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI
reset for this bit to have a determinate value. When writing to port 61h, this bit must
be a 0.
4
Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or
1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to
port 61h, this bit must be a 0.
IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.
3
0 = Enabled.
1 = Disabled and cleared.
Intel ® ICH7 Family Datasheet
415
LPC Interface Bridge Registers (D31:F0)
Bit
Description
PCI SERR# Enable (PCI_SERR_EN) — R/W.
2
0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
1
0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Speaker Data Enable (SPKR_DAT_EN) — R/W.
Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.
0
10.7.2
0 = Disable
1 = Enable
NMI_EN—NMI Enable (and Real Time Clock Index)
Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Note:
70h
80h
No
Attribute:
Size:
Power Well:
R/W (special)
8-bit
Core
The RTC Index field is write-only for normal operation. This field can only be read in AltAccess Mode. Note, however, that this register is aliased to Port 74h (documented in),
and all bits are readable at that address.
Bits
Description
NMI Enable (NMI_EN) — R/W (special).
7
6:0
10.7.3
0 = Enable NMI sources.
1 = Disable All NMI sources.
Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to
the RTC to select which register or CMOS RAM address is being accessed.
PORT92—Fast A20 and Init Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bit
7:2
1
0
416
92h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Description
Reserved
Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE
input signal to generate A20M# to the processor.
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the Intel® ICH7 will force
INIT# active for 16 PCI clocks.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.7.4
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
10.7.5
F0h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bits
Core
Bits
Description
7:0
Coprocessor Error (COPROC_ERR) — R/W. Any value written to this register will
cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to
generate an internal IRQ13, the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0,
Bit 13) must be 1. Reads to this register always return 00h.
RST_CNT—Reset Control Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bit
7:4
CF9h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Description
Reserved
Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#,
SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),
after PWROK going low (with RSMRST# high), or after two TCO timeouts.
3
0 = Intel® ICH7 will keep SLP_S3#, SLP_S4# and SLP_S5# high.
1 = ICH7 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)
in response to SYSRESET#, PWROK#, and Watchdog timer reset sources.
2
Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a
hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to
the processor.
1
0
0 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a soft reset by activating
INIT# for 16 PCI clocks.
1 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a hard reset by activating
PLTRST# and SUS_STAT# active for about 5-6 milliseconds, however the
SLP_S3#, SLP_S4# and SLP_S5# will NOT go active. The ICH7 main power well is
reset when this bit is 1. It also resets the resume well bits (except for those noted
throughout the datasheet).
Reserved
Intel ® ICH7 Family Datasheet
417
LPC Interface Bridge Registers (D31:F0)
10.8
Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicate, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
10.8.1
Power Management PCI Configuration Registers
(PM—D31:F0)
Table 10-9 shows a small part of the configuration space for PCI Device 31: Function 0.
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
Table 10-9. Power Management PCI Register Address Map (PM—D31:F0)
418
Offset
Mnemonic
A0h
GEN_PMCON_1
A2h
Register Name
Default
Type
General Power Management
Configuration 1
0000h
R/W, RO,
R/WO
GEN_PMCON_2
General Power Management
Configuration 2
00h
R/W, R/
WC
A4h
GEN_PMCON_3
General Power Management
Configuration 3
00h
R/W, R/
WC
A9h
Cx-STATE_CNF
Cx State Configuration (Mobile/Ultra
Mobile Only).
00h
R/W
AAh
C4-TIMING_CNT
C4 Timing Control (Mobile/Ultra Mobile
Only).
00h
R/W
ABh
BM_BREAK_EN
BM_BREAK_EN
00h
R/W
ADh
MSC_FUN
Miscellaneous Functionality
00h
R/W
00h
R/WC, RO
B0h
EL_STS
Intel® Quick Resume Technology Status
Register (Digital Home Only)
B1h-B2h
EL_CNTL1
Intel Quick Resume Technology Control 1
Register (Digital Home Only)
F000h
R/W, RO,
WO
B3h
EL_CNTL2
Intel Quick Resume Technology Control 2
Register (Digital Home Only)
00h
R/W, RO
B8–BBh
GPI_ROUT
GPI Route Control
0000000
0h
R/W
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address: A0h
Default Value:
0000h
Lockable:
No
Bit
15:11
10
(Desktop
and
Mobile
Only)
10
(Ultra
Mobile
Only)
Attribute:
Size:
Usage:
Power Well:
R/W, RO, R/WO
16-bit
ACPI, Legacy
Core
Description
Reserved
BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated
with the PCI Express* ports.
0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit to
go active.
1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to go
active.
Reserved
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
9
0 = Low.
1 = High.
8
Reserved
7
(Desktop
Only)
Reserved
7
(Mobile/
Ultra
Mobile
Only)
Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when
software does a LVL3 read, the Intel® ICH7-M/ICH7-U transitions to the C4 state.
6
5
(Desktop
Only)
5
(Mobile/
Ultra
Mobile
Only)
4
3:2
(Desktop
Only)
i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor,
not an IA_32 processor. This may be used in various state machines where there are
behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the
processor power.
Reserved
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE +
30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by
PLTRST#).
Reserved
Intel ® ICH7 Family Datasheet
419
LPC Interface Bridge Registers (D31:F0)
Bit
Description
3
(Mobile/
Ultra
Mobile
Only)
Intel SpeedStep Enable (SS_EN) — R/W.
0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not be
visible (reads to SS_CNT will return 00h and writes will have no effect).
1 = Intel SpeedStep technology logic is enabled.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. Intel® ICH7-M/ICH7-U drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and
STP_PCI# signals.
2
(Mobile/
Ultra
Mobile
Only)
NOTE: when the SLP_EN# bit is set, the ICH7 drives the CLKRUN# signal low
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control
the rate at which periodic SMI# is generated.
00 = 1 minute
1:0
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
10.8.1.2
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2h
Default Value:
00h
Lockable:
No
Bit
7
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
Resume
Description
DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any
way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence
and to clear this bit after completing the DRAM initialization sequence. BIOS can detect
that a DRAM initialization sequence was interrupted by a reset by reading this bit during
the boot sequence.
•
•
If the bit is 1, then the DRAM initialization was interrupted.
This bit is reset by the assertion of the RSMRST# pin.
CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the
processor needs to lock its PLLs. This is used wherever timing t270 (Chapter 23)
applies.
6:5
00
01
10
11
=
=
=
=
min
min
min
min
30.7 µs (Default)
61.4 µs
122.8 µs
245.6 µs
It is the responsibility of the BIOS to program the correct value in this field prior to the
first transition to C3 or C4 states (or performing Intel SpeedStep® technology
transitions).
NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to these
bits.
NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write
420
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
Description
System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
4
0 = SYS_RESET# button Not pressed.
1 = ICH7 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to
read this bit and clear it, if it is set.
NOTE: This bit is also reset by RSMRST# and CF9h resets.
CPU Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the
system is in an S0 or S1 state.
3
NOTES:
1.
This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the
shutdown and reboot associated with the CPUTHRMTRIP# event.
2.
The CF9h reset in the description refers to CF9h type core well reset which
includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO Timeout.
This type of reset will clear CTS bit.
Minimum SLP_S4# Assertion Width Violation Status — R/WC.
2
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time
programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset
A4h:bits 5:4). The ICH7 begins the timer when SLP_S4# is asserted during S4/S5
entry, or when the RSMRST# input is deasserted during G3 exit. Note that this bit
is functional regardless of the value in the SLP_S4# Assertion Stretch Enable
(D31:F0:Offset A4h:bit 3).
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some
cases before the default value is readable.
CPU Power Failure (CPUPWR_FLR) — R/WC.
1
0 = Software (typically BIOS) clears this bit by writing a 0 to it.
1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while the
system was in an S0 or S1 state.
NOTE: VRMPWRGD is sampled using the RTC clock. Therefore, low times that are less
than one RTC clock period may not be detected by the ICH7.
PWROK Failure (PWROK_FLR) — R/WC.
0
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3
state.
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1
state. The bit will be cleared only by software by writing a 1 to this bit or when the
system goes to a G3 state.
NOTE: See Chapter 5.14.11.3 for more details about the PWROK pin functionality.
NOTE: In the case of true PWROK failure, PWROK will go low first before the
VRMPWRGD.
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one
RTC clock period may not be detected by the ICH7.
Intel ® ICH7 Family Datasheet
421
LPC Interface Bridge Registers (D31:F0)
10.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4h
Default Value:
00h
Lockable:
No
Bit
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
RTC
Description
SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.
Valid values are:
7:6
00
01
10
11
=
=
=
=
1.5 ms ± 0.6 ms
16 ms ± 4 ms
32 ms ± 4 ms
64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum
assertion width of the SLP_S4# signal to ensure that the DRAMs have been safely
power-cycled.
Valid values are:
5:4
11
10
01
00
=
=
=
=
1
2
3
4
to
to
to
to
2
3
4
5
seconds
seconds
seconds
seconds
This value is used in two ways:
1.
If the SLP_S4# assertion width is ever shorter than this time, a status bit is set
for BIOS to read when S0 is entered.
2.
If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal
from deasserting within this minimum time period after asserting.
RTCRST# forces this field to the conservative default state (00b)
SLP_S4# Assertion Stretch Enable — R/W.
3
0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.
1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this
register.
This bit is cleared by RTCRST#
422
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
Description
2
RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates
a weak or missing battery. The bit is not cleared by any type of reset. The bit will
remain set until the software clears it by writing a 0 back to this bit position.
Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by
any type of reset except RTCRST#.
1
0 = Indicates that the trickle current has not failed since the last time the bit was
cleared. Software clears this bit by writing a 1 to it.
1 = Indicates that the trickle current (from the main battery or trickle supply) was
removed or failed.
NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied
after a power failure (G3 state). This bit is in the RTC well and is not cleared by any
type of reset except writes to CF9h or RTCRST#.
0
0 = System will return to S0 state (boot) after power is re-applied.
1 = System will return to the S5 state (except if it was in S4, in which case it will return
to S4). In the S5 state, the only enabled wake event is the Power Button or any
enabled wake event that was preserved through the power failure.
NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC
clock period may not be detected by the ICH7.
Intel ® ICH7 Family Datasheet
423
LPC Interface Bridge Registers (D31:F0)
10.8.1.4
Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0) (Mobile/Ultra Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
A9h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
This register is used to enable new C-state related modes.
Bit
7
6:5
Description
SCRATCHPAD (SP) — R/W.
Reserved
Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME
bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.
4
0 = The Intel® ICH7-M/ICH7-U will not attempt to automatically return to a previous
C3 or C4 state.
1 = When this bit is a 1 and ICH7-M/ICH7-U observes that there are no bus master
requests, it can return to a previous C3 or C4 state.
NOTE: This bit is separate from the PUME bit to cover cases where latency issues
permit POPUP but not POPDOWN.
Popup Mode Enable (PUME) — R/W. When this bit is a 0, the ICH7-M/ICH7-U
behaves like ICH5, in that bus master traffic is a break event, and it will return from
C3/C4 to C0 based on a break event. See Chapter 5.14.5 for additional details on this
mode.
3
0 = The ICH7 will treat Bus master traffic a break event, and will return from C3/C4 to
C0 based on a break event.
1 = When this bit is a 1 and ICH7 observes a bus master request, it will take the
system from a C3 or C4 state to a C2 state and auto enable bus masters. This will
let snoops and memory access occur.
Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.
0 = The ICH7 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from
PCI, PCI Express* and internal bus masters.
1 = When this bit is a 1, ICH7 will not set the BM_STS if there is bus master activity
from PCI, PCI Express and internal bus masters.
2
1:0
424
NOTES:
1.
If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the
BM_STS bit will remain set. Software will still need to clear the BM_STS bit.
2.
It is expected that if the PUME bit (this register, bit 3) is set, the
BM_STS_ZERO_EN bit should also be set. Setting one without the other would
mainly be for debug or errata workaround.
3.
BM_STS will be set by LPC DMA (Mobile Only) or LPC masters, even if
BM_STS_ZERO_EN is set.
Reserved
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.1.5
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile/Ultra Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
AAh
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
This register is used to enable C-state related modes.
Bit
7:4
Description
Reserved
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the Intel®
ICH7-M/ICH7-U waits for from the deassertion of DPRSLPVR to the deassertion of
STP_CPU#. This provides a programmable time for the processor’s voltage to stabilize
when exiting from a C4 state. This changes the value for t266.
3:2
Bits
t266min
t266max
00b
95 µs
101 µs
01b
22 µs
28 µs
10b
34 µs
40 µs
11b
Comment
Default
Value used for “Fast” VRMs
Recommended Value
Reserved
DPSLP-TO-SLP — R/W. This field selects the DPSLP# deassertion to CPU_SLP#
deassertion time (t270). Normally this value is determined by the
CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,
then the values in this register have higher priority. It is software’s responsibility to
program these fields in a consistent manner.
1:0
Intel ® ICH7 Family Datasheet
Bits
t270
00b
Use value in CPU_PLL_LOCK_TIME field (default is 30 µs)
01b
20 µs
10b
15 µs (Recommended Value)
11b
10 µs
425
LPC Interface Bridge Registers (D31:F0)
10.8.1.6
BM_BREAK_EN Register (PM—D31:F0) (Mobile/Ultra Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
ABh
00h
No
Core
Bit
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
Description
IDE_BREAK_EN — R/W.
7
0 = Parallel IDE or Serial ATA traffic will not act as a break event.
1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STSZERO_EN and POPUP_EN bits are set. Parallel IDE or Serial ATA master activity
will cause BM_STS to be set and will cause a break from C3/C4.
PCIE_BREAK_EN — R/W.
6
(Mobile
Only)
6
(Ultra
Mobile
Only)
0 = PCI Express* traffic will not act as a break event.
1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and
POPUP_EN bits are set. PCI Express master activity will cause BM_STS to be set
and will cause a break from C3/C4.
Reserved
PCI_BREAK_EN — R/W.
5
4:3
0 = PCI traffic will not act as a break event.
1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN
bits are set. PCI master activity will cause BM_STS to be set and will cause a
break from C3/C4.
Reserved
EHCI_BREAK_EN — R/W.
2
0 = EHCI traffic will not act as a break event.
1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN
bits are set. EHCI master activity will cause BM_STS to be set and will cause a
break from C3/C4.
UHCI_BREAK_EN — R/W.
1
0 = UHCI traffic will not act as a break event.
1 = USB traffic from any of the internal UHCIs acts as a break event, even if the
BM_STS-ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause
BM_STS to be set and will cause a break from C3/C4.
ACAZ_BREAK_EN — R/W.
0
0 = AC ‘97 or Intel® High Definition Audio traffic will not act as a break event.
1 = AC ‘97 or Intel High Definition Audio traffic acts as a break event, even if the
BM_STS-ZERO_EN and POPUP_EN bits are set. AC ‘97 or Intel High Definition
Audio master activity will cause BM_STS to be set and will cause a break from
C3/C4.
NOTE: For ICH7-U Ultra Mobile, only Intel High Definition is supported, AC ‘97 is not
supported.
426
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.1.7
MSC_FUN—Miscellaneous Functionality Register
(PM—D31:F0)
Offset Address: ADh
Default Value:
00h
Power Well:
Resume
Bit
10.8.1.8
Attribute:
Size:
R/W
8-bit
Description
7:2
Reserved
1:0
USB Transient Disconnect Detect (TDD) — R/W: This field prevents a short SingleEnded Zero (SE0) condition on the USB ports from being interpreted by the UHCI host
controller as a disconnect. BIOS should set to 11b.
EL_STS—Intel® Quick Resume Technology Status Register (PM—
D31:F0) (ICH7DH Only)
Offset Address: B0h
Default Value:
00h
Power Well:
Resume
Bit
7:5
4
Attribute:
Size:
R/WC, RO
8-bit
Description
Reserved
EL_SCI_NOW_STS— R/WC: This bit goes active when software writes a 1 to
EL_CNT1.SCI_NOW_CNT. It can be enabled to cause an SCI which will allow the Intel
Quick Resume Technology (QRT) software to transition the reaction to an Intel QRT
event from an SMI# handler to an SCI handler. This bit remains set until a 1 is written
to this bit position.
Once a 1 is written to this bit position, the logic will “re-arm” to allow the bit to be set
on the next write of 1 to SCI_NOW_CNT (Offset B1h:Bit 8).
3
EL_PB_SCI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from
high-to-low (post-debounce). It can be enabled to cause an SCI that will allow the
Intel QRT software to see when the power button has been pressed. It is a separate bit
from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide
any indication to other (i.e. Intel QRT) software.
The Intel QRT software clears EL_PB_SCI_STS by writing a 1 to this bit position.
2
1
Reserved
EL_PB_SMI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from
high-to-low (post-debounce). It can be enabled to cause an SMI# that will allow the
Intel QRT software to see when the power button has been pressed. It is a separate bit
from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide
any indication to other (i.e., Intel QRT) software.
The Intel QRT software clears EL_PB_SMI_STS by writing a 1 to this bit position.
0
Reserved.
Intel ® ICH7 Family Datasheet
427
LPC Interface Bridge Registers (D31:F0)
10.8.1.9
EL_CNT1—Intel® Quick Resume Technology Control 1 Register (PM—
D31:F0) (ICH7DH Only)
Offset Address: B1h-B2h
Default Value:
F000h
Power Well:
Resume
Bit
15:10
Attribute:
Size:
R/W, RO, WO
16-bit
Description
Reserved
SMI_OPTION_CNT—R/W:
9
8
0 = Disable. Platform does Not generate an SMI when an Intel Quick Resume
Technology (QRT) event occurs
1 = Enable. Platform generates an SMI when an Intel QRT event occurs (rather than
generating an SCI). The SMI handler can cause the SCI by setting the
SCI_NOW_CNT.
SCI_NOW_CNT—WO: When software writes a 1 to this bit, it causes
EL_SCI_NOW_STS (Offset B0:Bit 4) to assert (which can be enabled to cause an SCI).
This allows the SMI handler to cause the SCI.
PWRBTN_INT_EN—R/W:
7
0 = Disable.
1 = Enable. The Intel QRT logic is enabled to intercept the power button to cause the
Intel QRT SMI or SCI, and not immediately setting the PWRBTN_STS bit. The Intel
QRT software will later set the PWRBTN_STS bit by setting the PWRBTN_EVNT bit.
NOTE: This bit is effective only in S0.
PWRBTN_EVNT—WO: When this bit is set to 1 by software, the PWRBTN_STS bit is
set to 1. This allows software to communicate PWR_BTN event to OS.
6
NOTES:
1.
Power Button override still possible
2.
Software does not need to clear this bit, as it is treated as an event
EL_STATE1_CNT[1:0]—R/W: These bits controls the EL_STATE1 pin. The
EL_STATE[1:0] pins can be used to control a multi color LED to indicate the platform
power states to user. If EL_LED_OWN is 0 then these bits have no impact.
5:4
00 = Low
01 = High
10 = Blinking. Note that the blink rate is ~ 1 Hz
11 = Reserved. Software must not set this combination
EL_STATE0_CNT[1:0]—R/W: These bits controls the EL_STATE0 pin. The
EL_STATE[1:0] pins can be used to control a multi-color LED to indicate the platform
power states to user. If EL_LED_OWN is 0 then these bits have no impact.
3:2
00 = Low
01 = High
10 = Blinking. Note that the blink rate is ~ 1 Hz
11 = Reserved. Software must not set this combination
428
1
EL_LED_OWN—R/W: Software sets this bit to 1 to configure the multiplexed pins to
be EL_STATE[1:0] rather than GPIO[28:27].
0
Reserved
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.1.10
EL_CNT2—Intel® Quick Resume Technology Control 2 Register (PM—
D31:F0) (ICH7DH Only)
Offset Address: B3h
Default Value:
00h
Power Well:
RTC
Attribute:
Size:
Bit
7:1
R/W, RO
8-bit
Description
Reserved
Intel Quick Resume Technology Enable (EL_EN)—R/W: This bit enables Intel
Quick Resume Technology.
0
0 = Disabled
1 = Enabled
When this bit is 0, the R/W bits of Intel Quick Resume Technology Control Registers
(EL_CNT1, EL_CNT2) scratchpad with no effect on hardware functions. Also, WO bits
have no effect on hardware functions.
BIOS software is expected to set this bit after booting. Default value for this bit is 0.
10.8.1.11
GPIO_ROUT—GPIO Routing Control Register
(PM—D31:F0)
Offset Address: B8h – BBh
Default Value:
00000000h
Lockable:
No
Bit
31:30
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Description
GPIO15 Route — R/W. See bits 1:0 for description.
Same pattern for GPIO14 through GPIO3
5:4
GPIO2 Route — R/W. See bits 1:0 for description.
3:2
GPIO1 Route — R/W. See bits 1:0 for description.
GPIO0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the
GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect.
1:0
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
Note:
GPIOs that are not implemented will not have the corresponding bits implemented in
this register.
Intel ® ICH7 Family Datasheet
429
LPC Interface Bridge Registers (D31:F0)
10.8.2
APM I/O Decode
Table 10-10 shows the I/O registers associated with APM support. This register space is
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
Table 10-10. APM Register Map
10.8.2.1
Address
Mnemonic
B2h
APM_CNT
B3h
APM_STS
B2h
00h
No
Core
Bit
7:0
Type
Advanced Power Management Control Port
00h
R/W
Advanced Power Management Status Port
00h
R/W
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Description
Used to pass an APM command between the OS and the SMI handler. Writes to this
port not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
APM_STS—Advanced Power Management Status Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
7:0
430
Default
APM_CNT—Advanced Power Management Control Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
10.8.2.2
Register Name
B3h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Description
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not affected by any other register or function (other than a PCI reset).
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3
Power Management I/O Registers
Table 10-11 shows the registers associated with ACPI and Legacy power management
support. These registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers
are defined to support the ACPI 2.0 specification, and use the same bit names.
Note:
All reserved bits and registers will always return 0 when read, and will have no effect
when written.
Table 10-11. ACPI and Legacy I/O Register Map (Sheet 1 of 2)
PMBASE
+ Offset
Mnemonic
00h–01h
PM1_STS
02h–03h
Register Name
ACPI Pointer
Default
Type
PM1 Status
PM1a_EVT_BLK
0000h
R/WC
PM1_EN
PM1 Enable
PM1a_EVT_BLK+2
0000h
R/W
PM1a_CNT_BLK
00000000h
R/W, WO
PMTMR_BLK
xx000000h
RO
—
—
—
P_BLK
00000000h
R/W, RO, WO
04h–07h
PM1_CNT
PM1 Control
08h–0Bh
PM1_TMR
PM1 Timer
0Ch–0Fh
—
10h–13h
PROC_CNT
14h–16h
—
Reserved
Processor Control
Reserved (Desktop Only)
—
—
—
P_BLK+4
00h
RO
14h
LV2
Level 2 (Mobile/Ultra
Mobile Only)
15h
LV3
Level 3 (Mobile/Ultra
Mobile Only)
P_BLK+5
00h
RO
16h
LV4
Level 4 (Mobile/Ultra
Mobile Only)
P_BLK+6
00h
RO
17h–1Fh
—
Reserved
—
—
—
20h
—
Reserved (Desktop Only)
—
—
—
20h
PM2_CNT
PM2 Control (Mobile/
Ultra Mobile Only)
PM2a_CNT_BLK
00h
R/W
28h–2Bh
GPE0_STS
General Purpose Event 0
Status
GPE0_BLK
00000000h
R/WC
2Ch–2Fh
GPE0_EN
General Purpose Event 0
Enables
GPE0_BLK+4
00000000h
R/W
30h–33h
SMI_EN
SMI# Control and Enable
00000000h
R/W, WO,
R/W (special)
34h–37h
SMI_STS
SMI Status
00000000h
R/WC, RO
38h–39h
ALT_GP_SMI_EN
Alternate GPI SMI Enable
0000h
R/W
3Ah–3Bh
ALT_GP_SMI_ST
S
Alternate GPI SMI Status
0000h
R/WC
3Ch–41h
—
—
—
42h
GPE_CNTL
00h
RO, R/W
43h
—
—
—
44h–45h
DEVACT_STS
0000h
R/WC
46h–4Fh
—
Intel ® ICH7 Family Datasheet
Reserved
—
General Purpose Event
Control
Reserved
Device Activity Status
—
Reserved
431
LPC Interface Bridge Registers (D31:F0)
Table 10-11. ACPI and Legacy I/O Register Map (Sheet 2 of 2)
PMBASE
+ Offset
Mnemonic
Register Name
50h
—
Reserved (Desktop Only)
50h
SS_CNT
51h–5Fh
—
54h–57h
C3_RES
60h–7Fh
—
10.8.3.1
ACPI Pointer
Intel SpeedStep®
Technology Control
(Mobile/Ultra Mobile
Only)
Reserved
C3-Residency Register
(Mobile/Ultra Mobile
Only)
Reserved for TCO
—
—
—
Default
Type
01h
R/W (special)
—
—
00000000h
RO, R/W
—
—
PM1_STS—Power Management 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
No
Bits 0–7: Core,
Bits 8–15: Resume,
except Bit 11 in RTC
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN
register, then the ICH7 will generate a Wake Event. Once back in an S0 state (or if
already in an S0 state when the event occurs), the ICH7 will also generate an SCI if the
SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.
Note:
432
Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
can cause an SMI# or SCI.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
Description
Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused
by a CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN
bit) and an enabled wake event occurs. Upon setting this bit, the Intel® ICH7 will
transition the system to the ON state.
15
If the AFTERG3_EN bit is not set and a power failure (such as removed batteries on a
mobile/Ultra Mobile platform) occurs without the SLP_EN bit set, the system will
return to an S0 state when power returns, and the WAK_STS bit will not be set.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit
having been set, the system will go into an S5 state when power returns, and a
subsequent wake event will cause the WAK_STS bit to be set. Note that any
subsequent wake event would have to be caused by either a Power Button press, or
an enabled wake event that was preserved through the power failure (enable bit in
the RTC well).
PCI Express Wake Status (PCIEXPWAK_STS) — R/WC.
14
(Desktop
and
Mobile
Only)
0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during
the write or the PME message received indication has not been cleared in the
root port, then the bit will remain active (i.e. all inputs to this bit are levelsensitive).
1 = This bit is set by hardware to indicate that the system woke due to a PCI Express
wakeup event. This wakeup event can be caused by the PCI Express WAKE# pin
being active or receipt of a PCI Express PME message at a root port. This bit is
set only when one of these events causes the system to transition from a non-S0
system power state to the S0 system power state. This bit is set independent of
the state of the PCIEXP_WAKE_DIS bit.
NOTE: This bit does not itself cause a wake event or prevent entry to a sleeping
state. Thus, if the bit is 1 and the system is put into a sleeping state, the
system will not automatically wake.
14
(Ultra
Mobile
Only)
Reserved
13:12
Reserved
Power Button Override Status (PRBTNOR_STS) — R/WC.
11
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (i.e., the power button is
pressed for at least 4 consecutive seconds), or due to the corresponding bit in
the SMBus slave message. The power button override causes an unconditional
transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI
handler clears this bit by writing a 1 to it. This bit is not affected by hard resets
via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved
through power failures. Note that if this bit is still asserted when the global
SCI_EN is set then an SCI will be generated.
RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a
CF9 write, but is reset by RSMRST#.
10
9
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8#
signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting
of the RTC_STS bit will generate a wake event.
Reserved
Intel ® ICH7 Family Datasheet
433
LPC Interface Bridge Registers (D31:F0)
Bit
Description
Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard
resets caused by a CF9 write.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears
the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to
the S5 state with only PWRBTN# enabled as a wake event.
8
This bit can be cleared by software by writing a one to the bit position.
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low,
independent of any other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or
SMI# if SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and
PWRBTN_STS are both set, a wake event is generated.
NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is
sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN#
signal must go inactive and active again to set the PWRBTN_STS bit.
7:6
Reserved
Global Status (GBL _STS) — R/WC.
5
4
(Desktop
Only)
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI
handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and
set this bit.
Reserved
Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI or
SMI#.
4
(Mobile/
Ultra
Mobile
Only)
3:1
0 = Software clears this bit by writing a 1 to it.
1 = Set by the Intel® ICH7-M/ICH7-U when a bus master requests access to main
memory. Bus master activity is detected by any of the PCI Requests being active,
any internal bus master request being active, the BM_BUSY# signal being active,
or REQ-C2 message received while in C3 or C4 state.
NOTES:
1.
If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0.
LPC DMA (Mobile Only) and bus master activity will always set the BM_STS
bit, even if the BM_STS_ZERO_EN bit is set.
Reserved
Timer Overflow Status (TMROF_STS) — R/WC.
0
434
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered
from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit
(PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will
additionally generate an SCI or SMI# (depending on the SCI_EN).
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3.2
PM1_EN—Power Management 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 02h
(ACPI PM1a_EVT_BLK + 2) Attribute:
0000h
Size:
No
Usage:
Bits 0–7: Core,
Bits 8–9, 11–15: Resume,
Bit 10: RTC
Bit
15
14
(Desktop
and
Mobile
Only)
R/W
16-bit
ACPI or Legacy
Description
Reserved
PCI Express Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit
has no impact on the value of the PCIEXP_WAKE_STS bit.
0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake
the system.
1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from
waking the system.
14
(Ultra
Mobile
Only)
Reserved
13:11
Reserved
RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC
event to wake after a power failure. This bit is not cleared by any reset other than
RTCRST# or a Power Button Override event.
10
9
8
0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit
10) goes active.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS
bit goes active.
Reserved.
Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the
setting of the PWRBTN_STS bit to generate a power management event (SMI#,
SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8)
being set by the assertion of the power button. The Power Button is always enabled
as a Wake event.
0 = Disable.
1 = Enable.
7:6
5
4:1
Reserved.
Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit
(PMBASE + 00h, bit 5) are set, an SCI is raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
Reserved.
Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction
with the SCI_EN bit (PMBASE + 04h, bit 0) as described below:
0
Intel ® ICH7 Family Datasheet
TMROF_EN
SCI_EN
Effect when TMROF_STS is set
0
X
No SMI# or SCI
1
0
SMI#
1
1
SCI
435
LPC Interface Bridge Registers (D31:F0)
10.8.3.3
PM1_CNT—Power Management 1 Control
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
00000000h
No
Bits 0–7: Core,
Bits 8–12: RTC,
Bits 13–15: Resume
Bit
31:14
13
Attribute:
Size:
Usage:
R/W, WO
32-bit
ACPI or Legacy
Description
Reserved.
Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into
the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system
should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
Code
Master Interrupt
000b
ON: Typically maps to S0 state.
001b
Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to
assert CPUSLP# to put processor in sleep state: Typically, maps to S1
state.
010b
Reserved
011b
Reserved
100b
Reserved
12:10
9:3
101b
Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
110b
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to
S4 state.
Reserved.
Soft Off Assert SLP S3# SLP S4# and SLP S5#: Typically maps to
Global Release (GBL_RLS) — WO.
2
1
(Desktop
Only)
1
(Mobile/
Ultra
Mobile
Only)
0
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software
has a corresponding enable and status bits to control its ability to receive ACPI
events.
Reserved
Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This
bit is reset to 0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enable Bus Master requests (internal, external or BM_BUSY#) to cause a break
from the C3 state.
If software fails to set this bit before going to C3 state, the Intel® ICH7-M/ICH7-U will
still return to a snoopable state from C3 or C4 states due to bus master activity.
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in
GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
436
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3.4
PM1_TMR—Power Management 1 Timer Register
I/O Address:
PMBASE + 08h
(ACPI PMTMR_BLK)
Default Value:
Lockable:
Power Well:
xx000000h
No
Core
Bit
31:24
23:0
Attribute:
Size:
Usage:
RO
32-bit
ACPI
Description
Reserved
Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This
counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0
during a PCI reset, and then continues counting as long as the system is in the S0
state. After an S1 state, the counter will not be reset (it will continue counting from the
last value in S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the
TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur
every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI
interrupt is also generated.
10.8.3.5
PROC_CNT—Processor Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
31:18
PMBASE + 10h
(ACPI P_BLK)
Attribute:
00000000h
Size:
No (bits 7:5 are write once)Usage:
Core
R/W, RO, WO
32-bit
ACPI or Legacy
Description
Reserved
Throttle Status (THTL_STS) — RO.
17
16:9
0 = No clock throttling is occurring (maximum processor performance).
1 = Indicates that the clock state machine is throttling the processor performance. This
could be due to the THT_EN bit or the FORCE_THTL bit being set.
Reserved
Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force
the thermal throttling function.
8
0 = No forced throttling.
1 = Throttling at the duty cycle specified in THRM_DTY starts immediately, and no
SMI# is generated.
Intel ® ICH7 Family Datasheet
437
LPC Interface Bridge Registers (D31:F0)
Bit
Description
THRM_DTY — WO. This write-once field determines the duty cycle of the throttling
when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage
of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK#
throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in
the C0 state. For mobile/Ultra Mobile only, If in the C2, C3, or C4 state, no throttling
occurs.
Once the THRM_DTY field is written, any subsequent writes will have no effect until
PLTRST# goes active.
7:5
4
THRM_DTY
000b
001b
010b
011b
100b
101b
110b
111b
Throttle Mode
50% (Default)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
512
896
768
640
512
384
256
128
THTL_EN — R/W. When set and the system is in a C0 state, it enables a processorcontrolled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.
0 = Disable
1 = Enable
THTL_DTY — R/W. This field determines the duty cycle of the throttling when the
THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle
period is 1024 PCICLKs.
3:1
0
438
THTL_DTY
000b
001b
010b
011b
100b
101b
110b
111b
Throttle Mode
50% (Default)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
512
896
768
640
512
384
256
128
Reserved
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3.6
LV2 — Level 2 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
Attribute:
Size:
Usage:
RO
8-bit
ACPI or Legacy
Bit
Description
7:0
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a level 2 power state” (C2) to the clock control logic. This will
cause the STPCLK# signal to go active, and stay active until a break event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
NOTE: This register should not be used by Intel® iA64 processors or systems with more than 1
logical processor, unless appropriate semaphoring software has been put in place to ensure
that all threads/processors are ready for the C2 state when the “read to this register”
instruction occurs.
10.8.3.7
LV3—Level 3 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
Bit
7:0
PMBASE + 15h (ACPI P_BLK + 5)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C3 power state” to the clock control logic. The C3 state
persists until a break event occurs.
NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a
LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and
LVL3 registers (which is not permitted), the Intel® ICH7-M/ICH7-U will ignore the LVL3
read, and only perform a C2 transition.
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C3 state when the “read to this register”
instruction occurs.
10.8.3.8
LV4—Level 4 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
Bit
7:0
PMBASE + 16h (ACPI P_BLK + 6)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
register generate a “enter a C4 power state” to the clock control logic. The C4 state
persists until a break event occurs.
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C4 state when the “read to this register”
instruction occurs.
Intel ® ICH7 Family Datasheet
439
LPC Interface Bridge Registers (D31:F0)
10.8.3.9
PM2_CNT—Power Management 2 Control Register (Mobile/Ultra
Mobile Only)
I/O Address:
PMBASE + 20h
(ACPI PM2_BLK)
00h
No
Core
Default Value:
Lockable:
Power Well:
Bit
7:1
0
10.8.3.10
Attribute:
Size:
Usage:
R/W
8-bit
ACPI
Description
Reserved
Arbiter Disable (ARB_DIS) — R/W. This bit is a scratchpad bit for legacy software
compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state.
When a transition to a C3 or C4 state occurs, Intel® ICH7-M/ICH7-U will automatically
prevent any internal or external non-Isoch bus masters from initiating any cycles up to
the (G)MCH. This blocking starts immediately upon the ICH7 sending the Go–C3
message to the (G)MCH. The blocking stops when the Ack-C2 message is received.
Note that this is not really blocking, in that messages (such as from PCI Express*) are
just queued and held pending.
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 28h
(ACPI GPE0_BLK)
00000000h
No
Resume
Attribute:
Size:
Usage:
R/WC
32-bit
ACPI
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, the ICH7 will generate a Wake Event. Once back in an S0 state (or if already in
an S0 state when the event occurs), the ICH7 will also generate an SCI if the SCI_EN
bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are
reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#.
Bit
Description
GPIOn_STS — R/WC.
31:16
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
GPIO[n]_STS bit is set:
•
•
If the system is in an S1–S5 state, the event will also wake the system.
If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16
corresponds to GPIO0.
15
Reserved
USB4_STS — R/WC.
14
440
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set when USB UHCI controller #4 needs to cause a
wake. Additionally if the USB4_EN bit is set, the setting of the USB4_STS bit will
generate a wake event.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
13
Description
PME_B0_STS — R/WC. This bit will be set to 1 by the Intel® ICH7 when any internal
device with PCI Power Management capabilities on bus 0 asserts the equivalent of the
PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an S0
state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if
SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4 state
(or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit
will generate a wake event, and an SCI (or SMI# if SCI_EN is not set) will be
generated. If the system is in an S5 state due to power button override, then the
PME_B0_STS bit will not cause a wake event or SCI.
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
USB3_STS — R/WC.
12
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set when USB UHCI controller #3 needs to cause a
wake. Additionally if the USB3_EN bit is set, the setting of the USB3_STS bit will
generate a wake event.
PME_STS — R/WC.
11
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN
bit is set, and the system is in an S0 state, then the setting of the PME_STS bit
will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and
the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and
SLP_EN), then the setting of the PME_STS bit will generate a wake event, and an
SCI will be generated. If the system is in an S5 state due to power button
override or a power failure, then PME_STS will not cause a wake event or SCI.
Intel® ICH7DH Only:
10
(Desktop
Only)
EL_SCI_STS — R/WC. In Desktop Mode, when Intel Quick Resume Technology
feature is enabled, this bit will be set by hardware when the SCI_NOW_CNT or
EL_PB_SCI_STS bit goes high. Software clears the bit by writing a 1 to the bit
position.
In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit
will be treated as Reserved.
ICH7 and ICH7R Only:
Reserved
10
(Mobile/
Ultra
Mobile
Only)
BATLOW_STS — R/WC. (Mobile/Ultra Mobile Only) Software clears this bit by
writing a 1 to it.
0 = BATLOW# Not asserted
1 = Set by hardware when the BATLOW# signal is asserted.
Intel ® ICH7 Family Datasheet
441
LPC Interface Bridge Registers (D31:F0)
Bit
Description
PCI_EXP_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
•
•
9
The PME event message was received on one or more of the PCI Express* ports (Desktop and
Mobile Only)
An Assert PMEGPE message received from the (G)MCH via DMI
NOTES:
1.
The PCI WAKE# pin has no impact on this bit.
2.
If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a
Deassert PMEGPE message must be received prior to the software write in
order for the bit to be cleared.
3.
If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the
level-triggered SCI will remain active.
4.
A race condition exists where the PCI Express device sends another PME
message because the PCI Express device was not serviced within the time
when it must resend the message. This may result in a spurious interrupt,
and this is comprehended and approved by the PCI Express* Specification,
Revision 1.0a. The window for this race condition is approximately
95–105 milliseconds.
RI_STS — R/WC.
8
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can
independently cause an SMI# or SCI, so this bit does not need to do so (unlike the
other bits in this register). Software clears this bit by writing a 1 to it.
0 = Wake event Not caused by the ICH7’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the ICH7’s
SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the
system is already awake. The SMI handler should then clear this bit.
7
NOTES:
1.
This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the
system is in the S0 state. Therefore, to avoid an instant wake on subsequent
transitions to sleep states, software must clear this bit after each reception of
the Wake/SMI# command or just prior to entering the sleep state.
2.
If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be
cleared by internal logic when a THRMTRIP# event happens or a Power
Button Override event. However, THRMTRIP# or Power Button Override event
will not clear SMB_WAK_STS if it is set due to SMBALERT# signal going
active.
3.
The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by
software before the SMB_WAK_STS bit is cleared.
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
6
442
0 = TOC logic did Not cause SCI.
1 = Set by hardware when the TCO logic causes an SCI.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
Description
AC97_STS — R/WC. This bit will be set to 1 when the codecs are attempting to wake
the system and the PME events for the codecs are armed for wakeup. A PME is armed
by programming the appropriate PMEE bit in the Power Management Control and
Status register at bit 8 of offset 54h in each AC ’97 function.
5
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the codecs are attempting to wake the system. The
AC97_STS bit gets set only from the following two cases:
1. The PMEE bit for the function is set, and o The AC-link bit clock has been shut
and the routed ACZ_SDIN line is high (for audio, if routing is disabled, no
wake events are allowed).
2. For modem, if audio routing is disabled, then the wake event is an OR of all
ACZ_SDIN lines. If routing is enabled, then the wake event for modem is the
remaining non-routed ACZ_SDIN line), or o GPI Status Change Interrupt bit
(NABMBAR + 30h, bit 0) is 1.
NOTES:
1.
This bit is not affected by a hard reset caused by a CF9h write.
2.
This bit is also used for Intel® High Definition Audio when ICH7 is configured
to use the Intel High Definition Audio host controller rather than the AC97
host controller.
3.
For ICH7 Ultra Mobile, only Intel High Definition is supported, AC ‘97 is not
supported.
USB2_STS — R/WC. Software clears this bit by writing a 1 to it.
4
0 = USB UHCI controller 2 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event
will be generated if the corresponding USB2_EN bit is set.
USB1_STS — R/WC. Software clears this bit by writing a 1 to it.
3
2
1
(Desktop
and
Mobile
Only)
1
(Ultra
Mobile
Only)
0 = USB UHCI controller 1 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event
will be generated if the corresponding USB1_EN bit is set.
SWGPE_STS — R/WC.
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
HOT_PLUG_STS — R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the
HOT_PLUG_EN bit is set in the GEP0_EN register.
Reserved
Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0
0 = THRM# signal Not driven active as defined by the THRM_POL bit
1 = Set by hardware anytime the THRM# signal is driven active as defined by the
THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the
THRM_STS bit will also generate a power management event (SCI or SMI#).
Intel ® ICH7 Family Datasheet
443
LPC Interface Bridge Registers (D31:F0)
10.8.3.11
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
Attribute:
00000000h
Size:
No
Usage:
Bits 0–7, 9, 12, 14–31 Resume,
Bits 8, 10–11, 13 RTC
R/W
32-bit
ACPI
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override or processor
Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits
are cleared by RTCRST#.
Bit
Description
31:16
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16
corresponds to GPIO0.
15
Reserved
USB4_EN — R/W.
14
0 = Disable.
1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS
bit is set anytime USB UHCI controller #4 signals a wake event. Break events are
handled via the USB interrupt.
PME_B0_EN — R/W.
13
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an
SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from
S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
12
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS
bit is set anytime USB UHCI controller #3 signals a wake event. Break events are
handled via the USB interrupt.
PME_EN — R/W.
11
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered via
SLP_EN, but not power button override).
ICH7DH Only:
10
(Desktop
Only)
EL_SCI_EN — R/W. In Desktop Mode with Intel Quick Resume Technology feature
enabled, this bit enables the EL_SCI_STS signal to cause an SCI (depending on the
SCI_EN bit) when it is asserted.
In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit
will be treated as Reserved.
ICH7 and ICH7R Only:
Reserved
444
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
Description
10
(Mobile/
Ultra
Mobile
Only)
BATLOW_EN — R/W. (Mobile/Ultra Mobile Only)
9
(Desktop
and
Mobile
Only)
PCI_EXP_EN — R/W.
9
(Ultra
Mobile
Only)
8
7
0 = Disable.
1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN
bit) when it goes low. This bit does not prevent the BATLOW# signal from
inhibiting the wake event.
0 = Disable SCI generation upon PCI_EXP_STS bit being set.
1 = Enables Intel® ICH7 to cause an SCI when PCI_EXP_STS bit is set. This is used to
allow the PCI Express* ports, including the link to the (G)MCH, to cause an SCI
due to wake/PME events.
Reserved. Must be programmed to 0.
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not
affected by a hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved
TCOSCI_EN — R/W.
6
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN — R/W.
5
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
NOTE: This bit is also used for Intel® High Definition Audio when the Intel High
Definition Audio host controller is enabled rather than the AC97 host
controller.
USB2_EN — R/W.
4
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN — R/W.
3
2
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
SWGPE_EN— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is
written to a 1, hardware will set SWGPE_STS (acts as a level input)
If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated
If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1, then an
SMI# will be generated
Intel ® ICH7 Family Datasheet
445
LPC Interface Bridge Registers (D31:F0)
Bit
1
(Desktop
and
Mobile
Only)
1
(Ultra
Mobile
Only)
Description
HOT_PLUG_EN — R/W.
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1 = Enables the Intel® ICH7 to cause an SCI when the HOT_PLUG_STS bit is set. This
is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
Reserved
THRM_EN — R/W.
0
446
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set
the THRM_STS bit and generate a power management event (SCI or SMI).
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3.12
SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
Note:
PMBASE + 30h
00000000h
No
Core
Attribute:
Size:
Usage:
R/W, R/W (special), WO
32 bit
ACPI or Legacy
This register is symmetrical to the SMI status register.
Bit
31:26
Description
Reserved
Intel® ICH7DH Only:
EL_SMI_EN — R/W.
0 = Disable
25
1 = Software sets this bit to enable Intel Quick Resume Technology logic to cause
SMI#
ICH7 and ICH7R and Mobile/Ultra Mobile Only:
Reserved
24:19
Reserved
INTEL_USB2_EN — R/W.
18
0 = Disable
1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.
LEGACY_USB2_EN — R/W.
17
0 = Disable
1 = Enables legacy USB2 logic to cause SMI#.
16:15
Reserved
PERIODIC_EN — R/W.
14
0 = Disable.
1 = Enables the Intel® ICH7 to generate an SMI# when the PERIODIC_STS bit
(PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
TCO_EN — R/W.
13
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is
set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN
bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
12
Reserved
MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.
11
10:8
Intel ® ICH7 Family Datasheet
0 = Disable.
1 = Enables ICH7 to trap accesses to the microcontroller range (62h or 66h) and
generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH7 on
PCI, but not forwarded to LPC.
Reserved
447
LPC Interface Bridge Registers (D31:F0)
Bit
Description
BIOS Release (BIOS_RLS) — WO.
7
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is
written to this bit position by BIOS software.
NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.
Software must take great care not to set the BIOS_RLS bit (which causes
GBL_STS to be set) if the SCI handler is not in place.
Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W.
6
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset
the timer and the SMI# will not be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout
period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is
set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by
software.
APMC_EN — R/W.
5
0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
SLP_SMI_EN — R/W.
4
0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0
before the software attempts to transition the system into a sleep state by
writing a 1 to the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an
SMI#, and the system will not transition to the sleep state based on that write
to the SLP_EN bit.
LEGACY_USB_EN — R/W.
3
0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
BIOS_EN — R/W.
2
0 = Disable.
1 = Enables the generation of SMI# when ACPI software writes a 1 to the
GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit
(D31:F0:PMBase + 34h:bit 2), which gets set when software writes 1 to
GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# will
be generated when BIOS_EN gets set.
End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI
signal to the processor. This bit must be set for the Intel® ICH7 to assert SMI# low
to the processor after SMI# has been asserted previously.
1
0 = Once the ICH7 asserts SMI# low, the EOS bit is automatically cleared.
1 = When this bit is set to 1, SMI# signal will be deasserted for 4 PCI clocks before
its assertion. In the SMI handler, the processor should clear all pending SMIs
(by servicing them and then clearing their respective status bits), set the EOS
bit, and exit SMM. This will allow the SMI arbiter to re-assert SMI upon
detection of an SMI event and the setting of a SMI status bit.
NOTE: ICH7 is able to generate 1st SMI after reset even though EOS bit is not set.
Subsequent SMI require EOS bit is set.
GBL_SMI_EN — R/W.
0
448
0 = No SMI# will be generated by ICH7. This bit is reset by a PCI reset event.
1 = Enables the generation of SMI# in the system upon any enabled SMI event.
NOTE: When the SMI_LOCK bit is set, this bit cannot be changed.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3.13
SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
Note:
PMBASE + 34h
00000000h
No
Core
Attribute:
Size:
Usage:
RO, R/WC
32-bit
ACPI or Legacy
If the corresponding _EN bit is set when the _STS bit is set, the ICH7 will cause an
SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs
of other registers that have enable bits). The ICH7 uses the same GPE0_EN register (I/
O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose
input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec.
Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS,
and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns
off the enabled bit for any GPIx input signals that are not indicated as SCI generalpurpose events at boot, and exit from sleeping states. BIOS should define a dummy
control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.
Bit
31:27
26
(Desktop
and Mobile
Only)
26
(Ultra
Mobile
Only)
Description
Reserved
SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit
is read only because the sticky status and enable bits associated with this function
are located in the SPI registers.
Reserved
Intel® ICH7DH Only:
25
(Desktop
Only)
EL_SMI_STS — RO. This bit will be set if the Intel Quick Resume Technology logic
is generating an SMI#. Writing a 1 to this bit clears this bit to ‘0’.
ICH7 and ICH7R Only:
Reserved.
25
(Mobile
Only)
Reserved
24:22
Reserved
21
MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the
SMI. This will occur when the processor or a bus master accesses an assigned
register (or a sequence of accesses). See Section 7.1.36 through Section 7.1.39
for details on the specific cause of the SMI.
20
(Desktop
and Mobile
Only)
PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due
to a PCI Express PME event or Hot-Plug event.
20
(Ultra
Mobile
Only)
Reserved
19
Reserved
Intel ® ICH7 Family Datasheet
449
LPC Interface Bridge Registers (D31:F0)
Bit
Description
18
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of
the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
17
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each
of the SMI status bits in the USB2 Legacy Support Register ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by
writing a 1 to it.
16
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software
must wait at least 15.63 us after the initial assertion of this bit before clearing
it.
1 = Indicates that the SMI# was caused by:
1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
3. The SMBus Slave receiving a Host Notify message and the
HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or
4. The ICH7 detecting the SMLINK_SLAVE_SMI command while in the S0
state.
SERIRQ_SMI_STS — RO.
15
0 = SMI# was not caused by the SERIRQ decoder.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
14
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the
PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the Intel® ICH7
generates an SMI#.
TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
13
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake
event.
Device Monitor Status (DEVMON_STS) — RO.
12
0 = SMI# not caused by Device Monitor.
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not
sticky, so writes to this bit will have no effect.
Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit
by writing a 1 to it.
11
450
0 = Indicates that there has been no access to the power management
microcontroller range (62h or 66h).
1 = Set if there has been an access to the power management microcontroller
range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC
Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11).
Note that this implementation assumes that the Microcontroller is on LPC. If
this bit is set, and the MCSMI_EN bit is also set, the ICH7 will generate an
SMI#.
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit
10
Description
GPI_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS
register that are also set up to cause an SMI# (as indicated by the GPI_ROUT
registers) and have the corresponding bit set in the ALT_GP_SMI_EN register.
Bits that are not routed to cause an SMI# will have no effect on this bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
9
GPE0_STS — RO. This bit is a logical OR of the bits 14:10, 8:2, and 0 in the
GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in
the GPE0_EN register (PMBASE + 2Ch).
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
8
7
PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register
(offset PMBASE+00h) that can cause an SMI#.
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
Reserved
SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it.
6
0 = Software SMI# Timer has Not expired.
1 = Set by the hardware when the Software SMI# Timer expires.
APM_STS — R/WC. Software clears this bit by writing a 1 to it.
5
0 = No SMI# generated by write access to APM Control register with APMCH_EN
bit set.
1 = SMI# was generated by a write access to the APM Control register with the
APMC_EN bit set.
SLP_SMI_STS — R/WC. Software clears this bit by writing a 1 to the bit location.
4
3
0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when
SLP_SMI_EN bit is also set.
LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits in
the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding
enable bits. This bit will not be active if the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
BIOS_STS — R/WC.
2
1:0
Intel ® ICH7 Family Datasheet
0 = No SMI# generated due to ACPI software requesting attention.
1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS
bit (D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit
(D31:F0:PMBase + 30h:bit 2) and the BIOS_STS bit are set, an SMI# will be
generated. The BIOS_STS bit is cleared when software writes a 1 to its bit
position.
Reserved
451
LPC Interface Bridge Registers (D31:F0)
10.8.3.14
ALT_GP_SMI_EN—Alternate GPI SMI Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +38h
0000h
No
Resume
Bit
Attribute:
Size:
Usage:
R/W
16-bit
ACPI or Legacy
Description
Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding
GPIO to cause an SMI#. For these bits to have any effect, the following must be true.
15:0
•
•
•
The corresponding bit in the ALT_GP_SMI_EN register is set.
The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
The corresponding GPIO must be implemented.
NOTE: Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to
GPIO0.
10.8.3.15
ALT_GP_SMI_STS—Alternate GPI SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +3Ah
0000h
No
Resume
Bit
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
Description
Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding
GPIOs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
15:0
These bits are sticky. If the following conditions are true, then an SMI# will be
generated and the GPE0_STS bit set:
•
•
•
The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.
The corresponding GPIO must be implemented.
All bits are in the resume well. Default for these bits is dependent on the state of the
GPIO pins.
452
Intel ® ICH7 Family Datasheet
LPC Interface Bridge Registers (D31:F0)
10.8.3.16
GPE_CNTL— General Purpose Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
7:2
1
0
PMBASE +42h
00h
No
Resume
Attribute:
Size:
Usage:
R/W
8-bit
ACPI or Legacy
Description
Reserved
SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the
GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to
SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set
back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of
1 will clear SWGPE_STS to 0.
THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
Intel ® ICH7 Family Datasheet
453
LPC Interface Bridge Registers (D31:F0)
10.8.3.17
DEVACT_STS — Device Activity Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +44h
0000h
No
Core
Attribute:
Size:
Usage:
R/WC
16-bit
Legacy Only
Each bit indicates if an access has occurred to the corresponding device’s trap range, or
for bits 6:9 if the corresponding PCI interrupt is active. This register is used in
conjunction with the Periodic SMI# timer to detect any system activity for legacy power
management. The periodic SMI# timer indicates if it is the right time to read the
DEVACT_STS register (PMBASE + 44h).
Note:
Software clears bits that are set in this register by writing a 1 to the bit position.
Bit
15:13
Description
Reserved
KBC_ACT_STS — R/WC. KBC (60/64h).
12
11:10
0 = Indicates that there has been no access to this device’s I/O range.
1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit
location.
Reserved
PIRQDH_ACT_STS — R/WC. PIRQ[D or H].
9
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQCG_ACT_STS — R/WC. PIRQ[C or G].
8
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQBF_ACT_STS — R/WC. PIRQ[B or F].
7
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQAE_ACT_STS — R/WC. PIRQ[A or E].
6
5:1
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
Reserved
IDE_ACT_STS — R/WC. IDE Primary Drive 0 and Drive 1.
0
454
0 = Indicates that there has been no access to this device’s I/O range.
1 = This device’s I/O range has been accessed. The enable bit is in the ATC register
(D31:F1:Offset C0h). Cle