UCC5950 10-Bit Serial D/A Converter FEATURES DESCRIPTION • 10 Bit Resolution • 1.1µs Output Rise Time • 2.5µs Settling Time to 1% • Single +5V Supply The UCC5950 is a self-contained, microprocessor-compatible 10-bit D/A converter. It contains all of the functions required to take data directly from a threewire serial data bus and convert it to a precise voltage, including: an input shift register, data latches, a precision voltage reference, a precision 10-bit digital to analog converter, and an output buffer amplifier. • Monotonic • Low Power Sleep Mode • Three-wire Serial Interface • 20MHz Data Rate • 8 Pin SOIC and DIL Package The serial data interface is capable of clock frequencies as high as 20MHz, allowing update rates as high as two words per microsecond. The UCC5950 accepts commands encoded as 2’s-complement binary. The data converter in the UCC5950 is inherently monotonic, making this part ideal for use in closed-loop servo control systems as well as open-loop data conversion. The UCC5950 uses a unique segmented data converter which offers differential linearity better than 1 LSB, integral linearity better than 2 LSB, and fast conversion. BLOCK DIAGRAM UDG-95034 2/95 UCC5950 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Input Voltage, Any Input . . . . . . . . . . . . . . . . –0.3V to VDD+0.3V Output Current, Any Output . . . . . . . . . . . . . . . . . . . . . . . . ±5mA Operating Temperature . . . . . . . . . . . . . . . . . . −55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C All voltages with respect to GND. All currents are positive into, negative out of, the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. DIL-8, SOIC-8 (Top View) N or J, D Package ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for 4.5V < VDD < 5.5V, REFOUT Load < 100pF, DACOUT Load < 100pF, 0°C < TA < +70°C, and TA = TJ. PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS OVERALL SECTION Supply Current SLEEP = 0V 1.5 5 mA Supply Current SLEEP = 5V 0.1 10 µA 2.15 2.20 V REFERENCE SECTION REFOUT Output Voltage 2.10 REFOUT Change with VDD 4.5V < VDD < 5.5V 1 10 mV REFOUT Change with Load –1mA < IREFOUT < 1mA 1 10 mV 2 LSB D/A SECTION Integral Nonlinearity (Note 1) Differential Nonlinearity Full Scale Difference from 1.4924 x REF –8 Zero Scale Difference from 0.5089 x REF –8 1 LSB 8 LSB 8 LSB DACOUT Full Scale Rise/Fall Time From 10% to 90% of swing (Note 4) 0.7 1.1 µs DACOUT Full Scale Settling Time (TS) (Note 2, 3, 4) 1.4 2.5 µs DACOUT Change with VDD 4.5V < VDD < 5.5V 1.5 10 mV DACOUT Change with Load –1mA < IDACOUT < 1mA 1.2 10 mV 2.5 3.5 V 5 µA 10 pF LOGIC SECTION Logic Input Threshold 1.5 Logic Input Current 0V < VIN < VDD Logic Input Capacitance (Note 4) SLOD Setup Time to SCLK low (TSLS) (Note 4) 2.7 50 TH ns SLOD Hold Time from SCLK high (TSLH) From 10 50 ns SDIO Setup Time to SCLK high (TDS) (Note 4) 15 ns SDIO Hold Time from SCLK high (TDH) (Note 4) 7 ns SCLK high (Note 4) Note 1: Integral nonlinearity is defined as the worst deviation of the converter output from the best-fit straight line through all converter output codes. Note 2: From 10TH Rising Edge of SCLK. Note 3: Settling time is to 1% of final value. Note 4: Guaranteed by design. Not 100% tested in production. 2 UCC5950 TYPICAL CHARACTERISTICS REFOUT vs Temperature Supply Current vs Temperature DACOUT Rising Full Scale Step Response DACOUT Falling Full Scale Step Response Logic Input Threshold vs Temperature DACOUT Change with DACOUT Load Current 3 UCC5950 PIN DESCRIPTIONS SCLK: Data is clocked into the D/A after SLOD goes low on rising edges of SCLK. After 10 rising edges of SCLK, the data is latched into the D/A output register and the output is updated. Further clock signals on SCLK are ignored until SLOD initiates a new read cycle. DACOUT: The output of the 10-bit D/A Converter. For best settling time, minimize load capacitance. DACOUT will go to a voltage between 1.094V and 3.208V depending on the digital code loaded into the latches. The digital code follows this pattern: Input Code 1000000000 1000000001 1000000010 ... 1111111111 0000000000 0000000001 ... 0111111110 0111111111 Typical DACOUT 1.094V 1.096V 1.098V SDIO: After SLOD goes low, data is clocked into the D/A from the SDIO input, on rising edges of SCLK, LSB first. After 10 rising edges, data is latched and converted, and further SCLK and SDIO information is ignored. Significance Zero Scale SLEEP: SLEEP is the power-down input to the D/A. In systems not requiring this function, wire SLEEP to GND. 2.151V 2.153V 2.155V Mid Scale 3.206V 3.208V SLOD: SLOD is the chip-select input to the UCC5950. SLOD going low selects the D/A and enables clocking of data from SDIO into the D/A. After 10 SCLK pulses, the D/A is updated and SLOD is ignored until SLOD goes high and again goes low. Full Scale GND: All signals are referenced to GND. VDD: All analog and digital functions are powered from VDD. VDD should be a well-regulated supply to minimize output variations. Bypass VDD to GND with a ceramic capacitor very close to the UCC5950. REFOUT: The output of the temperature-compensated 2.15V reference. DO NOT BYPASS REFOUT! For best stability and transient response, minimize capacitance on REFOUT. SERIAL DATA INTERFACE TIMING AND LOGIC TABLE UDG-95035 SLOD Internal Flag SCLK SDIO 1 0 1 don’t care don’t care 0 rising edge DATA 0 0 rising edge DATA 0 1 don’t care don’t care Internal Count UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 4 Action DACOUT 0 no action V(t) <10 Shift In DATA V(t) 10 Latch New DATA Set Internal Flag Reset Count V(t+1) 0 no action V(t) IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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