SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 D D D D D D D D D D D SN54ABT16260 . . . WD PACKAGE SN74ABTH16260 . . . DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 LE2B SEL description The SN54ABT16260 and SN74ABTH16260 are 12-bit to 24-bit multiplexed D-type latches used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE2B LEA2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 LEA1B OE1B Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABT16260 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH16260 is characterized for operation from –40°C to 85°C. Function Tables B TO A (OEB = H) INPUTS 1B 2B SEL LE1B LE2B OEA OUTPUT A H X H H X L H L X H H X L L X X H L X L X H L X H L A0 H X L L X H L L X X L X L L X X X X X H A0 Z A TO B (OEA = H) OUTPUTS INPUTS 2 A LEA1B LEA2B H H H L H H H H L L H L H L H OE1B OE2B 1B 2B L L H H L L L L L L H L L L 2B0 2B0 L L 1B0 1B0 H 2B0 Z L L H L L X L L L L X X X H H 1B0 Z X X X L H Active Z X X X H L Z Active X X X L L Active Active POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 L SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 logic diagram (positive logic) LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL 2 27 30 55 56 29 1 28 C1 A1 8 G1 1 23 1D 1B1 1 C1 1D 6 2B1 C1 1D C1 1D To 11 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABTH16260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16260 MIN MAX 4.5 5.5 4.5 5.5 Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled NOTE 3: Unused control inputs must be held high or low to prevent them from floating. 4 MAX VCC VIH High-level input voltage SN74ABTH16260 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC –24 V V 0.8 0 UNIT VCC –32 V V mA 48 64 mA 10 10 ns/V µs/V 200 125 –40 85 °C SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN II(hold) I(h ld) SN54ABT16260 MIN –1.2 MAX SN74ABTH16260 MIN –1.2 MAX –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* VCC = 0 to 5.5 V, VI = VCC or GND A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND A or B ports VCC = 4 4.5 5V V V IOL = 64 mA 0.5 0.55* 0.55 100 Control inputs UNIT 2 0.36 Vhys II TA = 25°C TYP† MAX V mV ±1 ±1 ±1 ±20 ±100 ±20 µA VI = 0.8 V VI = 2 V 100 100 –100 –100 µA IOZPU‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZH§ VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA IOZL§ VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V ±100 µA 50 µA VCC = 5.5 V, VO = 2.5 V Outputs high –225 mA ICEX IO¶ ±100 Outputs high ICC VCC = 5.5 V, IO = 0, VI = VCC or GND ∆ICC# VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 50 –50 –100 Outputs low Outputs disabled –225 50 –50 –225 –50 1.5 1.5 1.5 63 63 63 1 1 1 1.5 1.5 1.5 3 Cio 11.5 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA mA pF pF 5 SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C† MIN tw tsu Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓ MAX SN54ABT16260 MIN SN74ABTH16260 MAX MIN UNIT MAX 3.3 3.3 ns 1.5 2 1.5 ns 1 1.5 1 ns th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓ † These values apply only to the SN74ABTH16260. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16260 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LE A or B tPLH tPHL SEL (B1) SEL (B2) A SEL (B1) SEL (B2) tPZH tPZL OE A or B tPHZ tPLZ OE A or B VCC = 5 V, TA = 25°C MIN MAX MIN TYP MAX 1 3.1 5.3 1 5.9 1 3.4 5.4 1 6.3 1.1 3.2 5.4 1.1 6.6 1.1 3.3 5.3 1.1 5.9 1.3 3.2 5.1 1.3 5.4 1.1 3.4 5.4 1.1 6.3 1.5 3.1 4.6 1.5 5 1.6 3.6 5.3 1.6 6.2 1 3.3 5.6 1 6.4 1.6 3.8 5.9 1.6 6.5 2.2 4.1 5.9 2.2 7.5 1.3 3.2 5 1.3 5.4 UNIT ns ns ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABTH16260 PARAMETER TO (OUTPUT) MIN MAX TYP MAX 1 3.1 4.8 1 5.6 1 3.4 5 1 5.9 1.1 3.2 4.9 1.1 5.8 1.1 3.3 4.9 1.1 5.3 SEL (B1) 1.3 3.2 4.6 1.3 5.3 SEL (B2) 1.1 3.4 4.9 1.1 6 1.5 3.1 4.4 1.5 4.4 1.6 3.6 5.1 1.6 5.9 1 3.3 4.7 1 5.7 1.6 3.8 5.1 1.6 5.8 2.2 4.1 5.4 2.2 6.4 1.3 3.2 4.4 1.3 4.8 A or B B or A tPLH tPHL LE A or B tPHL VCC = 5 V, TA = 25°C MIN tPLH tPHL tPLH 6 FROM (INPUT) SEL (B1) A SEL (B2) tPZH tPZL OE A or B tPHZ tPLZ OE A or B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns SN54ABT16260, SN74ABTH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS204C – JUNE 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V Data Input 0V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 3V 1.5 V Input Output Control 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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