SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 D D D D D D Members of the Texas Instruments Widebus+ Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Released as DSCC SMD 5962-9557801NXD D D D D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs (–32-mA IOH, 64-mA IOL) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch and Space-Saving 100-Pin Ceramic Quad Flat (HS) Package† 1A8 1A7 1A6 GND 1A5 1A4 1A3 1A2 1A1 1CEBA 1OEBA 1LEBA VCC 1LEAB 1OEAB 1CEAB 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 ’ABTH32543 . . . PZ PACKAGE (TOP VIEW) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1A9 1A10 GND 1A11 1A12 1A13 1A14 GND 1A15 1A16 1A17 1A18 VCC 2A1 2A2 2A3 2A4 GND 2A5 2A6 2A7 2A8 GND 2A9 2A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1B9 1B10 GND 1B11 1B12 1B13 1B14 GND 1B15 1B16 1B17 1B18 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 2B8 GND 2B9 2B10 2A11 2A12 2A13 GND 2A14 2A15 2A16 2A17 2A18 2CEBA 2OEBA 2LEBA VCC 2LEAB 2OEAB 2CEAB 2B18 2B17 2B16 2B15 2B14 GND 2B13 2B12 2B11 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 † The HS package is not production released. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1B7 1B8 1B9 1B10 GND 1B11 1B12 1B13 1B14 GND 1B15 1B16 1B17 1B18 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 2B8 GND 2B9 2B10 2B11 2B12 2B13 2A13 GND 2A14 2A15 2A16 2A17 2A18 2CEBA 2OEBA 2LEBA VCC 2LEAB 2OEAB 2CEAB 2B18 2B17 2B16 2B15 2B14 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1A6 1A7 1A8 1A9 1A10 GND 1A11 1A12 1A13 1A14 GND 1A15 1A16 1A17 1A18 VCC 2A1 2A2 2A3 2A4 GND 2A5 2A6 2A7 2A8 GND 2A9 2A10 2A11 2A12 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GND 1A5 1A4 1A3 1A2 1A1 1CEBA 1OEBA 1LEBA VCC 1LEAB 1OEAB 1CEAB 1B1 1B2 1B3 1B4 1B5 GND 1B6 SN54ABTH32543 . . . HS PACKAGE† (TOP VIEW) † For HS package availability, please contact the factory or your local TI Field Sales Office. description The ’ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH32543 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH32543 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† (each 18-bit section) INPUTS CEAB LEAB OEAB A OUTPUT B H X X X Z X X H X Z L H L X L L L L B0‡ L L L L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡ Output level before the indicated steady-state input conditions were established POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 logic diagram (positive logic) 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 90 91 89 86 85 87 C1 92 1D 84 1B1 C1 1D To 17 Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 36 35 37 40 41 39 C1 14 1D C1 1D To 17 Other Channels Pin numbers shown are for the PZ package. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 62 2B1 SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABTH32543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABTH32543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): PZ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABTH32543 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABTH32543 MIN 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled VCC –24 V V 0.8 0 UNIT VCC –32 V V mA 48 64 mA 10 10 ns/V µs/V 200 125 –40 85 °C NOTE 3: Unused control pins must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH II = –18 mA IOH = – 3 mA VCC = 5 V, IOH = – 3 mA IOH = – 24 mA –1.2 3 3 A or B ports 0.55 0.55 Control inputs A or B ports A or B ports VI = VCC or GND VI = VCC or GND VCC = 5 5.5 5V V, VI = VCC or GND VCC = 4 4.5 5V VI = 0.8 V VI = 2 V Ioff ICEX IO§ VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V Outputs high VCC = 5.5 V, VO = 2.5 V Outputs high 5 5 V, V IO = 0, 0 VCC = 5.5 VI = VCC or GND ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci Control inputs Cio A or B ports V mV ±1 ±20 ±1 µA ±20 100 VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ICC 100 µA –100 IOZPU‡ IOZPD‡ V 2 0.55 IOL = 64 mA VCC = 0 to 5.5 V, VCC = 2.1 V to 5.5 V, UNIT V 2 100 Control inputs II(hold) I(h ld) –1.2 2.5 Vhys II MIN 2.5 IOH = – 32 mA IOL = 48 mA VCC = 4 4.5 5V SN74ABTH32543 TYP† MAX MIN VCC = 4.5 V, VCC = 4.5 V, VCC = 4 4.5 5V VOL SN54ABTH32543 TYP† MAX TEST CONDITIONS ±50 ±50 µA ±50 ±50 µA ±100 µA 50 –50 –100 –180 Outputs low Outputs disabled VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V –50 –100 50 µA –180 mA 3 3 20 20 2 2 1 1 mA mA 3.5 3.5 pF 9.5 9.5 pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is specified by characterization. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C# MIN tw Pulse duration, LEAB or LEBA low tsu Setup time th Hold time MAX MIN MAX SN74ABTH32543 MIN 3.3 3.3 3.3 Data before LEAB↑ or LEBA↑ 2.1 2.6 2.1 Data before CEAB↑ or CEBA↑ 1.7 2 1.7 Data after LEAB↑ or LEBA↑ 0.6 1.1 0.6 Data after CEAB↑ or CEBA↑ 0.9 1.2 0.9 # These limits apply only to the SN74ABTH32543. 6 SN54ABTH32543 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX ns ns ns SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LE A or B tPZH tPZL CE A or B tPHZ tPLZ CE A or B tPZH tPZL OE A or B tPHZ tPLZ OE A or B PARAMETER VCC = 5 V, TA = 25°C† SN54ABTH32543 SN74ABTH32543 MIN TYP MAX MIN MAX MIN MAX 1 3.5 5.2 0.5 6.3 1 5.9 1 3.5 5.1 0.5 5.9 1 5.7 1.9 4.6 6.3 0.8 7.9 1.9 7.5 1.9 4.3 5.9 0.8 6.9 1.9 6.6 1.7 4.3 6.7 0.8 8.3 1.7 8 2.6 5.2 8 1 8.8 2.6 8.8 1.6 3.8 6.6 0.5 7.4 1.6 7.1 2.4 4.6 7 1 7.9 2.4 7.5 1.4 3.8 6.1 0.5 7.6 1.4 7.3 2.3 4.7 7.4 1 8.2 2.3 8.1 1.3 3.4 6.1 0.5 6.7 1.3 6.5 2 4.2 6.6 0.8 7.2 2 6.9 UNIT ns ns ns ns ns ns † These limits apply only to the SN74ABTH32543. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230F – JUNE 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated