MCNIX MX25L12855E

MX25L12855E
MX25L12855E
SECURED SERIAL FLASH SPECIFICATION
PRELIMINARY - PUBLIC
P/N: PM1466
REV. 0.05, MAR. 05, 2009
1
MX25L12855E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Features ..................................................................................................................................... 7
PIN CONFIGURATION................................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM........................................................................................................................................................ 9
DATA PROTECTION................................................................................................................................................... 10
Table 2. Protected Area Sizes.................................................................................................................................. 11
Table 3. 4K-bit Secured OTP Definition................................................................................................................... 11
Memory Organization................................................................................................................................................ 12
Table 4. Memory Organization................................................................................................................................ 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1-1. Serial Modes Supported (for Normal Serial mode)............................................................................... 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)................................................. 13
COMMAND DESCRIPTION........................................................................................................................................ 14
Table 5. Command Sets.......................................................................................................................................... 14
(1) Write Enable (WREN)........................................................................................................................................ 16
(2) Write Disable (WRDI)......................................................................................................................................... 16
(3) Read Identification (RDID)................................................................................................................................. 16
(4) Read Status Register (RDSR)............................................................................................................................ 17
(5) Write Status Register (WRSR)........................................................................................................................... 18
Protection Modes..................................................................................................................................................... 18
(6) Read Data Bytes (READ)................................................................................................................................... 19
(7) Read Data Bytes at Higher Speed (FAST_READ)............................................................................................. 19
(8) 2 x I/O Read Mode (2READ).............................................................................................................................. 19
(9) 4 x I/O Read Mode (4READ).............................................................................................................................. 20
(10) Fast Double Transfer Rate Read (FASTDTRD)............................................................................................... 20
(11) 2 x I/O Double Transfer Rate Read Mode (2DTRD)......................................................................................... 20
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)......................................................................................... 21
(13) Sector Erase (SE)............................................................................................................................................ 21
(14) Block Erase (BE).............................................................................................................................................. 22
(15) Block Erase (BE32K)........................................................................................................................................ 22
(16) Chip Erase (CE)............................................................................................................................................... 22
(17) Page Program (PP).......................................................................................................................................... 23
(18) 4 x I/O Page Program (4PP)............................................................................................................................ 23
Program/Erase Flow(1) with read array data........................................................................................................... 24
Program/Erase Flow(2) without read array data...................................................................................................... 25
(19) Continuously program mode (CP mode).......................................................................................................... 26
(20) Parallel Mode (Highly recommended for production throughputs increasing).................................................. 26
(21) Deep Power-down (DP)................................................................................................................................... 27
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(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES).................................................... 27
(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D).............................. 27
Table 6. ID Definitions . ........................................................................................................................................... 28
(24) Enter Secured OTP (ENSO)............................................................................................................................ 28
(25) Exit Secured OTP (EXSO)............................................................................................................................... 28
(26) Read Security Register (RDSCUR).................................................................................................................. 28
Security Register Definition..................................................................................................................................... 29
(27) Write Security Register (WRSCUR)................................................................................................................. 29
(28) GPIO Expander................................................................................................................................................ 30
(28-1) GPIO Function Enable (GPIOEN)................................................................................................................. 30
(28-2) GPIO Function Disable (GPIODIS)............................................................................................................... 30
(28-3) GPIO Register Read/Write (GPIORW).......................................................................................................... 30
(28-4) GPIO Register Reset (GPIORST)................................................................................................................. 30
(29) Write Protection Selection (WPSEL)................................................................................................................ 32
WPSEL Flow............................................................................................................................................................ 32
(30) Single Block Lock/Unlock Protection (SBLK/SBULK)...................................................................................... 33
Block Lock Flow....................................................................................................................................................... 33
Block Unlock Flow................................................................................................................................................... 34
(31) Read Block Lock Status (RDBLOCK).............................................................................................................. 35
(32) Gang Block Lock/Unlock (GBLK/GBULK)........................................................................................................ 35
(33) Clear SR Fail Flags (CLSR)............................................................................................................................. 35
(34) Output Driving Configure (ODC)...................................................................................................................... 35
(35) Enable SO to Output RY/BY# (ESRY)............................................................................................................. 36
(36) Disable SO to Output RY/BY# (DSRY)............................................................................................................ 36
(37) Enter CFI Mode (ENCFI).................................................................................................................................. 36
POWER-ON STATE.................................................................................................................................................... 37
ELECTRICAL SPECIFICATIONS............................................................................................................................... 38
ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 38
Figure 2. Maximum Negative Overshoot Waveform................................................................................................ 38
CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 38
Figure 3. Maximum Positive Overshoot Waveform.................................................................................................. 38
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 39
Figure 5. OUTPUT LOADING................................................................................................................................. 39
Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ........ 40
Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) . ...... 41
Timing Analysis......................................................................................................................................................... 43
Figure 6. Serial Input Timing.................................................................................................................................... 43
Figure 7. Output Timing........................................................................................................................................... 43
Figure 8. Serial Input Timing for Double Transfer Rate Mode................................................................................. 44
Figure 9. Serial Output Timing for Double Transfer Rate Mode............................................................................... 44
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...................................................... 45
Figure 11. Write Enable (WREN) Sequence (Command 06)................................................................................... 45
Figure 12. Write Disable (WRDI) Sequence (Command 04)................................................................................... 45
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MX25L12855E
Figure 13. Read Identification (RDID) Sequence (Command 9F)........................................................................... 46
Figure 14. Read Identification (RDID) Sequence (Parallel)..................................................................................... 46
Figure 15. Read Status Register (RDSR) Sequence (Command 05)...................................................................... 47
Figure 16. Write Status Register (WRSR) Sequence (Command 01).................................................................... 47
Figure 17. Read Data Bytes (READ) Sequence (Command 03)............................................................................ 48
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B)........................................................ 48
Figure 19. Fast DT Read (FASTDTRD) Sequence (Command 0D)........................................................................ 49
Figure 20. 2 x I/O Read Mode Sequence (Command BB)...................................................................................... 49
Figure 21. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)................................................................ 50
Figure 22. 4 x I/O Read Mode Sequence (Command EB)...................................................................................... 50
Figure 23. 4 x I/O Read Enhance Performance Mode Sequence (Command EB).................................................. 51
Figure 24. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)............................................................... 52
Figure 25. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED).......................... 53
Figure 26. Page Program (PP) Sequence (Command 02)..................................................................................... 54
Figure 27. 4 x I/O Page Program (4PP) Sequence (Command 38)....................................................................... 54
Figure 28. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)........................ 55
Figure 29. Sector Erase (SE) Sequence (Command 20)....................................................................................... 55
Figure 30. Block Erase (BE) Sequence (Command D8)........................................................................................ 55
Figure 31. Chip Erase (CE) Sequence (Command 60 or C7)................................................................................ 56
Figure 32. Deep Power-down (DP) Sequence (Command B9).............................................................................. 56
Figure 33. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)... 56
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB)..................................................... 57
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)..... 57
Figure 36. READ ARRAY SEQUENCE (Parallel)................................................................................................... 58
Figure 37. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel).................................................................... 59
Figure 38. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel).............. 60
Figure 39. Read Electronic Manufacturer & Device ID (REMS) Sequence (Parallel)............................................. 61
Figure 40. Write Protection Selection (WPSEL) Sequence (Command 68)........................................................... 62
Figure 41. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)............................ 62
Figure 42. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)........................................ 62
Figure 43. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98).............................................. 63
Figure 44. Power-up Timing..................................................................................................................................... 63
Table 9. Power-Up Timing and VWI Threshold........................................................................................................ 63
INITIAL DELIVERY STATE...................................................................................................................................... 63
RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 64
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 65
LATCH-UP CHARACTERISTICS............................................................................................................................... 65
ORDERING INFORMATION....................................................................................................................................... 66
PART NAME DESCRIPTION...................................................................................................................................... 66
PACKAGE INFORMATION......................................................................................................................................... 67
REVISION HISTORY ................................................................................................................................................. 69
P/N: PM1466
REV. 0.05, MAR. 05, 2009
4
PRELIMINARY
MX25L12855E
128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O
mode) structure
• 4096 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 512 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 256 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast read (Double Transfer Rate Mode)
- 1 I/O: 50MHz with 6 dummy cycles
- 2 I/O: 50MHz with 6 dummy cycles
- 4 I/O: 50MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 90ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 80s(typ.) /chip
• Low Power Consumption
- Low active read current: 45mA(max.) at 104MHz, 40mA(max.) at 66MHz and 30mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 100uA (max.)
- Deep power down current: 40uA (max.)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
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MX25L12855E
- Flexible block or individual block protect selection
- Individual block (or sector) permanent lock
The BP0-BP3 status bits define the size of the area to be software protection against program and erase instructions
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- Both REMS,REMS2, REMS4 and REMS4D commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Common Flash Interface (CFI) (TBD)
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1/PO7
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode or Parallel Mode Data
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• NC/SIO3
- NC pin or serial data Input/Output for 4 x I/O mode
• PO0~PO6
- For parallel mode data
• PACKAGE
- 16-pin SOP (300mil)
- 24-ball TFBGA (10x13 mm)
- All Pb-free devices are RoHS Compliant
Please contact Macronix sales for specific information regarding this Advanced Security Features
P/N: PM1466
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MX25L12855E
GENERAL DESCRIPTION
The MX25L12855E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When
it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L12855E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
The MX25L12855E provides high performance read mode, which may latch address and data on both rising and
falling edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover,
the performance may reach direct code execution, the RAM size of the system may be reduced and further saving
system cost.
The MX25L12855E provides sequential read operation on whole chip and multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see Security Features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC current.
The MX25L12855E utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Read Performance
Additional Protection and Security
Features
Individual
Permanent
1 I/O DT
2 I/O DT
block (or 1 I/O Read 2 I/O Read 4 I/O Read
Part
Lock and
Read
Read
sector)
(104 MHz) (70 MHz) (70 MHz)
Name
read lock
(50 MHz) (50 MHz)
protection
MX25L12855E
V
V
V
V
V
Additional
Features
Part
Name
MX25L12855E
V
4 I/O DT
Read
(50 MHz)
8 I/O
Parallel
Mode
(6 MHz)
V
V
V
Identifier
RES
(command: AB
hex)
88 (hex)
REMS
(command: 90
hex)
C2 88 (hex)
(if ADD=0)
REMS2
(command: EF
hex)
C2 88 (hex)
(if ADD=0)
P/N: PM1466
REMS4
(command: DF
hex)
C2 88 (hex)
(if ADD=0)
REMS4D
(command: CF
hex)
C2 88 (hex)
(if ADD=0)
RDID (command:
9F hex)
C2 26 18 (hex)
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MX25L12855E
PIN CONFIGURATION
Please contact Macronix sales for specific information regarding 16-pin SOP (300mil) and 24-ball TFBGA
(10x13mm) package pin configuration.
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/O mode)
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1/
Data Input & Output (for 2xI/O or 4xI/O
PO7
mode) / Parallel Data Output/Input
SI/SIO0
SCLK
Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
mode)
NC pin (Not connect) or Serial Data Input
NC/SIO3
& Output (for 4xI/O mode)
VCC
+ 3.3V Power Supply
GND
GPIO0/PO0
~ GPIO6/
PO6
NC
Ground
General Purpose Input & Output/ Parallel
data output/input (PO0~PO6 can be
connected to NC in serial mode)
No Connection
P/N: PM1466
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MX25L12855E
BLOCK DIAGRAM
Address
Generator
X-Decoder
PAD[6:0]
Memory Array
GPIO
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
NC/SIO3
SCLK
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
SO/SIO1
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MX25L12855E
DATA PROTECTION
The MX25L12855E is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system
noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
- Permanent Lock (PLOCK) instruction completion
- Write Read Lock Register (WRLCR) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES).
• Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protected Area Sizes".
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
If the system goes into four I/O mode, the feature of HPM will be disabled.
- MX25L12855E provide individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction. For sector(s) or block(s) that is (are) permanently locked, SBULK & GBULK does not influence the state of the permanently locked sector(s)' or block(s)'
status.
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MX25L12855E
Table 2. Protected Area Sizes
Status bit
Protection Area
BP3
BP2
BP1
BP0
128Mb
1
1
1
1
All
1
1
1
0
All
1
1
0
1
All
1
1
0
0
All
1
0
1
1
All
1
0
1
0
All
1
0
0
1
All
1
0
0
0
All
0
1
1
1
Upper half (hundrend and twenty-eight blocks: 128 to 255)
0
1
1
0
Upper quarter (sixty-four blocks: 192 to 255)
0
1
0
1
Upper eighth (thirty-two blocks: 224 to 255)
0
1
0
0
Upper sixteenth (sixteen blocks: 240 to 255)
0
0
1
1
Upper 32nd (eight blocks: 248 to 255)
0
0
1
0
Upper 64th (four blocks: 252 to 255)
0
0
0
1
Upper 128th (two blocks: 254 and 255)
0
0
0
0
None
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Secured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxx000~xxx00F
128-bit
ESN (electrical serial number)
xxx010~xxxFFF
3968-bit
N/A
P/N: PM1466
Customer Lock
Determined by customer
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MX25L12855E
Memory Organization
Table 4. Memory Organization
Block(64K-byte)
Block(32K-byte)
Sector
254
508
individual block
lock/unlock unit:64K-byte
507
253
506
FF7FFFh
individual 16 sectors
lock/unlock unit:4K-byte
…
FF8FFFh
FF7000h
4080
FF0000h
FF0FFFh
4079
FEF000h
FEFFFFh
…
509
FF8000h
4087
4072
FE8000h
FE8FFFh
4071
FE7000h
FE7FFFh
…
510
4088
4064
FE0000h
FE0FFFh
4063
FDF000h
FDFFFFh
…
255
FFFFFFh
4056
FD8000h
FD8FFFh
4055
FD7000h
FD7FFFh
4048
FD0000h
FD0FFFh
47
02F000h
02FFFFh
…
511
Address Range
FFF000h
…
4095
1
2
1
0
0
027FFFh
…
028FFFh
027000h
32
020000h
020FFFh
31
01F000h
01FFFFh
24
018000h
018FFFh
23
017000h
017FFFh
…
3
028000h
39
…
4
individual block
lock/unlock unit:64K-byte
40
16
010000h
010FFFh
15
00F000h
00FFFFh
…
2
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
individual 16 sectors
lock/unlock unit:4K-byte
…
5
…
individual block
lock/unlock unit:64K-byte
0
P/N: PM1466
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MX25L12855E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1-1.
For high performance (Double Transfer Rate Read serial mode), data is latched on both rising and falling edge
of clock and data shifts out on both rising and falling edge of clock as Figure 1-2.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,FASTDTRD,
2DTRD, 4DTRD, RDBLOCK, PRLCR, RES, REMS, REMS2, REMS4 and REMS4D the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, Parallel Mode WRSR, SE, BE, BE32K,CE, PP, CP, 4PP, RDP, DP, WPSEL,
SBLK, SBULK, GBLK, GBULK, PLOCK, WRLCR, ENSO, EXSO,and WRSCUR, the CS# must go high exactly
at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1-1. Serial Modes Supported (for Normal Serial mode)
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)
CPOL
data
in
CPHA
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
data
in
data
out
data
out
MSB
SO
P/N: PM1466
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13
MX25L12855E
COMMAND DESCRIPTION
Table 5. Command Sets
RDSR
WRSR
FASTDTRD
2DTRD (Dual
(read status (write status
(fast DT
I/O DT Read)
register)
register)
read)
06 (hex)
04 (hex)
9F (hex)
05 (hex)
01 (hex)
0D (hex)
BD (hex)
ADD(2) &
Values
ADD1
Dummy(2)
ADD(1) &
Dummy(2)
Dummy(1)
Dummy(1)
sets the
resets the outputs JEDEC to read out to write new n bytes read n bytes read
(WEL) write (WEL) write
ID: 1-byte
the values
values to
out (Double out (Double
enable latch enable latch Manufacturer of the status the status
Transfer
Transfer
bit
bit
ID & 2-byte
register
register
Rate) until Rate) by 2xI/
Device ID
CS# goes
O until CS#
high
goes high
COMMAND WREN (write
(byte)
enable)
1st byte
2nd byte
3rd byte
4th byte
Action
COMMAND READ (read
(byte)
data)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
03 (hex)
AD1
(A23-A16)
AD2
(A15-A8)
AD3
(A7-A0)
WRDI (write RDID (read
disable)
identification)
0B (hex)
2READ (2
x I/O read
command)
Note1
BB (hex)
AD1
ADD(2)
AD2
ADD(2) &
Dummy(2)
FAST READ
(fast read
data)
PP (Page
program)
1st byte
60 or C7
(hex)
02 (hex)
2nd byte
3rd byte
4th byte
Action
SE (sector
erase)
EB (hex)
ADD(4) &
Dummy(4)
38 (hex)
20 (hex)
D8 (hex)
52 (hex)
AD1
AD1
AD1
AD1
AD2
AD2
AD2
AD3
AD3
AD3
to erase the
selected
sector
to erase the
selected
64KB block
to erase the
selected
32KB block
Dummy(4)
to erase
whole chip
AD1
AD2
AD3
to program
the selected
page
CP
DP (Deep
(Continuously
power
program mode)
down)
AD (hex)
n bytes read
out (Double
Transfer
Rate) by 4xI/
O until CS#
goes high
4PP (quad
page
program)
Dummy
n bytes read n bytes read n bytes read n bytes read quad input
out until CS# out until CS# out by 2 x I/ out by 4 x I/ to program
goes high
goes high
O until CS# O until CS# the selected
goes high
goes high
page
CE (chip
erase)
Dummy(4)
4READ (4
x I/O read
command)
AD3
COMMAND
(byte)
4DTRD
(Quad I/O DT
Read)
ED (hex)
ADD(4) &
Dummy(4)
B9 (hex)
BE (block BE 32K (block
erase 64KB) erase 32KB)
RDP
REMS (read
(Release RES (read
electronic
from deep electronic
manufacturer
power
ID)
& device ID)
down)
AB (hex)
AB (hex)
90 (hex)
REMS2 (read
ID for 2x I/O
mode)
EF (hex)
AD1
x
x
x
AD2
x
x
x
AD3
x
ADD (Note 2) ADD (Note 2)
continously enters deep release
to read
output the
output the
program
power down from deep out 1-byte Manufacturer Manufacturer ID
whole chip,
mode
power down Device ID ID & Device
& Device ID
the address is
mode
ID
automatically
increase
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MX25L12855E
COMMAND
(byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
REMS4
(read ID
for 4x I/O
mode)
DF (hex)
x
x
ADD
(Note 2)
output the
Manufacturer ID &
device ID
ENPLM
(Enter
Parallel
Mode)
REMS4D
(read ID for
4x I/O DT
mode)
CF (hex)
x
x
ADD
(Note 2)
ENSO
(enter
secured
OTP)
B1 (hex)
EXSO (exit
secured
OTP)
C1 (hex)
output the
to enter
to exit
Manufact- the 4K-bit the 4K-bit
urer ID &
Secured
Secured
Device ID OTP mode OTP mode
RDSCUR
(read
security
register)
2B (hex)
to read
value of
security
register
WRSCUR
ESRY
DSRY
ENCFI
(write
(enable SO (disable SO (enter CFI
security
to output
to output
mode)
register)
RY/BY#)
RY/BY#)
2F (hex)
70 (hex)
80 (hex)
A5 (hex)
x
x
ADD (A7 is
don't care)
Dummy
to set the to enable to disable to enter CFI
lock-down
SO to
SO to
Query
bit as "1" output RY/ output RY/
(once lock- BY# during BY# during
down,
CP mode CP mode
cannot be
updated)
CLSR
HPM (High
ODC
GPIOEN
GPIODIS GPIORW
(Clear SR Perform(Output
(GPIO
(GPIO
(GPIO
COMMAND
Fail Flags)
ance
driving
function
function
register
(byte)
Enable
Configure)
enable)
Disable) read/write)
Mode)
1st byte
55 (hex)
45 (hex)
30 (hex)
A3 (hex)
6D (hex)
1A (hex)
18 (hex)
1C (hex)
2nd byte
Dummy
Values
Values
3rd byte
Dummy
Values
4th byte
Dummy
8xI/O
to exit
clear
Quad I/
change the enable the disable the change/
parallel
8xI/O
security
O high
option value function of function of read the
programparallel
register bit Performof output GPIO mode GPIO mode value of
Action
ming mode program- 6 and bit 5 ance mode
driving
GPIO
ming mode
registers
COMMAND
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
EXPLM
(EXIT
Parallel
Mode)
GPIORST
(GPIO
register
reset)
1E (hex)
reset all
the GPIO
registers
WPSEL
(write
protection
selection)
68 (hex)
SBLK
SBULK
RDBLOCK
GBLK
GBULK
(single (single block
(block
(gang block (gang block
block lock)
unlock) protect read)
lock)
unlock)
*Note 4
36 (hex)
39 (hex)
3C (hex)
7E (hex)
98 (hex)
AD1
AD1
AD1
AD2
AD2
AD2
AD3
AD3
AD3
to enter
individual individual
read
whole
whole chip
and enable block (64K- block (64K- individual chip write unprotect
individal
byte) or
byte) or
block or
protect
block protect sector (4Ksector
sector write
mode
byte) write (4K-byte)
protect
protect
unprotect
status
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from
1 x I/O condition.
Note 2: ADD=00h will output the Manufacturer ID first and ADD=01h will output Device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 4. In individual block write protection mode, all blocks/sectors is locked as defualt.
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MX25L12855E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, CP, SE, BE, BE32K, CE, WRSR, WRLCR, SBLK, SBULK, GBLK, GBULK, and PLOCK which are intended to
change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see
Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see
Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Write Read Lock Register (WRLCR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
- Permanent Lock (PLOCK) instruction completion
- Write Read Lock Register (WRLCR) command completion
(3) Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 26(hex) as the first-byte Device ID, and the individual Device ID
of second-byte ID are listed as table of "ID Definitions". (see Table 8 in page 31)
The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out
on SO -> to end RDID operation can use CS# to high at any time during data out. (see Figure 13 and Figure 14 for
parallel mode)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
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MX25L12855E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register
data out on SO (see Figure 15).
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected
area(as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode
being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
bit7
bit6
SRWD (status
register write
protect)
QE
(Quad
Enable)
1= Quad
1=status
Enable
register write
0=not Quad
disable
Enable
Non-volatile Non-volatile
bit
bit
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note 1: see the Table 2 "Protected Area Size".
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MX25L12855E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (see Figure 16)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Protection Modes
Mode
Software protection
mode(SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O mode, the feature of HPM will be disabled.
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MX25L12855E
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on
SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure 17)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte
address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (see Figure 18)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ
operation can use CS# to high at any time during data out (see Figure 20 for 2 x I/O Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(9) 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before seding the 4READ instruction.The address is latched on rising edge of SCLK,
and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
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MX25L12855E
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out (see Figure 22 for 4 x I/O Read Mode Timing Waveform).
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→ sending
4 READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit random access address (see Figure 23 for 4x I/O Read Enhance Performance Mode timing waveform).
In the performance-enhancing mode (Note of Figure. 23), P[7:4] must be toggling with P[3:0] ; likewise
P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is
no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. These commands will reset the performance
enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) Fast Double Transfer Rate Read (FASTDTRD)
The FASTDTRD instruction is for doubling reading data out, signals are triggered on both rising and falling edge of
clock. The address is latched on both rising and falling edge of SCLK, and data of each bit shifts out on both rising
and falling edge of SCLK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock, and 2-bit
data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock.
The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single FASTDTRD instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing FASTDTRD instruction is: CS# goes low → sending FASTDTRD instruction code (1bit
per clock) → 3-byte address on SI (2-bit per clock) → 6-dummy clocks (default) on SI → data out on SO (2-bit per
clock) → to end FASTDTRD operation can use CS# to high at any time during data out. (see Figure 19)
While Program/Erase/Write Status Register cycle is in progress, FASTDTRD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(11) 2 x I/O Double Transfer Rate Read Mode (2DTRD)
The 2DTRD instruction enables Double Transfer Rate throughput on dual I/O of Serial Flash in read mode. The address (interleave on dual I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on dual
I/O pins) shift out on both rising and falling edge of SCLK at a maximum frequency fT2. The 4-bit address can be
latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock,
the other two bits at falling edge of clock. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single 2DTRD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2DTRD instruction, the following address/dummy/ data out will perform as
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MX25L12855E
4-bit instead of previous 1-bit.
The sequence of issuing 2DTRD instruction is: CS# goes low → sending 2DTRD instruction (1-bit per clock) → 24bit address interleave on SIO1 & SIO0 (4-bit per clock) → 6-bit dummy clocks on SIO1 & SIO0 → data out interleave on SIO1 & SIO0 (4-bit per clock) → to end 2DTRD operation can use CS# to high at any time during data out (see
Figure 21 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address(interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on
both rising and falling edge of SCLK at a maximum frequency fQ2. The 8-bit address can be latched-in at one clock,
and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruction, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing 4DTRD instruction is: CS# goes low → sending 4DTRD instruction (1-bit per clock) → 24bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) →8 dummy clocks →data out interleave on
SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → to end 4DTRD operation can use CS# to high at any time during data
out (see Figure 24 for 4 x I/O Read Mode Double Transfer Rate Timing Waveform).
Another sequence of issuing enhanced mode of 4DTRD instruction especially useful in random access is : CS#
goes low → sending 4DTRD instruction (1-bit per clock) → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0
(8-bit per clock) → performance enhance toggling bit P[7:0] → 7 dummy clocks → data out(8-bit per clock) still CS#
goes high → CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (see Figure 25 for 4x I/
O Double Transfer Rate read enhance performance mode timing waveform).
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(13) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see Table 6) is a valid address for Sector Erase (SE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI →
CS# goes high. (see Figure 29)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
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tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
sector is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit still be reset.
(14) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see table 6) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI
→ CS# goes high. (see Figure 30)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
block is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit still be reset.
(15) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE32). Any address of the block (see table 6) is a valid address for
Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on
SI → CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
block is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit still be reset.
(16) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (see
Figure 31)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
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protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
(17) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are
not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of
the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the
last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are
sent to the device, the data is programmed at the requested address of the page without effect on other address of
the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→at
least 1-byte on data on SI→ CS# goes high. (see Figure 26)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array data
will be protected (no change) and the WEL bit will still be reset.
(18) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than
20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other
function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (see Figure 27)
If the page is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array
data will be protected (no change) and the WEL bit will still be reset.
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The Program/Erase function instruction function flow is as follows:
Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
WREN=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase successfully
Program/erase
another block?
No
Program/erase fail
Yes
*
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
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Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
WREN=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
Read array data
(same address of PGM/ERS)
Verify ok?
Yes
No
Program/erase fail
Program/erase successfully
CLSR(30h) command
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
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(19) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low→ sending CP instruction code → 3-byte address on SI
pin→ two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes are
programmed→ CS# goes high to low→ till last desired two data bytes are programmed → CS# goes high to low→
sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (see Figure 28 of CP mode timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0), RL7~0, or by individual lock/permanent lock (WPSEL=1), the array
data will be protected (no change) and the WEL bit will still be reset.
(20) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. The
parallel mode requires 55h command code, after writing the parallel mode command and then CS# going high, after
that, the Memory can be available to accept read/program/read status/read ID/RES/REMS command as the normal
writing command procedure.
a. Only effective for Read Array for normal read(not FAST_READ), Read ID, Page Program, RES and REMS write
data period.
b. For normal write command (by SI), No effect
c. Under parallel mode, the fastest access clock freq. will be changed to 6MHz(SCLK pin clock freq.)
d. For parallel mode, the tV will be change to 70ns.
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(21) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see Figure 32)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#)
must remain High for at least tRES2(max), as specified in Table 10. Once in the standby mode, the device waits to
be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/
write cycles in progress. The sequence is shown as Figure 33,34.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)
The REMS, REMS2, REMS4 and REMS4D instruction provides both the JEDEC assigned Manufacturer ID and the
specific Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "EFh", "DFh" or "CFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and
the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 35.
The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the DeP/N: PM1466
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vice ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Table 6. ID Definitions
RDID Command
manufacturer ID
C2
memory type
26
electronic ID
88
device ID
88
RES Command
REMS/REMS2/REMS4/
REMS4D Command
manufacturer ID
C2
memory density
18
(24) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering
the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not acceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands
are valid.
(25) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode-> CS# goes high.
(26) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction → Security Register data out on SO→ CS# goes high.
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be update any more. While it is in 4K-bit Secured OTP mode, array access is not allowed.
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Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by command CLSR (30h)
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h)
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits and Permanent Lock
bits.
Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Continuously
Program
mode
(CP mode)
x
x
LDSO
(indicate if
lock-down
Secrured
OTP
indicator bit
WPSEL
E_FAIL
P_FAIL
0=normal
WP mode
1=individual
WP mode
(default=0)
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
0=normal
Program
mode
1=CP mode
(default=0)
reserved
reserved
0 = not
lockdown
1 = lockdown
(cannot
program/
erase
OTP)
non-volatile
bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile
bit
0=
nonfactory
lock
1 = factory
lock
non-volatile
bit
(27) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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(28) GPIO Expander
GPIO expander is used for microcontrollers to expand the general purpose I/O pin with 7 extra General Purpose Input/Outputs. The outputs provided can be used for controlling simple on-off of system components.
(28-1) GPIO Function Enable (GPIOEN)
The GPIOEN instruction is for enabling the function of GPIO mode. For all of GPIO commands like GPIORW, GPIORST, and GPIODIS, they should be issued after GPIOEN is set. GPIO is not allowed in parallel mode and POR
read, but it is allowed in the other modes even in Deep Power down (DPW). If GPIO is active in DPW mode, the ISB2
may increase more than 40uA (see Table 9).
The sequence of issuing GPIOEN instruction is: CS# goes low -> GPIOEN instruction code is sent -> CS# goes
high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(28-2) GPIO Function Disable (GPIODIS)
The GPIODIS instruction is for disabling the function of GPIO mode. Moreover, the GPIO function is also disabled
after POR, and all of the GPIO registers will be reset if GPIO function is disabled. GPIOEN should be issued before
the setting of GPIODIS instruction to make sure the GPIO function is enabled, or the GPIODIS instruction will not be
executed. After GPIODIS is issued, other GPIO command will not be executed until GPIOEN is set again.
The sequence of issuing GPIODIS instruction is: CS# goes low -> GPIODIS instruction code is sent -> CS# goes
high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(28-3) GPIO Register Read/Write (GPIORW)
The GPIORW instruction is for changing the GPIO registers. Read and Write operation can be judged by bit7 of address byte. Read operation will be executed when bit7 = 1 and write operation will be executed when bit7 = 0. The
read/write operation is described in Table 10. GPIOEN should be issued before the setting of GPIORW instruction to
make sure the GPIO function is enabled, or the GPIORW instruction will not be executed.
The sequence of issuing GPIORW instruction is: CS# goes low -> GPIORW instruction code is sent -> issue R/W#
bit (Write as 0; Read as 1) and address bit (A6~A0) ->SI/SO 8 bit data in/out cycle -> CS# goes high.
The GPIO read/write waveform is shown as Figure 40 and Figure 41.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(28-4) GPIO Register Reset (GPIORST)
The GPIORST instruction is for resetting all the GPIO registers. The GPIO registers will be reset to 0 (default value)
if GPIORST or POR is issued. GPIOEN should be issued before the setting of GPIORST instruction to make sure
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the GPIO function is enabled, or the GPIORST instruction will not be executed.
The sequence of issuing GPIORST instruction is: CS# goes low -> GPIORST instruction code is sent -> CS# goes
high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
GPIO register definition is as follows:
Register
Name D[6:0]
Reg. Address
A[6:0]
GPDC[6:0]
0x00
GPIO Pin Direction
Configuration
GPOM[6:0]
0x01
GPIO Pin Output Mode
GPWD[6:0]
0x02
GPST[6:0]
0x03
GPPU[6:0]
0x04
GPPD[6:0]
0x05
GPDS[6:0]
0x06
GPRD[6:0]
0x07
GPII[6:0]
0x08
GPOI[6:0]
0x09
GPOS[6:0]
0x0C
Description
0:Configured as input pin
1: Configured as output pin
0: Open drain
1:Push-pull
Valid only when GPDC[n]=1
0: Data="0"
GPIO Pin Write Data
1: Data="1"
It's only valid for output pins.
GPIO Pin Smitt
0: Disable
Trigger enable
1: Enable
GPIO Pin pull-up
0: Disable
resistor enable
1: ~50K Ω to VDD
GPIO Pin pull-down
0: Disable
resistor enable
1: ~50K Ω to GND
GPIO Pin Driving
0: 2mA (weak)
Strength
1: 4mA (strong)
0: data="0"
GPIO Pin Read Data
1: data="1"
0: No inversion
GPIO Pin Input Inversion
1: Inversion enable
0: No inversion
GPIO Pin Output Inversion
1: Inversion enable
0 : Disable
1 : Enable
GPIO one shot enable
(When pin value is "1", keep "1"
until GPRD[n] is written "1")
P/N: PM1466
Reg. Value after
POR/GPIO reset
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
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(29) Write Protection Selection (WPSEL)
When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate
SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original
Software Protect Mode (SPM) use (BP3~BP0) indicated block methods.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode→ CS# goes high.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the
blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and
GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits and Permanent Lock
bits.
WPSEL instruction function flow is as follows:
WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
WIP=0?
No
Yes
RDSCUR(2Bh) command
WPSEL=1?
No
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
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MX25L12855E
(30) Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes
sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state.
This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h)
instruction→send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. (see
Figure 41) The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be
executed.
SBLK/SBULK instruction function flow is as follows:
Block Lock Flow
Start
RDSCUR(2Bh) command
WPSEL=1?
No
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
WIP=0?
No
Yes
RDBLOCK command
( 3Ch + 24bit address )
Data = FFh ?
No
Yes
Block lock successfully
Lock another block?
Block lock fail
Yes
No
Block lock completed
P/N: PM1466
REV. 0.05, MAR. 05, 2009
33
MX25L12855E
Block Unlock Flow
start
RDSCUR(2Bh) command
WPSEL=1?
No
WPSEL command
Yes
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDPLOCK command to verify
Data = FFh ?
No
Yes
Block is permanently locked,
cannot be unlocked
RDBLOCK command to verify
( 3Ch + 24bit address )
Data = FF ?
Yes
No
Block unlock successfully
Unlock another block?
Block unlock fail
Yes
Unlock block completed?
P/N: PM1466
REV. 0.05, MAR. 05, 2009
34
MX25L12855E
(31) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block(or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3
address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (see
Figure 42)
(32) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high. (see Figure 43)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(33) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed before program/erase another block during programing/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code→ CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(34) Output Driving Configure (ODC)
The ODC instruction is for changing the option value of output driving or sinking. The options of output current are
shown as follow table. In this table, bit [3:2] is for PMOS driving option and bit [1:0] is for NMOS sinking option.
The sequence of issuing ODC instruction is: CS# goes low→ send ODC instruction code→ set 8bit ODC data on SI (bit
[7:4] don't care)→ CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
Output Drive current option
Output Driving
Bit [3:2]
Note
Current
11
2mA
For GPIO
10
1mA
For GPIO
01
6mA
00
4mA
Output Sink current option
Output Sinking
Bit [1:0]
Note
Current
11
-2mA
For GPIO
10
-1mA
For GPIO
01
-6mA
00
-4mA
P/N: PM1466
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35
MX25L12855E
(35) Enable SO to Output RY/BY# (ESRY)
The ESRY instruction is for outputing the ready/busy status to SO during CP mode.
The sequence of issuing ESRY instruction is: CS# goes low→ sending ESRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(36) Disable SO to Output RY/BY# (DSRY)
The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after
DSRY issued.
The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(37) Enter CFI Mode (ENCFI)
TBD
P/N: PM1466
REV. 0.05, MAR. 05, 2009
36
MX25L12855E
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1466
REV. 0.05, MAR. 05, 2009
37
MX25L12855E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Industrial grade
Ambient Operating Temperature
Storage Temperature
-40°C to 85°C
-55°C to 125°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2.Specifications contained within the following tables are subject to change.
3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN
COUT
MIN.
TYP
MAX.
UNIT
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
P/N: PM1466
CONDITIONS
REV. 0.05, MAR. 05, 2009
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MX25L12855E
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
0.8VCC
Output timing referance level
0.7VCC
AC
Measurement
Level
0.8V
0.2VCC
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
(CL=15pF Including jig capacitance for 104MHz, 70MHz@2xI/O and 70MHz@4xI/O)
P/N: PM1466
REV. 0.05, MAR. 05, 2009
39
MX25L12855E
Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER
NOTES
MIN.
MAX.
UNITS TEST CONDITIONS
ILI
Input Load Current
1
±2
uA
VCC = VCC Max, VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max, VIN = VCC or GND
ISB1
VCC Standby Current
1
100
uA
VIN = VCC or GND, CS# = VCC
ISB2
Deep Power-down
Current
40
uA
VIN = VCC or GND, CS# = VCC
45
mA
f=104MHz, fQ=75MHz (2 x I/O read)
SCLK=0.1VCC/0.9VCC, SO=Open
40
mA
f=66MHz, fT=75MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC, SO=Open
30
mA
f=33MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
25
mA
Program in Progress, CS# = VCC
20
mA
Program status register in progress,
CS#=VCC
1
25
mA
Erase in Progress, CS#=VCC
1
20
mA
Erase in Progress, CS#=VCC
0.8
V
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector Erase
Current (SE)
VCC Chip Erase Current
(CE)
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
1
1
-0.5
0.7VCC VCC+0.4
0.4
VCC-0.2
V
V
V
IOL = 1.6mA; IOL=140uA for Parallel
mode
IOH = -100uA; IOH=65uA for Parallel
mode
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2.Typical value is calculated by simulation.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
40
MX25L12855E
Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol
Alt. Parameter
Min.
fSCLK
fC
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
fRSCLK
fR
fT
Clock Frequency for READ instructions
Clock Frequency for 2READ instructions
fQ
Clock Frequency for 4READ instructions
fTSCLK
f4PP
fC2 Clock Frequency for FASTDTRRD instructions
fT2 Clock Frequency for 2DTRRD instructions
fQ2 Clock Frequency for 4DTRRD instructions
Clock Frequency for 4PP (Quad page program)
tCH(1)
tCLH Clock High Time
tCL(1)
tCLL Clock Low Time
tCLCH(2)
Clock Rise Time (3) (peak to peak)
tCHCL(2)
Clock Fall Time (3) (peak to peak)
tSLCH
tCHSL
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDVCH
tDSU Data In Setup Time
tCHDX
tDH Data In Hold Time
tCHSH
CS# Active Hold Time (relative to SCLK)
tSHCH
CS# Not Active Setup Time (relative to SCLK)
tSHSL(3) tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
tCLQV
tV
Clock Low to Output Valid
VCC=2.7V~3.6V
Loading: 15pF
Loading: 30pF
Clock Low to Output Valid (DTR mode)
VCC=2.7V~3.6V, Loading: 15pF
tCLQX
tHO Output Hold Time
tWHSL(4)
Write Protect Setup Time
tSHWL(4)
Write Protect Hold Time
tCLQV2
tV2
P/N: PM1466
Serial
D.C.
D.C.
Parallel/GPIO
Serial
Parallel/GPIO
Serial
Parallel/GPIO
Serial
Parallel/GPIO
Serial
Parallel/GPIO
Serial
Parallel
Serial
Parallel
Serial
Parallel/GPIO
Read
Write/Erase/
Program
2.7V-3.6V
Serial
3.0V-3.6V
Serial
Parallel/GPIO
1 I/O
2 I/O & 4 I/O
2 I/O & 4 I/O
Parallel/GPIO
1 I/O, 2 I/O &
4 I/O
5.5
30
5.5
30
0.1
0.25
0.1
0.25
8
5
2
10
5
10
5
30
8
15
Max.
104
(Condition:15pF)
66
(Condition:30pF)
6
50
70
70
(Condition:15pF)
50
50
50
20
50
2
20
100
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
V/ns
V/ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
8
ns
20
9
9.5
12
70
ns
ns
ns
ns
ns
9.5
ns
ns
ns
ns
REV. 0.05, MAR. 05, 2009
41
MX25L12855E
Symbol
tDP(2)
tRES1(2)
tRES2(2)
tW
tBP
tPP
tSE
tBE
tBE
tCE
tRESE
tFALL
tLEAD
tLAG
tPL
tWRLR
tWPS
tWSR
Alt. Parameter
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic
Signature Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (64KB)
Block Erase Cycle Time (32KB)
Chip Erase Cycle Time
tr GPIO [6:0] 20%~80% at 3V
tf GPIO [6:0] 20%~80% at 3V
GPIO enable lead time (CS# Low to SCLK
High)
GPIO enable lag time (SCLK Low to CS# High)
Permanent Lock Time
Write Read Lock Register Time
Write Protection Selection Time
Write Security Register Time
Min.
70
90
Typ.
40
9
1.4
90
0.7
0.5
80
Max.
10
Unit
us
100
us
100
us
100
300
5
300
2
2
512
ms
us
ms
ms
s
s
s
ns
ns
60
ns
60
1
100
1
1
ns
ms
ms
ms
ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 4, 5.
6. Only valid in output phase delay configuration "00".
P/N: PM1466
REV. 0.05, MAR. 05, 2009
42
MX25L12855E
Timing Analysis
Figure 6. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
SI
ADDR.LSB IN
P/N: PM1466
REV. 0.05, MAR. 05, 2009
43
MX25L12855E
Figure 8. Serial Input Timing for Double Transfer Rate Mode
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tDVCH
tCHDX
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 9. Serial Output Timing for Double Transfer Rate Mode
CS#
tCH
SCLK
tCLQV2
tCLQX
tCLQV2
tCLQV2
tCL
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
SI
ADDR.LSB IN
P/N: PM1466
REV. 0.05, MAR. 05, 2009
44
MX25L12855E
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
High-Z
SO
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
04
High-Z
P/N: PM1466
REV. 0.05, MAR. 05, 2009
45
MX25L12855E
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
SO
High-Z
7
6
5
3
2
1
Device Identification
0 15 14 13
MSB
3
2
1
0
MSB
Figure 14. Read Identification (RDID) Sequence (Parallel)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SCLK
Command
SI
9F
Manufacturer Identification
PO7~0
High-Z
Device Identification
Notes :
1. Under parallel mode, the fastest access clock freg. will be changed to 6MHz(SCLK pin clock freg.)
To read identification in parallel mode, which requires a parallel mode command (55h) before the read identification command. To exit parallel mode, it requires a (45h) command or power-off/on sequence.
2.There are 3 data bytes which would be output sequentially for Manufacturer and Device ID 1'st byte (Memory
Type) and Device ID 2'nd byte (Memory Density).
P/N: PM1466
REV. 0.05, MAR. 05, 2009
46
MX25L12855E
Figure 15. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 16. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
SO
Status
Register In
01
High-Z
7
6
5
4
3
2
1
0
MSB
P/N: PM1466
REV. 0.05, MAR. 05, 2009
47
MX25L12855E
Figure 17. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
24-Bit Address
23 22 21
03
SI
3
2
1
0
MSB
Data Out 1
High-Z
7
SO
6
5
4
Data Out 2
2
3
1
7
0
MSB
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0B
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycles
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM1466
6
5
4
3
2
1
0
7
MSB
REV. 0.05, MAR. 05, 2009
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MX25L12855E
Figure 19. Fast DT Read (FASTDTRD) Sequence (Command 0D)
CS#
SCLK
0
7
...
8
8-Bit Instruction
SI/SIO0
19
...
...
12-Bit Address
A23 A22 s
0D (hex)
sss
25
26
27
28
29
30
31
32
......
Data output
6 Dummy Cycles
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SO/SIO1
s ss
WP#
Figure 20. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
18 19 20 21 22 23 24 25 26 27
9 10 11
SCLK
8 Bit Instruction
SI/SIO0
SO/SIO1
BB(hex)
High Impedance
12 Address Cycle
4 dummy
cycle
Data Output
address
bit22, bit20, bit18...bit0
dummy
data
bit6, bit4, bit2...bit0, bit6, bit4....
address
bit23, bit21, bit19...bit1
dummy
data
bit7, bit5, bit3...bit1, bit7, bit5....
P/N: PM1466
REV. 0.05, MAR. 05, 2009
49
MX25L12855E
Figure 21. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)
CS#
SCLK
0
...
7
8
8-Bit Instruction
SI/SIO0
13
...
...
6-Bit Address
BD (hex)
SO/SIO1
19
20
21
22
23
24
25
26
......
Data output
6 Dummy Cycles
A22 A20
ssss
A2 A0
ssssssss
D6 D4 D2 D0 D6 D4 D2 D0 D6 D4 D2 D0 D6 D4 D2
sss
A23 A21
ssss
A3
ssssssss
D7 D5 D3 D1 D7 D5 D3 D1 D7 D5 D3 D1 D7 D5 D3
sss
A1
WP#
Figure 22. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SI/SIO0
SO/SIO1
WP#/SIO2
NC/SIO3
6 Address cycles
Performance
enhance
indicator (Note 1,2)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EB(hex)
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will enter the performance enhance mode.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
50
MX25L12855E
Figure 23. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
WP#/SIO2
NC/SIO3
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EB(hex)
SI/SIO0
SO/SIO1
6 Address cycles
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
SCLK
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
SI/SIO0
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
SO/SIO1
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
WP#/SIO2
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
NC/SIO3
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM1466
REV. 0.05, MAR. 05, 2009
51
MX25L12855E
Figure 24. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)
CS#
SCLK
0
...
7
8-Bit Instruction
8
...
10
3 Address cycles
18
......
1 cycle
Performance
enhance
indicator (Note 1,2)
7 Dummy
cycles
19
20
21
22
23
24
25
......
Data output
A20 A16
A4 A0 P4 P0
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4
......
SO/SIO1
A21 A17
A5 A1 P5 P1
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5
......
WP#/SIO2
A22 A18
A6 A2 P6 P2
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6
......
A23 A19
A7 A3 P7 P3
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7
......
SI/SIO0
NC/SIO3
ED (hex)
Note:
1. Hi-impedance is inhibited for this clock cycle.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will enter the performance enhance mode.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
52
MX25L12855E
Figure 25. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)
CS#
SCLK
0
...
7
8
8-Bit Instruction
SI/SIO0
ED (hex)
...
10
3 Address cycles
18
......
1 cycle
Performance
enhance
indicator (Note)
19
20
7 Dummy
cycles
21
22
23
24
25
......
Data output
A20 A16 • • • • A4 A0 P4 P0 • • • • • • • •
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 • • •
SO/SIO1
A21 A17 • • • • A5 A1 P5 P1 • • • • • • • •
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 • • •
WP#/SIO2
A22 A18 • • • • A6 A2 P6 P2 • • • • • • • •
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 • • •
A23 A19 • • • • A7 A3 P7 P3 • • • • • • • •
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 • • •
NC/SIO3
CS#
SCLK
n+1
...
......
3 Address cycles
1 cycle
Performance
enhance
indicator (Note)
......
7 Dummy
cycles
Data output
SI/SIO0
A20 A16 • • • • A4 A0 P4 P0 • • • • • • • •
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 • • •
SO/SIO1
A21 A17 • • • • A5 A1 P5 P1 • • • • • • • •
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 • • •
WP#/SIO2
A22 A18 • • • • A6 A2 P6 P2 • • • • • • • •
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 • • •
NC/SIO3
A23 A19 • • • • A7 A3 P7 P3 • • • • • • • •
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 • • •
Note: Performance enhance, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling)
P/N: PM1466
REV. 0.05, MAR. 05, 2009
53
MX25L12855E
Figure 26. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
24-Bit Address
23 22 21
02
SI
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
2078
2079
2077
2076
2075
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2072
CS#
1
0
SCLK
Data Byte 2
7
SI
6
5
4
3
Data Byte 3
2
0
1
7
MSB
6
5
4
3
Data Byte 256
2
1
7
0
MSB
6
5
4
3
2
MSB
Figure 27. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Command
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
6 Address cycles
20 16 12 8 4
0
4
0
4
0
4
0
4
0
SO/SIO1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
WP#/SIO2
22 18 14 10 6
2
6
2
6
2
6
2
6
2
NC/SIO3
23 19 15 11 7
3
7
3
7
3
7
3
7
3
SI/SIO0
38
P/N: PM1466
REV. 0.05, MAR. 05, 2009
54
MX25L12855E
Figure 28. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
0 1
6 7 8 9
30 31 31 32
0 1
47 48
6 7 8
20 21 22 23 24
0
7
7 8
0
SCLK
Command
SI
S0
AD (hex)
Valid
Command (1)
data in
Byte 0, Byte1
24-bit address
high impedance
data in
Byte n-1, Byte n
04 (hex)
05 (hex)
status (2)
Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and
CS# goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI)
command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if
CP mode is ended.
Figure 29. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
20
2
1
0
MSB
Note: SE command is 20(hex).
Figure 30. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8
2
1
0
MSB
Note: BE command is D8(hex).
P/N: PM1466
REV. 0.05, MAR. 05, 2009
55
MX25L12855E
Figure 31. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
Note: CE command is 60(hex) or C7(hex).
Figure 32. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
B9
SI
Stand-by Mode
Deep Power-down Mode
Figure 33. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
AB
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
Electronic Signature Out
High-Z
7
SO
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1466
Stand-by Mode
REV. 0.05, MAR. 05, 2009
56
MX25L12855E
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
AB
High-Z
SO
Stand-by Mode
Deep Power-down Mode
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
X
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
MSB
MSB
2
1
0
7
MSB
Notes:
(1) ADD=00h will output the Manufacturer ID first and ADD=01h will output Device ID first
(2) Instruction is either 90(hex) or EF(hex) or DF(hex) or CF(hex).
P/N: PM1466
REV. 0.05, MAR. 05, 2009
57
MX25L12855E
Figure 36. READ ARRAY SEQUENCE (Parallel)
CS#
SCLK
SI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Hi-Z
PO7,PO6,
…PO0
1st byte (03h)
2nd byte (AD1)
CS#
SCLK
SI
PO7,PO6,
…PO0
Bit1
Bit0
Byte 1
………….
Byte 2
4th byte (AD3)
CS#
SCLK
SI
PO7,PO6,
…PO0
………….
Byte N
Hi-Z
Notes :
1. 1st Byte='03h'
2. 2nd Byte=Address 1(AD1), AD23=bit7, AD22=bit6, AD21=bit5, AD20=bit4,....AD16=bit0.
3. 3rd Byte=Address 2(AD2), AD15=bit7, AD14=bit6, AD13=bit5, AD12=bit4,....AD8=bit0.
4. 4th Byte=Address 3(AD3), AD7=bit7, AD6=bit6, ....AD0=bit0.
5. From Byte 5, PO7-0 Would Output Array Data.
6. Under parallel mode, the fastest access clock freq. will be changed to 6MHz(SCLK pin clock freq.).
7. To read array in parallel mode requires a parallel mode command (55h) before the read command.
To exit parallel mode, it requires a (45h) command or power-off/on sequence.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
58
MX25L12855E
Figure 37. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel)
CS#
SCLK
SI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Hi-Z
PO7,PO6,
…PO0
1st byte (02h)
2nd byte (AD1)
CS#
SCLK
SI
PO7,PO6,
…PO0
Bit1
Bit0
Byte 1
………….
Byte 2
4th byte (AD3)
CS#
SCLK
SI
PO7,PO6,
…PO0
………….
Byte N
Hi-Z
Notes :
1. 1st Byte='02h'
2. 2nd Byte=Address 1(AD1), AD23=bit7, AD22=bit6, AD21=bit5, AD20=bit4,....AD16=bit0.
3. 3rd Byte=Address 2(AD2), AD15=bit7, AD14=bit6, AD13=bit5, AD12=bit4,....AD8=bit0.
4. 4th Byte=Address 3(AD3), AD7=bit7, AD6=bit6, ....AD0=bit0.
5. 5th byte: 1st write data byte.
6. Under parallel mode, the fastest access clock freq. will be changed to 6MHz(SCLK pin clock freq.).
7. To program in parallel mode requires a parallel mode command (55h) before the program command.
To exit parallel mode, it requires a (45h) command or power-off/on sequence.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
59
MX25L12855E
Figure 38. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Instruction
SI
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
Electronic Signature Out
High Impedance
PO7~0
Byte Output
Deep Power-down Mode
Stand-by Mode
Notes :
1. Under parallel mode, the fastest access clock freg. will be changed to 6MHz(SCLK pin clock freg.)
To release from Deep Power-down mode and read ID in parallel mode, which requires a parallel mode command (55h) before the read status register command.
To exit parallel mode, it requires a (45h) command or power-off/on sequence.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
60
MX25L12855E
Figure 39. Read Electronic Manufacturer & Device ID (REMS) Sequence (Parallel)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
PO7~0
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
PO7~0
Device ID
Notes :
1. ADD=00h will output the Manufacturer ID first and ADD=01h will output Device ID first.
2. Under parallel mode, the fastest access clock freg. will be changed to 6MHz(SCLK pin clock freg.)
To read ID in parallel mode, which requires a parallel mode command (55h) before the read ID command.
To exit Parallel mode, it requires a (45h) command or power-off/on sequence.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
61
MX25L12855E
Figure 40. Write Protection Selection (WPSEL) Sequence (Command 68)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
68
Figure 41. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
36/39
2
1
0
MSB
Figure 42. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
3F
3 Address Bytes
23 22 21
3
2
MSB
SO
1
0
Block Protection Lock status out
High-Z
7
6
5
4
3
2
1
0
MSB
P/N: PM1466
REV. 0.05, MAR. 05, 2009
62
MX25L12855E
Figure 43. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
7E/98
Figure 44. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 9. Power-Up Timing
Symbol
tVSL(1)
Parameter
VCC(min) to CS# low
Min.
300
Max.
Unit
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1466
REV. 0.05, MAR. 05, 2009
63
MX25L12855E
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
tVR
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
64
MX25L12855E
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time (128Mb)
Byte Program Time (via page program command)
Page Program Time
Erase/Program Cycle
Min.
TYP. (1)
40
90
0.7
0.5
80
9
1.4
100,000
Max. (2)
100
300
2
2
512
300
5
UNIT
ms
ms
s
s
s
us
ms
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.0V, and 100K cycle with 90% confidence level.
L
ATCH-UP CHARACTERISTICS
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1466
MIN.
-1.0V
-1.0V
-100mA
MAX.
2 VCCmax
VCC + 1.0V
+100mA
REV. 0.05, MAR. 05, 2009
65
MX25L12855E
ORDERING INFORMATION
Please contact Macronix sales for specific information regarding 16-pin SOP (300mil) and 24-ball TFBGA
(10x13mm) ordering information.
PART NAME DESCRIPTION
Please contact Macronix sales for specific information regarding 16-pin SOP (300mil) and 24-ball TFBGA
(10x13mm) part name description.
P/N: PM1466
REV. 0.05, MAR. 05, 2009
66
MX25L12855E
PACKAGE INFORMATION
P/N: PM1466
REV. 0.05, MAR. 05, 2009
67
MX25L12855E
P/N: PM1466
REV. 0.05, MAR. 05, 2009
68
MX25L12855E
REVISION HISTORY
Revision No. Description
Page
0.01
1. Modified tSLCH, tSHCH (VIO=1.65~2.2V) from 10ns to 20ns
P46
0.02
1. Modified the performance enhance mode reset function description P24,58
0.03
1. Modified statement
All
2. Created additional instructions description
P34,41~43
0.04
1. Corrected wording error
All
2. Removed MX25L6455E
All
3. Removed VIO function
All
4. Modified Status Register QE definition
P17
5. Added Block Erase Time (32KB)
P65
6. Added Note for 4xI/O Read Mode Sequence, Fast Quad I/O DT P51,52
Read sequence and 4xI/O Read Enhance Mode Sequence
7. Added 24-ball TFBGA
P6,8,66,68
8. Renamed Double data rate as Double transfer rate
All
9. Electrical Specifications: notice/overshoot waveform figure
P38
10. Table 7. DC Characteristics
P40
11. Table 8. AC Characteristics/notes
P41,42
0.05
1. Added WRLCR command completion under "WEL bit is reset by P10,16
following situation"
2. Modified ICC2 & ICC4 from 20mA to 25mA
P5,40
3. Modified tCLQV, tCLQV2 and tCLQX
P41
4. Added tPL, tWRLR, tWPS & tWSR
P42
5. Changed tVSL spec from 200us (min.) to 300us (min.)
P63
6. Modified Figure 4. INPUT TEST WAVEFORMS AND P39
MEASUREMENT LEVEL
7. Revised RDSLOCK into RDBLOCK and added BE32K and 4PP P13,15,16
P24,25
8. Added CFh
P27
9. Changed title from "Advanced Information" to "Preliminary"
P5
P/N: PM1466
Date
JUN/16/2008
JUN/27/2008
JUL/29/2008
JAN/19/2009
MAR/05/2009
REV. 0.05, MAR. 05, 2009
69
MX25L12855E
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co. Ltd. 2008~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX
Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the respective
companies.
MACRONIX INTERNATIONAL CO., LTD.
Macronix Offices : Taiwan
Headquarters, FAB2
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Macronix Asia Limited.
Macronix, International Co., Ltd.
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Tel: +886-3-5786688
Fax: +886-3-5632888
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Macronix, International Co., Ltd.
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Macronix Pte. Ltd.
1 Marine Parade Central, #11-03 Parkway Centre,
Macronix (Hong Kong) Co., Limited.
NKF Bldg. 5F, 1-2 Higashida-cho,
Kawasaki-ku Kawasaki-shi,
Kanagawa Pref. 210-0005, Japan
Tel: +81-44-246-9100
Fax: +81-44-246-9105
Room 1401 & 1404, Blcok A, TianAN Hi-Tech PLAZA Tower,
Che Gong Miao, FutianDistrict, Shenzhen PRC 518040
Tel: +86-755-83433579
Fax: +86-755-83438078
Macronix America, Inc.
680 North McCarthy Blvd. Milpitas, CA 95035,
U.S.A.
Tel: +1-408-262-8887
Fax: +1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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