VISHAY SI9241AEY

Si9241AEY
Vishay Siliconix
Single-Ended Bus Transceiver
FEATURES
D
D
D
D
D
D
D
D Operating Power Supply Range 6 V v VBAT v 36 V
D Reverse Battery Protection Down to VBAT w –24 V
D Standby Mode With Very Low Current Consumption
IBAT(SB) = 1 A @ VDD = 0.5 V
D Low Quiescent Current in OFF Condition
IBAT = 120 A and IDD v 10 A
D ISO 9141 Compatible
Overtemperature Shutdown Function For K Output
Defined K Output OFF for Open GND
Defined Receive Output Status for Open K Input
Defined K Output OFF for TX Input Open
Open Drain Fault Output
2-kV ESD
Typical Transmit Speeds of 200 kBaud
DESCRIPTION
The Si9241AEY is a monolithic bus transceiver designed to
provide bidirectional serial communication in automotive
diagnostic applications.
The Si9241AEY is built on the Vishay Siliconix BiC/DMOS
process. An epitaxial layer prevents latchup.
The RX output is capable of driving CMOS or 1
The device incorporates protection against overvoltages and
short circuits to VBAT. The transceiver pin is protected and can
be driven beyond the VBAT voltage.
LSTTL load.
The Si9241AEY is available in a space efficient 8-pin SO
package. It operates reliably over the automotive temperature
range (–40 to 125_C).
PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM
VDD
VBAT
VBAT
–
+
RX
VDD
2
K
CS
TX
FAULT
Fault
Detector
GND
Document Number: 70787
S-02936—Rev. D, 22-Jan-01
www.vishay.com
1
Si9241AEY
Vishay Siliconix
OUTPUT TABLE AND STATE DIAGRAMS
Over Temp
Power On
A=1
A=0
Over Temp @CS
Short Circuit
Power On
B=1
B=0
CS
Note: Over Temp is an internal condition, not meant
to be a logic signal.
STATE
INPUTS VARIABLE
OUTPUT
TABLE
CS
TX
A
B
RX
K
FAULT
0
0
1
1
0
0
1
Comments
0
1
1
1
1
1
1
X
X
0
1
K
HiZ
0
Over Temp
0
X
1
0
K
HiZ
0
Short Circuit
1
X
1
1
0
0
1
Receive Mode
1
X
1
1
1
1
1
X = “1” or “0”
HiZ = High Impedance State
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to Ground
Voltage on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage On VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –24 V to 45 V
K Pin Only, Short Circuit Duration (to VBAT or GND) . . . . . . . . . . Continuous
Voltage K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –16 V to (VBAT + 1 V)
Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 to 125_C
Voltage Difference V(VBAT, K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 V
Voltage or Max. Current On Any Pin
(Except VBAT , K) . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V) or 10 mA
Junction and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C
Thermal Resistance JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltage Referenced to Ground
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 5.5 V
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V to 36 V
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K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V to 36 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
Document Number: 70787
S-02936—Rev. D, 22-Jan-01
Si9241AEY
Vishay Siliconix
SPECIFICATIONS
Limits
Test Conditions Unless Specified
Parameter
VDD = 4.5 to 5.5 V
VBAT = 6 to 36 V
Symbol
–40 to 125_C
Tempa
Minb
Typc
Maxb
Unit
Transmitter and Logic Levels
CS, TX Input Low Voltage
VILT
Full
CS, TX Input High Voltage
VIHT
Full
TX Input Capacitanced
CS, TX Input Pull-up Resistance
CINT
RTX, RCS
1.5
3.5
Full
10
20
V
10
pF
40
k
VDD = 5.5 V, TX or CS = 1.5 V, 3.5 V
Full
RL = 510 "5% , VBAT = 6 to 18 V
Full
0.2 VBAT
RL = 1 k "5% , VBAT = 16 to 36 V
Full
0.2 VBAT
RL = 510 "5% , VBAT = 4.5 V
Full
RL = 510 "5% , VBAT = 4.5 to 18 V
Full
0.95 VBAT
RL = 1 k "5% , VBAT = 16 to 36 V
Full
0.95 VBAT
See Test Circuit
K Transmit
K Output Low Voltage
K Output High Voltage
VOLK
VOHK
K Rise, Fall Times
tr, tf
K Output Sink Resistance
Rsi
K Output Capacitanced
CO
CS = 0 V, TX = 0 V
1.2
V
Full
9.6
s
Full
110
Full
20
pF
Receiver
K Input Low Voltage
VILK
Full
K Input High Voltage
VIHK
Full
K Input Hysteresis,c, d
VHYS
Full
K Input Currents
IIHK
RX Output Low Voltage
VOLR
RX Pull-up Resistance
RRX
RX Turn On Delay
RX Turn Off Delay
td(on)
td(off)
CS = 4 V
VIHK = VBAT
Full
VILK = 0.35 VBAT
IOLR = 1 mA
Full
Full
0.35 VBAT
0.65 VBAT
V
0.05 VBAT
20
5
A
0.4
V
20
k
RL = 510 "5% , VBAT = 6 to 18 V
CL = 10 nF, See Test Circuit
Full
3
10
RL = 1 k "5% , VBAT = 16 to 36 V
CL = 4.7 nF, See Test Circuit
Full
3
10
RL = 510 "5% , VBAT = 6 to 18 V
CL = 10 nF, See Test Circuit
Full
3
10
RL = 1 k "5% , VBAT = 16 to 36 V
CL = 4.7 nF, See Test Circuit
Full
3
10
s
Supplies
Bat Supply Current On
IBAT(on)
CS = TX = 0 V, VBAT v 16 V
Full
1.2
3
Bat Supply Current Off
IBAT(off)
CS = High, VBAT v 12 V, TX = Highf
Full
120
220
Bat Supply Current Standby
IBAT(SB)
VDD v 0.5 V, VBAT v 12 V
Full
t1
10
Logic Supply Current On
IDD(on)
VDD v 5.5 V, TX = 0 V
Full
1.4
2.3
mA
Logic Supply Current Off
IDD(off)
CS = High, VBAT v 12 V, TX = Highf
Full
10
mA
A
Miscellaneous
TX Transmit Baud Rate
BRT
RL = 510 , CL = 10 nF
Full
RX Receive Baud Ratec
BRR
6 V t VBAT < 16 V, CRX = 20 pF
Full
Transmission Frequency
fK-RXK
6 V t VBAT < 16 V, RK = 510 , CK v 1.3 nF
Full
Fault Output Low Voltage
VOLF
CS = TX = 0 V, K = VBAT, IOLF = 1 mA
Full
CS Minimum Pulse Widthd, e
tcs
Over Temperature Shutdownd
TSHUT
Temperature Shutdown Hysteresisc
THYST
Full
Temperature Rising
10.4
kBaud
200
50
200
kHz
0.4
160
V
s
1
180
30
_
_C
Notes
a. Room = 25_C, Cold and Hot = as determined by the operating temperature suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Guaranteed by design, not subject to production test.
e. Minimum pulse width to reset a fault condition.
f.
High referes to Logic High and Low refers to Logic Low.
Document Number: 70787
S-02936—Rev. D, 22-Jan-01
www.vishay.com
3
Si9241AEY
Vishay Siliconix
PIN CONFIGURATION
Narrow Body
SO Package
VDD
ORDERING INFORMATION
1
8
RX
TX
2
7
VBAT
CS
3
6
K
FAULT
4
5
GND
Part Number
Temperature Range
Si9241AEY
–40 to 125_C
Top View
PIN DESCRIPTION
Pin Number
Symbol
Description
1
VDD
Positive Power Supply
2
TX
Transmit, Input
3
CS
Chip Select, Input
4
FAULT
5
GND
6
K
7
VBAT
8
RX
Fault, Open Drain Output
Ground Connection
Transmit/Receive, Bidirectional
Battery Power Supply
Receiver, Output
FUNCTIONAL DESCRIPTION
The Si9241AEY can be either in transmit or receive mode and
it contains over temperature, and short circuit VBAT fault
detection circuits.
The voltage on K is internally compared to VBAT/2. If the
voltage on the K pin is less than VBAT/2 then RX output will be
“low.” If the voltage on the K pin is greater than VBAT/2 then RX
output will be “high.”
In order to be in transmit mode, CS must be set “low.” When
CS and TX are set “low” the internal MOSFET will turn on,
causing the K pin to be “low.” In the transmit mode, the
processor monitors RX and TX. When the two mirror each
other there is no fault. In the event of over temperature, or short
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circuit to VBAT, the Si9241AEY will turn off the K output to
protect the IC and the external open drain FAULT pin will be
asserted. The K pin will stay in high impedance and RX will
follow the K pin. The fault will be reset when CS is toggled high.
RX, CS and TX pins have an internal pull up resistor to VDD
while the K pin has internal pull down resistors. When any one
of the TX, VBAT or GND pins is open the K output is off.
When CS is set “high” the Si9241AEY is in receive mode and
the internal MOSFET for the K pin is turned off. The RX output
will follow the K pin. If CS is “low” while the IC is receiving data,
an incorrect fault signal will occur.
To inhibit the short detect, tie CS and TX together.
Document Number: 70787
S-02936—Rev. D, 22-Jan-01
Si9241AEY
Vishay Siliconix
TEST CIRCUIT AND TIMING DIAGRAMS (TRANSMIT ONLY)
VDD
VBAT
td(off)
RX
td(on)
Si9241AEY
TXmin
VDD
TX
VBAT
VBAT
+
–
RX
80%
VDD
V
80%
RL
+
–
K
CL
20%
20%
TX
VK
tr
GND
CS
tf
RL = 510 , CL = 10 nF, VBAT = 6 V to 18 V
RL = 1 k, CL = 4.7 nF, VBAT = 16 V to 36 V
APPLICATION CIRCUIT
ECU
VDD
Si9241AEY
Diagnostic Tester
VB
+
–
VDD
V
+
–
K-Line
510 I/Os
Microcontroller
0.4 VDD
Si9241AEY
VDD
+
–
V
+
–
L-Line
VBAT
VDD
C1
0.1 F
50 V
C1
0.1 F
Bus
ECU = Electronic Control Unit
Document Number: 70787
S-02936—Rev. D, 22-Jan-01
www.vishay.com
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