PLL501-05/-07 VCXO Clock Generator IC PIN CONFIGURATION FEATURES • • • • • XIN 1 VDD 2 VIN 3 GND 4 8 XOUT 7 GND 6 VDD 5 CLK Table 1: Crystal / Output Frequencies DEVICE PLL501-05 DESCRIPTIONS The PLL501-05 and PLL501-07 are monolithic low jitter, high performance CMOS VCXO chips. They allow the control of the output frequency with an input voltage (VIN), using a low cost crystal. The PLL501-05 and PLL501-07 are ideal for ADSL applications. With a low cost 13.248MHz crystal, the PLL501-05 provides a pullable 35.328MHz output clock, while the PLL501-07 provides a 70.656MHz output clock. PLL501-XX • • • Integrated voltage-controlled crystal oscillator circuitry (VCXO) (pull range 200ppm minimum). Ideal for ADSL (35.328MHz and 70.656MHz). VCXO tuning range: 0 - 3.3V. Integrated phase-locked loop (PLL) provides pullable output at 35.328MHz (for PLL501-05) and 70.656MHz (for PLL501-07) with a 13.248MHz low cost parallel resonant crystal. Accepts fundamental-mode parallel resonant crystals from 8 to 15 MHz. 3.3V supply voltage. Small circuit board footprint (8-pin 0.150’’ SOIC). 12mA output drives capability at TTL level. PLL501-07 F XIN (MHz) CLK (MHz) 13.248 35.328 (8 to 15) (2.667 x F XIN ) 13.248 70.656 (8 to 15) (5.333 x F XIN ) Note: Contact PhaseLink for custom PLL Frequencies BLOCK DIAGRAM XIN VCXO XOUT PLL Output Buffer CLK VIN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/10/01 Page 1 PLL501-05/-07 VCXO Clock Generator IC PIN DESCRIPTIONS Name Number Type Description XIN 1 I Crystal input connection (parallel resonant crystal, C L = 10pF). VDD 2 P 3.3V Power Supply. VIN 3 I Voltage Input for VCXO Frequency Control. GND 4 P Ground for PLL Core. CLK 5 O Clock Output. VDD 6 P 3.3V Power Supply. GND 7 P Ground. XOUT 8 O Crystal connection. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/10/01 Page 2 PLL501-05/-07 VCXO Clock Generator IC ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 7 V Input Voltage, dc VI V SS - 0.5 V DD + 0.5 V Output Voltage, dc VO V SS - 0.5 V DD + 0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature TA 0 70 °C Junction Temperature TJ 125 °C 260 °C 2 kV Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. DC Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs I DD Operating Voltage V DD Output High Voltage V OH I OH = -12mA Output Low Voltage V OL I LO = 12mA Output High Voltage at CMOS level V OHC I OH = -4mA Operating Supply Current I DD CONDITIONS MIN. F XIN = 8 - 15MHz TYP. MAX. 20 Ouput load of 10pF 3.13 mA 3.47 2.4 V DD – 0.4 Short Circuit Current VIN, VCXO Control Voltage 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 0 V V 0.4 No Load UNITS V V 7 mA ±50 mA 3.3 V Rev 05/10/01 Page 3 PLL501-05/-07 VCXO Clock Generator IC 3. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. Input Crystal Frequency TYP. 8 MAX. UNITS 15 MHz Output Clock Rise Time tr 0.8V ~ 2.0V 1.5 ns Output Clock Fall Time tf 2.0V ~ 0.8V 1.5 ns 55 % Output Clock Duty Cycle Measured @ 1.4V Max Absolute Jitter Short Term 45 Short Circuit Current 50 100 ps ±50 mA 4. Voltage Control Crystal Oscillator PARAMETERS PLL Stabilization Time * VCXO Stabilization Time * SYMBOL T PLLSTB T VCXOSTB Output Frequency Synthesis Error CONDITIONS MIN. TYP. MAX. UNITS From VCXO stable 500 µs From power valid 10 ms (Unless otherwise noted in Frequency Table) ±30 ppm F XIN = 8 - 15MHz; VCXO Tuning Range XTAL C 0 /C 1 < 250; C L =10pF CLK output pullability 0V≤VIN≤3.3V 200 ppm ±100 ppm VCXO Tuning Characteristic 100 ppm/V Note: Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. 5. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. Crystal Resonator Frequency F XIN Parallel Fundamental Mode 8 Crystal Loading Capacitance Rating C L (xtal) Crystal Pullability Recommended ESR TYP. MAX. UNITS 15 MHz 10 pF C 0 /C 1 (xtal) At cut 250 - RE At cut 30 Ω 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/10/01 Page 4 PLL501-05/-07 VCXO Clock Generator IC 6. External Components and Layout Recommendations The PLL501-05/-07 requires a minimum number of external components for proper operation. A standard low frequency decoupling capacitor of 2µF or more should be used between VDD and GND (pin 2 and pin 4, as well as pin 6 and pin 7). Additionally, higher frequency decoupling capacitors of 0.01µF are required between VDD and GND (between pin 2 and 4, and between pin 6 and 7). These higher frequency decoupling capacitors must be connected as close to the PLL501-05/-07 chip as possible, and preferably directly next to the PLL501-05/-07 pins. A series termination resistor of 33Ω may be used for the clock output. The input crystal must be connected as close to the chip as possible, and preferably directly next to the PLL501-05/-07 pins. If a crystal with C L higher than 10pF is used, it will requires additional loading capacitors externally to complement the internal 10pF of the PLL501-05/-07: one between each crystal electrode and GND, as close to the crystal as possible, and preferably directly next to the crystal electrodes. Consult PhaseLink for recommended suppliers. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/10/01 Page 5 PLL501-05/-07 VCXO Clock Generator IC PACKAGE INFORMATION 8 PIN Narrow SOIC ( mm ) SOIC Symbol Min. Max. A 1.55 1.73 A1 B 0.15 0.35 0.18 0.49 C D E 0.19 4.80 3.81 0.25 4.98 3.99 H L 5.84 0.41 6.20 0.89 e 1.27 BSC E H D A A 1 C L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL501-0x S C PART NUMBER TEMPERATURATRE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/10/01 Page 6